root/drivers/usb/musb/musb_core.c

DEFINITIONS

1. dev_to_musb
2. musb_get_mode
3. musb_ulpi_read
4. musb_ulpi_write
5. musb_default_fifo_offset
6. musb_flat_ep_select
7. musb_flat_ep_offset
8. musb_indexed_ep_select
9. musb_indexed_ep_offset
10. musb_default_busctl_offset
11. musb_default_readb
12. musb_default_writeb
13. musb_default_readw
14. musb_default_writew
15. musb_default_write_fifo
16. musb_default_read_fifo
17. musb_readl
18. musb_writel
19. musb_read_fifo
20. musb_write_fifo
21. musb_load_testpacket
22. musb_otg_timer_func
23. musb_hnp_stop
24. musb_handle_intr_resume
25. musb_handle_intr_sessreq
26. musb_handle_intr_vbuserr
27. musb_handle_intr_suspend
28. musb_handle_intr_connect
29. musb_handle_intr_disconnect
30. musb_handle_intr_reset
31. musb_stage0_irq
32. musb_disable_interrupts
33. musb_enable_interrupts
34. musb_start
35. musb_stop
36. fifo_setup
37. ep_config_from_table
38. ep_config_from_hw
39. musb_core_init
40. musb_interrupt
41. musb_dma_completion
42. musb_mailbox
43. mode_show
44. mode_store
45. vbus_store
46. vbus_show
47. srp_store
48. musb_pm_runtime_check_session
49. musb_irq_work
50. musb_recover_from_babble
51. allocate_instance
52. musb_free
53. musb_run_resume_work
54. musb_queue_resume_work
55. musb_deassert_reset
56. musb_init_controller
57. musb_probe
58. musb_remove
59. musb_save_context
60. musb_restore_context
61. musb_suspend
62. musb_resume
63. musb_runtime_suspend
64. musb_runtime_resume

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MUSB OTG driver core code
   4  *
   5  * Copyright 2005 Mentor Graphics Corporation
   6  * Copyright (C) 2005-2006 by Texas Instruments
   7  * Copyright (C) 2006-2007 Nokia Corporation
   8  */
   9 
  10 /*
  11  * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
  12  *
  13  * This consists of a Host Controller Driver (HCD) and a peripheral
  14  * controller driver implementing the "Gadget" API; OTG support is
  15  * in the works.  These are normal Linux-USB controller drivers which
  16  * use IRQs and have no dedicated thread.
  17  *
  18  * This version of the driver has only been used with products from
  19  * Texas Instruments.  Those products integrate the Inventra logic
  20  * with other DMA, IRQ, and bus modules, as well as other logic that
  21  * needs to be reflected in this driver.
  22  *
  23  *
  24  * NOTE:  the original Mentor code here was pretty much a collection
  25  * of mechanisms that don't seem to have been fully integrated/working
  26  * for *any* Linux kernel version.  This version aims at Linux 2.6.now,
  27  * Key open issues include:
  28  *
  29  *  - Lack of host-side transaction scheduling, for all transfer types.
  30  *    The hardware doesn't do it; instead, software must.
  31  *
  32  *    This is not an issue for OTG devices that don't support external
  33  *    hubs, but for more "normal" USB hosts it's a user issue that the
  34  *    "multipoint" support doesn't scale in the expected ways.  That
  35  *    includes DaVinci EVM in a common non-OTG mode.
  36  *
  37  *      * Control and bulk use dedicated endpoints, and there's as
  38  *        yet no mechanism to either (a) reclaim the hardware when
  39  *        peripherals are NAKing, which gets complicated with bulk
  40  *        endpoints, or (b) use more than a single bulk endpoint in
  41  *        each direction.
  42  *
  43  *        RESULT:  one device may be perceived as blocking another one.
  44  *
  45  *      * Interrupt and isochronous will dynamically allocate endpoint
  46  *        hardware, but (a) there's no record keeping for bandwidth;
  47  *        (b) in the common case that few endpoints are available, there
  48  *        is no mechanism to reuse endpoints to talk to multiple devices.
  49  *
  50  *        RESULT:  At one extreme, bandwidth can be overcommitted in
  51  *        some hardware configurations, no faults will be reported.
  52  *        At the other extreme, the bandwidth capabilities which do
  53  *        exist tend to be severely undercommitted.  You can't yet hook
  54  *        up both a keyboard and a mouse to an external USB hub.
  55  */
  56 
  57 /*
  58  * This gets many kinds of configuration information:
  59  *      - Kconfig for everything user-configurable
  60  *      - platform_device for addressing, irq, and platform_data
  61  *      - platform_data is mostly for board-specific information
  62  *        (plus recentrly, SOC or family details)
  63  *
  64  * Most of the conditional compilation will (someday) vanish.
  65  */
  66 
  67 #include <linux/module.h>
  68 #include <linux/kernel.h>
  69 #include <linux/sched.h>
  70 #include <linux/slab.h>
  71 #include <linux/list.h>
  72 #include <linux/kobject.h>
  73 #include <linux/prefetch.h>
  74 #include <linux/platform_device.h>
  75 #include <linux/io.h>
  76 #include <linux/dma-mapping.h>
  77 #include <linux/usb.h>
  78 #include <linux/usb/of.h>
  79 
  80 #include "musb_core.h"
  81 #include "musb_trace.h"
  82 
  83 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
  84 
  85 
  86 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
  87 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
  88 
  89 #define MUSB_VERSION "6.0"
  90 
  91 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
  92 
  93 #define MUSB_DRIVER_NAME "musb-hdrc"
  94 const char musb_driver_name[] = MUSB_DRIVER_NAME;
  95 
  96 MODULE_DESCRIPTION(DRIVER_INFO);
  97 MODULE_AUTHOR(DRIVER_AUTHOR);
  98 MODULE_LICENSE("GPL");
  99 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
 100 
 101 
 102 /*-------------------------------------------------------------------------*/
 103 
 104 static inline struct musb *dev_to_musb(struct device *dev)
 105 {
 106         return dev_get_drvdata(dev);
 107 }
 108 
 109 enum musb_mode musb_get_mode(struct device *dev)
 110 {
 111         enum usb_dr_mode mode;
 112 
 113         mode = usb_get_dr_mode(dev);
 114         switch (mode) {
 115         case USB_DR_MODE_HOST:
 116                 return MUSB_HOST;
 117         case USB_DR_MODE_PERIPHERAL:
 118                 return MUSB_PERIPHERAL;
 119         case USB_DR_MODE_OTG:
 120         case USB_DR_MODE_UNKNOWN:
 121         default:
 122                 return MUSB_OTG;
 123         }
 124 }
 125 EXPORT_SYMBOL_GPL(musb_get_mode);
 126 
 127 /*-------------------------------------------------------------------------*/
 128 
 129 static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
 130 {
 131         void __iomem *addr = phy->io_priv;
 132         int     i = 0;
 133         u8      r;
 134         u8      power;
 135         int     ret;
 136 
 137         pm_runtime_get_sync(phy->io_dev);
 138 
 139         /* Make sure the transceiver is not in low power mode */
 140         power = musb_readb(addr, MUSB_POWER);
 141         power &= ~MUSB_POWER_SUSPENDM;
 142         musb_writeb(addr, MUSB_POWER, power);
 143 
 144         /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
 145          * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
 146          */
 147 
 148         musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
 149         musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
 150                         MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
 151 
 152         while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
 153                                 & MUSB_ULPI_REG_CMPLT)) {
 154                 i++;
 155                 if (i == 10000) {
 156                         ret = -ETIMEDOUT;
 157                         goto out;
 158                 }
 159 
 160         }
 161         r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
 162         r &= ~MUSB_ULPI_REG_CMPLT;
 163         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
 164 
 165         ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
 166 
 167 out:
 168         pm_runtime_put(phy->io_dev);
 169 
 170         return ret;
 171 }
 172 
 173 static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
 174 {
 175         void __iomem *addr = phy->io_priv;
 176         int     i = 0;
 177         u8      r = 0;
 178         u8      power;
 179         int     ret = 0;
 180 
 181         pm_runtime_get_sync(phy->io_dev);
 182 
 183         /* Make sure the transceiver is not in low power mode */
 184         power = musb_readb(addr, MUSB_POWER);
 185         power &= ~MUSB_POWER_SUSPENDM;
 186         musb_writeb(addr, MUSB_POWER, power);
 187 
 188         musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
 189         musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
 190         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
 191 
 192         while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
 193                                 & MUSB_ULPI_REG_CMPLT)) {
 194                 i++;
 195                 if (i == 10000) {
 196                         ret = -ETIMEDOUT;
 197                         goto out;
 198                 }
 199         }
 200 
 201         r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
 202         r &= ~MUSB_ULPI_REG_CMPLT;
 203         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
 204 
 205 out:
 206         pm_runtime_put(phy->io_dev);
 207 
 208         return ret;
 209 }
 210 
 211 static struct usb_phy_io_ops musb_ulpi_access = {
 212         .read = musb_ulpi_read,
 213         .write = musb_ulpi_write,
 214 };
 215 
 216 /*-------------------------------------------------------------------------*/
 217 
 218 static u32 musb_default_fifo_offset(u8 epnum)
 219 {
 220         return 0x20 + (epnum * 4);
 221 }
 222 
 223 /* "flat" mapping: each endpoint has its own i/o address */
 224 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
 225 {
 226 }
 227 
 228 static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
 229 {
 230         return 0x100 + (0x10 * epnum) + offset;
 231 }
 232 
 233 /* "indexed" mapping: INDEX register controls register bank select */
 234 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
 235 {
 236         musb_writeb(mbase, MUSB_INDEX, epnum);
 237 }
 238 
 239 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
 240 {
 241         return 0x10 + offset;
 242 }
 243 
 244 static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
 245 {
 246         return 0x80 + (0x08 * epnum) + offset;
 247 }
 248 
 249 static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
 250 {
 251         u8 data =  __raw_readb(addr + offset);
 252 
 253         trace_musb_readb(__builtin_return_address(0), addr, offset, data);
 254         return data;
 255 }
 256 
 257 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
 258 {
 259         trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
 260         __raw_writeb(data, addr + offset);
 261 }
 262 
 263 static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
 264 {
 265         u16 data = __raw_readw(addr + offset);
 266 
 267         trace_musb_readw(__builtin_return_address(0), addr, offset, data);
 268         return data;
 269 }
 270 
 271 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
 272 {
 273         trace_musb_writew(__builtin_return_address(0), addr, offset, data);
 274         __raw_writew(data, addr + offset);
 275 }
 276 
 277 /*
 278  * Load an endpoint's FIFO
 279  */
 280 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
 281                                     const u8 *src)
 282 {
 283         struct musb *musb = hw_ep->musb;
 284         void __iomem *fifo = hw_ep->fifo;
 285 
 286         if (unlikely(len == 0))
 287                 return;
 288 
 289         prefetch((u8 *)src);
 290 
 291         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
 292                         'T', hw_ep->epnum, fifo, len, src);
 293 
 294         /* we can't assume unaligned reads work */
 295         if (likely((0x01 & (unsigned long) src) == 0)) {
 296                 u16     index = 0;
 297 
 298                 /* best case is 32bit-aligned source address */
 299                 if ((0x02 & (unsigned long) src) == 0) {
 300                         if (len >= 4) {
 301                                 iowrite32_rep(fifo, src + index, len >> 2);
 302                                 index += len & ~0x03;
 303                         }
 304                         if (len & 0x02) {
 305                                 __raw_writew(*(u16 *)&src[index], fifo);
 306                                 index += 2;
 307                         }
 308                 } else {
 309                         if (len >= 2) {
 310                                 iowrite16_rep(fifo, src + index, len >> 1);
 311                                 index += len & ~0x01;
 312                         }
 313                 }
 314                 if (len & 0x01)
 315                         __raw_writeb(src[index], fifo);
 316         } else  {
 317                 /* byte aligned */
 318                 iowrite8_rep(fifo, src, len);
 319         }
 320 }
 321 
 322 /*
 323  * Unload an endpoint's FIFO
 324  */
 325 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
 326 {
 327         struct musb *musb = hw_ep->musb;
 328         void __iomem *fifo = hw_ep->fifo;
 329 
 330         if (unlikely(len == 0))
 331                 return;
 332 
 333         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
 334                         'R', hw_ep->epnum, fifo, len, dst);
 335 
 336         /* we can't assume unaligned writes work */
 337         if (likely((0x01 & (unsigned long) dst) == 0)) {
 338                 u16     index = 0;
 339 
 340                 /* best case is 32bit-aligned destination address */
 341                 if ((0x02 & (unsigned long) dst) == 0) {
 342                         if (len >= 4) {
 343                                 ioread32_rep(fifo, dst, len >> 2);
 344                                 index = len & ~0x03;
 345                         }
 346                         if (len & 0x02) {
 347                                 *(u16 *)&dst[index] = __raw_readw(fifo);
 348                                 index += 2;
 349                         }
 350                 } else {
 351                         if (len >= 2) {
 352                                 ioread16_rep(fifo, dst, len >> 1);
 353                                 index = len & ~0x01;
 354                         }
 355                 }
 356                 if (len & 0x01)
 357                         dst[index] = __raw_readb(fifo);
 358         } else  {
 359                 /* byte aligned */
 360                 ioread8_rep(fifo, dst, len);
 361         }
 362 }
 363 
 364 /*
 365  * Old style IO functions
 366  */
 367 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
 368 EXPORT_SYMBOL_GPL(musb_readb);
 369 
 370 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
 371 EXPORT_SYMBOL_GPL(musb_writeb);
 372 
 373 u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
 374 EXPORT_SYMBOL_GPL(musb_readw);
 375 
 376 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
 377 EXPORT_SYMBOL_GPL(musb_writew);
 378 
 379 u32 musb_readl(const void __iomem *addr, unsigned offset)
 380 {
 381         u32 data = __raw_readl(addr + offset);
 382 
 383         trace_musb_readl(__builtin_return_address(0), addr, offset, data);
 384         return data;
 385 }
 386 EXPORT_SYMBOL_GPL(musb_readl);
 387 
 388 void musb_writel(void __iomem *addr, unsigned offset, u32 data)
 389 {
 390         trace_musb_writel(__builtin_return_address(0), addr, offset, data);
 391         __raw_writel(data, addr + offset);
 392 }
 393 EXPORT_SYMBOL_GPL(musb_writel);
 394 
 395 #ifndef CONFIG_MUSB_PIO_ONLY
 396 struct dma_controller *
 397 (*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
 398 EXPORT_SYMBOL(musb_dma_controller_create);
 399 
 400 void (*musb_dma_controller_destroy)(struct dma_controller *c);
 401 EXPORT_SYMBOL(musb_dma_controller_destroy);
 402 #endif
 403 
 404 /*
 405  * New style IO functions
 406  */
 407 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
 408 {
 409         return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
 410 }
 411 
 412 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
 413 {
 414         return hw_ep->musb->io.write_fifo(hw_ep, len, src);
 415 }
 416 
 417 /*-------------------------------------------------------------------------*/
 418 
 419 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
 420 static const u8 musb_test_packet[53] = {
 421         /* implicit SYNC then DATA0 to start */
 422 
 423         /* JKJKJKJK x9 */
 424         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 425         /* JJKKJJKK x8 */
 426         0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
 427         /* JJJJKKKK x8 */
 428         0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
 429         /* JJJJJJJKKKKKKK x8 */
 430         0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 431         /* JJJJJJJK x8 */
 432         0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
 433         /* JKKKKKKK x10, JK */
 434         0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
 435 
 436         /* implicit CRC16 then EOP to end */
 437 };
 438 
 439 void musb_load_testpacket(struct musb *musb)
 440 {
 441         void __iomem    *regs = musb->endpoints[0].regs;
 442 
 443         musb_ep_select(musb->mregs, 0);
 444         musb_write_fifo(musb->control_ep,
 445                         sizeof(musb_test_packet), musb_test_packet);
 446         musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
 447 }
 448 
 449 /*-------------------------------------------------------------------------*/
 450 
 451 /*
 452  * Handles OTG hnp timeouts, such as b_ase0_brst
 453  */
 454 static void musb_otg_timer_func(struct timer_list *t)
 455 {
 456         struct musb     *musb = from_timer(musb, t, otg_timer);
 457         unsigned long   flags;
 458 
 459         spin_lock_irqsave(&musb->lock, flags);
 460         switch (musb->xceiv->otg->state) {
 461         case OTG_STATE_B_WAIT_ACON:
 462                 musb_dbg(musb,
 463                         "HNP: b_wait_acon timeout; back to b_peripheral");
 464                 musb_g_disconnect(musb);
 465                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
 466                 musb->is_active = 0;
 467                 break;
 468         case OTG_STATE_A_SUSPEND:
 469         case OTG_STATE_A_WAIT_BCON:
 470                 musb_dbg(musb, "HNP: %s timeout",
 471                         usb_otg_state_string(musb->xceiv->otg->state));
 472                 musb_platform_set_vbus(musb, 0);
 473                 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
 474                 break;
 475         default:
 476                 musb_dbg(musb, "HNP: Unhandled mode %s",
 477                         usb_otg_state_string(musb->xceiv->otg->state));
 478         }
 479         spin_unlock_irqrestore(&musb->lock, flags);
 480 }
 481 
 482 /*
 483  * Stops the HNP transition. Caller must take care of locking.
 484  */
 485 void musb_hnp_stop(struct musb *musb)
 486 {
 487         struct usb_hcd  *hcd = musb->hcd;
 488         void __iomem    *mbase = musb->mregs;
 489         u8      reg;
 490 
 491         musb_dbg(musb, "HNP: stop from %s",
 492                         usb_otg_state_string(musb->xceiv->otg->state));
 493 
 494         switch (musb->xceiv->otg->state) {
 495         case OTG_STATE_A_PERIPHERAL:
 496                 musb_g_disconnect(musb);
 497                 musb_dbg(musb, "HNP: back to %s",
 498                         usb_otg_state_string(musb->xceiv->otg->state));
 499                 break;
 500         case OTG_STATE_B_HOST:
 501                 musb_dbg(musb, "HNP: Disabling HR");
 502                 if (hcd)
 503                         hcd->self.is_b_host = 0;
 504                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
 505                 MUSB_DEV_MODE(musb);
 506                 reg = musb_readb(mbase, MUSB_POWER);
 507                 reg |= MUSB_POWER_SUSPENDM;
 508                 musb_writeb(mbase, MUSB_POWER, reg);
 509                 /* REVISIT: Start SESSION_REQUEST here? */
 510                 break;
 511         default:
 512                 musb_dbg(musb, "HNP: Stopping in unknown state %s",
 513                         usb_otg_state_string(musb->xceiv->otg->state));
 514         }
 515 
 516         /*
 517          * When returning to A state after HNP, avoid hub_port_rebounce(),
 518          * which cause occasional OPT A "Did not receive reset after connect"
 519          * errors.
 520          */
 521         musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
 522 }
 523 
 524 static void musb_recover_from_babble(struct musb *musb);
 525 
 526 static void musb_handle_intr_resume(struct musb *musb, u8 devctl)
 527 {
 528         musb_dbg(musb, "RESUME (%s)",
 529                         usb_otg_state_string(musb->xceiv->otg->state));
 530 
 531         if (devctl & MUSB_DEVCTL_HM) {
 532                 switch (musb->xceiv->otg->state) {
 533                 case OTG_STATE_A_SUSPEND:
 534                         /* remote wakeup? */
 535                         musb->port1_status |=
 536                                         (USB_PORT_STAT_C_SUSPEND << 16)
 537                                         | MUSB_PORT_STAT_RESUME;
 538                         musb->rh_timer = jiffies
 539                                 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
 540                         musb->xceiv->otg->state = OTG_STATE_A_HOST;
 541                         musb->is_active = 1;
 542                         musb_host_resume_root_hub(musb);
 543                         schedule_delayed_work(&musb->finish_resume_work,
 544                                 msecs_to_jiffies(USB_RESUME_TIMEOUT));
 545                         break;
 546                 case OTG_STATE_B_WAIT_ACON:
 547                         musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
 548                         musb->is_active = 1;
 549                         MUSB_DEV_MODE(musb);
 550                         break;
 551                 default:
 552                         WARNING("bogus %s RESUME (%s)\n",
 553                                 "host",
 554                                 usb_otg_state_string(musb->xceiv->otg->state));
 555                 }
 556         } else {
 557                 switch (musb->xceiv->otg->state) {
 558                 case OTG_STATE_A_SUSPEND:
 559                         /* possibly DISCONNECT is upcoming */
 560                         musb->xceiv->otg->state = OTG_STATE_A_HOST;
 561                         musb_host_resume_root_hub(musb);
 562                         break;
 563                 case OTG_STATE_B_WAIT_ACON:
 564                 case OTG_STATE_B_PERIPHERAL:
 565                         /* disconnect while suspended?  we may
 566                          * not get a disconnect irq...
 567                          */
 568                         if ((devctl & MUSB_DEVCTL_VBUS)
 569                                         != (3 << MUSB_DEVCTL_VBUS_SHIFT)
 570                                         ) {
 571                                 musb->int_usb |= MUSB_INTR_DISCONNECT;
 572                                 musb->int_usb &= ~MUSB_INTR_SUSPEND;
 573                                 break;
 574                         }
 575                         musb_g_resume(musb);
 576                         break;
 577                 case OTG_STATE_B_IDLE:
 578                         musb->int_usb &= ~MUSB_INTR_SUSPEND;
 579                         break;
 580                 default:
 581                         WARNING("bogus %s RESUME (%s)\n",
 582                                 "peripheral",
 583                                 usb_otg_state_string(musb->xceiv->otg->state));
 584                 }
 585         }
 586 }
 587 
 588 /* return IRQ_HANDLED to tell the caller to return immediately */
 589 static irqreturn_t musb_handle_intr_sessreq(struct musb *musb, u8 devctl)
 590 {
 591         void __iomem *mbase = musb->mregs;
 592 
 593         if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
 594                         && (devctl & MUSB_DEVCTL_BDEVICE)) {
 595                 musb_dbg(musb, "SessReq while on B state");
 596                 return IRQ_HANDLED;
 597         }
 598 
 599         musb_dbg(musb, "SESSION_REQUEST (%s)",
 600                 usb_otg_state_string(musb->xceiv->otg->state));
 601 
 602         /* IRQ arrives from ID pin sense or (later, if VBUS power
 603          * is removed) SRP.  responses are time critical:
 604          *  - turn on VBUS (with silicon-specific mechanism)
 605          *  - go through A_WAIT_VRISE
 606          *  - ... to A_WAIT_BCON.
 607          * a_wait_vrise_tmout triggers VBUS_ERROR transitions
 608          */
 609         musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
 610         musb->ep0_stage = MUSB_EP0_START;
 611         musb->xceiv->otg->state = OTG_STATE_A_IDLE;
 612         MUSB_HST_MODE(musb);
 613         musb_platform_set_vbus(musb, 1);
 614 
 615         return IRQ_NONE;
 616 }
 617 
 618 static void musb_handle_intr_vbuserr(struct musb *musb, u8 devctl)
 619 {
 620         int     ignore = 0;
 621 
 622         /* During connection as an A-Device, we may see a short
 623          * current spikes causing voltage drop, because of cable
 624          * and peripheral capacitance combined with vbus draw.
 625          * (So: less common with truly self-powered devices, where
 626          * vbus doesn't act like a power supply.)
 627          *
 628          * Such spikes are short; usually less than ~500 usec, max
 629          * of ~2 msec.  That is, they're not sustained overcurrent
 630          * errors, though they're reported using VBUSERROR irqs.
 631          *
 632          * Workarounds:  (a) hardware: use self powered devices.
 633          * (b) software:  ignore non-repeated VBUS errors.
 634          *
 635          * REVISIT:  do delays from lots of DEBUG_KERNEL checks
 636          * make trouble here, keeping VBUS < 4.4V ?
 637          */
 638         switch (musb->xceiv->otg->state) {
 639         case OTG_STATE_A_HOST:
 640                 /* recovery is dicey once we've gotten past the
 641                  * initial stages of enumeration, but if VBUS
 642                  * stayed ok at the other end of the link, and
 643                  * another reset is due (at least for high speed,
 644                  * to redo the chirp etc), it might work OK...
 645                  */
 646         case OTG_STATE_A_WAIT_BCON:
 647         case OTG_STATE_A_WAIT_VRISE:
 648                 if (musb->vbuserr_retry) {
 649                         void __iomem *mbase = musb->mregs;
 650 
 651                         musb->vbuserr_retry--;
 652                         ignore = 1;
 653                         devctl |= MUSB_DEVCTL_SESSION;
 654                         musb_writeb(mbase, MUSB_DEVCTL, devctl);
 655                 } else {
 656                         musb->port1_status |=
 657                                   USB_PORT_STAT_OVERCURRENT
 658                                 | (USB_PORT_STAT_C_OVERCURRENT << 16);
 659                 }
 660                 break;
 661         default:
 662                 break;
 663         }
 664 
 665         dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
 666                         "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
 667                         usb_otg_state_string(musb->xceiv->otg->state),
 668                         devctl,
 669                         ({ char *s;
 670                         switch (devctl & MUSB_DEVCTL_VBUS) {
 671                         case 0 << MUSB_DEVCTL_VBUS_SHIFT:
 672                                 s = "<SessEnd"; break;
 673                         case 1 << MUSB_DEVCTL_VBUS_SHIFT:
 674                                 s = "<AValid"; break;
 675                         case 2 << MUSB_DEVCTL_VBUS_SHIFT:
 676                                 s = "<VBusValid"; break;
 677                         /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
 678                         default:
 679                                 s = "VALID"; break;
 680                         } s; }),
 681                         VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
 682                         musb->port1_status);
 683 
 684         /* go through A_WAIT_VFALL then start a new session */
 685         if (!ignore)
 686                 musb_platform_set_vbus(musb, 0);
 687 }
 688 
 689 static void musb_handle_intr_suspend(struct musb *musb, u8 devctl)
 690 {
 691         musb_dbg(musb, "SUSPEND (%s) devctl %02x",
 692                 usb_otg_state_string(musb->xceiv->otg->state), devctl);
 693 
 694         switch (musb->xceiv->otg->state) {
 695         case OTG_STATE_A_PERIPHERAL:
 696                 /* We also come here if the cable is removed, since
 697                  * this silicon doesn't report ID-no-longer-grounded.
 698                  *
 699                  * We depend on T(a_wait_bcon) to shut us down, and
 700                  * hope users don't do anything dicey during this
 701                  * undesired detour through A_WAIT_BCON.
 702                  */
 703                 musb_hnp_stop(musb);
 704                 musb_host_resume_root_hub(musb);
 705                 musb_root_disconnect(musb);
 706                 musb_platform_try_idle(musb, jiffies
 707                                 + msecs_to_jiffies(musb->a_wait_bcon
 708                                         ? : OTG_TIME_A_WAIT_BCON));
 709 
 710                 break;
 711         case OTG_STATE_B_IDLE:
 712                 if (!musb->is_active)
 713                         break;
 714                 /* fall through */
 715         case OTG_STATE_B_PERIPHERAL:
 716                 musb_g_suspend(musb);
 717                 musb->is_active = musb->g.b_hnp_enable;
 718                 if (musb->is_active) {
 719                         musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
 720                         musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
 721                         mod_timer(&musb->otg_timer, jiffies
 722                                 + msecs_to_jiffies(
 723                                                 OTG_TIME_B_ASE0_BRST));
 724                 }
 725                 break;
 726         case OTG_STATE_A_WAIT_BCON:
 727                 if (musb->a_wait_bcon != 0)
 728                         musb_platform_try_idle(musb, jiffies
 729                                 + msecs_to_jiffies(musb->a_wait_bcon));
 730                 break;
 731         case OTG_STATE_A_HOST:
 732                 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
 733                 musb->is_active = musb->hcd->self.b_hnp_enable;
 734                 break;
 735         case OTG_STATE_B_HOST:
 736                 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
 737                 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
 738                 break;
 739         default:
 740                 /* "should not happen" */
 741                 musb->is_active = 0;
 742                 break;
 743         }
 744 }
 745 
 746 static void musb_handle_intr_connect(struct musb *musb, u8 devctl, u8 int_usb)
 747 {
 748         struct usb_hcd *hcd = musb->hcd;
 749 
 750         musb->is_active = 1;
 751         musb->ep0_stage = MUSB_EP0_START;
 752 
 753         musb->intrtxe = musb->epmask;
 754         musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
 755         musb->intrrxe = musb->epmask & 0xfffe;
 756         musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
 757         musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
 758         musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
 759                                 |USB_PORT_STAT_HIGH_SPEED
 760                                 |USB_PORT_STAT_ENABLE
 761                                 );
 762         musb->port1_status |= USB_PORT_STAT_CONNECTION
 763                                 |(USB_PORT_STAT_C_CONNECTION << 16);
 764 
 765         /* high vs full speed is just a guess until after reset */
 766         if (devctl & MUSB_DEVCTL_LSDEV)
 767                 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
 768 
 769         /* indicate new connection to OTG machine */
 770         switch (musb->xceiv->otg->state) {
 771         case OTG_STATE_B_PERIPHERAL:
 772                 if (int_usb & MUSB_INTR_SUSPEND) {
 773                         musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
 774                         int_usb &= ~MUSB_INTR_SUSPEND;
 775                         goto b_host;
 776                 } else
 777                         musb_dbg(musb, "CONNECT as b_peripheral???");
 778                 break;
 779         case OTG_STATE_B_WAIT_ACON:
 780                 musb_dbg(musb, "HNP: CONNECT, now b_host");
 781 b_host:
 782                 musb->xceiv->otg->state = OTG_STATE_B_HOST;
 783                 if (musb->hcd)
 784                         musb->hcd->self.is_b_host = 1;
 785                 del_timer(&musb->otg_timer);
 786                 break;
 787         default:
 788                 if ((devctl & MUSB_DEVCTL_VBUS)
 789                                 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
 790                         musb->xceiv->otg->state = OTG_STATE_A_HOST;
 791                         if (hcd)
 792                                 hcd->self.is_b_host = 0;
 793                 }
 794                 break;
 795         }
 796 
 797         musb_host_poke_root_hub(musb);
 798 
 799         musb_dbg(musb, "CONNECT (%s) devctl %02x",
 800                         usb_otg_state_string(musb->xceiv->otg->state), devctl);
 801 }
 802 
 803 static void musb_handle_intr_disconnect(struct musb *musb, u8 devctl)
 804 {
 805         musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
 806                         usb_otg_state_string(musb->xceiv->otg->state),
 807                         MUSB_MODE(musb), devctl);
 808 
 809         switch (musb->xceiv->otg->state) {
 810         case OTG_STATE_A_HOST:
 811         case OTG_STATE_A_SUSPEND:
 812                 musb_host_resume_root_hub(musb);
 813                 musb_root_disconnect(musb);
 814                 if (musb->a_wait_bcon != 0)
 815                         musb_platform_try_idle(musb, jiffies
 816                                 + msecs_to_jiffies(musb->a_wait_bcon));
 817                 break;
 818         case OTG_STATE_B_HOST:
 819                 /* REVISIT this behaves for "real disconnect"
 820                  * cases; make sure the other transitions from
 821                  * from B_HOST act right too.  The B_HOST code
 822                  * in hnp_stop() is currently not used...
 823                  */
 824                 musb_root_disconnect(musb);
 825                 if (musb->hcd)
 826                         musb->hcd->self.is_b_host = 0;
 827                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
 828                 MUSB_DEV_MODE(musb);
 829                 musb_g_disconnect(musb);
 830                 break;
 831         case OTG_STATE_A_PERIPHERAL:
 832                 musb_hnp_stop(musb);
 833                 musb_root_disconnect(musb);
 834                 /* FALLTHROUGH */
 835         case OTG_STATE_B_WAIT_ACON:
 836                 /* FALLTHROUGH */
 837         case OTG_STATE_B_PERIPHERAL:
 838         case OTG_STATE_B_IDLE:
 839                 musb_g_disconnect(musb);
 840                 break;
 841         default:
 842                 WARNING("unhandled DISCONNECT transition (%s)\n",
 843                         usb_otg_state_string(musb->xceiv->otg->state));
 844                 break;
 845         }
 846 }
 847 
 848 /*
 849  * mentor saves a bit: bus reset and babble share the same irq.
 850  * only host sees babble; only peripheral sees bus reset.
 851  */
 852 static void musb_handle_intr_reset(struct musb *musb)
 853 {
 854         if (is_host_active(musb)) {
 855                 /*
 856                  * When BABBLE happens what we can depends on which
 857                  * platform MUSB is running, because some platforms
 858                  * implemented proprietary means for 'recovering' from
 859                  * Babble conditions. One such platform is AM335x. In
 860                  * most cases, however, the only thing we can do is
 861                  * drop the session.
 862                  */
 863                 dev_err(musb->controller, "Babble\n");
 864                 musb_recover_from_babble(musb);
 865         } else {
 866                 musb_dbg(musb, "BUS RESET as %s",
 867                         usb_otg_state_string(musb->xceiv->otg->state));
 868                 switch (musb->xceiv->otg->state) {
 869                 case OTG_STATE_A_SUSPEND:
 870                         musb_g_reset(musb);
 871                         /* FALLTHROUGH */
 872                 case OTG_STATE_A_WAIT_BCON:     /* OPT TD.4.7-900ms */
 873                         /* never use invalid T(a_wait_bcon) */
 874                         musb_dbg(musb, "HNP: in %s, %d msec timeout",
 875                                 usb_otg_state_string(musb->xceiv->otg->state),
 876                                 TA_WAIT_BCON(musb));
 877                         mod_timer(&musb->otg_timer, jiffies
 878                                 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
 879                         break;
 880                 case OTG_STATE_A_PERIPHERAL:
 881                         del_timer(&musb->otg_timer);
 882                         musb_g_reset(musb);
 883                         break;
 884                 case OTG_STATE_B_WAIT_ACON:
 885                         musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
 886                                 usb_otg_state_string(musb->xceiv->otg->state));
 887                         musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
 888                         musb_g_reset(musb);
 889                         break;
 890                 case OTG_STATE_B_IDLE:
 891                         musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
 892                         /* FALLTHROUGH */
 893                 case OTG_STATE_B_PERIPHERAL:
 894                         musb_g_reset(musb);
 895                         break;
 896                 default:
 897                         musb_dbg(musb, "Unhandled BUS RESET as %s",
 898                                 usb_otg_state_string(musb->xceiv->otg->state));
 899                 }
 900         }
 901 }
 902 
 903 /*
 904  * Interrupt Service Routine to record USB "global" interrupts.
 905  * Since these do not happen often and signify things of
 906  * paramount importance, it seems OK to check them individually;
 907  * the order of the tests is specified in the manual
 908  *
 909  * @param musb instance pointer
 910  * @param int_usb register contents
 911  * @param devctl
 912  * @param power
 913  */
 914 
 915 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
 916                                 u8 devctl)
 917 {
 918         irqreturn_t handled = IRQ_NONE;
 919 
 920         musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
 921 
 922         /* in host mode, the peripheral may issue remote wakeup.
 923          * in peripheral mode, the host may resume the link.
 924          * spurious RESUME irqs happen too, paired with SUSPEND.
 925          */
 926         if (int_usb & MUSB_INTR_RESUME) {
 927                 musb_handle_intr_resume(musb, devctl);
 928                 handled = IRQ_HANDLED;
 929         }
 930 
 931         /* see manual for the order of the tests */
 932         if (int_usb & MUSB_INTR_SESSREQ) {
 933                 if (musb_handle_intr_sessreq(musb, devctl))
 934                         return IRQ_HANDLED;
 935                 handled = IRQ_HANDLED;
 936         }
 937 
 938         if (int_usb & MUSB_INTR_VBUSERROR) {
 939                 musb_handle_intr_vbuserr(musb, devctl);
 940                 handled = IRQ_HANDLED;
 941         }
 942 
 943         if (int_usb & MUSB_INTR_SUSPEND) {
 944                 musb_handle_intr_suspend(musb, devctl);
 945                 handled = IRQ_HANDLED;
 946         }
 947 
 948         if (int_usb & MUSB_INTR_CONNECT) {
 949                 musb_handle_intr_connect(musb, devctl, int_usb);
 950                 handled = IRQ_HANDLED;
 951         }
 952 
 953         if (int_usb & MUSB_INTR_DISCONNECT) {
 954                 musb_handle_intr_disconnect(musb, devctl);
 955                 handled = IRQ_HANDLED;
 956         }
 957 
 958         if (int_usb & MUSB_INTR_RESET) {
 959                 musb_handle_intr_reset(musb);
 960                 handled = IRQ_HANDLED;
 961         }
 962 
 963 #if 0
 964 /* REVISIT ... this would be for multiplexing periodic endpoints, or
 965  * supporting transfer phasing to prevent exceeding ISO bandwidth
 966  * limits of a given frame or microframe.
 967  *
 968  * It's not needed for peripheral side, which dedicates endpoints;
 969  * though it _might_ use SOF irqs for other purposes.
 970  *
 971  * And it's not currently needed for host side, which also dedicates
 972  * endpoints, relies on TX/RX interval registers, and isn't claimed
 973  * to support ISO transfers yet.
 974  */
 975         if (int_usb & MUSB_INTR_SOF) {
 976                 void __iomem *mbase = musb->mregs;
 977                 struct musb_hw_ep       *ep;
 978                 u8 epnum;
 979                 u16 frame;
 980 
 981                 dev_dbg(musb->controller, "START_OF_FRAME\n");
 982                 handled = IRQ_HANDLED;
 983 
 984                 /* start any periodic Tx transfers waiting for current frame */
 985                 frame = musb_readw(mbase, MUSB_FRAME);
 986                 ep = musb->endpoints;
 987                 for (epnum = 1; (epnum < musb->nr_endpoints)
 988                                         && (musb->epmask >= (1 << epnum));
 989                                 epnum++, ep++) {
 990                         /*
 991                          * FIXME handle framecounter wraps (12 bits)
 992                          * eliminate duplicated StartUrb logic
 993                          */
 994                         if (ep->dwWaitFrame >= frame) {
 995                                 ep->dwWaitFrame = 0;
 996                                 pr_debug("SOF --> periodic TX%s on %d\n",
 997                                         ep->tx_channel ? " DMA" : "",
 998                                         epnum);
 999                                 if (!ep->tx_channel)
1000                                         musb_h_tx_start(musb, epnum);
1001                                 else
1002                                         cppi_hostdma_start(musb, epnum);
1003                         }
1004                 }               /* end of for loop */
1005         }
1006 #endif
1007 
1008         schedule_delayed_work(&musb->irq_work, 0);
1009 
1010         return handled;
1011 }
1012 
1013 /*-------------------------------------------------------------------------*/
1014 
1015 static void musb_disable_interrupts(struct musb *musb)
1016 {
1017         void __iomem    *mbase = musb->mregs;
1018         u16     temp;
1019 
1020         /* disable interrupts */
1021         musb_writeb(mbase, MUSB_INTRUSBE, 0);
1022         musb->intrtxe = 0;
1023         musb_writew(mbase, MUSB_INTRTXE, 0);
1024         musb->intrrxe = 0;
1025         musb_writew(mbase, MUSB_INTRRXE, 0);
1026 
1027         /*  flush pending interrupts */
1028         temp = musb_readb(mbase, MUSB_INTRUSB);
1029         temp = musb_readw(mbase, MUSB_INTRTX);
1030         temp = musb_readw(mbase, MUSB_INTRRX);
1031 }
1032 
1033 static void musb_enable_interrupts(struct musb *musb)
1034 {
1035         void __iomem    *regs = musb->mregs;
1036 
1037         /*  Set INT enable registers, enable interrupts */
1038         musb->intrtxe = musb->epmask;
1039         musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1040         musb->intrrxe = musb->epmask & 0xfffe;
1041         musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1042         musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1043 
1044 }
1045 
1046 /*
1047  * Program the HDRC to start (enable interrupts, dma, etc.).
1048  */
1049 void musb_start(struct musb *musb)
1050 {
1051         void __iomem    *regs = musb->mregs;
1052         u8              devctl = musb_readb(regs, MUSB_DEVCTL);
1053         u8              power;
1054 
1055         musb_dbg(musb, "<== devctl %02x", devctl);
1056 
1057         musb_enable_interrupts(musb);
1058         musb_writeb(regs, MUSB_TESTMODE, 0);
1059 
1060         power = MUSB_POWER_ISOUPDATE;
1061         /*
1062          * treating UNKNOWN as unspecified maximum speed, in which case
1063          * we will default to high-speed.
1064          */
1065         if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1066                         musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1067                 power |= MUSB_POWER_HSENAB;
1068         musb_writeb(regs, MUSB_POWER, power);
1069 
1070         musb->is_active = 0;
1071         devctl = musb_readb(regs, MUSB_DEVCTL);
1072         devctl &= ~MUSB_DEVCTL_SESSION;
1073 
1074         /* session started after:
1075          * (a) ID-grounded irq, host mode;
1076          * (b) vbus present/connect IRQ, peripheral mode;
1077          * (c) peripheral initiates, using SRP
1078          */
1079         if (musb->port_mode != MUSB_HOST &&
1080                         musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
1081                         (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1082                 musb->is_active = 1;
1083         } else {
1084                 devctl |= MUSB_DEVCTL_SESSION;
1085         }
1086 
1087         musb_platform_enable(musb);
1088         musb_writeb(regs, MUSB_DEVCTL, devctl);
1089 }
1090 
1091 /*
1092  * Make the HDRC stop (disable interrupts, etc.);
1093  * reversible by musb_start
1094  * called on gadget driver unregister
1095  * with controller locked, irqs blocked
1096  * acts as a NOP unless some role activated the hardware
1097  */
1098 void musb_stop(struct musb *musb)
1099 {
1100         /* stop IRQs, timers, ... */
1101         musb_platform_disable(musb);
1102         musb_disable_interrupts(musb);
1103         musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1104 
1105         /* FIXME
1106          *  - mark host and/or peripheral drivers unusable/inactive
1107          *  - disable DMA (and enable it in HdrcStart)
1108          *  - make sure we can musb_start() after musb_stop(); with
1109          *    OTG mode, gadget driver module rmmod/modprobe cycles that
1110          *  - ...
1111          */
1112         musb_platform_try_idle(musb, 0);
1113 }
1114 
1115 /*-------------------------------------------------------------------------*/
1116 
1117 /*
1118  * The silicon either has hard-wired endpoint configurations, or else
1119  * "dynamic fifo" sizing.  The driver has support for both, though at this
1120  * writing only the dynamic sizing is very well tested.   Since we switched
1121  * away from compile-time hardware parameters, we can no longer rely on
1122  * dead code elimination to leave only the relevant one in the object file.
1123  *
1124  * We don't currently use dynamic fifo setup capability to do anything
1125  * more than selecting one of a bunch of predefined configurations.
1126  */
1127 static ushort fifo_mode;
1128 
1129 /* "modprobe ... fifo_mode=1" etc */
1130 module_param(fifo_mode, ushort, 0);
1131 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1132 
1133 /*
1134  * tables defining fifo_mode values.  define more if you like.
1135  * for host side, make sure both halves of ep1 are set up.
1136  */
1137 
1138 /* mode 0 - fits in 2KB */
1139 static struct musb_fifo_cfg mode_0_cfg[] = {
1140 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1141 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1142 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1143 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1144 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1145 };
1146 
1147 /* mode 1 - fits in 4KB */
1148 static struct musb_fifo_cfg mode_1_cfg[] = {
1149 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1150 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1151 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1152 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1153 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1154 };
1155 
1156 /* mode 2 - fits in 4KB */
1157 static struct musb_fifo_cfg mode_2_cfg[] = {
1158 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1159 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1160 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1161 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1162 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 960, },
1163 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 1024, },
1164 };
1165 
1166 /* mode 3 - fits in 4KB */
1167 static struct musb_fifo_cfg mode_3_cfg[] = {
1168 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1169 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1170 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1171 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1172 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1173 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1174 };
1175 
1176 /* mode 4 - fits in 16KB */
1177 static struct musb_fifo_cfg mode_4_cfg[] = {
1178 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1179 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1180 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1181 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1182 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1183 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1184 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1185 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1186 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1187 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1188 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 512, },
1189 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 512, },
1190 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 512, },
1191 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 512, },
1192 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 512, },
1193 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 512, },
1194 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 512, },
1195 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 512, },
1196 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
1197 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
1198 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
1199 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
1200 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
1201 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
1202 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1203 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1204 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1205 };
1206 
1207 /* mode 5 - fits in 8KB */
1208 static struct musb_fifo_cfg mode_5_cfg[] = {
1209 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1210 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1211 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1212 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1213 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1214 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1215 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1216 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1217 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1218 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1219 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 32, },
1220 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 32, },
1221 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 32, },
1222 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 32, },
1223 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 32, },
1224 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 32, },
1225 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 32, },
1226 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 32, },
1227 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 32, },
1228 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 32, },
1229 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 32, },
1230 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 32, },
1231 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 32, },
1232 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 32, },
1233 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1234 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1235 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1236 };
1237 
1238 /*
1239  * configure a fifo; for non-shared endpoints, this may be called
1240  * once for a tx fifo and once for an rx fifo.
1241  *
1242  * returns negative errno or offset for next fifo.
1243  */
1244 static int
1245 fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
1246                 const struct musb_fifo_cfg *cfg, u16 offset)
1247 {
1248         void __iomem    *mbase = musb->mregs;
1249         int     size = 0;
1250         u16     maxpacket = cfg->maxpacket;
1251         u16     c_off = offset >> 3;
1252         u8      c_size;
1253 
1254         /* expect hw_ep has already been zero-initialized */
1255 
1256         size = ffs(max(maxpacket, (u16) 8)) - 1;
1257         maxpacket = 1 << size;
1258 
1259         c_size = size - 3;
1260         if (cfg->mode == BUF_DOUBLE) {
1261                 if ((offset + (maxpacket << 1)) >
1262                                 (1 << (musb->config->ram_bits + 2)))
1263                         return -EMSGSIZE;
1264                 c_size |= MUSB_FIFOSZ_DPB;
1265         } else {
1266                 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1267                         return -EMSGSIZE;
1268         }
1269 
1270         /* configure the FIFO */
1271         musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1272 
1273         /* EP0 reserved endpoint for control, bidirectional;
1274          * EP1 reserved for bulk, two unidirectional halves.
1275          */
1276         if (hw_ep->epnum == 1)
1277                 musb->bulk_ep = hw_ep;
1278         /* REVISIT error check:  be sure ep0 can both rx and tx ... */
1279         switch (cfg->style) {
1280         case FIFO_TX:
1281                 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1282                 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1283                 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1284                 hw_ep->max_packet_sz_tx = maxpacket;
1285                 break;
1286         case FIFO_RX:
1287                 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1288                 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1289                 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1290                 hw_ep->max_packet_sz_rx = maxpacket;
1291                 break;
1292         case FIFO_RXTX:
1293                 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1294                 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1295                 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1296                 hw_ep->max_packet_sz_rx = maxpacket;
1297 
1298                 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1299                 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1300                 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1301                 hw_ep->max_packet_sz_tx = maxpacket;
1302 
1303                 hw_ep->is_shared_fifo = true;
1304                 break;
1305         }
1306 
1307         /* NOTE rx and tx endpoint irqs aren't managed separately,
1308          * which happens to be ok
1309          */
1310         musb->epmask |= (1 << hw_ep->epnum);
1311 
1312         return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1313 }
1314 
1315 static struct musb_fifo_cfg ep0_cfg = {
1316         .style = FIFO_RXTX, .maxpacket = 64,
1317 };
1318 
1319 static int ep_config_from_table(struct musb *musb)
1320 {
1321         const struct musb_fifo_cfg      *cfg;
1322         unsigned                i, n;
1323         int                     offset;
1324         struct musb_hw_ep       *hw_ep = musb->endpoints;
1325 
1326         if (musb->config->fifo_cfg) {
1327                 cfg = musb->config->fifo_cfg;
1328                 n = musb->config->fifo_cfg_size;
1329                 goto done;
1330         }
1331 
1332         switch (fifo_mode) {
1333         default:
1334                 fifo_mode = 0;
1335                 /* FALLTHROUGH */
1336         case 0:
1337                 cfg = mode_0_cfg;
1338                 n = ARRAY_SIZE(mode_0_cfg);
1339                 break;
1340         case 1:
1341                 cfg = mode_1_cfg;
1342                 n = ARRAY_SIZE(mode_1_cfg);
1343                 break;
1344         case 2:
1345                 cfg = mode_2_cfg;
1346                 n = ARRAY_SIZE(mode_2_cfg);
1347                 break;
1348         case 3:
1349                 cfg = mode_3_cfg;
1350                 n = ARRAY_SIZE(mode_3_cfg);
1351                 break;
1352         case 4:
1353                 cfg = mode_4_cfg;
1354                 n = ARRAY_SIZE(mode_4_cfg);
1355                 break;
1356         case 5:
1357                 cfg = mode_5_cfg;
1358                 n = ARRAY_SIZE(mode_5_cfg);
1359                 break;
1360         }
1361 
1362         pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1363 
1364 
1365 done:
1366         offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1367         /* assert(offset > 0) */
1368 
1369         /* NOTE:  for RTL versions >= 1.400 EPINFO and RAMINFO would
1370          * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1371          */
1372 
1373         for (i = 0; i < n; i++) {
1374                 u8      epn = cfg->hw_ep_num;
1375 
1376                 if (epn >= musb->config->num_eps) {
1377                         pr_debug("%s: invalid ep %d\n",
1378                                         musb_driver_name, epn);
1379                         return -EINVAL;
1380                 }
1381                 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1382                 if (offset < 0) {
1383                         pr_debug("%s: mem overrun, ep %d\n",
1384                                         musb_driver_name, epn);
1385                         return offset;
1386                 }
1387                 epn++;
1388                 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1389         }
1390 
1391         pr_debug("%s: %d/%d max ep, %d/%d memory\n",
1392                         musb_driver_name,
1393                         n + 1, musb->config->num_eps * 2 - 1,
1394                         offset, (1 << (musb->config->ram_bits + 2)));
1395 
1396         if (!musb->bulk_ep) {
1397                 pr_debug("%s: missing bulk\n", musb_driver_name);
1398                 return -EINVAL;
1399         }
1400 
1401         return 0;
1402 }
1403 
1404 
1405 /*
1406  * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1407  * @param musb the controller
1408  */
1409 static int ep_config_from_hw(struct musb *musb)
1410 {
1411         u8 epnum = 0;
1412         struct musb_hw_ep *hw_ep;
1413         void __iomem *mbase = musb->mregs;
1414         int ret = 0;
1415 
1416         musb_dbg(musb, "<== static silicon ep config");
1417 
1418         /* FIXME pick up ep0 maxpacket size */
1419 
1420         for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1421                 musb_ep_select(mbase, epnum);
1422                 hw_ep = musb->endpoints + epnum;
1423 
1424                 ret = musb_read_fifosize(musb, hw_ep, epnum);
1425                 if (ret < 0)
1426                         break;
1427 
1428                 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1429 
1430                 /* pick an RX/TX endpoint for bulk */
1431                 if (hw_ep->max_packet_sz_tx < 512
1432                                 || hw_ep->max_packet_sz_rx < 512)
1433                         continue;
1434 
1435                 /* REVISIT:  this algorithm is lazy, we should at least
1436                  * try to pick a double buffered endpoint.
1437                  */
1438                 if (musb->bulk_ep)
1439                         continue;
1440                 musb->bulk_ep = hw_ep;
1441         }
1442 
1443         if (!musb->bulk_ep) {
1444                 pr_debug("%s: missing bulk\n", musb_driver_name);
1445                 return -EINVAL;
1446         }
1447 
1448         return 0;
1449 }
1450 
1451 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1452 
1453 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1454  * configure endpoints, or take their config from silicon
1455  */
1456 static int musb_core_init(u16 musb_type, struct musb *musb)
1457 {
1458         u8 reg;
1459         char *type;
1460         char aInfo[90];
1461         void __iomem    *mbase = musb->mregs;
1462         int             status = 0;
1463         int             i;
1464 
1465         /* log core options (read using indexed model) */
1466         reg = musb_read_configdata(mbase);
1467 
1468         strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1469         if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1470                 strcat(aInfo, ", dyn FIFOs");
1471                 musb->dyn_fifo = true;
1472         }
1473         if (reg & MUSB_CONFIGDATA_MPRXE) {
1474                 strcat(aInfo, ", bulk combine");
1475                 musb->bulk_combine = true;
1476         }
1477         if (reg & MUSB_CONFIGDATA_MPTXE) {
1478                 strcat(aInfo, ", bulk split");
1479                 musb->bulk_split = true;
1480         }
1481         if (reg & MUSB_CONFIGDATA_HBRXE) {
1482                 strcat(aInfo, ", HB-ISO Rx");
1483                 musb->hb_iso_rx = true;
1484         }
1485         if (reg & MUSB_CONFIGDATA_HBTXE) {
1486                 strcat(aInfo, ", HB-ISO Tx");
1487                 musb->hb_iso_tx = true;
1488         }
1489         if (reg & MUSB_CONFIGDATA_SOFTCONE)
1490                 strcat(aInfo, ", SoftConn");
1491 
1492         pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1493 
1494         if (MUSB_CONTROLLER_MHDRC == musb_type) {
1495                 musb->is_multipoint = 1;
1496                 type = "M";
1497         } else {
1498                 musb->is_multipoint = 0;
1499                 type = "";
1500                 if (IS_ENABLED(CONFIG_USB) &&
1501                     !IS_ENABLED(CONFIG_USB_OTG_BLACKLIST_HUB)) {
1502                         pr_err("%s: kernel must blacklist external hubs\n",
1503                                musb_driver_name);
1504                 }
1505         }
1506 
1507         /* log release info */
1508         musb->hwvers = musb_readw(mbase, MUSB_HWVERS);
1509         pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
1510                  musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
1511                  MUSB_HWVERS_MINOR(musb->hwvers),
1512                  (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1513 
1514         /* configure ep0 */
1515         musb_configure_ep0(musb);
1516 
1517         /* discover endpoint configuration */
1518         musb->nr_endpoints = 1;
1519         musb->epmask = 1;
1520 
1521         if (musb->dyn_fifo)
1522                 status = ep_config_from_table(musb);
1523         else
1524                 status = ep_config_from_hw(musb);
1525 
1526         if (status < 0)
1527                 return status;
1528 
1529         /* finish init, and print endpoint config */
1530         for (i = 0; i < musb->nr_endpoints; i++) {
1531                 struct musb_hw_ep       *hw_ep = musb->endpoints + i;
1532 
1533                 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1534 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1535                 if (musb->ops->quirks & MUSB_IN_TUSB) {
1536                         hw_ep->fifo_async = musb->async + 0x400 +
1537                                 musb->io.fifo_offset(i);
1538                         hw_ep->fifo_sync = musb->sync + 0x400 +
1539                                 musb->io.fifo_offset(i);
1540                         hw_ep->fifo_sync_va =
1541                                 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1542 
1543                         if (i == 0)
1544                                 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1545                         else
1546                                 hw_ep->conf = mbase + 0x400 +
1547                                         (((i - 1) & 0xf) << 2);
1548                 }
1549 #endif
1550 
1551                 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1552                 hw_ep->rx_reinit = 1;
1553                 hw_ep->tx_reinit = 1;
1554 
1555                 if (hw_ep->max_packet_sz_tx) {
1556                         musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1557                                 musb_driver_name, i,
1558                                 hw_ep->is_shared_fifo ? "shared" : "tx",
1559                                 hw_ep->tx_double_buffered
1560                                         ? "doublebuffer, " : "",
1561                                 hw_ep->max_packet_sz_tx);
1562                 }
1563                 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1564                         musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1565                                 musb_driver_name, i,
1566                                 "rx",
1567                                 hw_ep->rx_double_buffered
1568                                         ? "doublebuffer, " : "",
1569                                 hw_ep->max_packet_sz_rx);
1570                 }
1571                 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1572                         musb_dbg(musb, "hw_ep %d not configured", i);
1573         }
1574 
1575         return 0;
1576 }
1577 
1578 /*-------------------------------------------------------------------------*/
1579 
1580 /*
1581  * handle all the irqs defined by the HDRC core. for now we expect:  other
1582  * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1583  * will be assigned, and the irq will already have been acked.
1584  *
1585  * called in irq context with spinlock held, irqs blocked
1586  */
1587 irqreturn_t musb_interrupt(struct musb *musb)
1588 {
1589         irqreturn_t     retval = IRQ_NONE;
1590         unsigned long   status;
1591         unsigned long   epnum;
1592         u8              devctl;
1593 
1594         if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1595                 return IRQ_NONE;
1596 
1597         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1598 
1599         trace_musb_isr(musb);
1600 
1601         /**
1602          * According to Mentor Graphics' documentation, flowchart on page 98,
1603          * IRQ should be handled as follows:
1604          *
1605          * . Resume IRQ
1606          * . Session Request IRQ
1607          * . VBUS Error IRQ
1608          * . Suspend IRQ
1609          * . Connect IRQ
1610          * . Disconnect IRQ
1611          * . Reset/Babble IRQ
1612          * . SOF IRQ (we're not using this one)
1613          * . Endpoint 0 IRQ
1614          * . TX Endpoints
1615          * . RX Endpoints
1616          *
1617          * We will be following that flowchart in order to avoid any problems
1618          * that might arise with internal Finite State Machine.
1619          */
1620 
1621         if (musb->int_usb)
1622                 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1623 
1624         if (musb->int_tx & 1) {
1625                 if (is_host_active(musb))
1626                         retval |= musb_h_ep0_irq(musb);
1627                 else
1628                         retval |= musb_g_ep0_irq(musb);
1629 
1630                 /* we have just handled endpoint 0 IRQ, clear it */
1631                 musb->int_tx &= ~BIT(0);
1632         }
1633 
1634         status = musb->int_tx;
1635 
1636         for_each_set_bit(epnum, &status, 16) {
1637                 retval = IRQ_HANDLED;
1638                 if (is_host_active(musb))
1639                         musb_host_tx(musb, epnum);
1640                 else
1641                         musb_g_tx(musb, epnum);
1642         }
1643 
1644         status = musb->int_rx;
1645 
1646         for_each_set_bit(epnum, &status, 16) {
1647                 retval = IRQ_HANDLED;
1648                 if (is_host_active(musb))
1649                         musb_host_rx(musb, epnum);
1650                 else
1651                         musb_g_rx(musb, epnum);
1652         }
1653 
1654         return retval;
1655 }
1656 EXPORT_SYMBOL_GPL(musb_interrupt);
1657 
1658 #ifndef CONFIG_MUSB_PIO_ONLY
1659 static bool use_dma = 1;
1660 
1661 /* "modprobe ... use_dma=0" etc */
1662 module_param(use_dma, bool, 0644);
1663 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1664 
1665 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1666 {
1667         /* called with controller lock already held */
1668 
1669         if (!epnum) {
1670                 if (!is_cppi_enabled(musb)) {
1671                         /* endpoint 0 */
1672                         if (is_host_active(musb))
1673                                 musb_h_ep0_irq(musb);
1674                         else
1675                                 musb_g_ep0_irq(musb);
1676                 }
1677         } else {
1678                 /* endpoints 1..15 */
1679                 if (transmit) {
1680                         if (is_host_active(musb))
1681                                 musb_host_tx(musb, epnum);
1682                         else
1683                                 musb_g_tx(musb, epnum);
1684                 } else {
1685                         /* receive */
1686                         if (is_host_active(musb))
1687                                 musb_host_rx(musb, epnum);
1688                         else
1689                                 musb_g_rx(musb, epnum);
1690                 }
1691         }
1692 }
1693 EXPORT_SYMBOL_GPL(musb_dma_completion);
1694 
1695 #else
1696 #define use_dma                 0
1697 #endif
1698 
1699 static int (*musb_phy_callback)(enum musb_vbus_id_status status);
1700 
1701 /*
1702  * musb_mailbox - optional phy notifier function
1703  * @status phy state change
1704  *
1705  * Optionally gets called from the USB PHY. Note that the USB PHY must be
1706  * disabled at the point the phy_callback is registered or unregistered.
1707  */
1708 int musb_mailbox(enum musb_vbus_id_status status)
1709 {
1710         if (musb_phy_callback)
1711                 return musb_phy_callback(status);
1712 
1713         return -ENODEV;
1714 };
1715 EXPORT_SYMBOL_GPL(musb_mailbox);
1716 
1717 /*-------------------------------------------------------------------------*/
1718 
1719 static ssize_t
1720 mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1721 {
1722         struct musb *musb = dev_to_musb(dev);
1723         unsigned long flags;
1724         int ret;
1725 
1726         spin_lock_irqsave(&musb->lock, flags);
1727         ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1728         spin_unlock_irqrestore(&musb->lock, flags);
1729 
1730         return ret;
1731 }
1732 
1733 static ssize_t
1734 mode_store(struct device *dev, struct device_attribute *attr,
1735                 const char *buf, size_t n)
1736 {
1737         struct musb     *musb = dev_to_musb(dev);
1738         unsigned long   flags;
1739         int             status;
1740 
1741         spin_lock_irqsave(&musb->lock, flags);
1742         if (sysfs_streq(buf, "host"))
1743                 status = musb_platform_set_mode(musb, MUSB_HOST);
1744         else if (sysfs_streq(buf, "peripheral"))
1745                 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1746         else if (sysfs_streq(buf, "otg"))
1747                 status = musb_platform_set_mode(musb, MUSB_OTG);
1748         else
1749                 status = -EINVAL;
1750         spin_unlock_irqrestore(&musb->lock, flags);
1751 
1752         return (status == 0) ? n : status;
1753 }
1754 static DEVICE_ATTR_RW(mode);
1755 
1756 static ssize_t
1757 vbus_store(struct device *dev, struct device_attribute *attr,
1758                 const char *buf, size_t n)
1759 {
1760         struct musb     *musb = dev_to_musb(dev);
1761         unsigned long   flags;
1762         unsigned long   val;
1763 
1764         if (sscanf(buf, "%lu", &val) < 1) {
1765                 dev_err(dev, "Invalid VBUS timeout ms value\n");
1766                 return -EINVAL;
1767         }
1768 
1769         spin_lock_irqsave(&musb->lock, flags);
1770         /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1771         musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1772         if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1773                 musb->is_active = 0;
1774         musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1775         spin_unlock_irqrestore(&musb->lock, flags);
1776 
1777         return n;
1778 }
1779 
1780 static ssize_t
1781 vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1782 {
1783         struct musb     *musb = dev_to_musb(dev);
1784         unsigned long   flags;
1785         unsigned long   val;
1786         int             vbus;
1787         u8              devctl;
1788 
1789         pm_runtime_get_sync(dev);
1790         spin_lock_irqsave(&musb->lock, flags);
1791         val = musb->a_wait_bcon;
1792         vbus = musb_platform_get_vbus_status(musb);
1793         if (vbus < 0) {
1794                 /* Use default MUSB method by means of DEVCTL register */
1795                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1796                 if ((devctl & MUSB_DEVCTL_VBUS)
1797                                 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1798                         vbus = 1;
1799                 else
1800                         vbus = 0;
1801         }
1802         spin_unlock_irqrestore(&musb->lock, flags);
1803         pm_runtime_put_sync(dev);
1804 
1805         return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1806                         vbus ? "on" : "off", val);
1807 }
1808 static DEVICE_ATTR_RW(vbus);
1809 
1810 /* Gadget drivers can't know that a host is connected so they might want
1811  * to start SRP, but users can.  This allows userspace to trigger SRP.
1812  */
1813 static ssize_t srp_store(struct device *dev, struct device_attribute *attr,
1814                 const char *buf, size_t n)
1815 {
1816         struct musb     *musb = dev_to_musb(dev);
1817         unsigned short  srp;
1818 
1819         if (sscanf(buf, "%hu", &srp) != 1
1820                         || (srp != 1)) {
1821                 dev_err(dev, "SRP: Value must be 1\n");
1822                 return -EINVAL;
1823         }
1824 
1825         if (srp == 1)
1826                 musb_g_wakeup(musb);
1827 
1828         return n;
1829 }
1830 static DEVICE_ATTR_WO(srp);
1831 
1832 static struct attribute *musb_attrs[] = {
1833         &dev_attr_mode.attr,
1834         &dev_attr_vbus.attr,
1835         &dev_attr_srp.attr,
1836         NULL
1837 };
1838 ATTRIBUTE_GROUPS(musb);
1839 
1840 #define MUSB_QUIRK_B_INVALID_VBUS_91    (MUSB_DEVCTL_BDEVICE | \
1841                                          (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
1842                                          MUSB_DEVCTL_SESSION)
1843 #define MUSB_QUIRK_B_DISCONNECT_99      (MUSB_DEVCTL_BDEVICE | \
1844                                          (3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1845                                          MUSB_DEVCTL_SESSION)
1846 #define MUSB_QUIRK_A_DISCONNECT_19      ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1847                                          MUSB_DEVCTL_SESSION)
1848 
1849 /*
1850  * Check the musb devctl session bit to determine if we want to
1851  * allow PM runtime for the device. In general, we want to keep things
1852  * active when the session bit is set except after host disconnect.
1853  *
1854  * Only called from musb_irq_work. If this ever needs to get called
1855  * elsewhere, proper locking must be implemented for musb->session.
1856  */
1857 static void musb_pm_runtime_check_session(struct musb *musb)
1858 {
1859         u8 devctl, s;
1860         int error;
1861 
1862         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1863 
1864         /* Handle session status quirks first */
1865         s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
1866                 MUSB_DEVCTL_HR;
1867         switch (devctl & ~s) {
1868         case MUSB_QUIRK_B_DISCONNECT_99:
1869                 musb_dbg(musb, "Poll devctl in case of suspend after disconnect\n");
1870                 schedule_delayed_work(&musb->irq_work,
1871                                       msecs_to_jiffies(1000));
1872                 break;
1873         case MUSB_QUIRK_B_INVALID_VBUS_91:
1874                 if (musb->quirk_retries && !musb->flush_irq_work) {
1875                         musb_dbg(musb,
1876                                  "Poll devctl on invalid vbus, assume no session");
1877                         schedule_delayed_work(&musb->irq_work,
1878                                               msecs_to_jiffies(1000));
1879                         musb->quirk_retries--;
1880                         return;
1881                 }
1882                 /* fall through */
1883         case MUSB_QUIRK_A_DISCONNECT_19:
1884                 if (musb->quirk_retries && !musb->flush_irq_work) {
1885                         musb_dbg(musb,
1886                                  "Poll devctl on possible host mode disconnect");
1887                         schedule_delayed_work(&musb->irq_work,
1888                                               msecs_to_jiffies(1000));
1889                         musb->quirk_retries--;
1890                         return;
1891                 }
1892                 if (!musb->session)
1893                         break;
1894                 musb_dbg(musb, "Allow PM on possible host mode disconnect");
1895                 pm_runtime_mark_last_busy(musb->controller);
1896                 pm_runtime_put_autosuspend(musb->controller);
1897                 musb->session = false;
1898                 return;
1899         default:
1900                 break;
1901         }
1902 
1903         /* No need to do anything if session has not changed */
1904         s = devctl & MUSB_DEVCTL_SESSION;
1905         if (s == musb->session)
1906                 return;
1907 
1908         /* Block PM or allow PM? */
1909         if (s) {
1910                 musb_dbg(musb, "Block PM on active session: %02x", devctl);
1911                 error = pm_runtime_get_sync(musb->controller);
1912                 if (error < 0)
1913                         dev_err(musb->controller, "Could not enable: %i\n",
1914                                 error);
1915                 musb->quirk_retries = 3;
1916         } else {
1917                 musb_dbg(musb, "Allow PM with no session: %02x", devctl);
1918                 pm_runtime_mark_last_busy(musb->controller);
1919                 pm_runtime_put_autosuspend(musb->controller);
1920         }
1921 
1922         musb->session = s;
1923 }
1924 
1925 /* Only used to provide driver mode change events */
1926 static void musb_irq_work(struct work_struct *data)
1927 {
1928         struct musb *musb = container_of(data, struct musb, irq_work.work);
1929         int error;
1930 
1931         error = pm_runtime_get_sync(musb->controller);
1932         if (error < 0) {
1933                 dev_err(musb->controller, "Could not enable: %i\n", error);
1934 
1935                 return;
1936         }
1937 
1938         musb_pm_runtime_check_session(musb);
1939 
1940         if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1941                 musb->xceiv_old_state = musb->xceiv->otg->state;
1942                 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1943         }
1944 
1945         pm_runtime_mark_last_busy(musb->controller);
1946         pm_runtime_put_autosuspend(musb->controller);
1947 }
1948 
1949 static void musb_recover_from_babble(struct musb *musb)
1950 {
1951         int ret;
1952         u8 devctl;
1953 
1954         musb_disable_interrupts(musb);
1955 
1956         /*
1957          * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1958          * it some slack and wait for 10us.
1959          */
1960         udelay(10);
1961 
1962         ret  = musb_platform_recover(musb);
1963         if (ret) {
1964                 musb_enable_interrupts(musb);
1965                 return;
1966         }
1967 
1968         /* drop session bit */
1969         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1970         devctl &= ~MUSB_DEVCTL_SESSION;
1971         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1972 
1973         /* tell usbcore about it */
1974         musb_root_disconnect(musb);
1975 
1976         /*
1977          * When a babble condition occurs, the musb controller
1978          * removes the session bit and the endpoint config is lost.
1979          */
1980         if (musb->dyn_fifo)
1981                 ret = ep_config_from_table(musb);
1982         else
1983                 ret = ep_config_from_hw(musb);
1984 
1985         /* restart session */
1986         if (ret == 0)
1987                 musb_start(musb);
1988 }
1989 
1990 /* --------------------------------------------------------------------------
1991  * Init support
1992  */
1993 
1994 static struct musb *allocate_instance(struct device *dev,
1995                 const struct musb_hdrc_config *config, void __iomem *mbase)
1996 {
1997         struct musb             *musb;
1998         struct musb_hw_ep       *ep;
1999         int                     epnum;
2000         int                     ret;
2001 
2002         musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
2003         if (!musb)
2004                 return NULL;
2005 
2006         INIT_LIST_HEAD(&musb->control);
2007         INIT_LIST_HEAD(&musb->in_bulk);
2008         INIT_LIST_HEAD(&musb->out_bulk);
2009         INIT_LIST_HEAD(&musb->pending_list);
2010 
2011         musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
2012         musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
2013         musb->mregs = mbase;
2014         musb->ctrl_base = mbase;
2015         musb->nIrq = -ENODEV;
2016         musb->config = config;
2017         BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
2018         for (epnum = 0, ep = musb->endpoints;
2019                         epnum < musb->config->num_eps;
2020                         epnum++, ep++) {
2021                 ep->musb = musb;
2022                 ep->epnum = epnum;
2023         }
2024 
2025         musb->controller = dev;
2026 
2027         ret = musb_host_alloc(musb);
2028         if (ret < 0)
2029                 goto err_free;
2030 
2031         dev_set_drvdata(dev, musb);
2032 
2033         return musb;
2034 
2035 err_free:
2036         return NULL;
2037 }
2038 
2039 static void musb_free(struct musb *musb)
2040 {
2041         /* this has multiple entry modes. it handles fault cleanup after
2042          * probe(), where things may be partially set up, as well as rmmod
2043          * cleanup after everything's been de-activated.
2044          */
2045 
2046         if (musb->nIrq >= 0) {
2047                 if (musb->irq_wake)
2048                         disable_irq_wake(musb->nIrq);
2049                 free_irq(musb->nIrq, musb);
2050         }
2051 
2052         musb_host_free(musb);
2053 }
2054 
2055 struct musb_pending_work {
2056         int (*callback)(struct musb *musb, void *data);
2057         void *data;
2058         struct list_head node;
2059 };
2060 
2061 #ifdef CONFIG_PM
2062 /*
2063  * Called from musb_runtime_resume(), musb_resume(), and
2064  * musb_queue_resume_work(). Callers must take musb->lock.
2065  */
2066 static int musb_run_resume_work(struct musb *musb)
2067 {
2068         struct musb_pending_work *w, *_w;
2069         unsigned long flags;
2070         int error = 0;
2071 
2072         spin_lock_irqsave(&musb->list_lock, flags);
2073         list_for_each_entry_safe(w, _w, &musb->pending_list, node) {
2074                 if (w->callback) {
2075                         error = w->callback(musb, w->data);
2076                         if (error < 0) {
2077                                 dev_err(musb->controller,
2078                                         "resume callback %p failed: %i\n",
2079                                         w->callback, error);
2080                         }
2081                 }
2082                 list_del(&w->node);
2083                 devm_kfree(musb->controller, w);
2084         }
2085         spin_unlock_irqrestore(&musb->list_lock, flags);
2086 
2087         return error;
2088 }
2089 #endif
2090 
2091 /*
2092  * Called to run work if device is active or else queue the work to happen
2093  * on resume. Caller must take musb->lock and must hold an RPM reference.
2094  *
2095  * Note that we cowardly refuse queuing work after musb PM runtime
2096  * resume is done calling musb_run_resume_work() and return -EINPROGRESS
2097  * instead.
2098  */
2099 int musb_queue_resume_work(struct musb *musb,
2100                            int (*callback)(struct musb *musb, void *data),
2101                            void *data)
2102 {
2103         struct musb_pending_work *w;
2104         unsigned long flags;
2105         int error;
2106 
2107         if (WARN_ON(!callback))
2108                 return -EINVAL;
2109 
2110         if (pm_runtime_active(musb->controller))
2111                 return callback(musb, data);
2112 
2113         w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC);
2114         if (!w)
2115                 return -ENOMEM;
2116 
2117         w->callback = callback;
2118         w->data = data;
2119         spin_lock_irqsave(&musb->list_lock, flags);
2120         if (musb->is_runtime_suspended) {
2121                 list_add_tail(&w->node, &musb->pending_list);
2122                 error = 0;
2123         } else {
2124                 dev_err(musb->controller, "could not add resume work %p\n",
2125                         callback);
2126                 devm_kfree(musb->controller, w);
2127                 error = -EINPROGRESS;
2128         }
2129         spin_unlock_irqrestore(&musb->list_lock, flags);
2130 
2131         return error;
2132 }
2133 EXPORT_SYMBOL_GPL(musb_queue_resume_work);
2134 
2135 static void musb_deassert_reset(struct work_struct *work)
2136 {
2137         struct musb *musb;
2138         unsigned long flags;
2139 
2140         musb = container_of(work, struct musb, deassert_reset_work.work);
2141 
2142         spin_lock_irqsave(&musb->lock, flags);
2143 
2144         if (musb->port1_status & USB_PORT_STAT_RESET)
2145                 musb_port_reset(musb, false);
2146 
2147         spin_unlock_irqrestore(&musb->lock, flags);
2148 }
2149 
2150 /*
2151  * Perform generic per-controller initialization.
2152  *
2153  * @dev: the controller (already clocked, etc)
2154  * @nIrq: IRQ number
2155  * @ctrl: virtual address of controller registers,
2156  *      not yet corrected for platform-specific offsets
2157  */
2158 static int
2159 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2160 {
2161         int                     status;
2162         struct musb             *musb;
2163         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
2164 
2165         /* The driver might handle more features than the board; OK.
2166          * Fail when the board needs a feature that's not enabled.
2167          */
2168         if (!plat) {
2169                 dev_err(dev, "no platform_data?\n");
2170                 status = -ENODEV;
2171                 goto fail0;
2172         }
2173 
2174         /* allocate */
2175         musb = allocate_instance(dev, plat->config, ctrl);
2176         if (!musb) {
2177                 status = -ENOMEM;
2178                 goto fail0;
2179         }
2180 
2181         spin_lock_init(&musb->lock);
2182         spin_lock_init(&musb->list_lock);
2183         musb->board_set_power = plat->set_power;
2184         musb->min_power = plat->min_power;
2185         musb->ops = plat->platform_ops;
2186         musb->port_mode = plat->mode;
2187 
2188         /*
2189          * Initialize the default IO functions. At least omap2430 needs
2190          * these early. We initialize the platform specific IO functions
2191          * later on.
2192          */
2193         musb_readb = musb_default_readb;
2194         musb_writeb = musb_default_writeb;
2195         musb_readw = musb_default_readw;
2196         musb_writew = musb_default_writew;
2197 
2198         /* The musb_platform_init() call:
2199          *   - adjusts musb->mregs
2200          *   - sets the musb->isr
2201          *   - may initialize an integrated transceiver
2202          *   - initializes musb->xceiv, usually by otg_get_phy()
2203          *   - stops powering VBUS
2204          *
2205          * There are various transceiver configurations.
2206          * DaVinci, TUSB60x0, and others integrate them.  OMAP3 uses
2207          * external/discrete ones in various flavors (twl4030 family,
2208          * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2209          */
2210         status = musb_platform_init(musb);
2211         if (status < 0)
2212                 goto fail1;
2213 
2214         if (!musb->isr) {
2215                 status = -ENODEV;
2216                 goto fail2;
2217         }
2218 
2219 
2220         /* Most devices use indexed offset or flat offset */
2221         if (musb->ops->quirks & MUSB_INDEXED_EP) {
2222                 musb->io.ep_offset = musb_indexed_ep_offset;
2223                 musb->io.ep_select = musb_indexed_ep_select;
2224         } else {
2225                 musb->io.ep_offset = musb_flat_ep_offset;
2226                 musb->io.ep_select = musb_flat_ep_select;
2227         }
2228 
2229         if (musb->ops->quirks & MUSB_G_NO_SKB_RESERVE)
2230                 musb->g.quirk_avoids_skb_reserve = 1;
2231 
2232         /* At least tusb6010 has its own offsets */
2233         if (musb->ops->ep_offset)
2234                 musb->io.ep_offset = musb->ops->ep_offset;
2235         if (musb->ops->ep_select)
2236                 musb->io.ep_select = musb->ops->ep_select;
2237 
2238         if (musb->ops->fifo_mode)
2239                 fifo_mode = musb->ops->fifo_mode;
2240         else
2241                 fifo_mode = 4;
2242 
2243         if (musb->ops->fifo_offset)
2244                 musb->io.fifo_offset = musb->ops->fifo_offset;
2245         else
2246                 musb->io.fifo_offset = musb_default_fifo_offset;
2247 
2248         if (musb->ops->busctl_offset)
2249                 musb->io.busctl_offset = musb->ops->busctl_offset;
2250         else
2251                 musb->io.busctl_offset = musb_default_busctl_offset;
2252 
2253         if (musb->ops->readb)
2254                 musb_readb = musb->ops->readb;
2255         if (musb->ops->writeb)
2256                 musb_writeb = musb->ops->writeb;
2257         if (musb->ops->readw)
2258                 musb_readw = musb->ops->readw;
2259         if (musb->ops->writew)
2260                 musb_writew = musb->ops->writew;
2261 
2262 #ifndef CONFIG_MUSB_PIO_ONLY
2263         if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2264                 dev_err(dev, "DMA controller not set\n");
2265                 status = -ENODEV;
2266                 goto fail2;
2267         }
2268         musb_dma_controller_create = musb->ops->dma_init;
2269         musb_dma_controller_destroy = musb->ops->dma_exit;
2270 #endif
2271 
2272         if (musb->ops->read_fifo)
2273                 musb->io.read_fifo = musb->ops->read_fifo;
2274         else
2275                 musb->io.read_fifo = musb_default_read_fifo;
2276 
2277         if (musb->ops->write_fifo)
2278                 musb->io.write_fifo = musb->ops->write_fifo;
2279         else
2280                 musb->io.write_fifo = musb_default_write_fifo;
2281 
2282         if (!musb->xceiv->io_ops) {
2283                 musb->xceiv->io_dev = musb->controller;
2284                 musb->xceiv->io_priv = musb->mregs;
2285                 musb->xceiv->io_ops = &musb_ulpi_access;
2286         }
2287 
2288         if (musb->ops->phy_callback)
2289                 musb_phy_callback = musb->ops->phy_callback;
2290 
2291         /*
2292          * We need musb_read/write functions initialized for PM.
2293          * Note that at least 2430 glue needs autosuspend delay
2294          * somewhere above 300 ms for the hardware to idle properly
2295          * after disconnecting the cable in host mode. Let's use
2296          * 500 ms for some margin.
2297          */
2298         pm_runtime_use_autosuspend(musb->controller);
2299         pm_runtime_set_autosuspend_delay(musb->controller, 500);
2300         pm_runtime_enable(musb->controller);
2301         pm_runtime_get_sync(musb->controller);
2302 
2303         status = usb_phy_init(musb->xceiv);
2304         if (status < 0)
2305                 goto err_usb_phy_init;
2306 
2307         if (use_dma && dev->dma_mask) {
2308                 musb->dma_controller =
2309                         musb_dma_controller_create(musb, musb->mregs);
2310                 if (IS_ERR(musb->dma_controller)) {
2311                         status = PTR_ERR(musb->dma_controller);
2312                         goto fail2_5;
2313                 }
2314         }
2315 
2316         /* be sure interrupts are disabled before connecting ISR */
2317         musb_platform_disable(musb);
2318         musb_disable_interrupts(musb);
2319         musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2320 
2321         /* MUSB_POWER_SOFTCONN might be already set, JZ4740 does this. */
2322         musb_writeb(musb->mregs, MUSB_POWER, 0);
2323 
2324         /* Init IRQ workqueue before request_irq */
2325         INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work);
2326         INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2327         INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2328 
2329         /* setup musb parts of the core (especially endpoints) */
2330         status = musb_core_init(plat->config->multipoint
2331                         ? MUSB_CONTROLLER_MHDRC
2332                         : MUSB_CONTROLLER_HDRC, musb);
2333         if (status < 0)
2334                 goto fail3;
2335 
2336         timer_setup(&musb->otg_timer, musb_otg_timer_func, 0);
2337 
2338         /* attach to the IRQ */
2339         if (request_irq(nIrq, musb->isr, IRQF_SHARED, dev_name(dev), musb)) {
2340                 dev_err(dev, "request_irq %d failed!\n", nIrq);
2341                 status = -ENODEV;
2342                 goto fail3;
2343         }
2344         musb->nIrq = nIrq;
2345         /* FIXME this handles wakeup irqs wrong */
2346         if (enable_irq_wake(nIrq) == 0) {
2347                 musb->irq_wake = 1;
2348                 device_init_wakeup(dev, 1);
2349         } else {
2350                 musb->irq_wake = 0;
2351         }
2352 
2353         /* program PHY to use external vBus if required */
2354         if (plat->extvbus) {
2355                 u8 busctl = musb_readb(musb->mregs, MUSB_ULPI_BUSCONTROL);
2356                 busctl |= MUSB_ULPI_USE_EXTVBUS;
2357                 musb_writeb(musb->mregs, MUSB_ULPI_BUSCONTROL, busctl);
2358         }
2359 
2360         MUSB_DEV_MODE(musb);
2361         musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2362 
2363         switch (musb->port_mode) {
2364         case MUSB_HOST:
2365                 status = musb_host_setup(musb, plat->power);
2366                 if (status < 0)
2367                         goto fail3;
2368                 status = musb_platform_set_mode(musb, MUSB_HOST);
2369                 break;
2370         case MUSB_PERIPHERAL:
2371                 status = musb_gadget_setup(musb);
2372                 if (status < 0)
2373                         goto fail3;
2374                 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2375                 break;
2376         case MUSB_OTG:
2377                 status = musb_host_setup(musb, plat->power);
2378                 if (status < 0)
2379                         goto fail3;
2380                 status = musb_gadget_setup(musb);
2381                 if (status) {
2382                         musb_host_cleanup(musb);
2383                         goto fail3;
2384                 }
2385                 status = musb_platform_set_mode(musb, MUSB_OTG);
2386                 break;
2387         default:
2388                 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2389                 break;
2390         }
2391 
2392         if (status < 0)
2393                 goto fail3;
2394 
2395         musb_init_debugfs(musb);
2396 
2397         musb->is_initialized = 1;
2398         pm_runtime_mark_last_busy(musb->controller);
2399         pm_runtime_put_autosuspend(musb->controller);
2400 
2401         return 0;
2402 
2403 fail3:
2404         cancel_delayed_work_sync(&musb->irq_work);
2405         cancel_delayed_work_sync(&musb->finish_resume_work);
2406         cancel_delayed_work_sync(&musb->deassert_reset_work);
2407         if (musb->dma_controller)
2408                 musb_dma_controller_destroy(musb->dma_controller);
2409 
2410 fail2_5:
2411         usb_phy_shutdown(musb->xceiv);
2412 
2413 err_usb_phy_init:
2414         pm_runtime_dont_use_autosuspend(musb->controller);
2415         pm_runtime_put_sync(musb->controller);
2416         pm_runtime_disable(musb->controller);
2417 
2418 fail2:
2419         if (musb->irq_wake)
2420                 device_init_wakeup(dev, 0);
2421         musb_platform_exit(musb);
2422 
2423 fail1:
2424         if (status != -EPROBE_DEFER)
2425                 dev_err(musb->controller,
2426                         "%s failed with status %d\n", __func__, status);
2427 
2428         musb_free(musb);
2429 
2430 fail0:
2431 
2432         return status;
2433 
2434 }
2435 
2436 /*-------------------------------------------------------------------------*/
2437 
2438 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2439  * bridge to a platform device; this driver then suffices.
2440  */
2441 static int musb_probe(struct platform_device *pdev)
2442 {
2443         struct device   *dev = &pdev->dev;
2444         int             irq = platform_get_irq_byname(pdev, "mc");
2445         struct resource *iomem;
2446         void __iomem    *base;
2447 
2448         if (irq <= 0)
2449                 return -ENODEV;
2450 
2451         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2452         base = devm_ioremap_resource(dev, iomem);
2453         if (IS_ERR(base))
2454                 return PTR_ERR(base);
2455 
2456         return musb_init_controller(dev, irq, base);
2457 }
2458 
2459 static int musb_remove(struct platform_device *pdev)
2460 {
2461         struct device   *dev = &pdev->dev;
2462         struct musb     *musb = dev_to_musb(dev);
2463         unsigned long   flags;
2464 
2465         /* this gets called on rmmod.
2466          *  - Host mode: host may still be active
2467          *  - Peripheral mode: peripheral is deactivated (or never-activated)
2468          *  - OTG mode: both roles are deactivated (or never-activated)
2469          */
2470         musb_exit_debugfs(musb);
2471 
2472         cancel_delayed_work_sync(&musb->irq_work);
2473         cancel_delayed_work_sync(&musb->finish_resume_work);
2474         cancel_delayed_work_sync(&musb->deassert_reset_work);
2475         pm_runtime_get_sync(musb->controller);
2476         musb_host_cleanup(musb);
2477         musb_gadget_cleanup(musb);
2478 
2479         musb_platform_disable(musb);
2480         spin_lock_irqsave(&musb->lock, flags);
2481         musb_disable_interrupts(musb);
2482         musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2483         spin_unlock_irqrestore(&musb->lock, flags);
2484         musb_platform_exit(musb);
2485 
2486         pm_runtime_dont_use_autosuspend(musb->controller);
2487         pm_runtime_put_sync(musb->controller);
2488         pm_runtime_disable(musb->controller);
2489         musb_phy_callback = NULL;
2490         if (musb->dma_controller)
2491                 musb_dma_controller_destroy(musb->dma_controller);
2492         usb_phy_shutdown(musb->xceiv);
2493         musb_free(musb);
2494         device_init_wakeup(dev, 0);
2495         return 0;
2496 }
2497 
2498 #ifdef  CONFIG_PM
2499 
2500 static void musb_save_context(struct musb *musb)
2501 {
2502         int i;
2503         void __iomem *musb_base = musb->mregs;
2504         void __iomem *epio;
2505 
2506         musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2507         musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2508         musb->context.busctl = musb_readb(musb_base, MUSB_ULPI_BUSCONTROL);
2509         musb->context.power = musb_readb(musb_base, MUSB_POWER);
2510         musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2511         musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2512         musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2513 
2514         for (i = 0; i < musb->config->num_eps; ++i) {
2515                 struct musb_hw_ep       *hw_ep;
2516 
2517                 hw_ep = &musb->endpoints[i];
2518                 if (!hw_ep)
2519                         continue;
2520 
2521                 epio = hw_ep->regs;
2522                 if (!epio)
2523                         continue;
2524 
2525                 musb_writeb(musb_base, MUSB_INDEX, i);
2526                 musb->context.index_regs[i].txmaxp =
2527                         musb_readw(epio, MUSB_TXMAXP);
2528                 musb->context.index_regs[i].txcsr =
2529                         musb_readw(epio, MUSB_TXCSR);
2530                 musb->context.index_regs[i].rxmaxp =
2531                         musb_readw(epio, MUSB_RXMAXP);
2532                 musb->context.index_regs[i].rxcsr =
2533                         musb_readw(epio, MUSB_RXCSR);
2534 
2535                 if (musb->dyn_fifo) {
2536                         musb->context.index_regs[i].txfifoadd =
2537                                         musb_readw(musb_base, MUSB_TXFIFOADD);
2538                         musb->context.index_regs[i].rxfifoadd =
2539                                         musb_readw(musb_base, MUSB_RXFIFOADD);
2540                         musb->context.index_regs[i].txfifosz =
2541                                         musb_readb(musb_base, MUSB_TXFIFOSZ);
2542                         musb->context.index_regs[i].rxfifosz =
2543                                         musb_readb(musb_base, MUSB_RXFIFOSZ);
2544                 }
2545 
2546                 musb->context.index_regs[i].txtype =
2547                         musb_readb(epio, MUSB_TXTYPE);
2548                 musb->context.index_regs[i].txinterval =
2549                         musb_readb(epio, MUSB_TXINTERVAL);
2550                 musb->context.index_regs[i].rxtype =
2551                         musb_readb(epio, MUSB_RXTYPE);
2552                 musb->context.index_regs[i].rxinterval =
2553                         musb_readb(epio, MUSB_RXINTERVAL);
2554 
2555                 musb->context.index_regs[i].txfunaddr =
2556                         musb_read_txfunaddr(musb, i);
2557                 musb->context.index_regs[i].txhubaddr =
2558                         musb_read_txhubaddr(musb, i);
2559                 musb->context.index_regs[i].txhubport =
2560                         musb_read_txhubport(musb, i);
2561 
2562                 musb->context.index_regs[i].rxfunaddr =
2563                         musb_read_rxfunaddr(musb, i);
2564                 musb->context.index_regs[i].rxhubaddr =
2565                         musb_read_rxhubaddr(musb, i);
2566                 musb->context.index_regs[i].rxhubport =
2567                         musb_read_rxhubport(musb, i);
2568         }
2569 }
2570 
2571 static void musb_restore_context(struct musb *musb)
2572 {
2573         int i;
2574         void __iomem *musb_base = musb->mregs;
2575         void __iomem *epio;
2576         u8 power;
2577 
2578         musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2579         musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2580         musb_writeb(musb_base, MUSB_ULPI_BUSCONTROL, musb->context.busctl);
2581 
2582         /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2583         power = musb_readb(musb_base, MUSB_POWER);
2584         power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2585         musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2586         power |= musb->context.power;
2587         musb_writeb(musb_base, MUSB_POWER, power);
2588 
2589         musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2590         musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2591         musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2592         if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2593                 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2594 
2595         for (i = 0; i < musb->config->num_eps; ++i) {
2596                 struct musb_hw_ep       *hw_ep;
2597 
2598                 hw_ep = &musb->endpoints[i];
2599                 if (!hw_ep)
2600                         continue;
2601 
2602                 epio = hw_ep->regs;
2603                 if (!epio)
2604                         continue;
2605 
2606                 musb_writeb(musb_base, MUSB_INDEX, i);
2607                 musb_writew(epio, MUSB_TXMAXP,
2608                         musb->context.index_regs[i].txmaxp);
2609                 musb_writew(epio, MUSB_TXCSR,
2610                         musb->context.index_regs[i].txcsr);
2611                 musb_writew(epio, MUSB_RXMAXP,
2612                         musb->context.index_regs[i].rxmaxp);
2613                 musb_writew(epio, MUSB_RXCSR,
2614                         musb->context.index_regs[i].rxcsr);
2615 
2616                 if (musb->dyn_fifo) {
2617                         musb_writeb(musb_base, MUSB_TXFIFOSZ,
2618                                 musb->context.index_regs[i].txfifosz);
2619                         musb_writeb(musb_base, MUSB_RXFIFOSZ,
2620                                 musb->context.index_regs[i].rxfifosz);
2621                         musb_writew(musb_base, MUSB_TXFIFOADD,
2622                                 musb->context.index_regs[i].txfifoadd);
2623                         musb_writew(musb_base, MUSB_RXFIFOADD,
2624                                 musb->context.index_regs[i].rxfifoadd);
2625                 }
2626 
2627                 musb_writeb(epio, MUSB_TXTYPE,
2628                                 musb->context.index_regs[i].txtype);
2629                 musb_writeb(epio, MUSB_TXINTERVAL,
2630                                 musb->context.index_regs[i].txinterval);
2631                 musb_writeb(epio, MUSB_RXTYPE,
2632                                 musb->context.index_regs[i].rxtype);
2633                 musb_writeb(epio, MUSB_RXINTERVAL,
2634 
2635                                 musb->context.index_regs[i].rxinterval);
2636                 musb_write_txfunaddr(musb, i,
2637                                 musb->context.index_regs[i].txfunaddr);
2638                 musb_write_txhubaddr(musb, i,
2639                                 musb->context.index_regs[i].txhubaddr);
2640                 musb_write_txhubport(musb, i,
2641                                 musb->context.index_regs[i].txhubport);
2642 
2643                 musb_write_rxfunaddr(musb, i,
2644                                 musb->context.index_regs[i].rxfunaddr);
2645                 musb_write_rxhubaddr(musb, i,
2646                                 musb->context.index_regs[i].rxhubaddr);
2647                 musb_write_rxhubport(musb, i,
2648                                 musb->context.index_regs[i].rxhubport);
2649         }
2650         musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2651 }
2652 
2653 static int musb_suspend(struct device *dev)
2654 {
2655         struct musb     *musb = dev_to_musb(dev);
2656         unsigned long   flags;
2657         int ret;
2658 
2659         ret = pm_runtime_get_sync(dev);
2660         if (ret < 0) {
2661                 pm_runtime_put_noidle(dev);
2662                 return ret;
2663         }
2664 
2665         musb_platform_disable(musb);
2666         musb_disable_interrupts(musb);
2667 
2668         musb->flush_irq_work = true;
2669         while (flush_delayed_work(&musb->irq_work))
2670                 ;
2671         musb->flush_irq_work = false;
2672 
2673         if (!(musb->ops->quirks & MUSB_PRESERVE_SESSION))
2674                 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2675 
2676         WARN_ON(!list_empty(&musb->pending_list));
2677 
2678         spin_lock_irqsave(&musb->lock, flags);
2679 
2680         if (is_peripheral_active(musb)) {
2681                 /* FIXME force disconnect unless we know USB will wake
2682                  * the system up quickly enough to respond ...
2683                  */
2684         } else if (is_host_active(musb)) {
2685                 /* we know all the children are suspended; sometimes
2686                  * they will even be wakeup-enabled.
2687                  */
2688         }
2689 
2690         musb_save_context(musb);
2691 
2692         spin_unlock_irqrestore(&musb->lock, flags);
2693         return 0;
2694 }
2695 
2696 static int musb_resume(struct device *dev)
2697 {
2698         struct musb *musb = dev_to_musb(dev);
2699         unsigned long flags;
2700         int error;
2701         u8 devctl;
2702         u8 mask;
2703 
2704         /*
2705          * For static cmos like DaVinci, register values were preserved
2706          * unless for some reason the whole soc powered down or the USB
2707          * module got reset through the PSC (vs just being disabled).
2708          *
2709          * For the DSPS glue layer though, a full register restore has to
2710          * be done. As it shouldn't harm other platforms, we do it
2711          * unconditionally.
2712          */
2713 
2714         musb_restore_context(musb);
2715 
2716         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2717         mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2718         if ((devctl & mask) != (musb->context.devctl & mask))
2719                 musb->port1_status = 0;
2720 
2721         musb_enable_interrupts(musb);
2722         musb_platform_enable(musb);
2723 
2724         /* session might be disabled in suspend */
2725         if (musb->port_mode == MUSB_HOST &&
2726             !(musb->ops->quirks & MUSB_PRESERVE_SESSION)) {
2727                 devctl |= MUSB_DEVCTL_SESSION;
2728                 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
2729         }
2730 
2731         spin_lock_irqsave(&musb->lock, flags);
2732         error = musb_run_resume_work(musb);
2733         if (error)
2734                 dev_err(musb->controller, "resume work failed with %i\n",
2735                         error);
2736         spin_unlock_irqrestore(&musb->lock, flags);
2737 
2738         pm_runtime_mark_last_busy(dev);
2739         pm_runtime_put_autosuspend(dev);
2740 
2741         return 0;
2742 }
2743 
2744 static int musb_runtime_suspend(struct device *dev)
2745 {
2746         struct musb     *musb = dev_to_musb(dev);
2747 
2748         musb_save_context(musb);
2749         musb->is_runtime_suspended = 1;
2750 
2751         return 0;
2752 }
2753 
2754 static int musb_runtime_resume(struct device *dev)
2755 {
2756         struct musb *musb = dev_to_musb(dev);
2757         unsigned long flags;
2758         int error;
2759 
2760         /*
2761          * When pm_runtime_get_sync called for the first time in driver
2762          * init,  some of the structure is still not initialized which is
2763          * used in restore function. But clock needs to be
2764          * enabled before any register access, so
2765          * pm_runtime_get_sync has to be called.
2766          * Also context restore without save does not make
2767          * any sense
2768          */
2769         if (!musb->is_initialized)
2770                 return 0;
2771 
2772         musb_restore_context(musb);
2773 
2774         spin_lock_irqsave(&musb->lock, flags);
2775         error = musb_run_resume_work(musb);
2776         if (error)
2777                 dev_err(musb->controller, "resume work failed with %i\n",
2778                         error);
2779         musb->is_runtime_suspended = 0;
2780         spin_unlock_irqrestore(&musb->lock, flags);
2781 
2782         return 0;
2783 }
2784 
2785 static const struct dev_pm_ops musb_dev_pm_ops = {
2786         .suspend        = musb_suspend,
2787         .resume         = musb_resume,
2788         .runtime_suspend = musb_runtime_suspend,
2789         .runtime_resume = musb_runtime_resume,
2790 };
2791 
2792 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2793 #else
2794 #define MUSB_DEV_PM_OPS NULL
2795 #endif
2796 
2797 static struct platform_driver musb_driver = {
2798         .driver = {
2799                 .name           = (char *)musb_driver_name,
2800                 .bus            = &platform_bus_type,
2801                 .pm             = MUSB_DEV_PM_OPS,
2802                 .dev_groups     = musb_groups,
2803         },
2804         .probe          = musb_probe,
2805         .remove         = musb_remove,
2806 };
2807 
2808 module_platform_driver(musb_driver);