1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MUSB OTG driver host support
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
8 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
9 */
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/sched.h>
15 #include <linux/slab.h>
16 #include <linux/errno.h>
17 #include <linux/list.h>
18 #include <linux/dma-mapping.h>
19
20 #include "musb_core.h"
21 #include "musb_host.h"
22 #include "musb_trace.h"
23
24 /* MUSB HOST status 22-mar-2006
25 *
26 * - There's still lots of partial code duplication for fault paths, so
27 * they aren't handled as consistently as they need to be.
28 *
29 * - PIO mostly behaved when last tested.
30 * + including ep0, with all usbtest cases 9, 10
31 * + usbtest 14 (ep0out) doesn't seem to run at all
32 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
33 * configurations, but otherwise double buffering passes basic tests.
34 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
35 *
36 * - DMA (CPPI) ... partially behaves, not currently recommended
37 * + about 1/15 the speed of typical EHCI implementations (PCI)
38 * + RX, all too often reqpkt seems to misbehave after tx
39 * + TX, no known issues (other than evident silicon issue)
40 *
41 * - DMA (Mentor/OMAP) ...has at least toggle update problems
42 *
43 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
44 * starvation ... nothing yet for TX, interrupt, or bulk.
45 *
46 * - Not tested with HNP, but some SRP paths seem to behave.
47 *
48 * NOTE 24-August-2006:
49 *
50 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
51 * extra endpoint for periodic use enabling hub + keybd + mouse. That
52 * mostly works, except that with "usbnet" it's easy to trigger cases
53 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
54 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
55 * although ARP RX wins. (That test was done with a full speed link.)
56 */
57
58
59 /*
60 * NOTE on endpoint usage:
61 *
62 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
63 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
64 * (Yes, bulk _could_ use more of the endpoints than that, and would even
65 * benefit from it.)
66 *
67 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
68 * So far that scheduling is both dumb and optimistic: the endpoint will be
69 * "claimed" until its software queue is no longer refilled. No multiplexing
70 * of transfers between endpoints, or anything clever.
71 */
72
73 struct musb *hcd_to_musb(struct usb_hcd *hcd)
74 {
75 return *(struct musb **) hcd->hcd_priv;
76 }
77
78
79 static void musb_ep_program(struct musb *musb, u8 epnum,
80 struct urb *urb, int is_out,
81 u8 *buf, u32 offset, u32 len);
82
83 /*
84 * Clear TX fifo. Needed to avoid BABBLE errors.
85 */
86 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
87 {
88 struct musb *musb = ep->musb;
89 void __iomem *epio = ep->regs;
90 u16 csr;
91 int retries = 1000;
92
93 csr = musb_readw(epio, MUSB_TXCSR);
94 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
95 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY;
96 musb_writew(epio, MUSB_TXCSR, csr);
97 csr = musb_readw(epio, MUSB_TXCSR);
98
99 /*
100 * FIXME: sometimes the tx fifo flush failed, it has been
101 * observed during device disconnect on AM335x.
102 *
103 * To reproduce the issue, ensure tx urb(s) are queued when
104 * unplug the usb device which is connected to AM335x usb
105 * host port.
106 *
107 * I found using a usb-ethernet device and running iperf
108 * (client on AM335x) has very high chance to trigger it.
109 *
110 * Better to turn on musb_dbg() in musb_cleanup_urb() with
111 * CPPI enabled to see the issue when aborting the tx channel.
112 */
113 if (dev_WARN_ONCE(musb->controller, retries-- < 1,
114 "Could not flush host TX%d fifo: csr: %04x\n",
115 ep->epnum, csr))
116 return;
117 mdelay(1);
118 }
119 }
120
121 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
122 {
123 void __iomem *epio = ep->regs;
124 u16 csr;
125 int retries = 5;
126
127 /* scrub any data left in the fifo */
128 do {
129 csr = musb_readw(epio, MUSB_TXCSR);
130 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
131 break;
132 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
133 csr = musb_readw(epio, MUSB_TXCSR);
134 udelay(10);
135 } while (--retries);
136
137 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
138 ep->epnum, csr);
139
140 /* and reset for the next transfer */
141 musb_writew(epio, MUSB_TXCSR, 0);
142 }
143
144 /*
145 * Start transmit. Caller is responsible for locking shared resources.
146 * musb must be locked.
147 */
148 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
149 {
150 u16 txcsr;
151
152 /* NOTE: no locks here; caller should lock and select EP */
153 if (ep->epnum) {
154 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
155 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
156 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
157 } else {
158 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
159 musb_writew(ep->regs, MUSB_CSR0, txcsr);
160 }
161
162 }
163
164 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
165 {
166 u16 txcsr;
167
168 /* NOTE: no locks here; caller should lock and select EP */
169 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
170 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
171 if (is_cppi_enabled(ep->musb))
172 txcsr |= MUSB_TXCSR_DMAMODE;
173 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
174 }
175
176 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
177 {
178 if (is_in != 0 || ep->is_shared_fifo)
179 ep->in_qh = qh;
180 if (is_in == 0 || ep->is_shared_fifo)
181 ep->out_qh = qh;
182 }
183
184 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
185 {
186 return is_in ? ep->in_qh : ep->out_qh;
187 }
188
189 /*
190 * Start the URB at the front of an endpoint's queue
191 * end must be claimed from the caller.
192 *
193 * Context: controller locked, irqs blocked
194 */
195 static void
196 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
197 {
198 u32 len;
199 void __iomem *mbase = musb->mregs;
200 struct urb *urb = next_urb(qh);
201 void *buf = urb->transfer_buffer;
202 u32 offset = 0;
203 struct musb_hw_ep *hw_ep = qh->hw_ep;
204 int epnum = hw_ep->epnum;
205
206 /* initialize software qh state */
207 qh->offset = 0;
208 qh->segsize = 0;
209
210 /* gather right source of data */
211 switch (qh->type) {
212 case USB_ENDPOINT_XFER_CONTROL:
213 /* control transfers always start with SETUP */
214 is_in = 0;
215 musb->ep0_stage = MUSB_EP0_START;
216 buf = urb->setup_packet;
217 len = 8;
218 break;
219 case USB_ENDPOINT_XFER_ISOC:
220 qh->iso_idx = 0;
221 qh->frame = 0;
222 offset = urb->iso_frame_desc[0].offset;
223 len = urb->iso_frame_desc[0].length;
224 break;
225 default: /* bulk, interrupt */
226 /* actual_length may be nonzero on retry paths */
227 buf = urb->transfer_buffer + urb->actual_length;
228 len = urb->transfer_buffer_length - urb->actual_length;
229 }
230
231 trace_musb_urb_start(musb, urb);
232
233 /* Configure endpoint */
234 musb_ep_set_qh(hw_ep, is_in, qh);
235 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
236
237 /* transmit may have more work: start it when it is time */
238 if (is_in)
239 return;
240
241 /* determine if the time is right for a periodic transfer */
242 switch (qh->type) {
243 case USB_ENDPOINT_XFER_ISOC:
244 case USB_ENDPOINT_XFER_INT:
245 musb_dbg(musb, "check whether there's still time for periodic Tx");
246 /* FIXME this doesn't implement that scheduling policy ...
247 * or handle framecounter wrapping
248 */
249 if (1) { /* Always assume URB_ISO_ASAP */
250 /* REVISIT the SOF irq handler shouldn't duplicate
251 * this code; and we don't init urb->start_frame...
252 */
253 qh->frame = 0;
254 goto start;
255 } else {
256 qh->frame = urb->start_frame;
257 /* enable SOF interrupt so we can count down */
258 musb_dbg(musb, "SOF for %d", epnum);
259 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
260 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
261 #endif
262 }
263 break;
264 default:
265 start:
266 musb_dbg(musb, "Start TX%d %s", epnum,
267 hw_ep->tx_channel ? "dma" : "pio");
268
269 if (!hw_ep->tx_channel)
270 musb_h_tx_start(hw_ep);
271 else if (is_cppi_enabled(musb) || tusb_dma_omap(musb))
272 musb_h_tx_dma_start(hw_ep);
273 }
274 }
275
276 /* Context: caller owns controller lock, IRQs are blocked */
277 static void musb_giveback(struct musb *musb, struct urb *urb, int status)
278 __releases(musb->lock)
279 __acquires(musb->lock)
280 {
281 trace_musb_urb_gb(musb, urb);
282
283 usb_hcd_unlink_urb_from_ep(musb->hcd, urb);
284 spin_unlock(&musb->lock);
285 usb_hcd_giveback_urb(musb->hcd, urb, status);
286 spin_lock(&musb->lock);
287 }
288
289 /* For bulk/interrupt endpoints only */
290 static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
291 struct urb *urb)
292 {
293 void __iomem *epio = qh->hw_ep->regs;
294 u16 csr;
295
296 /*
297 * FIXME: the current Mentor DMA code seems to have
298 * problems getting toggle correct.
299 */
300
301 if (is_in)
302 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
303 else
304 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
305
306 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
307 }
308
309 /*
310 * Advance this hardware endpoint's queue, completing the specified URB and
311 * advancing to either the next URB queued to that qh, or else invalidating
312 * that qh and advancing to the next qh scheduled after the current one.
313 *
314 * Context: caller owns controller lock, IRQs are blocked
315 */
316 static void musb_advance_schedule(struct musb *musb, struct urb *urb,
317 struct musb_hw_ep *hw_ep, int is_in)
318 {
319 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
320 struct musb_hw_ep *ep = qh->hw_ep;
321 int ready = qh->is_ready;
322 int status;
323
324 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
325
326 /* save toggle eagerly, for paranoia */
327 switch (qh->type) {
328 case USB_ENDPOINT_XFER_BULK:
329 case USB_ENDPOINT_XFER_INT:
330 musb_save_toggle(qh, is_in, urb);
331 break;
332 case USB_ENDPOINT_XFER_ISOC:
333 if (status == 0 && urb->error_count)
334 status = -EXDEV;
335 break;
336 }
337
338 qh->is_ready = 0;
339 musb_giveback(musb, urb, status);
340 qh->is_ready = ready;
341
342 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
343 * invalidate qh as soon as list_empty(&hep->urb_list)
344 */
345 if (list_empty(&qh->hep->urb_list)) {
346 struct list_head *head;
347 struct dma_controller *dma = musb->dma_controller;
348
349 if (is_in) {
350 ep->rx_reinit = 1;
351 if (ep->rx_channel) {
352 dma->channel_release(ep->rx_channel);
353 ep->rx_channel = NULL;
354 }
355 } else {
356 ep->tx_reinit = 1;
357 if (ep->tx_channel) {
358 dma->channel_release(ep->tx_channel);
359 ep->tx_channel = NULL;
360 }
361 }
362
363 /* Clobber old pointers to this qh */
364 musb_ep_set_qh(ep, is_in, NULL);
365 qh->hep->hcpriv = NULL;
366
367 switch (qh->type) {
368
369 case USB_ENDPOINT_XFER_CONTROL:
370 case USB_ENDPOINT_XFER_BULK:
371 /* fifo policy for these lists, except that NAKing
372 * should rotate a qh to the end (for fairness).
373 */
374 if (qh->mux == 1) {
375 head = qh->ring.prev;
376 list_del(&qh->ring);
377 kfree(qh);
378 qh = first_qh(head);
379 break;
380 }
381 /* fall through */
382
383 case USB_ENDPOINT_XFER_ISOC:
384 case USB_ENDPOINT_XFER_INT:
385 /* this is where periodic bandwidth should be
386 * de-allocated if it's tracked and allocated;
387 * and where we'd update the schedule tree...
388 */
389 kfree(qh);
390 qh = NULL;
391 break;
392 }
393 }
394
395 if (qh != NULL && qh->is_ready) {
396 musb_dbg(musb, "... next ep%d %cX urb %p",
397 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
398 musb_start_urb(musb, is_in, qh);
399 }
400 }
401
402 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
403 {
404 /* we don't want fifo to fill itself again;
405 * ignore dma (various models),
406 * leave toggle alone (may not have been saved yet)
407 */
408 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
409 csr &= ~(MUSB_RXCSR_H_REQPKT
410 | MUSB_RXCSR_H_AUTOREQ
411 | MUSB_RXCSR_AUTOCLEAR);
412
413 /* write 2x to allow double buffering */
414 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
415 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
416
417 /* flush writebuffer */
418 return musb_readw(hw_ep->regs, MUSB_RXCSR);
419 }
420
421 /*
422 * PIO RX for a packet (or part of it).
423 */
424 static bool
425 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
426 {
427 u16 rx_count;
428 u8 *buf;
429 u16 csr;
430 bool done = false;
431 u32 length;
432 int do_flush = 0;
433 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
434 void __iomem *epio = hw_ep->regs;
435 struct musb_qh *qh = hw_ep->in_qh;
436 int pipe = urb->pipe;
437 void *buffer = urb->transfer_buffer;
438
439 /* musb_ep_select(mbase, epnum); */
440 rx_count = musb_readw(epio, MUSB_RXCOUNT);
441 musb_dbg(musb, "RX%d count %d, buffer %p len %d/%d", epnum, rx_count,
442 urb->transfer_buffer, qh->offset,
443 urb->transfer_buffer_length);
444
445 /* unload FIFO */
446 if (usb_pipeisoc(pipe)) {
447 int status = 0;
448 struct usb_iso_packet_descriptor *d;
449
450 if (iso_err) {
451 status = -EILSEQ;
452 urb->error_count++;
453 }
454
455 d = urb->iso_frame_desc + qh->iso_idx;
456 buf = buffer + d->offset;
457 length = d->length;
458 if (rx_count > length) {
459 if (status == 0) {
460 status = -EOVERFLOW;
461 urb->error_count++;
462 }
463 musb_dbg(musb, "OVERFLOW %d into %d", rx_count, length);
464 do_flush = 1;
465 } else
466 length = rx_count;
467 urb->actual_length += length;
468 d->actual_length = length;
469
470 d->status = status;
471
472 /* see if we are done */
473 done = (++qh->iso_idx >= urb->number_of_packets);
474 } else {
475 /* non-isoch */
476 buf = buffer + qh->offset;
477 length = urb->transfer_buffer_length - qh->offset;
478 if (rx_count > length) {
479 if (urb->status == -EINPROGRESS)
480 urb->status = -EOVERFLOW;
481 musb_dbg(musb, "OVERFLOW %d into %d", rx_count, length);
482 do_flush = 1;
483 } else
484 length = rx_count;
485 urb->actual_length += length;
486 qh->offset += length;
487
488 /* see if we are done */
489 done = (urb->actual_length == urb->transfer_buffer_length)
490 || (rx_count < qh->maxpacket)
491 || (urb->status != -EINPROGRESS);
492 if (done
493 && (urb->status == -EINPROGRESS)
494 && (urb->transfer_flags & URB_SHORT_NOT_OK)
495 && (urb->actual_length
496 < urb->transfer_buffer_length))
497 urb->status = -EREMOTEIO;
498 }
499
500 musb_read_fifo(hw_ep, length, buf);
501
502 csr = musb_readw(epio, MUSB_RXCSR);
503 csr |= MUSB_RXCSR_H_WZC_BITS;
504 if (unlikely(do_flush))
505 musb_h_flush_rxfifo(hw_ep, csr);
506 else {
507 /* REVISIT this assumes AUTOCLEAR is never set */
508 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
509 if (!done)
510 csr |= MUSB_RXCSR_H_REQPKT;
511 musb_writew(epio, MUSB_RXCSR, csr);
512 }
513
514 return done;
515 }
516
517 /* we don't always need to reinit a given side of an endpoint...
518 * when we do, use tx/rx reinit routine and then construct a new CSR
519 * to address data toggle, NYET, and DMA or PIO.
520 *
521 * it's possible that driver bugs (especially for DMA) or aborting a
522 * transfer might have left the endpoint busier than it should be.
523 * the busy/not-empty tests are basically paranoia.
524 */
525 static void
526 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, u8 epnum)
527 {
528 struct musb_hw_ep *ep = musb->endpoints + epnum;
529 u16 csr;
530
531 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
532 * That always uses tx_reinit since ep0 repurposes TX register
533 * offsets; the initial SETUP packet is also a kind of OUT.
534 */
535
536 /* if programmed for Tx, put it in RX mode */
537 if (ep->is_shared_fifo) {
538 csr = musb_readw(ep->regs, MUSB_TXCSR);
539 if (csr & MUSB_TXCSR_MODE) {
540 musb_h_tx_flush_fifo(ep);
541 csr = musb_readw(ep->regs, MUSB_TXCSR);
542 musb_writew(ep->regs, MUSB_TXCSR,
543 csr | MUSB_TXCSR_FRCDATATOG);
544 }
545
546 /*
547 * Clear the MODE bit (and everything else) to enable Rx.
548 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
549 */
550 if (csr & MUSB_TXCSR_DMAMODE)
551 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
552 musb_writew(ep->regs, MUSB_TXCSR, 0);
553
554 /* scrub all previous state, clearing toggle */
555 }
556 csr = musb_readw(ep->regs, MUSB_RXCSR);
557 if (csr & MUSB_RXCSR_RXPKTRDY)
558 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
559 musb_readw(ep->regs, MUSB_RXCOUNT));
560
561 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
562
563 /* target addr and (for multipoint) hub addr/port */
564 if (musb->is_multipoint) {
565 musb_write_rxfunaddr(musb, epnum, qh->addr_reg);
566 musb_write_rxhubaddr(musb, epnum, qh->h_addr_reg);
567 musb_write_rxhubport(musb, epnum, qh->h_port_reg);
568 } else
569 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
570
571 /* protocol/endpoint, interval/NAKlimit, i/o size */
572 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
573 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
574 /* NOTE: bulk combining rewrites high bits of maxpacket */
575 /* Set RXMAXP with the FIFO size of the endpoint
576 * to disable double buffer mode.
577 */
578 musb_writew(ep->regs, MUSB_RXMAXP,
579 qh->maxpacket | ((qh->hb_mult - 1) << 11));
580
581 ep->rx_reinit = 0;
582 }
583
584 static void musb_tx_dma_set_mode_mentor(struct dma_controller *dma,
585 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
586 struct urb *urb, u32 offset,
587 u32 *length, u8 *mode)
588 {
589 struct dma_channel *channel = hw_ep->tx_channel;
590 void __iomem *epio = hw_ep->regs;
591 u16 pkt_size = qh->maxpacket;
592 u16 csr;
593
594 if (*length > channel->max_len)
595 *length = channel->max_len;
596
597 csr = musb_readw(epio, MUSB_TXCSR);
598 if (*length > pkt_size) {
599 *mode = 1;
600 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
601 /* autoset shouldn't be set in high bandwidth */
602 /*
603 * Enable Autoset according to table
604 * below
605 * bulk_split hb_mult Autoset_Enable
606 * 0 1 Yes(Normal)
607 * 0 >1 No(High BW ISO)
608 * 1 1 Yes(HS bulk)
609 * 1 >1 Yes(FS bulk)
610 */
611 if (qh->hb_mult == 1 || (qh->hb_mult > 1 &&
612 can_bulk_split(hw_ep->musb, qh->type)))
613 csr |= MUSB_TXCSR_AUTOSET;
614 } else {
615 *mode = 0;
616 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
617 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
618 }
619 channel->desired_mode = *mode;
620 musb_writew(epio, MUSB_TXCSR, csr);
621 }
622
623 static void musb_tx_dma_set_mode_cppi_tusb(struct dma_controller *dma,
624 struct musb_hw_ep *hw_ep,
625 struct musb_qh *qh,
626 struct urb *urb,
627 u32 offset,
628 u32 *length,
629 u8 *mode)
630 {
631 struct dma_channel *channel = hw_ep->tx_channel;
632
633 channel->actual_len = 0;
634
635 /*
636 * TX uses "RNDIS" mode automatically but needs help
637 * to identify the zero-length-final-packet case.
638 */
639 *mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
640 }
641
642 static bool musb_tx_dma_program(struct dma_controller *dma,
643 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
644 struct urb *urb, u32 offset, u32 length)
645 {
646 struct dma_channel *channel = hw_ep->tx_channel;
647 u16 pkt_size = qh->maxpacket;
648 u8 mode;
649
650 if (musb_dma_inventra(hw_ep->musb) || musb_dma_ux500(hw_ep->musb))
651 musb_tx_dma_set_mode_mentor(dma, hw_ep, qh, urb, offset,
652 &length, &mode);
653 else if (is_cppi_enabled(hw_ep->musb) || tusb_dma_omap(hw_ep->musb))
654 musb_tx_dma_set_mode_cppi_tusb(dma, hw_ep, qh, urb, offset,
655 &length, &mode);
656 else
657 return false;
658
659 qh->segsize = length;
660
661 /*
662 * Ensure the data reaches to main memory before starting
663 * DMA transfer
664 */
665 wmb();
666
667 if (!dma->channel_program(channel, pkt_size, mode,
668 urb->transfer_dma + offset, length)) {
669 void __iomem *epio = hw_ep->regs;
670 u16 csr;
671
672 dma->channel_release(channel);
673 hw_ep->tx_channel = NULL;
674
675 csr = musb_readw(epio, MUSB_TXCSR);
676 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
677 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
678 return false;
679 }
680 return true;
681 }
682
683 /*
684 * Program an HDRC endpoint as per the given URB
685 * Context: irqs blocked, controller lock held
686 */
687 static void musb_ep_program(struct musb *musb, u8 epnum,
688 struct urb *urb, int is_out,
689 u8 *buf, u32 offset, u32 len)
690 {
691 struct dma_controller *dma_controller;
692 struct dma_channel *dma_channel;
693 u8 dma_ok;
694 void __iomem *mbase = musb->mregs;
695 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
696 void __iomem *epio = hw_ep->regs;
697 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
698 u16 packet_sz = qh->maxpacket;
699 u8 use_dma = 1;
700 u16 csr;
701
702 musb_dbg(musb, "%s hw%d urb %p spd%d dev%d ep%d%s "
703 "h_addr%02x h_port%02x bytes %d",
704 is_out ? "-->" : "<--",
705 epnum, urb, urb->dev->speed,
706 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
707 qh->h_addr_reg, qh->h_port_reg,
708 len);
709
710 musb_ep_select(mbase, epnum);
711
712 if (is_out && !len) {
713 use_dma = 0;
714 csr = musb_readw(epio, MUSB_TXCSR);
715 csr &= ~MUSB_TXCSR_DMAENAB;
716 musb_writew(epio, MUSB_TXCSR, csr);
717 hw_ep->tx_channel = NULL;
718 }
719
720 /* candidate for DMA? */
721 dma_controller = musb->dma_controller;
722 if (use_dma && is_dma_capable() && epnum && dma_controller) {
723 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
724 if (!dma_channel) {
725 dma_channel = dma_controller->channel_alloc(
726 dma_controller, hw_ep, is_out);
727 if (is_out)
728 hw_ep->tx_channel = dma_channel;
729 else
730 hw_ep->rx_channel = dma_channel;
731 }
732 } else
733 dma_channel = NULL;
734
735 /* make sure we clear DMAEnab, autoSet bits from previous run */
736
737 /* OUT/transmit/EP0 or IN/receive? */
738 if (is_out) {
739 u16 csr;
740 u16 int_txe;
741 u16 load_count;
742
743 csr = musb_readw(epio, MUSB_TXCSR);
744
745 /* disable interrupt in case we flush */
746 int_txe = musb->intrtxe;
747 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
748
749 /* general endpoint setup */
750 if (epnum) {
751 /* flush all old state, set default */
752 /*
753 * We could be flushing valid
754 * packets in double buffering
755 * case
756 */
757 if (!hw_ep->tx_double_buffered)
758 musb_h_tx_flush_fifo(hw_ep);
759
760 /*
761 * We must not clear the DMAMODE bit before or in
762 * the same cycle with the DMAENAB bit, so we clear
763 * the latter first...
764 */
765 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
766 | MUSB_TXCSR_AUTOSET
767 | MUSB_TXCSR_DMAENAB
768 | MUSB_TXCSR_FRCDATATOG
769 | MUSB_TXCSR_H_RXSTALL
770 | MUSB_TXCSR_H_ERROR
771 | MUSB_TXCSR_TXPKTRDY
772 );
773 csr |= MUSB_TXCSR_MODE;
774
775 if (!hw_ep->tx_double_buffered) {
776 if (usb_gettoggle(urb->dev, qh->epnum, 1))
777 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
778 | MUSB_TXCSR_H_DATATOGGLE;
779 else
780 csr |= MUSB_TXCSR_CLRDATATOG;
781 }
782
783 musb_writew(epio, MUSB_TXCSR, csr);
784 /* REVISIT may need to clear FLUSHFIFO ... */
785 csr &= ~MUSB_TXCSR_DMAMODE;
786 musb_writew(epio, MUSB_TXCSR, csr);
787 csr = musb_readw(epio, MUSB_TXCSR);
788 } else {
789 /* endpoint 0: just flush */
790 musb_h_ep0_flush_fifo(hw_ep);
791 }
792
793 /* target addr and (for multipoint) hub addr/port */
794 if (musb->is_multipoint) {
795 musb_write_txfunaddr(musb, epnum, qh->addr_reg);
796 musb_write_txhubaddr(musb, epnum, qh->h_addr_reg);
797 musb_write_txhubport(musb, epnum, qh->h_port_reg);
798 /* FIXME if !epnum, do the same for RX ... */
799 } else
800 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
801
802 /* protocol/endpoint/interval/NAKlimit */
803 if (epnum) {
804 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
805 if (can_bulk_split(musb, qh->type)) {
806 qh->hb_mult = hw_ep->max_packet_sz_tx
807 / packet_sz;
808 musb_writew(epio, MUSB_TXMAXP, packet_sz
809 | ((qh->hb_mult) - 1) << 11);
810 } else {
811 musb_writew(epio, MUSB_TXMAXP,
812 qh->maxpacket |
813 ((qh->hb_mult - 1) << 11));
814 }
815 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
816 } else {
817 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
818 if (musb->is_multipoint)
819 musb_writeb(epio, MUSB_TYPE0,
820 qh->type_reg);
821 }
822
823 if (can_bulk_split(musb, qh->type))
824 load_count = min((u32) hw_ep->max_packet_sz_tx,
825 len);
826 else
827 load_count = min((u32) packet_sz, len);
828
829 if (dma_channel && musb_tx_dma_program(dma_controller,
830 hw_ep, qh, urb, offset, len))
831 load_count = 0;
832
833 if (load_count) {
834 /* PIO to load FIFO */
835 qh->segsize = load_count;
836 if (!buf) {
837 sg_miter_start(&qh->sg_miter, urb->sg, 1,
838 SG_MITER_ATOMIC
839 | SG_MITER_FROM_SG);
840 if (!sg_miter_next(&qh->sg_miter)) {
841 dev_err(musb->controller,
842 "error: sg"
843 "list empty\n");
844 sg_miter_stop(&qh->sg_miter);
845 goto finish;
846 }
847 buf = qh->sg_miter.addr + urb->sg->offset +
848 urb->actual_length;
849 load_count = min_t(u32, load_count,
850 qh->sg_miter.length);
851 musb_write_fifo(hw_ep, load_count, buf);
852 qh->sg_miter.consumed = load_count;
853 sg_miter_stop(&qh->sg_miter);
854 } else
855 musb_write_fifo(hw_ep, load_count, buf);
856 }
857 finish:
858 /* re-enable interrupt */
859 musb_writew(mbase, MUSB_INTRTXE, int_txe);
860
861 /* IN/receive */
862 } else {
863 u16 csr;
864
865 if (hw_ep->rx_reinit) {
866 musb_rx_reinit(musb, qh, epnum);
867
868 /* init new state: toggle and NYET, maybe DMA later */
869 if (usb_gettoggle(urb->dev, qh->epnum, 0))
870 csr = MUSB_RXCSR_H_WR_DATATOGGLE
871 | MUSB_RXCSR_H_DATATOGGLE;
872 else
873 csr = 0;
874 if (qh->type == USB_ENDPOINT_XFER_INT)
875 csr |= MUSB_RXCSR_DISNYET;
876
877 } else {
878 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
879
880 if (csr & (MUSB_RXCSR_RXPKTRDY
881 | MUSB_RXCSR_DMAENAB
882 | MUSB_RXCSR_H_REQPKT))
883 ERR("broken !rx_reinit, ep%d csr %04x\n",
884 hw_ep->epnum, csr);
885
886 /* scrub any stale state, leaving toggle alone */
887 csr &= MUSB_RXCSR_DISNYET;
888 }
889
890 /* kick things off */
891
892 if ((is_cppi_enabled(musb) || tusb_dma_omap(musb)) && dma_channel) {
893 /* Candidate for DMA */
894 dma_channel->actual_len = 0L;
895 qh->segsize = len;
896
897 /* AUTOREQ is in a DMA register */
898 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
899 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
900
901 /*
902 * Unless caller treats short RX transfers as
903 * errors, we dare not queue multiple transfers.
904 */
905 dma_ok = dma_controller->channel_program(dma_channel,
906 packet_sz, !(urb->transfer_flags &
907 URB_SHORT_NOT_OK),
908 urb->transfer_dma + offset,
909 qh->segsize);
910 if (!dma_ok) {
911 dma_controller->channel_release(dma_channel);
912 hw_ep->rx_channel = dma_channel = NULL;
913 } else
914 csr |= MUSB_RXCSR_DMAENAB;
915 }
916
917 csr |= MUSB_RXCSR_H_REQPKT;
918 musb_dbg(musb, "RXCSR%d := %04x", epnum, csr);
919 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
920 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
921 }
922 }
923
924 /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to
925 * the end; avoids starvation for other endpoints.
926 */
927 static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep,
928 int is_in)
929 {
930 struct dma_channel *dma;
931 struct urb *urb;
932 void __iomem *mbase = musb->mregs;
933 void __iomem *epio = ep->regs;
934 struct musb_qh *cur_qh, *next_qh;
935 u16 rx_csr, tx_csr;
936
937 musb_ep_select(mbase, ep->epnum);
938 if (is_in) {
939 dma = is_dma_capable() ? ep->rx_channel : NULL;
940
941 /*
942 * Need to stop the transaction by clearing REQPKT first
943 * then the NAK Timeout bit ref MUSBMHDRC USB 2.0 HIGH-SPEED
944 * DUAL-ROLE CONTROLLER Programmer's Guide, section 9.2.2
945 */
946 rx_csr = musb_readw(epio, MUSB_RXCSR);
947 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
948 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
949 musb_writew(epio, MUSB_RXCSR, rx_csr);
950 rx_csr &= ~MUSB_RXCSR_DATAERROR;
951 musb_writew(epio, MUSB_RXCSR, rx_csr);
952
953 cur_qh = first_qh(&musb->in_bulk);
954 } else {
955 dma = is_dma_capable() ? ep->tx_channel : NULL;
956
957 /* clear nak timeout bit */
958 tx_csr = musb_readw(epio, MUSB_TXCSR);
959 tx_csr |= MUSB_TXCSR_H_WZC_BITS;
960 tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT;
961 musb_writew(epio, MUSB_TXCSR, tx_csr);
962
963 cur_qh = first_qh(&musb->out_bulk);
964 }
965 if (cur_qh) {
966 urb = next_urb(cur_qh);
967 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
968 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
969 musb->dma_controller->channel_abort(dma);
970 urb->actual_length += dma->actual_len;
971 dma->actual_len = 0L;
972 }
973 musb_save_toggle(cur_qh, is_in, urb);
974
975 if (is_in) {
976 /* move cur_qh to end of queue */
977 list_move_tail(&cur_qh->ring, &musb->in_bulk);
978
979 /* get the next qh from musb->in_bulk */
980 next_qh = first_qh(&musb->in_bulk);
981
982 /* set rx_reinit and schedule the next qh */
983 ep->rx_reinit = 1;
984 } else {
985 /* move cur_qh to end of queue */
986 list_move_tail(&cur_qh->ring, &musb->out_bulk);
987
988 /* get the next qh from musb->out_bulk */
989 next_qh = first_qh(&musb->out_bulk);
990
991 /* set tx_reinit and schedule the next qh */
992 ep->tx_reinit = 1;
993 }
994
995 if (next_qh)
996 musb_start_urb(musb, is_in, next_qh);
997 }
998 }
999
1000 /*
1001 * Service the default endpoint (ep0) as host.
1002 * Return true until it's time to start the status stage.
1003 */
1004 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
1005 {
1006 bool more = false;
1007 u8 *fifo_dest = NULL;
1008 u16 fifo_count = 0;
1009 struct musb_hw_ep *hw_ep = musb->control_ep;
1010 struct musb_qh *qh = hw_ep->in_qh;
1011 struct usb_ctrlrequest *request;
1012
1013 switch (musb->ep0_stage) {
1014 case MUSB_EP0_IN:
1015 fifo_dest = urb->transfer_buffer + urb->actual_length;
1016 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
1017 urb->actual_length);
1018 if (fifo_count < len)
1019 urb->status = -EOVERFLOW;
1020
1021 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
1022
1023 urb->actual_length += fifo_count;
1024 if (len < qh->maxpacket) {
1025 /* always terminate on short read; it's
1026 * rarely reported as an error.
1027 */
1028 } else if (urb->actual_length <
1029 urb->transfer_buffer_length)
1030 more = true;
1031 break;
1032 case MUSB_EP0_START:
1033 request = (struct usb_ctrlrequest *) urb->setup_packet;
1034
1035 if (!request->wLength) {
1036 musb_dbg(musb, "start no-DATA");
1037 break;
1038 } else if (request->bRequestType & USB_DIR_IN) {
1039 musb_dbg(musb, "start IN-DATA");
1040 musb->ep0_stage = MUSB_EP0_IN;
1041 more = true;
1042 break;
1043 } else {
1044 musb_dbg(musb, "start OUT-DATA");
1045 musb->ep0_stage = MUSB_EP0_OUT;
1046 more = true;
1047 }
1048 /* FALLTHROUGH */
1049 case MUSB_EP0_OUT:
1050 fifo_count = min_t(size_t, qh->maxpacket,
1051 urb->transfer_buffer_length -
1052 urb->actual_length);
1053 if (fifo_count) {
1054 fifo_dest = (u8 *) (urb->transfer_buffer
1055 + urb->actual_length);
1056 musb_dbg(musb, "Sending %d byte%s to ep0 fifo %p",
1057 fifo_count,
1058 (fifo_count == 1) ? "" : "s",
1059 fifo_dest);
1060 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
1061
1062 urb->actual_length += fifo_count;
1063 more = true;
1064 }
1065 break;
1066 default:
1067 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
1068 break;
1069 }
1070
1071 return more;
1072 }
1073
1074 /*
1075 * Handle default endpoint interrupt as host. Only called in IRQ time
1076 * from musb_interrupt().
1077 *
1078 * called with controller irqlocked
1079 */
1080 irqreturn_t musb_h_ep0_irq(struct musb *musb)
1081 {
1082 struct urb *urb;
1083 u16 csr, len;
1084 int status = 0;
1085 void __iomem *mbase = musb->mregs;
1086 struct musb_hw_ep *hw_ep = musb->control_ep;
1087 void __iomem *epio = hw_ep->regs;
1088 struct musb_qh *qh = hw_ep->in_qh;
1089 bool complete = false;
1090 irqreturn_t retval = IRQ_NONE;
1091
1092 /* ep0 only has one queue, "in" */
1093 urb = next_urb(qh);
1094
1095 musb_ep_select(mbase, 0);
1096 csr = musb_readw(epio, MUSB_CSR0);
1097 len = (csr & MUSB_CSR0_RXPKTRDY)
1098 ? musb_readb(epio, MUSB_COUNT0)
1099 : 0;
1100
1101 musb_dbg(musb, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d",
1102 csr, qh, len, urb, musb->ep0_stage);
1103
1104 /* if we just did status stage, we are done */
1105 if (MUSB_EP0_STATUS == musb->ep0_stage) {
1106 retval = IRQ_HANDLED;
1107 complete = true;
1108 }
1109
1110 /* prepare status */
1111 if (csr & MUSB_CSR0_H_RXSTALL) {
1112 musb_dbg(musb, "STALLING ENDPOINT");
1113 status = -EPIPE;
1114
1115 } else if (csr & MUSB_CSR0_H_ERROR) {
1116 musb_dbg(musb, "no response, csr0 %04x", csr);
1117 status = -EPROTO;
1118
1119 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1120 musb_dbg(musb, "control NAK timeout");
1121
1122 /* NOTE: this code path would be a good place to PAUSE a
1123 * control transfer, if another one is queued, so that
1124 * ep0 is more likely to stay busy. That's already done
1125 * for bulk RX transfers.
1126 *
1127 * if (qh->ring.next != &musb->control), then
1128 * we have a candidate... NAKing is *NOT* an error
1129 */
1130 musb_writew(epio, MUSB_CSR0, 0);
1131 retval = IRQ_HANDLED;
1132 }
1133
1134 if (status) {
1135 musb_dbg(musb, "aborting");
1136 retval = IRQ_HANDLED;
1137 if (urb)
1138 urb->status = status;
1139 complete = true;
1140
1141 /* use the proper sequence to abort the transfer */
1142 if (csr & MUSB_CSR0_H_REQPKT) {
1143 csr &= ~MUSB_CSR0_H_REQPKT;
1144 musb_writew(epio, MUSB_CSR0, csr);
1145 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1146 musb_writew(epio, MUSB_CSR0, csr);
1147 } else {
1148 musb_h_ep0_flush_fifo(hw_ep);
1149 }
1150
1151 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1152
1153 /* clear it */
1154 musb_writew(epio, MUSB_CSR0, 0);
1155 }
1156
1157 if (unlikely(!urb)) {
1158 /* stop endpoint since we have no place for its data, this
1159 * SHOULD NEVER HAPPEN! */
1160 ERR("no URB for end 0\n");
1161
1162 musb_h_ep0_flush_fifo(hw_ep);
1163 goto done;
1164 }
1165
1166 if (!complete) {
1167 /* call common logic and prepare response */
1168 if (musb_h_ep0_continue(musb, len, urb)) {
1169 /* more packets required */
1170 csr = (MUSB_EP0_IN == musb->ep0_stage)
1171 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1172 } else {
1173 /* data transfer complete; perform status phase */
1174 if (usb_pipeout(urb->pipe)
1175 || !urb->transfer_buffer_length)
1176 csr = MUSB_CSR0_H_STATUSPKT
1177 | MUSB_CSR0_H_REQPKT;
1178 else
1179 csr = MUSB_CSR0_H_STATUSPKT
1180 | MUSB_CSR0_TXPKTRDY;
1181
1182 /* disable ping token in status phase */
1183 csr |= MUSB_CSR0_H_DIS_PING;
1184
1185 /* flag status stage */
1186 musb->ep0_stage = MUSB_EP0_STATUS;
1187
1188 musb_dbg(musb, "ep0 STATUS, csr %04x", csr);
1189
1190 }
1191 musb_writew(epio, MUSB_CSR0, csr);
1192 retval = IRQ_HANDLED;
1193 } else
1194 musb->ep0_stage = MUSB_EP0_IDLE;
1195
1196 /* call completion handler if done */
1197 if (complete)
1198 musb_advance_schedule(musb, urb, hw_ep, 1);
1199 done:
1200 return retval;
1201 }
1202
1203
1204 #ifdef CONFIG_USB_INVENTRA_DMA
1205
1206 /* Host side TX (OUT) using Mentor DMA works as follows:
1207 submit_urb ->
1208 - if queue was empty, Program Endpoint
1209 - ... which starts DMA to fifo in mode 1 or 0
1210
1211 DMA Isr (transfer complete) -> TxAvail()
1212 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1213 only in musb_cleanup_urb)
1214 - TxPktRdy has to be set in mode 0 or for
1215 short packets in mode 1.
1216 */
1217
1218 #endif
1219
1220 /* Service a Tx-Available or dma completion irq for the endpoint */
1221 void musb_host_tx(struct musb *musb, u8 epnum)
1222 {
1223 int pipe;
1224 bool done = false;
1225 u16 tx_csr;
1226 size_t length = 0;
1227 size_t offset = 0;
1228 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1229 void __iomem *epio = hw_ep->regs;
1230 struct musb_qh *qh = hw_ep->out_qh;
1231 struct urb *urb = next_urb(qh);
1232 u32 status = 0;
1233 void __iomem *mbase = musb->mregs;
1234 struct dma_channel *dma;
1235 bool transfer_pending = false;
1236
1237 musb_ep_select(mbase, epnum);
1238 tx_csr = musb_readw(epio, MUSB_TXCSR);
1239
1240 /* with CPPI, DMA sometimes triggers "extra" irqs */
1241 if (!urb) {
1242 musb_dbg(musb, "extra TX%d ready, csr %04x", epnum, tx_csr);
1243 return;
1244 }
1245
1246 pipe = urb->pipe;
1247 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1248 trace_musb_urb_tx(musb, urb);
1249 musb_dbg(musb, "OUT/TX%d end, csr %04x%s", epnum, tx_csr,
1250 dma ? ", dma" : "");
1251
1252 /* check for errors */
1253 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1254 /* dma was disabled, fifo flushed */
1255 musb_dbg(musb, "TX end %d stall", epnum);
1256
1257 /* stall; record URB status */
1258 status = -EPIPE;
1259
1260 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1261 /* (NON-ISO) dma was disabled, fifo flushed */
1262 musb_dbg(musb, "TX 3strikes on ep=%d", epnum);
1263
1264 status = -ETIMEDOUT;
1265
1266 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1267 if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1
1268 && !list_is_singular(&musb->out_bulk)) {
1269 musb_dbg(musb, "NAK timeout on TX%d ep", epnum);
1270 musb_bulk_nak_timeout(musb, hw_ep, 0);
1271 } else {
1272 musb_dbg(musb, "TX ep%d device not responding", epnum);
1273 /* NOTE: this code path would be a good place to PAUSE a
1274 * transfer, if there's some other (nonperiodic) tx urb
1275 * that could use this fifo. (dma complicates it...)
1276 * That's already done for bulk RX transfers.
1277 *
1278 * if (bulk && qh->ring.next != &musb->out_bulk), then
1279 * we have a candidate... NAKing is *NOT* an error
1280 */
1281 musb_ep_select(mbase, epnum);
1282 musb_writew(epio, MUSB_TXCSR,
1283 MUSB_TXCSR_H_WZC_BITS
1284 | MUSB_TXCSR_TXPKTRDY);
1285 }
1286 return;
1287 }
1288
1289 done:
1290 if (status) {
1291 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1292 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1293 musb->dma_controller->channel_abort(dma);
1294 }
1295
1296 /* do the proper sequence to abort the transfer in the
1297 * usb core; the dma engine should already be stopped.
1298 */
1299 musb_h_tx_flush_fifo(hw_ep);
1300 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1301 | MUSB_TXCSR_DMAENAB
1302 | MUSB_TXCSR_H_ERROR
1303 | MUSB_TXCSR_H_RXSTALL
1304 | MUSB_TXCSR_H_NAKTIMEOUT
1305 );
1306
1307 musb_ep_select(mbase, epnum);
1308 musb_writew(epio, MUSB_TXCSR, tx_csr);
1309 /* REVISIT may need to clear FLUSHFIFO ... */
1310 musb_writew(epio, MUSB_TXCSR, tx_csr);
1311 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1312
1313 done = true;
1314 }
1315
1316 /* second cppi case */
1317 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1318 musb_dbg(musb, "extra TX%d ready, csr %04x", epnum, tx_csr);
1319 return;
1320 }
1321
1322 if (is_dma_capable() && dma && !status) {
1323 /*
1324 * DMA has completed. But if we're using DMA mode 1 (multi
1325 * packet DMA), we need a terminal TXPKTRDY interrupt before
1326 * we can consider this transfer completed, lest we trash
1327 * its last packet when writing the next URB's data. So we
1328 * switch back to mode 0 to get that interrupt; we'll come
1329 * back here once it happens.
1330 */
1331 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1332 /*
1333 * We shouldn't clear DMAMODE with DMAENAB set; so
1334 * clear them in a safe order. That should be OK
1335 * once TXPKTRDY has been set (and I've never seen
1336 * it being 0 at this moment -- DMA interrupt latency
1337 * is significant) but if it hasn't been then we have
1338 * no choice but to stop being polite and ignore the
1339 * programmer's guide... :-)
1340 *
1341 * Note that we must write TXCSR with TXPKTRDY cleared
1342 * in order not to re-trigger the packet send (this bit
1343 * can't be cleared by CPU), and there's another caveat:
1344 * TXPKTRDY may be set shortly and then cleared in the
1345 * double-buffered FIFO mode, so we do an extra TXCSR
1346 * read for debouncing...
1347 */
1348 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1349 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1350 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1351 MUSB_TXCSR_TXPKTRDY);
1352 musb_writew(epio, MUSB_TXCSR,
1353 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1354 }
1355 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1356 MUSB_TXCSR_TXPKTRDY);
1357 musb_writew(epio, MUSB_TXCSR,
1358 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1359
1360 /*
1361 * There is no guarantee that we'll get an interrupt
1362 * after clearing DMAMODE as we might have done this
1363 * too late (after TXPKTRDY was cleared by controller).
1364 * Re-read TXCSR as we have spoiled its previous value.
1365 */
1366 tx_csr = musb_readw(epio, MUSB_TXCSR);
1367 }
1368
1369 /*
1370 * We may get here from a DMA completion or TXPKTRDY interrupt.
1371 * In any case, we must check the FIFO status here and bail out
1372 * only if the FIFO still has data -- that should prevent the
1373 * "missed" TXPKTRDY interrupts and deal with double-buffered
1374 * FIFO mode too...
1375 */
1376 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1377 musb_dbg(musb,
1378 "DMA complete but FIFO not empty, CSR %04x",
1379 tx_csr);
1380 return;
1381 }
1382 }
1383
1384 if (!status || dma || usb_pipeisoc(pipe)) {
1385 if (dma)
1386 length = dma->actual_len;
1387 else
1388 length = qh->segsize;
1389 qh->offset += length;
1390
1391 if (usb_pipeisoc(pipe)) {
1392 struct usb_iso_packet_descriptor *d;
1393
1394 d = urb->iso_frame_desc + qh->iso_idx;
1395 d->actual_length = length;
1396 d->status = status;
1397 if (++qh->iso_idx >= urb->number_of_packets) {
1398 done = true;
1399 } else {
1400 d++;
1401 offset = d->offset;
1402 length = d->length;
1403 }
1404 } else if (dma && urb->transfer_buffer_length == qh->offset) {
1405 done = true;
1406 } else {
1407 /* see if we need to send more data, or ZLP */
1408 if (qh->segsize < qh->maxpacket)
1409 done = true;
1410 else if (qh->offset == urb->transfer_buffer_length
1411 && !(urb->transfer_flags
1412 & URB_ZERO_PACKET))
1413 done = true;
1414 if (!done) {
1415 offset = qh->offset;
1416 length = urb->transfer_buffer_length - offset;
1417 transfer_pending = true;
1418 }
1419 }
1420 }
1421
1422 /* urb->status != -EINPROGRESS means request has been faulted,
1423 * so we must abort this transfer after cleanup
1424 */
1425 if (urb->status != -EINPROGRESS) {
1426 done = true;
1427 if (status == 0)
1428 status = urb->status;
1429 }
1430
1431 if (done) {
1432 /* set status */
1433 urb->status = status;
1434 urb->actual_length = qh->offset;
1435 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1436 return;
1437 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
1438 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
1439 offset, length)) {
1440 if (is_cppi_enabled(musb) || tusb_dma_omap(musb))
1441 musb_h_tx_dma_start(hw_ep);
1442 return;
1443 }
1444 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1445 musb_dbg(musb, "not complete, but DMA enabled?");
1446 return;
1447 }
1448
1449 /*
1450 * PIO: start next packet in this URB.
1451 *
1452 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1453 * (and presumably, FIFO is not half-full) we should write *two*
1454 * packets before updating TXCSR; other docs disagree...
1455 */
1456 if (length > qh->maxpacket)
1457 length = qh->maxpacket;
1458 /* Unmap the buffer so that CPU can use it */
1459 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
1460
1461 /*
1462 * We need to map sg if the transfer_buffer is
1463 * NULL.
1464 */
1465 if (!urb->transfer_buffer) {
1466 /* sg_miter_start is already done in musb_ep_program */
1467 if (!sg_miter_next(&qh->sg_miter)) {
1468 dev_err(musb->controller, "error: sg list empty\n");
1469 sg_miter_stop(&qh->sg_miter);
1470 status = -EINVAL;
1471 goto done;
1472 }
1473 length = min_t(u32, length, qh->sg_miter.length);
1474 musb_write_fifo(hw_ep, length, qh->sg_miter.addr);
1475 qh->sg_miter.consumed = length;
1476 sg_miter_stop(&qh->sg_miter);
1477 } else {
1478 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1479 }
1480
1481 qh->segsize = length;
1482
1483 musb_ep_select(mbase, epnum);
1484 musb_writew(epio, MUSB_TXCSR,
1485 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1486 }
1487
1488 #ifdef CONFIG_USB_TI_CPPI41_DMA
1489 /* Seems to set up ISO for cppi41 and not advance len. See commit c57c41d */
1490 static int musb_rx_dma_iso_cppi41(struct dma_controller *dma,
1491 struct musb_hw_ep *hw_ep,
1492 struct musb_qh *qh,
1493 struct urb *urb,
1494 size_t len)
1495 {
1496 struct dma_channel *channel = hw_ep->rx_channel;
1497 void __iomem *epio = hw_ep->regs;
1498 dma_addr_t *buf;
1499 u32 length;
1500 u16 val;
1501
1502 buf = (void *)urb->iso_frame_desc[qh->iso_idx].offset +
1503 (u32)urb->transfer_dma;
1504
1505 length = urb->iso_frame_desc[qh->iso_idx].length;
1506
1507 val = musb_readw(epio, MUSB_RXCSR);
1508 val |= MUSB_RXCSR_DMAENAB;
1509 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1510
1511 return dma->channel_program(channel, qh->maxpacket, 0,
1512 (u32)buf, length);
1513 }
1514 #else
1515 static inline int musb_rx_dma_iso_cppi41(struct dma_controller *dma,
1516 struct musb_hw_ep *hw_ep,
1517 struct musb_qh *qh,
1518 struct urb *urb,
1519 size_t len)
1520 {
1521 return false;
1522 }
1523 #endif
1524
1525 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) || \
1526 defined(CONFIG_USB_TI_CPPI41_DMA)
1527 /* Host side RX (IN) using Mentor DMA works as follows:
1528 submit_urb ->
1529 - if queue was empty, ProgramEndpoint
1530 - first IN token is sent out (by setting ReqPkt)
1531 LinuxIsr -> RxReady()
1532 /\ => first packet is received
1533 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1534 | -> DMA Isr (transfer complete) -> RxReady()
1535 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1536 | - if urb not complete, send next IN token (ReqPkt)
1537 | | else complete urb.
1538 | |
1539 ---------------------------
1540 *
1541 * Nuances of mode 1:
1542 * For short packets, no ack (+RxPktRdy) is sent automatically
1543 * (even if AutoClear is ON)
1544 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1545 * automatically => major problem, as collecting the next packet becomes
1546 * difficult. Hence mode 1 is not used.
1547 *
1548 * REVISIT
1549 * All we care about at this driver level is that
1550 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1551 * (b) termination conditions are: short RX, or buffer full;
1552 * (c) fault modes include
1553 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1554 * (and that endpoint's dma queue stops immediately)
1555 * - overflow (full, PLUS more bytes in the terminal packet)
1556 *
1557 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1558 * thus be a great candidate for using mode 1 ... for all but the
1559 * last packet of one URB's transfer.
1560 */
1561 static int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
1562 struct musb_hw_ep *hw_ep,
1563 struct musb_qh *qh,
1564 struct urb *urb,
1565 size_t len)
1566 {
1567 struct dma_channel *channel = hw_ep->rx_channel;
1568 void __iomem *epio = hw_ep->regs;
1569 u16 val;
1570 int pipe;
1571 bool done;
1572
1573 pipe = urb->pipe;
1574
1575 if (usb_pipeisoc(pipe)) {
1576 struct usb_iso_packet_descriptor *d;
1577
1578 d = urb->iso_frame_desc + qh->iso_idx;
1579 d->actual_length = len;
1580
1581 /* even if there was an error, we did the dma
1582 * for iso_frame_desc->length
1583 */
1584 if (d->status != -EILSEQ && d->status != -EOVERFLOW)
1585 d->status = 0;
1586
1587 if (++qh->iso_idx >= urb->number_of_packets) {
1588 done = true;
1589 } else {
1590 /* REVISIT: Why ignore return value here? */
1591 if (musb_dma_cppi41(hw_ep->musb))
1592 done = musb_rx_dma_iso_cppi41(dma, hw_ep, qh,
1593 urb, len);
1594 done = false;
1595 }
1596
1597 } else {
1598 /* done if urb buffer is full or short packet is recd */
1599 done = (urb->actual_length + len >=
1600 urb->transfer_buffer_length
1601 || channel->actual_len < qh->maxpacket
1602 || channel->rx_packet_done);
1603 }
1604
1605 /* send IN token for next packet, without AUTOREQ */
1606 if (!done) {
1607 val = musb_readw(epio, MUSB_RXCSR);
1608 val |= MUSB_RXCSR_H_REQPKT;
1609 musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val);
1610 }
1611
1612 return done;
1613 }
1614
1615 /* Disadvantage of using mode 1:
1616 * It's basically usable only for mass storage class; essentially all
1617 * other protocols also terminate transfers on short packets.
1618 *
1619 * Details:
1620 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1621 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1622 * to use the extra IN token to grab the last packet using mode 0, then
1623 * the problem is that you cannot be sure when the device will send the
1624 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1625 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1626 * transfer, while sometimes it is recd just a little late so that if you
1627 * try to configure for mode 0 soon after the mode 1 transfer is
1628 * completed, you will find rxcount 0. Okay, so you might think why not
1629 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1630 */
1631 static int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma,
1632 struct musb_hw_ep *hw_ep,
1633 struct musb_qh *qh,
1634 struct urb *urb,
1635 size_t len,
1636 u8 iso_err)
1637 {
1638 struct musb *musb = hw_ep->musb;
1639 void __iomem *epio = hw_ep->regs;
1640 struct dma_channel *channel = hw_ep->rx_channel;
1641 u16 rx_count, val;
1642 int length, pipe, done;
1643 dma_addr_t buf;
1644
1645 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1646 pipe = urb->pipe;
1647
1648 if (usb_pipeisoc(pipe)) {
1649 int d_status = 0;
1650 struct usb_iso_packet_descriptor *d;
1651
1652 d = urb->iso_frame_desc + qh->iso_idx;
1653
1654 if (iso_err) {
1655 d_status = -EILSEQ;
1656 urb->error_count++;
1657 }
1658 if (rx_count > d->length) {
1659 if (d_status == 0) {
1660 d_status = -EOVERFLOW;
1661 urb->error_count++;
1662 }
1663 musb_dbg(musb, "** OVERFLOW %d into %d",
1664 rx_count, d->length);
1665
1666 length = d->length;
1667 } else
1668 length = rx_count;
1669 d->status = d_status;
1670 buf = urb->transfer_dma + d->offset;
1671 } else {
1672 length = rx_count;
1673 buf = urb->transfer_dma + urb->actual_length;
1674 }
1675
1676 channel->desired_mode = 0;
1677 #ifdef USE_MODE1
1678 /* because of the issue below, mode 1 will
1679 * only rarely behave with correct semantics.
1680 */
1681 if ((urb->transfer_flags & URB_SHORT_NOT_OK)
1682 && (urb->transfer_buffer_length - urb->actual_length)
1683 > qh->maxpacket)
1684 channel->desired_mode = 1;
1685 if (rx_count < hw_ep->max_packet_sz_rx) {
1686 length = rx_count;
1687 channel->desired_mode = 0;
1688 } else {
1689 length = urb->transfer_buffer_length;
1690 }
1691 #endif
1692
1693 /* See comments above on disadvantages of using mode 1 */
1694 val = musb_readw(epio, MUSB_RXCSR);
1695 val &= ~MUSB_RXCSR_H_REQPKT;
1696
1697 if (channel->desired_mode == 0)
1698 val &= ~MUSB_RXCSR_H_AUTOREQ;
1699 else
1700 val |= MUSB_RXCSR_H_AUTOREQ;
1701 val |= MUSB_RXCSR_DMAENAB;
1702
1703 /* autoclear shouldn't be set in high bandwidth */
1704 if (qh->hb_mult == 1)
1705 val |= MUSB_RXCSR_AUTOCLEAR;
1706
1707 musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val);
1708
1709 /* REVISIT if when actual_length != 0,
1710 * transfer_buffer_length needs to be
1711 * adjusted first...
1712 */
1713 done = dma->channel_program(channel, qh->maxpacket,
1714 channel->desired_mode,
1715 buf, length);
1716
1717 if (!done) {
1718 dma->channel_release(channel);
1719 hw_ep->rx_channel = NULL;
1720 channel = NULL;
1721 val = musb_readw(epio, MUSB_RXCSR);
1722 val &= ~(MUSB_RXCSR_DMAENAB
1723 | MUSB_RXCSR_H_AUTOREQ
1724 | MUSB_RXCSR_AUTOCLEAR);
1725 musb_writew(epio, MUSB_RXCSR, val);
1726 }
1727
1728 return done;
1729 }
1730 #else
1731 static inline int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
1732 struct musb_hw_ep *hw_ep,
1733 struct musb_qh *qh,
1734 struct urb *urb,
1735 size_t len)
1736 {
1737 return false;
1738 }
1739
1740 static inline int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma,
1741 struct musb_hw_ep *hw_ep,
1742 struct musb_qh *qh,
1743 struct urb *urb,
1744 size_t len,
1745 u8 iso_err)
1746 {
1747 return false;
1748 }
1749 #endif
1750
1751 /*
1752 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1753 * and high-bandwidth IN transfer cases.
1754 */
1755 void musb_host_rx(struct musb *musb, u8 epnum)
1756 {
1757 struct urb *urb;
1758 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1759 struct dma_controller *c = musb->dma_controller;
1760 void __iomem *epio = hw_ep->regs;
1761 struct musb_qh *qh = hw_ep->in_qh;
1762 size_t xfer_len;
1763 void __iomem *mbase = musb->mregs;
1764 u16 rx_csr, val;
1765 bool iso_err = false;
1766 bool done = false;
1767 u32 status;
1768 struct dma_channel *dma;
1769 unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG;
1770
1771 musb_ep_select(mbase, epnum);
1772
1773 urb = next_urb(qh);
1774 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1775 status = 0;
1776 xfer_len = 0;
1777
1778 rx_csr = musb_readw(epio, MUSB_RXCSR);
1779 val = rx_csr;
1780
1781 if (unlikely(!urb)) {
1782 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1783 * usbtest #11 (unlinks) triggers it regularly, sometimes
1784 * with fifo full. (Only with DMA??)
1785 */
1786 musb_dbg(musb, "BOGUS RX%d ready, csr %04x, count %d",
1787 epnum, val, musb_readw(epio, MUSB_RXCOUNT));
1788 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1789 return;
1790 }
1791
1792 trace_musb_urb_rx(musb, urb);
1793
1794 /* check for errors, concurrent stall & unlink is not really
1795 * handled yet! */
1796 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1797 musb_dbg(musb, "RX end %d STALL", epnum);
1798
1799 /* stall; record URB status */
1800 status = -EPIPE;
1801
1802 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1803 musb_dbg(musb, "end %d RX proto error", epnum);
1804
1805 status = -EPROTO;
1806 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1807
1808 rx_csr &= ~MUSB_RXCSR_H_ERROR;
1809 musb_writew(epio, MUSB_RXCSR, rx_csr);
1810
1811 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1812
1813 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1814 musb_dbg(musb, "RX end %d NAK timeout", epnum);
1815
1816 /* NOTE: NAKing is *NOT* an error, so we want to
1817 * continue. Except ... if there's a request for
1818 * another QH, use that instead of starving it.
1819 *
1820 * Devices like Ethernet and serial adapters keep
1821 * reads posted at all times, which will starve
1822 * other devices without this logic.
1823 */
1824 if (usb_pipebulk(urb->pipe)
1825 && qh->mux == 1
1826 && !list_is_singular(&musb->in_bulk)) {
1827 musb_bulk_nak_timeout(musb, hw_ep, 1);
1828 return;
1829 }
1830 musb_ep_select(mbase, epnum);
1831 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1832 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1833 musb_writew(epio, MUSB_RXCSR, rx_csr);
1834
1835 goto finish;
1836 } else {
1837 musb_dbg(musb, "RX end %d ISO data error", epnum);
1838 /* packet error reported later */
1839 iso_err = true;
1840 }
1841 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1842 musb_dbg(musb, "end %d high bandwidth incomplete ISO packet RX",
1843 epnum);
1844 status = -EPROTO;
1845 }
1846
1847 /* faults abort the transfer */
1848 if (status) {
1849 /* clean up dma and collect transfer count */
1850 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1851 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1852 musb->dma_controller->channel_abort(dma);
1853 xfer_len = dma->actual_len;
1854 }
1855 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1856 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1857 done = true;
1858 goto finish;
1859 }
1860
1861 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1862 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1863 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1864 goto finish;
1865 }
1866
1867 /* thorough shutdown for now ... given more precise fault handling
1868 * and better queueing support, we might keep a DMA pipeline going
1869 * while processing this irq for earlier completions.
1870 */
1871
1872 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1873 if (!musb_dma_inventra(musb) && !musb_dma_ux500(musb) &&
1874 (rx_csr & MUSB_RXCSR_H_REQPKT)) {
1875 /* REVISIT this happened for a while on some short reads...
1876 * the cleanup still needs investigation... looks bad...
1877 * and also duplicates dma cleanup code above ... plus,
1878 * shouldn't this be the "half full" double buffer case?
1879 */
1880 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1881 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1882 musb->dma_controller->channel_abort(dma);
1883 xfer_len = dma->actual_len;
1884 done = true;
1885 }
1886
1887 musb_dbg(musb, "RXCSR%d %04x, reqpkt, len %zu%s", epnum, rx_csr,
1888 xfer_len, dma ? ", dma" : "");
1889 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1890
1891 musb_ep_select(mbase, epnum);
1892 musb_writew(epio, MUSB_RXCSR,
1893 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1894 }
1895
1896 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1897 xfer_len = dma->actual_len;
1898
1899 val &= ~(MUSB_RXCSR_DMAENAB
1900 | MUSB_RXCSR_H_AUTOREQ
1901 | MUSB_RXCSR_AUTOCLEAR
1902 | MUSB_RXCSR_RXPKTRDY);
1903 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1904
1905 if (musb_dma_inventra(musb) || musb_dma_ux500(musb) ||
1906 musb_dma_cppi41(musb)) {
1907 done = musb_rx_dma_inventra_cppi41(c, hw_ep, qh, urb, xfer_len);
1908 musb_dbg(hw_ep->musb,
1909 "ep %d dma %s, rxcsr %04x, rxcount %d",
1910 epnum, done ? "off" : "reset",
1911 musb_readw(epio, MUSB_RXCSR),
1912 musb_readw(epio, MUSB_RXCOUNT));
1913 } else {
1914 done = true;
1915 }
1916
1917 } else if (urb->status == -EINPROGRESS) {
1918 /* if no errors, be sure a packet is ready for unloading */
1919 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1920 status = -EPROTO;
1921 ERR("Rx interrupt with no errors or packet!\n");
1922
1923 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1924
1925 /* SCRUB (RX) */
1926 /* do the proper sequence to abort the transfer */
1927 musb_ep_select(mbase, epnum);
1928 val &= ~MUSB_RXCSR_H_REQPKT;
1929 musb_writew(epio, MUSB_RXCSR, val);
1930 goto finish;
1931 }
1932
1933 /* we are expecting IN packets */
1934 if ((musb_dma_inventra(musb) || musb_dma_ux500(musb) ||
1935 musb_dma_cppi41(musb)) && dma) {
1936 musb_dbg(hw_ep->musb,
1937 "RX%d count %d, buffer 0x%llx len %d/%d",
1938 epnum, musb_readw(epio, MUSB_RXCOUNT),
1939 (unsigned long long) urb->transfer_dma
1940 + urb->actual_length,
1941 qh->offset,
1942 urb->transfer_buffer_length);
1943
1944 if (musb_rx_dma_in_inventra_cppi41(c, hw_ep, qh, urb,
1945 xfer_len, iso_err))
1946 goto finish;
1947 else
1948 dev_err(musb->controller, "error: rx_dma failed\n");
1949 }
1950
1951 if (!dma) {
1952 unsigned int received_len;
1953
1954 /* Unmap the buffer so that CPU can use it */
1955 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
1956
1957 /*
1958 * We need to map sg if the transfer_buffer is
1959 * NULL.
1960 */
1961 if (!urb->transfer_buffer) {
1962 qh->use_sg = true;
1963 sg_miter_start(&qh->sg_miter, urb->sg, 1,
1964 sg_flags);
1965 }
1966
1967 if (qh->use_sg) {
1968 if (!sg_miter_next(&qh->sg_miter)) {
1969 dev_err(musb->controller, "error: sg list empty\n");
1970 sg_miter_stop(&qh->sg_miter);
1971 status = -EINVAL;
1972 done = true;
1973 goto finish;
1974 }
1975 urb->transfer_buffer = qh->sg_miter.addr;
1976 received_len = urb->actual_length;
1977 qh->offset = 0x0;
1978 done = musb_host_packet_rx(musb, urb, epnum,
1979 iso_err);
1980 /* Calculate the number of bytes received */
1981 received_len = urb->actual_length -
1982 received_len;
1983 qh->sg_miter.consumed = received_len;
1984 sg_miter_stop(&qh->sg_miter);
1985 } else {
1986 done = musb_host_packet_rx(musb, urb,
1987 epnum, iso_err);
1988 }
1989 musb_dbg(musb, "read %spacket", done ? "last " : "");
1990 }
1991 }
1992
1993 finish:
1994 urb->actual_length += xfer_len;
1995 qh->offset += xfer_len;
1996 if (done) {
1997 if (qh->use_sg) {
1998 qh->use_sg = false;
1999 urb->transfer_buffer = NULL;
2000 }
2001
2002 if (urb->status == -EINPROGRESS)
2003 urb->status = status;
2004 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
2005 }
2006 }
2007
2008 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
2009 * the software schedule associates multiple such nodes with a given
2010 * host side hardware endpoint + direction; scheduling may activate
2011 * that hardware endpoint.
2012 */
2013 static int musb_schedule(
2014 struct musb *musb,
2015 struct musb_qh *qh,
2016 int is_in)
2017 {
2018 int idle = 0;
2019 int best_diff;
2020 int best_end, epnum;
2021 struct musb_hw_ep *hw_ep = NULL;
2022 struct list_head *head = NULL;
2023 u8 toggle;
2024 u8 txtype;
2025 struct urb *urb = next_urb(qh);
2026
2027 /* use fixed hardware for control and bulk */
2028 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
2029 head = &musb->control;
2030 hw_ep = musb->control_ep;
2031 goto success;
2032 }
2033
2034 /* else, periodic transfers get muxed to other endpoints */
2035
2036 /*
2037 * We know this qh hasn't been scheduled, so all we need to do
2038 * is choose which hardware endpoint to put it on ...
2039 *
2040 * REVISIT what we really want here is a regular schedule tree
2041 * like e.g. OHCI uses.
2042 */
2043 best_diff = 4096;
2044 best_end = -1;
2045
2046 for (epnum = 1, hw_ep = musb->endpoints + 1;
2047 epnum < musb->nr_endpoints;
2048 epnum++, hw_ep++) {
2049 int diff;
2050
2051 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
2052 continue;
2053
2054 if (hw_ep == musb->bulk_ep)
2055 continue;
2056
2057 if (is_in)
2058 diff = hw_ep->max_packet_sz_rx;
2059 else
2060 diff = hw_ep->max_packet_sz_tx;
2061 diff -= (qh->maxpacket * qh->hb_mult);
2062
2063 if (diff >= 0 && best_diff > diff) {
2064
2065 /*
2066 * Mentor controller has a bug in that if we schedule
2067 * a BULK Tx transfer on an endpoint that had earlier
2068 * handled ISOC then the BULK transfer has to start on
2069 * a zero toggle. If the BULK transfer starts on a 1
2070 * toggle then this transfer will fail as the mentor
2071 * controller starts the Bulk transfer on a 0 toggle
2072 * irrespective of the programming of the toggle bits
2073 * in the TXCSR register. Check for this condition
2074 * while allocating the EP for a Tx Bulk transfer. If
2075 * so skip this EP.
2076 */
2077 hw_ep = musb->endpoints + epnum;
2078 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
2079 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
2080 >> 4) & 0x3;
2081 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
2082 toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
2083 continue;
2084
2085 best_diff = diff;
2086 best_end = epnum;
2087 }
2088 }
2089 /* use bulk reserved ep1 if no other ep is free */
2090 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
2091 hw_ep = musb->bulk_ep;
2092 if (is_in)
2093 head = &musb->in_bulk;
2094 else
2095 head = &musb->out_bulk;
2096
2097 /* Enable bulk RX/TX NAK timeout scheme when bulk requests are
2098 * multiplexed. This scheme does not work in high speed to full
2099 * speed scenario as NAK interrupts are not coming from a
2100 * full speed device connected to a high speed device.
2101 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
2102 * 4 (8 frame or 8ms) for FS device.
2103 */
2104 if (qh->dev)
2105 qh->intv_reg =
2106 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
2107 goto success;
2108 } else if (best_end < 0) {
2109 dev_err(musb->controller,
2110 "%s hwep alloc failed for %dx%d\n",
2111 musb_ep_xfertype_string(qh->type),
2112 qh->hb_mult, qh->maxpacket);
2113 return -ENOSPC;
2114 }
2115
2116 idle = 1;
2117 qh->mux = 0;
2118 hw_ep = musb->endpoints + best_end;
2119 musb_dbg(musb, "qh %p periodic slot %d", qh, best_end);
2120 success:
2121 if (head) {
2122 idle = list_empty(head);
2123 list_add_tail(&qh->ring, head);
2124 qh->mux = 1;
2125 }
2126 qh->hw_ep = hw_ep;
2127 qh->hep->hcpriv = qh;
2128 if (idle)
2129 musb_start_urb(musb, is_in, qh);
2130 return 0;
2131 }
2132
2133 static int musb_urb_enqueue(
2134 struct usb_hcd *hcd,
2135 struct urb *urb,
2136 gfp_t mem_flags)
2137 {
2138 unsigned long flags;
2139 struct musb *musb = hcd_to_musb(hcd);
2140 struct usb_host_endpoint *hep = urb->ep;
2141 struct musb_qh *qh;
2142 struct usb_endpoint_descriptor *epd = &hep->desc;
2143 int ret;
2144 unsigned type_reg;
2145 unsigned interval;
2146
2147 /* host role must be active */
2148 if (!is_host_active(musb) || !musb->is_active)
2149 return -ENODEV;
2150
2151 trace_musb_urb_enq(musb, urb);
2152
2153 spin_lock_irqsave(&musb->lock, flags);
2154 ret = usb_hcd_link_urb_to_ep(hcd, urb);
2155 qh = ret ? NULL : hep->hcpriv;
2156 if (qh)
2157 urb->hcpriv = qh;
2158 spin_unlock_irqrestore(&musb->lock, flags);
2159
2160 /* DMA mapping was already done, if needed, and this urb is on
2161 * hep->urb_list now ... so we're done, unless hep wasn't yet
2162 * scheduled onto a live qh.
2163 *
2164 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
2165 * disabled, testing for empty qh->ring and avoiding qh setup costs
2166 * except for the first urb queued after a config change.
2167 */
2168 if (qh || ret)
2169 return ret;
2170
2171 /* Allocate and initialize qh, minimizing the work done each time
2172 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
2173 *
2174 * REVISIT consider a dedicated qh kmem_cache, so it's harder
2175 * for bugs in other kernel code to break this driver...
2176 */
2177 qh = kzalloc(sizeof *qh, mem_flags);
2178 if (!qh) {
2179 spin_lock_irqsave(&musb->lock, flags);
2180 usb_hcd_unlink_urb_from_ep(hcd, urb);
2181 spin_unlock_irqrestore(&musb->lock, flags);
2182 return -ENOMEM;
2183 }
2184
2185 qh->hep = hep;
2186 qh->dev = urb->dev;
2187 INIT_LIST_HEAD(&qh->ring);
2188 qh->is_ready = 1;
2189
2190 qh->maxpacket = usb_endpoint_maxp(epd);
2191 qh->type = usb_endpoint_type(epd);
2192
2193 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
2194 * Some musb cores don't support high bandwidth ISO transfers; and
2195 * we don't (yet!) support high bandwidth interrupt transfers.
2196 */
2197 qh->hb_mult = usb_endpoint_maxp_mult(epd);
2198 if (qh->hb_mult > 1) {
2199 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
2200
2201 if (ok)
2202 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
2203 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
2204 if (!ok) {
2205 dev_err(musb->controller,
2206 "high bandwidth %s (%dx%d) not supported\n",
2207 musb_ep_xfertype_string(qh->type),
2208 qh->hb_mult, qh->maxpacket & 0x7ff);
2209 ret = -EMSGSIZE;
2210 goto done;
2211 }
2212 qh->maxpacket &= 0x7ff;
2213 }
2214
2215 qh->epnum = usb_endpoint_num(epd);
2216
2217 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
2218 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
2219
2220 /* precompute rxtype/txtype/type0 register */
2221 type_reg = (qh->type << 4) | qh->epnum;
2222 switch (urb->dev->speed) {
2223 case USB_SPEED_LOW:
2224 type_reg |= 0xc0;
2225 break;
2226 case USB_SPEED_FULL:
2227 type_reg |= 0x80;
2228 break;
2229 default:
2230 type_reg |= 0x40;
2231 }
2232 qh->type_reg = type_reg;
2233
2234 /* Precompute RXINTERVAL/TXINTERVAL register */
2235 switch (qh->type) {
2236 case USB_ENDPOINT_XFER_INT:
2237 /*
2238 * Full/low speeds use the linear encoding,
2239 * high speed uses the logarithmic encoding.
2240 */
2241 if (urb->dev->speed <= USB_SPEED_FULL) {
2242 interval = max_t(u8, epd->bInterval, 1);
2243 break;
2244 }
2245 /* FALLTHROUGH */
2246 case USB_ENDPOINT_XFER_ISOC:
2247 /* ISO always uses logarithmic encoding */
2248 interval = min_t(u8, epd->bInterval, 16);
2249 break;
2250 default:
2251 /* REVISIT we actually want to use NAK limits, hinting to the
2252 * transfer scheduling logic to try some other qh, e.g. try
2253 * for 2 msec first:
2254 *
2255 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
2256 *
2257 * The downside of disabling this is that transfer scheduling
2258 * gets VERY unfair for nonperiodic transfers; a misbehaving
2259 * peripheral could make that hurt. That's perfectly normal
2260 * for reads from network or serial adapters ... so we have
2261 * partial NAKlimit support for bulk RX.
2262 *
2263 * The upside of disabling it is simpler transfer scheduling.
2264 */
2265 interval = 0;
2266 }
2267 qh->intv_reg = interval;
2268
2269 /* precompute addressing for external hub/tt ports */
2270 if (musb->is_multipoint) {
2271 struct usb_device *parent = urb->dev->parent;
2272
2273 if (parent != hcd->self.root_hub) {
2274 qh->h_addr_reg = (u8) parent->devnum;
2275
2276 /* set up tt info if needed */
2277 if (urb->dev->tt) {
2278 qh->h_port_reg = (u8) urb->dev->ttport;
2279 if (urb->dev->tt->hub)
2280 qh->h_addr_reg =
2281 (u8) urb->dev->tt->hub->devnum;
2282 if (urb->dev->tt->multi)
2283 qh->h_addr_reg |= 0x80;
2284 }
2285 }
2286 }
2287
2288 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2289 * until we get real dma queues (with an entry for each urb/buffer),
2290 * we only have work to do in the former case.
2291 */
2292 spin_lock_irqsave(&musb->lock, flags);
2293 if (hep->hcpriv || !next_urb(qh)) {
2294 /* some concurrent activity submitted another urb to hep...
2295 * odd, rare, error prone, but legal.
2296 */
2297 kfree(qh);
2298 qh = NULL;
2299 ret = 0;
2300 } else
2301 ret = musb_schedule(musb, qh,
2302 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2303
2304 if (ret == 0) {
2305 urb->hcpriv = qh;
2306 /* FIXME set urb->start_frame for iso/intr, it's tested in
2307 * musb_start_urb(), but otherwise only konicawc cares ...
2308 */
2309 }
2310 spin_unlock_irqrestore(&musb->lock, flags);
2311
2312 done:
2313 if (ret != 0) {
2314 spin_lock_irqsave(&musb->lock, flags);
2315 usb_hcd_unlink_urb_from_ep(hcd, urb);
2316 spin_unlock_irqrestore(&musb->lock, flags);
2317 kfree(qh);
2318 }
2319 return ret;
2320 }
2321
2322
2323 /*
2324 * abort a transfer that's at the head of a hardware queue.
2325 * called with controller locked, irqs blocked
2326 * that hardware queue advances to the next transfer, unless prevented
2327 */
2328 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2329 {
2330 struct musb_hw_ep *ep = qh->hw_ep;
2331 struct musb *musb = ep->musb;
2332 void __iomem *epio = ep->regs;
2333 unsigned hw_end = ep->epnum;
2334 void __iomem *regs = ep->musb->mregs;
2335 int is_in = usb_pipein(urb->pipe);
2336 int status = 0;
2337 u16 csr;
2338 struct dma_channel *dma = NULL;
2339
2340 musb_ep_select(regs, hw_end);
2341
2342 if (is_dma_capable()) {
2343 dma = is_in ? ep->rx_channel : ep->tx_channel;
2344 if (dma) {
2345 status = ep->musb->dma_controller->channel_abort(dma);
2346 musb_dbg(musb, "abort %cX%d DMA for urb %p --> %d",
2347 is_in ? 'R' : 'T', ep->epnum,
2348 urb, status);
2349 urb->actual_length += dma->actual_len;
2350 }
2351 }
2352
2353 /* turn off DMA requests, discard state, stop polling ... */
2354 if (ep->epnum && is_in) {
2355 /* giveback saves bulk toggle */
2356 csr = musb_h_flush_rxfifo(ep, 0);
2357
2358 /* clear the endpoint's irq status here to avoid bogus irqs */
2359 if (is_dma_capable() && dma)
2360 musb_platform_clear_ep_rxintr(musb, ep->epnum);
2361 } else if (ep->epnum) {
2362 musb_h_tx_flush_fifo(ep);
2363 csr = musb_readw(epio, MUSB_TXCSR);
2364 csr &= ~(MUSB_TXCSR_AUTOSET
2365 | MUSB_TXCSR_DMAENAB
2366 | MUSB_TXCSR_H_RXSTALL
2367 | MUSB_TXCSR_H_NAKTIMEOUT
2368 | MUSB_TXCSR_H_ERROR
2369 | MUSB_TXCSR_TXPKTRDY);
2370 musb_writew(epio, MUSB_TXCSR, csr);
2371 /* REVISIT may need to clear FLUSHFIFO ... */
2372 musb_writew(epio, MUSB_TXCSR, csr);
2373 /* flush cpu writebuffer */
2374 csr = musb_readw(epio, MUSB_TXCSR);
2375 } else {
2376 musb_h_ep0_flush_fifo(ep);
2377 }
2378 if (status == 0)
2379 musb_advance_schedule(ep->musb, urb, ep, is_in);
2380 return status;
2381 }
2382
2383 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2384 {
2385 struct musb *musb = hcd_to_musb(hcd);
2386 struct musb_qh *qh;
2387 unsigned long flags;
2388 int is_in = usb_pipein(urb->pipe);
2389 int ret;
2390
2391 trace_musb_urb_deq(musb, urb);
2392
2393 spin_lock_irqsave(&musb->lock, flags);
2394 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2395 if (ret)
2396 goto done;
2397
2398 qh = urb->hcpriv;
2399 if (!qh)
2400 goto done;
2401
2402 /*
2403 * Any URB not actively programmed into endpoint hardware can be
2404 * immediately given back; that's any URB not at the head of an
2405 * endpoint queue, unless someday we get real DMA queues. And even
2406 * if it's at the head, it might not be known to the hardware...
2407 *
2408 * Otherwise abort current transfer, pending DMA, etc.; urb->status
2409 * has already been updated. This is a synchronous abort; it'd be
2410 * OK to hold off until after some IRQ, though.
2411 *
2412 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
2413 */
2414 if (!qh->is_ready
2415 || urb->urb_list.prev != &qh->hep->urb_list
2416 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2417 int ready = qh->is_ready;
2418
2419 qh->is_ready = 0;
2420 musb_giveback(musb, urb, 0);
2421 qh->is_ready = ready;
2422
2423 /* If nothing else (usually musb_giveback) is using it
2424 * and its URB list has emptied, recycle this qh.
2425 */
2426 if (ready && list_empty(&qh->hep->urb_list)) {
2427 qh->hep->hcpriv = NULL;
2428 list_del(&qh->ring);
2429 kfree(qh);
2430 }
2431 } else
2432 ret = musb_cleanup_urb(urb, qh);
2433 done:
2434 spin_unlock_irqrestore(&musb->lock, flags);
2435 return ret;
2436 }
2437
2438 /* disable an endpoint */
2439 static void
2440 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2441 {
2442 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2443 unsigned long flags;
2444 struct musb *musb = hcd_to_musb(hcd);
2445 struct musb_qh *qh;
2446 struct urb *urb;
2447
2448 spin_lock_irqsave(&musb->lock, flags);
2449
2450 qh = hep->hcpriv;
2451 if (qh == NULL)
2452 goto exit;
2453
2454 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2455
2456 /* Kick the first URB off the hardware, if needed */
2457 qh->is_ready = 0;
2458 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2459 urb = next_urb(qh);
2460
2461 /* make software (then hardware) stop ASAP */
2462 if (!urb->unlinked)
2463 urb->status = -ESHUTDOWN;
2464
2465 /* cleanup */
2466 musb_cleanup_urb(urb, qh);
2467
2468 /* Then nuke all the others ... and advance the
2469 * queue on hw_ep (e.g. bulk ring) when we're done.
2470 */
2471 while (!list_empty(&hep->urb_list)) {
2472 urb = next_urb(qh);
2473 urb->status = -ESHUTDOWN;
2474 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2475 }
2476 } else {
2477 /* Just empty the queue; the hardware is busy with
2478 * other transfers, and since !qh->is_ready nothing
2479 * will activate any of these as it advances.
2480 */
2481 while (!list_empty(&hep->urb_list))
2482 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2483
2484 hep->hcpriv = NULL;
2485 list_del(&qh->ring);
2486 kfree(qh);
2487 }
2488 exit:
2489 spin_unlock_irqrestore(&musb->lock, flags);
2490 }
2491
2492 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2493 {
2494 struct musb *musb = hcd_to_musb(hcd);
2495
2496 return musb_readw(musb->mregs, MUSB_FRAME);
2497 }
2498
2499 static int musb_h_start(struct usb_hcd *hcd)
2500 {
2501 struct musb *musb = hcd_to_musb(hcd);
2502
2503 /* NOTE: musb_start() is called when the hub driver turns
2504 * on port power, or when (OTG) peripheral starts.
2505 */
2506 hcd->state = HC_STATE_RUNNING;
2507 musb->port1_status = 0;
2508 return 0;
2509 }
2510
2511 static void musb_h_stop(struct usb_hcd *hcd)
2512 {
2513 musb_stop(hcd_to_musb(hcd));
2514 hcd->state = HC_STATE_HALT;
2515 }
2516
2517 static int musb_bus_suspend(struct usb_hcd *hcd)
2518 {
2519 struct musb *musb = hcd_to_musb(hcd);
2520 u8 devctl;
2521 int ret;
2522
2523 ret = musb_port_suspend(musb, true);
2524 if (ret)
2525 return ret;
2526
2527 if (!is_host_active(musb))
2528 return 0;
2529
2530 switch (musb->xceiv->otg->state) {
2531 case OTG_STATE_A_SUSPEND:
2532 return 0;
2533 case OTG_STATE_A_WAIT_VRISE:
2534 /* ID could be grounded even if there's no device
2535 * on the other end of the cable. NOTE that the
2536 * A_WAIT_VRISE timers are messy with MUSB...
2537 */
2538 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2539 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2540 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
2541 break;
2542 default:
2543 break;
2544 }
2545
2546 if (musb->is_active) {
2547 WARNING("trying to suspend as %s while active\n",
2548 usb_otg_state_string(musb->xceiv->otg->state));
2549 return -EBUSY;
2550 } else
2551 return 0;
2552 }
2553
2554 static int musb_bus_resume(struct usb_hcd *hcd)
2555 {
2556 struct musb *musb = hcd_to_musb(hcd);
2557
2558 if (musb->config &&
2559 musb->config->host_port_deassert_reset_at_resume)
2560 musb_port_reset(musb, false);
2561
2562 return 0;
2563 }
2564
2565 #ifndef CONFIG_MUSB_PIO_ONLY
2566
2567 #define MUSB_USB_DMA_ALIGN 4
2568
2569 struct musb_temp_buffer {
2570 void *kmalloc_ptr;
2571 void *old_xfer_buffer;
2572 u8 data[0];
2573 };
2574
2575 static void musb_free_temp_buffer(struct urb *urb)
2576 {
2577 enum dma_data_direction dir;
2578 struct musb_temp_buffer *temp;
2579 size_t length;
2580
2581 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2582 return;
2583
2584 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2585
2586 temp = container_of(urb->transfer_buffer, struct musb_temp_buffer,
2587 data);
2588
2589 if (dir == DMA_FROM_DEVICE) {
2590 if (usb_pipeisoc(urb->pipe))
2591 length = urb->transfer_buffer_length;
2592 else
2593 length = urb->actual_length;
2594
2595 memcpy(temp->old_xfer_buffer, temp->data, length);
2596 }
2597 urb->transfer_buffer = temp->old_xfer_buffer;
2598 kfree(temp->kmalloc_ptr);
2599
2600 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2601 }
2602
2603 static int musb_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
2604 {
2605 enum dma_data_direction dir;
2606 struct musb_temp_buffer *temp;
2607 void *kmalloc_ptr;
2608 size_t kmalloc_size;
2609
2610 if (urb->num_sgs || urb->sg ||
2611 urb->transfer_buffer_length == 0 ||
2612 !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1)))
2613 return 0;
2614
2615 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2616
2617 /* Allocate a buffer with enough padding for alignment */
2618 kmalloc_size = urb->transfer_buffer_length +
2619 sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1;
2620
2621 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2622 if (!kmalloc_ptr)
2623 return -ENOMEM;
2624
2625 /* Position our struct temp_buffer such that data is aligned */
2626 temp = PTR_ALIGN(kmalloc_ptr, MUSB_USB_DMA_ALIGN);
2627
2628
2629 temp->kmalloc_ptr = kmalloc_ptr;
2630 temp->old_xfer_buffer = urb->transfer_buffer;
2631 if (dir == DMA_TO_DEVICE)
2632 memcpy(temp->data, urb->transfer_buffer,
2633 urb->transfer_buffer_length);
2634 urb->transfer_buffer = temp->data;
2635
2636 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2637
2638 return 0;
2639 }
2640
2641 static int musb_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2642 gfp_t mem_flags)
2643 {
2644 struct musb *musb = hcd_to_musb(hcd);
2645 int ret;
2646
2647 /*
2648 * The DMA engine in RTL1.8 and above cannot handle
2649 * DMA addresses that are not aligned to a 4 byte boundary.
2650 * For such engine implemented (un)map_urb_for_dma hooks.
2651 * Do not use these hooks for RTL<1.8
2652 */
2653 if (musb->hwvers < MUSB_HWVERS_1800)
2654 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2655
2656 ret = musb_alloc_temp_buffer(urb, mem_flags);
2657 if (ret)
2658 return ret;
2659
2660 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2661 if (ret)
2662 musb_free_temp_buffer(urb);
2663
2664 return ret;
2665 }
2666
2667 static void musb_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2668 {
2669 struct musb *musb = hcd_to_musb(hcd);
2670
2671 usb_hcd_unmap_urb_for_dma(hcd, urb);
2672
2673 /* Do not use this hook for RTL<1.8 (see description above) */
2674 if (musb->hwvers < MUSB_HWVERS_1800)
2675 return;
2676
2677 musb_free_temp_buffer(urb);
2678 }
2679 #endif /* !CONFIG_MUSB_PIO_ONLY */
2680
2681 static const struct hc_driver musb_hc_driver = {
2682 .description = "musb-hcd",
2683 .product_desc = "MUSB HDRC host driver",
2684 .hcd_priv_size = sizeof(struct musb *),
2685 .flags = HCD_USB2 | HCD_DMA | HCD_MEMORY,
2686
2687 /* not using irq handler or reset hooks from usbcore, since
2688 * those must be shared with peripheral code for OTG configs
2689 */
2690
2691 .start = musb_h_start,
2692 .stop = musb_h_stop,
2693
2694 .get_frame_number = musb_h_get_frame_number,
2695
2696 .urb_enqueue = musb_urb_enqueue,
2697 .urb_dequeue = musb_urb_dequeue,
2698 .endpoint_disable = musb_h_disable,
2699
2700 #ifndef CONFIG_MUSB_PIO_ONLY
2701 .map_urb_for_dma = musb_map_urb_for_dma,
2702 .unmap_urb_for_dma = musb_unmap_urb_for_dma,
2703 #endif
2704
2705 .hub_status_data = musb_hub_status_data,
2706 .hub_control = musb_hub_control,
2707 .bus_suspend = musb_bus_suspend,
2708 .bus_resume = musb_bus_resume,
2709 /* .start_port_reset = NULL, */
2710 /* .hub_irq_enable = NULL, */
2711 };
2712
2713 int musb_host_alloc(struct musb *musb)
2714 {
2715 struct device *dev = musb->controller;
2716
2717 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
2718 musb->hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
2719 if (!musb->hcd)
2720 return -EINVAL;
2721
2722 *musb->hcd->hcd_priv = (unsigned long) musb;
2723 musb->hcd->self.uses_pio_for_control = 1;
2724 musb->hcd->uses_new_polling = 1;
2725 musb->hcd->has_tt = 1;
2726
2727 return 0;
2728 }
2729
2730 void musb_host_cleanup(struct musb *musb)
2731 {
2732 if (musb->port_mode == MUSB_PERIPHERAL)
2733 return;
2734 usb_remove_hcd(musb->hcd);
2735 }
2736
2737 void musb_host_free(struct musb *musb)
2738 {
2739 usb_put_hcd(musb->hcd);
2740 }
2741
2742 int musb_host_setup(struct musb *musb, int power_budget)
2743 {
2744 int ret;
2745 struct usb_hcd *hcd = musb->hcd;
2746
2747 if (musb->port_mode == MUSB_HOST) {
2748 MUSB_HST_MODE(musb);
2749 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2750 }
2751 otg_set_host(musb->xceiv->otg, &hcd->self);
2752 /* don't support otg protocols */
2753 hcd->self.otg_port = 0;
2754 musb->xceiv->otg->host = &hcd->self;
2755 hcd->power_budget = 2 * (power_budget ? : 250);
2756 hcd->skip_phy_initialization = 1;
2757
2758 ret = usb_add_hcd(hcd, 0, 0);
2759 if (ret < 0)
2760 return ret;
2761
2762 device_wakeup_enable(hcd->self.controller);
2763 return 0;
2764 }
2765
2766 void musb_host_resume_root_hub(struct musb *musb)
2767 {
2768 usb_hcd_resume_root_hub(musb->hcd);
2769 }
2770
2771 void musb_host_poke_root_hub(struct musb *musb)
2772 {
2773 MUSB_HST_MODE(musb);
2774 if (musb->hcd->status_urb)
2775 usb_hcd_poll_rh_status(musb->hcd);
2776 else
2777 usb_hcd_resume_root_hub(musb->hcd);
2778 }