1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * core.h - DesignWare HS OTG Controller common declarations
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #ifndef __DWC2_CORE_H__
39 #define __DWC2_CORE_H__
40
41 #include <linux/phy/phy.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/usb/gadget.h>
44 #include <linux/usb/otg.h>
45 #include <linux/usb/phy.h>
46 #include "hw.h"
47
48 /*
49 * Suggested defines for tracers:
50 * - no_printk: Disable tracing
51 * - pr_info: Print this info to the console
52 * - trace_printk: Print this info to trace buffer (good for verbose logging)
53 */
54
55 #define DWC2_TRACE_SCHEDULER no_printk
56 #define DWC2_TRACE_SCHEDULER_VB no_printk
57
58 /* Detailed scheduler tracing, but won't overwhelm console */
59 #define dwc2_sch_dbg(hsotg, fmt, ...) \
60 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
61 dev_name(hsotg->dev), ##__VA_ARGS__)
62
63 /* Verbose scheduler tracing */
64 #define dwc2_sch_vdbg(hsotg, fmt, ...) \
65 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
66 dev_name(hsotg->dev), ##__VA_ARGS__)
67
68 /* Maximum number of Endpoints/HostChannels */
69 #define MAX_EPS_CHANNELS 16
70
71 /* dwc2-hsotg declarations */
72 static const char * const dwc2_hsotg_supply_names[] = {
73 "vusb_d", /* digital USB supply, 1.2V */
74 "vusb_a", /* analog USB supply, 1.1V */
75 };
76
77 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
78
79 /*
80 * EP0_MPS_LIMIT
81 *
82 * Unfortunately there seems to be a limit of the amount of data that can
83 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
84 * packets (which practically means 1 packet and 63 bytes of data) when the
85 * MPS is set to 64.
86 *
87 * This means if we are wanting to move >127 bytes of data, we need to
88 * split the transactions up, but just doing one packet at a time does
89 * not work (this may be an implicit DATA0 PID on first packet of the
90 * transaction) and doing 2 packets is outside the controller's limits.
91 *
92 * If we try to lower the MPS size for EP0, then no transfers work properly
93 * for EP0, and the system will fail basic enumeration. As no cause for this
94 * has currently been found, we cannot support any large IN transfers for
95 * EP0.
96 */
97 #define EP0_MPS_LIMIT 64
98
99 struct dwc2_hsotg;
100 struct dwc2_hsotg_req;
101
102 /**
103 * struct dwc2_hsotg_ep - driver endpoint definition.
104 * @ep: The gadget layer representation of the endpoint.
105 * @name: The driver generated name for the endpoint.
106 * @queue: Queue of requests for this endpoint.
107 * @parent: Reference back to the parent device structure.
108 * @req: The current request that the endpoint is processing. This is
109 * used to indicate an request has been loaded onto the endpoint
110 * and has yet to be completed (maybe due to data move, or simply
111 * awaiting an ack from the core all the data has been completed).
112 * @debugfs: File entry for debugfs file for this endpoint.
113 * @dir_in: Set to true if this endpoint is of the IN direction, which
114 * means that it is sending data to the Host.
115 * @index: The index for the endpoint registers.
116 * @mc: Multi Count - number of transactions per microframe
117 * @interval: Interval for periodic endpoints, in frames or microframes.
118 * @name: The name array passed to the USB core.
119 * @halted: Set if the endpoint has been halted.
120 * @periodic: Set if this is a periodic ep, such as Interrupt
121 * @isochronous: Set if this is a isochronous ep
122 * @send_zlp: Set if we need to send a zero-length packet.
123 * @desc_list_dma: The DMA address of descriptor chain currently in use.
124 * @desc_list: Pointer to descriptor DMA chain head currently in use.
125 * @desc_count: Count of entries within the DMA descriptor chain of EP.
126 * @next_desc: index of next free descriptor in the ISOC chain under SW control.
127 * @compl_desc: index of next descriptor to be completed by xFerComplete
128 * @total_data: The total number of data bytes done.
129 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
130 * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0.
131 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
132 * @last_load: The offset of data for the last start of request.
133 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
134 * @target_frame: Targeted frame num to setup next ISOC transfer
135 * @frame_overrun: Indicates SOF number overrun in DSTS
136 *
137 * This is the driver's state for each registered enpoint, allowing it
138 * to keep track of transactions that need doing. Each endpoint has a
139 * lock to protect the state, to try and avoid using an overall lock
140 * for the host controller as much as possible.
141 *
142 * For periodic IN endpoints, we have fifo_size and fifo_load to try
143 * and keep track of the amount of data in the periodic FIFO for each
144 * of these as we don't have a status register that tells us how much
145 * is in each of them. (note, this may actually be useless information
146 * as in shared-fifo mode periodic in acts like a single-frame packet
147 * buffer than a fifo)
148 */
149 struct dwc2_hsotg_ep {
150 struct usb_ep ep;
151 struct list_head queue;
152 struct dwc2_hsotg *parent;
153 struct dwc2_hsotg_req *req;
154 struct dentry *debugfs;
155
156 unsigned long total_data;
157 unsigned int size_loaded;
158 unsigned int last_load;
159 unsigned int fifo_load;
160 unsigned short fifo_size;
161 unsigned short fifo_index;
162
163 unsigned char dir_in;
164 unsigned char index;
165 unsigned char mc;
166 u16 interval;
167
168 unsigned int halted:1;
169 unsigned int periodic:1;
170 unsigned int isochronous:1;
171 unsigned int send_zlp:1;
172 unsigned int target_frame;
173 #define TARGET_FRAME_INITIAL 0xFFFFFFFF
174 bool frame_overrun;
175
176 dma_addr_t desc_list_dma;
177 struct dwc2_dma_desc *desc_list;
178 u8 desc_count;
179
180 unsigned int next_desc;
181 unsigned int compl_desc;
182
183 char name[10];
184 };
185
186 /**
187 * struct dwc2_hsotg_req - data transfer request
188 * @req: The USB gadget request
189 * @queue: The list of requests for the endpoint this is queued for.
190 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
191 */
192 struct dwc2_hsotg_req {
193 struct usb_request req;
194 struct list_head queue;
195 void *saved_req_buf;
196 };
197
198 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
199 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
200 #define call_gadget(_hs, _entry) \
201 do { \
202 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
203 (_hs)->driver && (_hs)->driver->_entry) { \
204 spin_unlock(&_hs->lock); \
205 (_hs)->driver->_entry(&(_hs)->gadget); \
206 spin_lock(&_hs->lock); \
207 } \
208 } while (0)
209 #else
210 #define call_gadget(_hs, _entry) do {} while (0)
211 #endif
212
213 struct dwc2_hsotg;
214 struct dwc2_host_chan;
215
216 /* Device States */
217 enum dwc2_lx_state {
218 DWC2_L0, /* On state */
219 DWC2_L1, /* LPM sleep state */
220 DWC2_L2, /* USB suspend state */
221 DWC2_L3, /* Off state */
222 };
223
224 /* Gadget ep0 states */
225 enum dwc2_ep0_state {
226 DWC2_EP0_SETUP,
227 DWC2_EP0_DATA_IN,
228 DWC2_EP0_DATA_OUT,
229 DWC2_EP0_STATUS_IN,
230 DWC2_EP0_STATUS_OUT,
231 };
232
233 /**
234 * struct dwc2_core_params - Parameters for configuring the core
235 *
236 * @otg_cap: Specifies the OTG capabilities.
237 * 0 - HNP and SRP capable
238 * 1 - SRP Only capable
239 * 2 - No HNP/SRP capable (always available)
240 * Defaults to best available option (0, 1, then 2)
241 * @host_dma: Specifies whether to use slave or DMA mode for accessing
242 * the data FIFOs. The driver will automatically detect the
243 * value for this parameter if none is specified.
244 * 0 - Slave (always available)
245 * 1 - DMA (default, if available)
246 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
247 * address DMA mode or descriptor DMA mode for accessing
248 * the data FIFOs. The driver will automatically detect the
249 * value for this if none is specified.
250 * 0 - Address DMA
251 * 1 - Descriptor DMA (default, if available)
252 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
253 * address DMA mode or descriptor DMA mode for accessing
254 * the data FIFOs in Full Speed mode only. The driver
255 * will automatically detect the value for this if none is
256 * specified.
257 * 0 - Address DMA
258 * 1 - Descriptor DMA in FS (default, if available)
259 * @speed: Specifies the maximum speed of operation in host and
260 * device mode. The actual speed depends on the speed of
261 * the attached device and the value of phy_type.
262 * 0 - High Speed
263 * (default when phy_type is UTMI+ or ULPI)
264 * 1 - Full Speed
265 * (default when phy_type is Full Speed)
266 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
267 * 1 - Allow dynamic FIFO sizing (default, if available)
268 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
269 * are enabled for non-periodic IN endpoints in device
270 * mode.
271 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
272 * dynamic FIFO sizing is enabled
273 * 16 to 32768
274 * Actual maximum value is autodetected and also
275 * the default.
276 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
277 * in host mode when dynamic FIFO sizing is enabled
278 * 16 to 32768
279 * Actual maximum value is autodetected and also
280 * the default.
281 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
282 * host mode when dynamic FIFO sizing is enabled
283 * 16 to 32768
284 * Actual maximum value is autodetected and also
285 * the default.
286 * @max_transfer_size: The maximum transfer size supported, in bytes
287 * 2047 to 65,535
288 * Actual maximum value is autodetected and also
289 * the default.
290 * @max_packet_count: The maximum number of packets in a transfer
291 * 15 to 511
292 * Actual maximum value is autodetected and also
293 * the default.
294 * @host_channels: The number of host channel registers to use
295 * 1 to 16
296 * Actual maximum value is autodetected and also
297 * the default.
298 * @phy_type: Specifies the type of PHY interface to use. By default,
299 * the driver will automatically detect the phy_type.
300 * 0 - Full Speed Phy
301 * 1 - UTMI+ Phy
302 * 2 - ULPI Phy
303 * Defaults to best available option (2, 1, then 0)
304 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
305 * is applicable for a phy_type of UTMI+ or ULPI. (For a
306 * ULPI phy_type, this parameter indicates the data width
307 * between the MAC and the ULPI Wrapper.) Also, this
308 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
309 * parameter was set to "8 and 16 bits", meaning that the
310 * core has been configured to work at either data path
311 * width.
312 * 8 or 16 (default 16 if available)
313 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
314 * data rate. This parameter is only applicable if phy_type
315 * is ULPI.
316 * 0 - single data rate ULPI interface with 8 bit wide
317 * data bus (default)
318 * 1 - double data rate ULPI interface with 4 bit wide
319 * data bus
320 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
321 * external supply to drive the VBus
322 * 0 - Internal supply (default)
323 * 1 - External supply
324 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
325 * speed PHY. This parameter is only applicable if phy_type
326 * is FS.
327 * 0 - No (default)
328 * 1 - Yes
329 * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled.
330 * 0 - Disable (default)
331 * 1 - Enable
332 * @acg_enable: For enabling Active Clock Gating in the controller
333 * 0 - No
334 * 1 - Yes
335 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
336 * 0 - No (default)
337 * 1 - Yes
338 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
339 * when attached to a Full Speed or Low Speed device in
340 * host mode.
341 * 0 - Don't support low power mode (default)
342 * 1 - Support low power mode
343 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
344 * when connected to a Low Speed device in host
345 * mode. This parameter is applicable only if
346 * host_support_fs_ls_low_power is enabled.
347 * 0 - 48 MHz
348 * (default when phy_type is UTMI+ or ULPI)
349 * 1 - 6 MHz
350 * (default when phy_type is Full Speed)
351 * @oc_disable: Flag to disable overcurrent condition.
352 * 0 - Allow overcurrent condition to get detected
353 * 1 - Disable overcurrent condtion to get detected
354 * @ts_dline: Enable Term Select Dline pulsing
355 * 0 - No (default)
356 * 1 - Yes
357 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
358 * 0 - No (default for core < 2.92a)
359 * 1 - Yes (default for core >= 2.92a)
360 * @ahbcfg: This field allows the default value of the GAHBCFG
361 * register to be overridden
362 * -1 - GAHBCFG value will be set to 0x06
363 * (INCR, default)
364 * all others - GAHBCFG value will be overridden with
365 * this value
366 * Not all bits can be controlled like this, the
367 * bits defined by GAHBCFG_CTRL_MASK are controlled
368 * by the driver and are ignored in this
369 * configuration value.
370 * @uframe_sched: True to enable the microframe scheduler
371 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
372 * Disable CONIDSTSCHNG controller interrupt in such
373 * case.
374 * 0 - No (default)
375 * 1 - Yes
376 * @power_down: Specifies whether the controller support power_down.
377 * If power_down is enabled, the controller will enter
378 * power_down in both peripheral and host mode when
379 * needed.
380 * 0 - No (default)
381 * 1 - Partial power down
382 * 2 - Hibernation
383 * @lpm: Enable LPM support.
384 * 0 - No
385 * 1 - Yes
386 * @lpm_clock_gating: Enable core PHY clock gating.
387 * 0 - No
388 * 1 - Yes
389 * @besl: Enable LPM Errata support.
390 * 0 - No
391 * 1 - Yes
392 * @hird_threshold_en: HIRD or HIRD Threshold enable.
393 * 0 - No
394 * 1 - Yes
395 * @hird_threshold: Value of BESL or HIRD Threshold.
396 * @ref_clk_per: Indicates in terms of pico seconds the period
397 * of ref_clk.
398 * 62500 - 16MHz
399 * 58823 - 17MHz
400 * 52083 - 19.2MHz
401 * 50000 - 20MHz
402 * 41666 - 24MHz
403 * 33333 - 30MHz (default)
404 * 25000 - 40MHz
405 * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which
406 * the controller should generate an interrupt if the
407 * device had been in L1 state until that period.
408 * This is used by SW to initiate Remote WakeUp in the
409 * controller so as to sync to the uF number from the host.
410 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
411 * register.
412 * 0 - Deactivate the transceiver (default)
413 * 1 - Activate the transceiver
414 * @g_dma: Enables gadget dma usage (default: autodetect).
415 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
416 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
417 * DWORDS from 16-32768 (default: 2048 if
418 * possible, otherwise autodetect).
419 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
420 * DWORDS from 16-32768 (default: 1024 if
421 * possible, otherwise autodetect).
422 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
423 * mode. Each value corresponds to one EP
424 * starting from EP1 (max 15 values). Sizes are
425 * in DWORDS with possible values from from
426 * 16-32768 (default: 256, 256, 256, 256, 768,
427 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
428 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
429 * while full&low speed device connect. And change speed
430 * back to DWC2_SPEED_PARAM_HIGH while device is gone.
431 * 0 - No (default)
432 * 1 - Yes
433 * @service_interval: Enable service interval based scheduling.
434 * 0 - No
435 * 1 - Yes
436 *
437 * The following parameters may be specified when starting the module. These
438 * parameters define how the DWC_otg controller should be configured. A
439 * value of -1 (or any other out of range value) for any parameter means
440 * to read the value from hardware (if possible) or use the builtin
441 * default described above.
442 */
443 struct dwc2_core_params {
444 u8 otg_cap;
445 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
446 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
447 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
448
449 u8 phy_type;
450 #define DWC2_PHY_TYPE_PARAM_FS 0
451 #define DWC2_PHY_TYPE_PARAM_UTMI 1
452 #define DWC2_PHY_TYPE_PARAM_ULPI 2
453
454 u8 speed;
455 #define DWC2_SPEED_PARAM_HIGH 0
456 #define DWC2_SPEED_PARAM_FULL 1
457 #define DWC2_SPEED_PARAM_LOW 2
458
459 u8 phy_utmi_width;
460 bool phy_ulpi_ddr;
461 bool phy_ulpi_ext_vbus;
462 bool enable_dynamic_fifo;
463 bool en_multiple_tx_fifo;
464 bool i2c_enable;
465 bool acg_enable;
466 bool ulpi_fs_ls;
467 bool ts_dline;
468 bool reload_ctl;
469 bool uframe_sched;
470 bool external_id_pin_ctl;
471
472 int power_down;
473 #define DWC2_POWER_DOWN_PARAM_NONE 0
474 #define DWC2_POWER_DOWN_PARAM_PARTIAL 1
475 #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2
476
477 bool lpm;
478 bool lpm_clock_gating;
479 bool besl;
480 bool hird_threshold_en;
481 bool service_interval;
482 u8 hird_threshold;
483 bool activate_stm_fs_transceiver;
484 bool ipg_isoc_en;
485 u16 max_packet_count;
486 u32 max_transfer_size;
487 u32 ahbcfg;
488
489 /* GREFCLK parameters */
490 u32 ref_clk_per;
491 u16 sof_cnt_wkup_alert;
492
493 /* Host parameters */
494 bool host_dma;
495 bool dma_desc_enable;
496 bool dma_desc_fs_enable;
497 bool host_support_fs_ls_low_power;
498 bool host_ls_low_power_phy_clk;
499 bool oc_disable;
500
501 u8 host_channels;
502 u16 host_rx_fifo_size;
503 u16 host_nperio_tx_fifo_size;
504 u16 host_perio_tx_fifo_size;
505
506 /* Gadget parameters */
507 bool g_dma;
508 bool g_dma_desc;
509 u32 g_rx_fifo_size;
510 u32 g_np_tx_fifo_size;
511 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
512
513 bool change_speed_quirk;
514 };
515
516 /**
517 * struct dwc2_hw_params - Autodetected parameters.
518 *
519 * These parameters are the various parameters read from hardware
520 * registers during initialization. They typically contain the best
521 * supported or maximum value that can be configured in the
522 * corresponding dwc2_core_params value.
523 *
524 * The values that are not in dwc2_core_params are documented below.
525 *
526 * @op_mode: Mode of Operation
527 * 0 - HNP- and SRP-Capable OTG (Host & Device)
528 * 1 - SRP-Capable OTG (Host & Device)
529 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
530 * 3 - SRP-Capable Device
531 * 4 - Non-OTG Device
532 * 5 - SRP-Capable Host
533 * 6 - Non-OTG Host
534 * @arch: Architecture
535 * 0 - Slave only
536 * 1 - External DMA
537 * 2 - Internal DMA
538 * @ipg_isoc_en: This feature indicates that the controller supports
539 * the worst-case scenario of Rx followed by Rx
540 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi
541 * specification for any token following ISOC OUT token.
542 * 0 - Don't support
543 * 1 - Support
544 * @power_optimized: Are power optimizations enabled?
545 * @num_dev_ep: Number of device endpoints available
546 * @num_dev_in_eps: Number of device IN endpoints available
547 * @num_dev_perio_in_ep: Number of device periodic IN endpoints
548 * available
549 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue
550 * Depth
551 * 0 to 30
552 * @host_perio_tx_q_depth:
553 * Host Mode Periodic Request Queue Depth
554 * 2, 4 or 8
555 * @nperio_tx_q_depth:
556 * Non-Periodic Request Queue Depth
557 * 2, 4 or 8
558 * @hs_phy_type: High-speed PHY interface type
559 * 0 - High-speed interface not supported
560 * 1 - UTMI+
561 * 2 - ULPI
562 * 3 - UTMI+ and ULPI
563 * @fs_phy_type: Full-speed PHY interface type
564 * 0 - Full speed interface not supported
565 * 1 - Dedicated full speed interface
566 * 2 - FS pins shared with UTMI+ pins
567 * 3 - FS pins shared with ULPI pins
568 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
569 * @hibernation: Is hibernation enabled?
570 * @utmi_phy_data_width: UTMI+ PHY data width
571 * 0 - 8 bits
572 * 1 - 16 bits
573 * 2 - 8 or 16 bits
574 * @snpsid: Value from SNPSID register
575 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
576 * @g_tx_fifo_size: Power-on values of TxFIFO sizes
577 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
578 * address DMA mode or descriptor DMA mode for accessing
579 * the data FIFOs. The driver will automatically detect the
580 * value for this if none is specified.
581 * 0 - Address DMA
582 * 1 - Descriptor DMA (default, if available)
583 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
584 * 1 - Allow dynamic FIFO sizing (default, if available)
585 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
586 * are enabled for non-periodic IN endpoints in device
587 * mode.
588 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
589 * in host mode when dynamic FIFO sizing is enabled
590 * 16 to 32768
591 * Actual maximum value is autodetected and also
592 * the default.
593 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
594 * host mode when dynamic FIFO sizing is enabled
595 * 16 to 32768
596 * Actual maximum value is autodetected and also
597 * the default.
598 * @max_transfer_size: The maximum transfer size supported, in bytes
599 * 2047 to 65,535
600 * Actual maximum value is autodetected and also
601 * the default.
602 * @max_packet_count: The maximum number of packets in a transfer
603 * 15 to 511
604 * Actual maximum value is autodetected and also
605 * the default.
606 * @host_channels: The number of host channel registers to use
607 * 1 to 16
608 * Actual maximum value is autodetected and also
609 * the default.
610 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
611 * in device mode when dynamic FIFO sizing is enabled
612 * 16 to 32768
613 * Actual maximum value is autodetected and also
614 * the default.
615 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
616 * speed PHY. This parameter is only applicable if phy_type
617 * is FS.
618 * 0 - No (default)
619 * 1 - Yes
620 * @acg_enable: For enabling Active Clock Gating in the controller
621 * 0 - Disable
622 * 1 - Enable
623 * @lpm_mode: For enabling Link Power Management in the controller
624 * 0 - Disable
625 * 1 - Enable
626 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic
627 * FIFO sizing is enabled 16 to 32768
628 * Actual maximum value is autodetected and also
629 * the default.
630 * @service_interval_mode: For enabling service interval based scheduling in the
631 * controller.
632 * 0 - Disable
633 * 1 - Enable
634 */
635 struct dwc2_hw_params {
636 unsigned op_mode:3;
637 unsigned arch:2;
638 unsigned dma_desc_enable:1;
639 unsigned enable_dynamic_fifo:1;
640 unsigned en_multiple_tx_fifo:1;
641 unsigned rx_fifo_size:16;
642 unsigned host_nperio_tx_fifo_size:16;
643 unsigned dev_nperio_tx_fifo_size:16;
644 unsigned host_perio_tx_fifo_size:16;
645 unsigned nperio_tx_q_depth:3;
646 unsigned host_perio_tx_q_depth:3;
647 unsigned dev_token_q_depth:5;
648 unsigned max_transfer_size:26;
649 unsigned max_packet_count:11;
650 unsigned host_channels:5;
651 unsigned hs_phy_type:2;
652 unsigned fs_phy_type:2;
653 unsigned i2c_enable:1;
654 unsigned acg_enable:1;
655 unsigned num_dev_ep:4;
656 unsigned num_dev_in_eps : 4;
657 unsigned num_dev_perio_in_ep:4;
658 unsigned total_fifo_size:16;
659 unsigned power_optimized:1;
660 unsigned hibernation:1;
661 unsigned utmi_phy_data_width:2;
662 unsigned lpm_mode:1;
663 unsigned ipg_isoc_en:1;
664 unsigned service_interval_mode:1;
665 u32 snpsid;
666 u32 dev_ep_dirs;
667 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
668 };
669
670 /* Size of control and EP0 buffers */
671 #define DWC2_CTRL_BUFF_SIZE 8
672
673 /**
674 * struct dwc2_gregs_backup - Holds global registers state before
675 * entering partial power down
676 * @gotgctl: Backup of GOTGCTL register
677 * @gintmsk: Backup of GINTMSK register
678 * @gahbcfg: Backup of GAHBCFG register
679 * @gusbcfg: Backup of GUSBCFG register
680 * @grxfsiz: Backup of GRXFSIZ register
681 * @gnptxfsiz: Backup of GNPTXFSIZ register
682 * @gi2cctl: Backup of GI2CCTL register
683 * @glpmcfg: Backup of GLPMCFG register
684 * @gdfifocfg: Backup of GDFIFOCFG register
685 * @pcgcctl: Backup of PCGCCTL register
686 * @pcgcctl1: Backup of PCGCCTL1 register
687 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
688 * @gpwrdn: Backup of GPWRDN register
689 * @valid: True if registers values backuped.
690 */
691 struct dwc2_gregs_backup {
692 u32 gotgctl;
693 u32 gintmsk;
694 u32 gahbcfg;
695 u32 gusbcfg;
696 u32 grxfsiz;
697 u32 gnptxfsiz;
698 u32 gi2cctl;
699 u32 glpmcfg;
700 u32 pcgcctl;
701 u32 pcgcctl1;
702 u32 gdfifocfg;
703 u32 gpwrdn;
704 bool valid;
705 };
706
707 /**
708 * struct dwc2_dregs_backup - Holds device registers state before
709 * entering partial power down
710 * @dcfg: Backup of DCFG register
711 * @dctl: Backup of DCTL register
712 * @daintmsk: Backup of DAINTMSK register
713 * @diepmsk: Backup of DIEPMSK register
714 * @doepmsk: Backup of DOEPMSK register
715 * @diepctl: Backup of DIEPCTL register
716 * @dieptsiz: Backup of DIEPTSIZ register
717 * @diepdma: Backup of DIEPDMA register
718 * @doepctl: Backup of DOEPCTL register
719 * @doeptsiz: Backup of DOEPTSIZ register
720 * @doepdma: Backup of DOEPDMA register
721 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
722 * @valid: True if registers values backuped.
723 */
724 struct dwc2_dregs_backup {
725 u32 dcfg;
726 u32 dctl;
727 u32 daintmsk;
728 u32 diepmsk;
729 u32 doepmsk;
730 u32 diepctl[MAX_EPS_CHANNELS];
731 u32 dieptsiz[MAX_EPS_CHANNELS];
732 u32 diepdma[MAX_EPS_CHANNELS];
733 u32 doepctl[MAX_EPS_CHANNELS];
734 u32 doeptsiz[MAX_EPS_CHANNELS];
735 u32 doepdma[MAX_EPS_CHANNELS];
736 u32 dtxfsiz[MAX_EPS_CHANNELS];
737 bool valid;
738 };
739
740 /**
741 * struct dwc2_hregs_backup - Holds host registers state before
742 * entering partial power down
743 * @hcfg: Backup of HCFG register
744 * @haintmsk: Backup of HAINTMSK register
745 * @hcintmsk: Backup of HCINTMSK register
746 * @hprt0: Backup of HPTR0 register
747 * @hfir: Backup of HFIR register
748 * @hptxfsiz: Backup of HPTXFSIZ register
749 * @valid: True if registers values backuped.
750 */
751 struct dwc2_hregs_backup {
752 u32 hcfg;
753 u32 haintmsk;
754 u32 hcintmsk[MAX_EPS_CHANNELS];
755 u32 hprt0;
756 u32 hfir;
757 u32 hptxfsiz;
758 bool valid;
759 };
760
761 /*
762 * Constants related to high speed periodic scheduling
763 *
764 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
765 * reservation point of view it's assumed that the schedule goes right back to
766 * the beginning after the end of the schedule.
767 *
768 * What does that mean for scheduling things with a long interval? It means
769 * we'll reserve time for them in every possible microframe that they could
770 * ever be scheduled in. ...but we'll still only actually schedule them as
771 * often as they were requested.
772 *
773 * We keep our schedule in a "bitmap" structure. This simplifies having
774 * to keep track of and merge intervals: we just let the bitmap code do most
775 * of the heavy lifting. In a way scheduling is much like memory allocation.
776 *
777 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
778 * supposed to schedule for periodic transfers). That's according to spec.
779 *
780 * Note that though we only schedule 80% of each microframe, the bitmap that we
781 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
782 * space for each uFrame).
783 *
784 * Requirements:
785 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
786 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
787 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
788 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
789 */
790 #define DWC2_US_PER_UFRAME 125
791 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100
792
793 #define DWC2_HS_SCHEDULE_UFRAMES 8
794 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
795 DWC2_HS_PERIODIC_US_PER_UFRAME)
796
797 /*
798 * Constants related to low speed scheduling
799 *
800 * For high speed we schedule every 1us. For low speed that's a bit overkill,
801 * so we make up a unit called a "slice" that's worth 25us. There are 40
802 * slices in a full frame and we can schedule 36 of those (90%) for periodic
803 * transfers.
804 *
805 * Our low speed schedule can be as short as 1 frame or could be longer. When
806 * we only schedule 1 frame it means that we'll need to reserve a time every
807 * frame even for things that only transfer very rarely, so something that runs
808 * every 2048 frames will get time reserved in every frame. Our low speed
809 * schedule can be longer and we'll be able to handle more overlap, but that
810 * will come at increased memory cost and increased time to schedule.
811 *
812 * Note: one other advantage of a short low speed schedule is that if we mess
813 * up and miss scheduling we can jump in and use any of the slots that we
814 * happened to reserve.
815 *
816 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
817 * the schedule. There will be one schedule per TT.
818 *
819 * Requirements:
820 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
821 */
822 #define DWC2_US_PER_SLICE 25
823 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
824
825 #define DWC2_ROUND_US_TO_SLICE(us) \
826 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
827 DWC2_US_PER_SLICE)
828
829 #define DWC2_LS_PERIODIC_US_PER_FRAME \
830 900
831 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
832 (DWC2_LS_PERIODIC_US_PER_FRAME / \
833 DWC2_US_PER_SLICE)
834
835 #define DWC2_LS_SCHEDULE_FRAMES 1
836 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
837 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
838
839 /**
840 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
841 * and periodic schedules
842 *
843 * These are common for both host and peripheral modes:
844 *
845 * @dev: The struct device pointer
846 * @regs: Pointer to controller regs
847 * @hw_params: Parameters that were autodetected from the
848 * hardware registers
849 * @params: Parameters that define how the core should be configured
850 * @op_state: The operational State, during transitions (a_host=>
851 * a_peripheral and b_device=>b_host) this may not match
852 * the core, but allows the software to determine
853 * transitions
854 * @dr_mode: Requested mode of operation, one of following:
855 * - USB_DR_MODE_PERIPHERAL
856 * - USB_DR_MODE_HOST
857 * - USB_DR_MODE_OTG
858 * @hcd_enabled: Host mode sub-driver initialization indicator.
859 * @gadget_enabled: Peripheral mode sub-driver initialization indicator.
860 * @ll_hw_enabled: Status of low-level hardware resources.
861 * @hibernated: True if core is hibernated
862 * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a
863 * remote wakeup.
864 * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend.
865 * @need_phy_for_wake: Quirk saying that we should keep the PHY on at
866 * suspend if we need USB to wake us up.
867 * @frame_number: Frame number read from the core. For both device
868 * and host modes. The value ranges are from 0
869 * to HFNUM_MAX_FRNUM.
870 * @phy: The otg phy transceiver structure for phy control.
871 * @uphy: The otg phy transceiver structure for old USB phy
872 * control.
873 * @plat: The platform specific configuration data. This can be
874 * removed once all SoCs support usb transceiver.
875 * @supplies: Definition of USB power supplies
876 * @vbus_supply: Regulator supplying vbus.
877 * @lock: Spinlock that protects all the driver data structures
878 * @priv: Stores a pointer to the struct usb_hcd
879 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
880 * transfer are in process of being queued
881 * @srp_success: Stores status of SRP request in the case of a FS PHY
882 * with an I2C interface
883 * @wq_otg: Workqueue object used for handling of some interrupts
884 * @wf_otg: Work object for handling Connector ID Status Change
885 * interrupt
886 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
887 * @lx_state: Lx state of connected device
888 * @gr_backup: Backup of global registers during suspend
889 * @dr_backup: Backup of device registers during suspend
890 * @hr_backup: Backup of host registers during suspend
891 * @needs_byte_swap: Specifies whether the opposite endianness.
892 *
893 * These are for host mode:
894 *
895 * @flags: Flags for handling root port state changes
896 * @flags.d32: Contain all root port flags
897 * @flags.b: Separate root port flags from each other
898 * @flags.b.port_connect_status_change: True if root port connect status
899 * changed
900 * @flags.b.port_connect_status: True if device connected to root port
901 * @flags.b.port_reset_change: True if root port reset status changed
902 * @flags.b.port_enable_change: True if root port enable status changed
903 * @flags.b.port_suspend_change: True if root port suspend status changed
904 * @flags.b.port_over_current_change: True if root port over current state
905 * changed.
906 * @flags.b.port_l1_change: True if root port l1 status changed
907 * @flags.b.reserved: Reserved bits of root port register
908 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
909 * Transfers associated with these QHs are not currently
910 * assigned to a host channel.
911 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
912 * Transfers associated with these QHs are currently
913 * assigned to a host channel.
914 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
915 * non-periodic schedule
916 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule.
917 * Transfers associated with these QHs are not currently
918 * assigned to a host channel.
919 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
920 * list of QHs for periodic transfers that are _not_
921 * scheduled for the next frame. Each QH in the list has an
922 * interval counter that determines when it needs to be
923 * scheduled for execution. This scheduling mechanism
924 * allows only a simple calculation for periodic bandwidth
925 * used (i.e. must assume that all periodic transfers may
926 * need to execute in the same frame). However, it greatly
927 * simplifies scheduling and should be sufficient for the
928 * vast majority of OTG hosts, which need to connect to a
929 * small number of peripherals at one time. Items move from
930 * this list to periodic_sched_ready when the QH interval
931 * counter is 0 at SOF.
932 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
933 * the next frame, but have not yet been assigned to host
934 * channels. Items move from this list to
935 * periodic_sched_assigned as host channels become
936 * available during the current frame.
937 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
938 * frame that are assigned to host channels. Items move
939 * from this list to periodic_sched_queued as the
940 * transactions for the QH are queued to the DWC_otg
941 * controller.
942 * @periodic_sched_queued: List of periodic QHs that have been queued for
943 * execution. Items move from this list to either
944 * periodic_sched_inactive or periodic_sched_ready when the
945 * channel associated with the transfer is released. If the
946 * interval for the QH is 1, the item moves to
947 * periodic_sched_ready because it must be rescheduled for
948 * the next frame. Otherwise, the item moves to
949 * periodic_sched_inactive.
950 * @split_order: List keeping track of channels doing splits, in order.
951 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
952 * This value is in microseconds per (micro)frame. The
953 * assumption is that all periodic transfers may occur in
954 * the same (micro)frame.
955 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
956 * host is in high speed mode; low speed schedules are
957 * stored elsewhere since we need one per TT.
958 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
959 * SOF enable/disable.
960 * @free_hc_list: Free host channels in the controller. This is a list of
961 * struct dwc2_host_chan items.
962 * @periodic_channels: Number of host channels assigned to periodic transfers.
963 * Currently assuming that there is a dedicated host
964 * channel for each periodic transaction and at least one
965 * host channel is available for non-periodic transactions.
966 * @non_periodic_channels: Number of host channels assigned to non-periodic
967 * transfers
968 * @available_host_channels: Number of host channels available for the
969 * microframe scheduler to use
970 * @hc_ptr_array: Array of pointers to the host channel descriptors.
971 * Allows accessing a host channel descriptor given the
972 * host channel number. This is useful in interrupt
973 * handlers.
974 * @status_buf: Buffer used for data received during the status phase of
975 * a control transfer.
976 * @status_buf_dma: DMA address for status_buf
977 * @start_work: Delayed work for handling host A-cable connection
978 * @reset_work: Delayed work for handling a port reset
979 * @phy_reset_work: Work structure for doing a PHY reset
980 * @otg_port: OTG port number
981 * @frame_list: Frame list
982 * @frame_list_dma: Frame list DMA address
983 * @frame_list_sz: Frame list size
984 * @desc_gen_cache: Kmem cache for generic descriptors
985 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
986 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf
987 *
988 * These are for peripheral mode:
989 *
990 * @driver: USB gadget driver
991 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
992 * @num_of_eps: Number of available EPs (excluding EP0)
993 * @debug_root: Root directrory for debugfs.
994 * @ep0_reply: Request used for ep0 reply.
995 * @ep0_buff: Buffer for EP0 reply data, if needed.
996 * @ctrl_buff: Buffer for EP0 control requests.
997 * @ctrl_req: Request for EP0 control packets.
998 * @ep0_state: EP0 control transfers state
999 * @delayed_status: true when gadget driver asks for delayed status
1000 * @test_mode: USB test mode requested by the host
1001 * @remote_wakeup_allowed: True if device is allowed to wake-up host by
1002 * remote-wakeup signalling
1003 * @setup_desc_dma: EP0 setup stage desc chain DMA address
1004 * @setup_desc: EP0 setup stage desc chain pointer
1005 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
1006 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
1007 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
1008 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
1009 * @irq: Interrupt request line number
1010 * @clk: Pointer to otg clock
1011 * @reset: Pointer to dwc2 reset controller
1012 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10.
1013 * @regset: A pointer to a struct debugfs_regset32, which contains
1014 * a pointer to an array of register definitions, the
1015 * array size and the base address where the register bank
1016 * is to be found.
1017 * @bus_suspended: True if bus is suspended
1018 * @last_frame_num: Number of last frame. Range from 0 to 32768
1019 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1020 * defined, for missed SOFs tracking. Array holds that
1021 * frame numbers, which not equal to last_frame_num +1
1022 * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1023 * defined, for missed SOFs tracking.
1024 * If current_frame_number != last_frame_num+1
1025 * then last_frame_num added to this array
1026 * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array
1027 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed
1028 * 0 - if missed SOFs frame numbers not dumbed
1029 * @fifo_mem: Total internal RAM for FIFOs (bytes)
1030 * @fifo_map: Each bit intend for concrete fifo. If that bit is set,
1031 * then that fifo is used
1032 * @gadget: Represents a usb slave device
1033 * @connected: Used in slave mode. True if device connected with host
1034 * @eps_in: The IN endpoints being supplied to the gadget framework
1035 * @eps_out: The OUT endpoints being supplied to the gadget framework
1036 * @new_connection: Used in host mode. True if there are new connected
1037 * device
1038 * @enabled: Indicates the enabling state of controller
1039 *
1040 */
1041 struct dwc2_hsotg {
1042 struct device *dev;
1043 void __iomem *regs;
1044 /** Params detected from hardware */
1045 struct dwc2_hw_params hw_params;
1046 /** Params to actually use */
1047 struct dwc2_core_params params;
1048 enum usb_otg_state op_state;
1049 enum usb_dr_mode dr_mode;
1050 unsigned int hcd_enabled:1;
1051 unsigned int gadget_enabled:1;
1052 unsigned int ll_hw_enabled:1;
1053 unsigned int hibernated:1;
1054 unsigned int reset_phy_on_wake:1;
1055 unsigned int need_phy_for_wake:1;
1056 unsigned int phy_off_for_suspend:1;
1057 u16 frame_number;
1058
1059 struct phy *phy;
1060 struct usb_phy *uphy;
1061 struct dwc2_hsotg_plat *plat;
1062 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
1063 struct regulator *vbus_supply;
1064
1065 spinlock_t lock;
1066 void *priv;
1067 int irq;
1068 struct clk *clk;
1069 struct reset_control *reset;
1070 struct reset_control *reset_ecc;
1071
1072 unsigned int queuing_high_bandwidth:1;
1073 unsigned int srp_success:1;
1074
1075 struct workqueue_struct *wq_otg;
1076 struct work_struct wf_otg;
1077 struct timer_list wkp_timer;
1078 enum dwc2_lx_state lx_state;
1079 struct dwc2_gregs_backup gr_backup;
1080 struct dwc2_dregs_backup dr_backup;
1081 struct dwc2_hregs_backup hr_backup;
1082
1083 struct dentry *debug_root;
1084 struct debugfs_regset32 *regset;
1085 bool needs_byte_swap;
1086
1087 /* DWC OTG HW Release versions */
1088 #define DWC2_CORE_REV_2_71a 0x4f54271a
1089 #define DWC2_CORE_REV_2_72a 0x4f54272a
1090 #define DWC2_CORE_REV_2_80a 0x4f54280a
1091 #define DWC2_CORE_REV_2_90a 0x4f54290a
1092 #define DWC2_CORE_REV_2_91a 0x4f54291a
1093 #define DWC2_CORE_REV_2_92a 0x4f54292a
1094 #define DWC2_CORE_REV_2_94a 0x4f54294a
1095 #define DWC2_CORE_REV_3_00a 0x4f54300a
1096 #define DWC2_CORE_REV_3_10a 0x4f54310a
1097 #define DWC2_CORE_REV_4_00a 0x4f54400a
1098 #define DWC2_FS_IOT_REV_1_00a 0x5531100a
1099 #define DWC2_HS_IOT_REV_1_00a 0x5532100a
1100
1101 /* DWC OTG HW Core ID */
1102 #define DWC2_OTG_ID 0x4f540000
1103 #define DWC2_FS_IOT_ID 0x55310000
1104 #define DWC2_HS_IOT_ID 0x55320000
1105
1106 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1107 union dwc2_hcd_internal_flags {
1108 u32 d32;
1109 struct {
1110 unsigned port_connect_status_change:1;
1111 unsigned port_connect_status:1;
1112 unsigned port_reset_change:1;
1113 unsigned port_enable_change:1;
1114 unsigned port_suspend_change:1;
1115 unsigned port_over_current_change:1;
1116 unsigned port_l1_change:1;
1117 unsigned reserved:25;
1118 } b;
1119 } flags;
1120
1121 struct list_head non_periodic_sched_inactive;
1122 struct list_head non_periodic_sched_waiting;
1123 struct list_head non_periodic_sched_active;
1124 struct list_head *non_periodic_qh_ptr;
1125 struct list_head periodic_sched_inactive;
1126 struct list_head periodic_sched_ready;
1127 struct list_head periodic_sched_assigned;
1128 struct list_head periodic_sched_queued;
1129 struct list_head split_order;
1130 u16 periodic_usecs;
1131 unsigned long hs_periodic_bitmap[
1132 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
1133 u16 periodic_qh_count;
1134 bool bus_suspended;
1135 bool new_connection;
1136
1137 u16 last_frame_num;
1138
1139 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
1140 #define FRAME_NUM_ARRAY_SIZE 1000
1141 u16 *frame_num_array;
1142 u16 *last_frame_num_array;
1143 int frame_num_idx;
1144 int dumped_frame_num_array;
1145 #endif
1146
1147 struct list_head free_hc_list;
1148 int periodic_channels;
1149 int non_periodic_channels;
1150 int available_host_channels;
1151 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
1152 u8 *status_buf;
1153 dma_addr_t status_buf_dma;
1154 #define DWC2_HCD_STATUS_BUF_SIZE 64
1155
1156 struct delayed_work start_work;
1157 struct delayed_work reset_work;
1158 struct work_struct phy_reset_work;
1159 u8 otg_port;
1160 u32 *frame_list;
1161 dma_addr_t frame_list_dma;
1162 u32 frame_list_sz;
1163 struct kmem_cache *desc_gen_cache;
1164 struct kmem_cache *desc_hsisoc_cache;
1165 struct kmem_cache *unaligned_cache;
1166 #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024
1167
1168 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1169
1170 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1171 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1172 /* Gadget structures */
1173 struct usb_gadget_driver *driver;
1174 int fifo_mem;
1175 unsigned int dedicated_fifos:1;
1176 unsigned char num_of_eps;
1177 u32 fifo_map;
1178
1179 struct usb_request *ep0_reply;
1180 struct usb_request *ctrl_req;
1181 void *ep0_buff;
1182 void *ctrl_buff;
1183 enum dwc2_ep0_state ep0_state;
1184 unsigned delayed_status : 1;
1185 u8 test_mode;
1186
1187 dma_addr_t setup_desc_dma[2];
1188 struct dwc2_dma_desc *setup_desc[2];
1189 dma_addr_t ctrl_in_desc_dma;
1190 struct dwc2_dma_desc *ctrl_in_desc;
1191 dma_addr_t ctrl_out_desc_dma;
1192 struct dwc2_dma_desc *ctrl_out_desc;
1193
1194 struct usb_gadget gadget;
1195 unsigned int enabled:1;
1196 unsigned int connected:1;
1197 unsigned int remote_wakeup_allowed:1;
1198 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1199 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
1200 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
1201 };
1202
1203 /* Normal architectures just use readl/write */
1204 static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
1205 {
1206 u32 val;
1207
1208 val = readl(hsotg->regs + offset);
1209 if (hsotg->needs_byte_swap)
1210 return swab32(val);
1211 else
1212 return val;
1213 }
1214
1215 static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
1216 {
1217 if (hsotg->needs_byte_swap)
1218 writel(swab32(value), hsotg->regs + offset);
1219 else
1220 writel(value, hsotg->regs + offset);
1221
1222 #ifdef DWC2_LOG_WRITES
1223 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
1224 #endif
1225 }
1226
1227 static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset,
1228 void *buffer, unsigned int count)
1229 {
1230 if (count) {
1231 u32 *buf = buffer;
1232
1233 do {
1234 u32 x = dwc2_readl(hsotg, offset);
1235 *buf++ = x;
1236 } while (--count);
1237 }
1238 }
1239
1240 static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset,
1241 const void *buffer, unsigned int count)
1242 {
1243 if (count) {
1244 const u32 *buf = buffer;
1245
1246 do {
1247 dwc2_writel(hsotg, *buf++, offset);
1248 } while (--count);
1249 }
1250 }
1251
1252 /* Reasons for halting a host channel */
1253 enum dwc2_halt_status {
1254 DWC2_HC_XFER_NO_HALT_STATUS,
1255 DWC2_HC_XFER_COMPLETE,
1256 DWC2_HC_XFER_URB_COMPLETE,
1257 DWC2_HC_XFER_ACK,
1258 DWC2_HC_XFER_NAK,
1259 DWC2_HC_XFER_NYET,
1260 DWC2_HC_XFER_STALL,
1261 DWC2_HC_XFER_XACT_ERR,
1262 DWC2_HC_XFER_FRAME_OVERRUN,
1263 DWC2_HC_XFER_BABBLE_ERR,
1264 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1265 DWC2_HC_XFER_AHB_ERR,
1266 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1267 DWC2_HC_XFER_URB_DEQUEUE,
1268 };
1269
1270 /* Core version information */
1271 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1272 {
1273 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1274 }
1275
1276 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1277 {
1278 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1279 }
1280
1281 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1282 {
1283 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1284 }
1285
1286 /*
1287 * The following functions support initialization of the core driver component
1288 * and the DWC_otg controller
1289 */
1290 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
1291 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1292 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore);
1293 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host);
1294 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
1295 int reset, int is_host);
1296 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg);
1297 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy);
1298
1299 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host);
1300 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1301
1302 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
1303
1304 /*
1305 * Common core Functions.
1306 * The following functions support managing the DWC_otg controller in either
1307 * device or host mode.
1308 */
1309 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1310 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1311 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1312
1313 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1314 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1315
1316 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
1317 int is_host);
1318 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg);
1319 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg);
1320
1321 void dwc2_enable_acg(struct dwc2_hsotg *hsotg);
1322
1323 /* This function should be called on every hardware interrupt. */
1324 irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1325
1326 /* The device ID match table */
1327 extern const struct of_device_id dwc2_of_match_table[];
1328
1329 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1330 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1331
1332 /* Common polling functions */
1333 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1334 u32 timeout);
1335 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1336 u32 timeout);
1337 /* Parameters */
1338 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1339 int dwc2_init_params(struct dwc2_hsotg *hsotg);
1340
1341 /*
1342 * The following functions check the controller's OTG operation mode
1343 * capability (GHWCFG2.OTG_MODE).
1344 *
1345 * These functions can be used before the internal hsotg->hw_params
1346 * are read in and cached so they always read directly from the
1347 * GHWCFG2 register.
1348 */
1349 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
1350 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1351 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1352 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1353
1354 /*
1355 * Returns the mode of operation, host or device
1356 */
1357 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1358 {
1359 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1360 }
1361
1362 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1363 {
1364 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1365 }
1366
1367 /*
1368 * Dump core registers and SPRAM
1369 */
1370 void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1371 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1372 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1373
1374 /* Gadget defines */
1375 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1376 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1377 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1378 int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1379 int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1380 int dwc2_gadget_init(struct dwc2_hsotg *hsotg);
1381 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1382 bool reset);
1383 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1384 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1385 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1386 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1387 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1388 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup);
1389 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg);
1390 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1391 int rem_wakeup, int reset);
1392 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg);
1393 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
1394 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
1395 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg);
1396 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg);
1397 #else
1398 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
1399 { return 0; }
1400 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
1401 { return 0; }
1402 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1403 { return 0; }
1404 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
1405 { return 0; }
1406 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1407 bool reset) {}
1408 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1409 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1410 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1411 int testmode)
1412 { return 0; }
1413 #define dwc2_is_device_connected(hsotg) (0)
1414 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1415 { return 0; }
1416 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg,
1417 int remote_wakeup)
1418 { return 0; }
1419 static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
1420 { return 0; }
1421 static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1422 int rem_wakeup, int reset)
1423 { return 0; }
1424 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
1425 { return 0; }
1426 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
1427 { return 0; }
1428 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
1429 { return 0; }
1430 static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {}
1431 static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {}
1432 #endif
1433
1434 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1435 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1436 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1437 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1438 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1439 void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1440 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
1441 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1442 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
1443 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg);
1444 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1445 int rem_wakeup, int reset);
1446 bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2);
1447 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg)
1448 { schedule_work(&hsotg->phy_reset_work); }
1449 #else
1450 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1451 { return 0; }
1452 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1453 int us)
1454 { return 0; }
1455 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1456 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
1457 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1458 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
1459 static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
1460 { return 0; }
1461 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
1462 { return 0; }
1463 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1464 { return 0; }
1465 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1466 { return 0; }
1467 static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
1468 { return 0; }
1469 static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1470 int rem_wakeup, int reset)
1471 { return 0; }
1472 static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
1473 { return false; }
1474 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {}
1475
1476 #endif
1477
1478 #endif /* __DWC2_CORE_H__ */