root/drivers/usb/dwc2/hw.h

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   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * hw.h - DesignWare HS OTG Controller hardware definitions
   4  *
   5  * Copyright 2004-2013 Synopsys, Inc.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. The names of the above-listed copyright holders may not be used
  17  *    to endorse or promote products derived from this software without
  18  *    specific prior written permission.
  19  *
  20  * ALTERNATIVELY, this software may be distributed under the terms of the
  21  * GNU General Public License ("GPL") as published by the Free Software
  22  * Foundation; either version 2 of the License, or (at your option) any
  23  * later version.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37 
  38 #ifndef __DWC2_HW_H__
  39 #define __DWC2_HW_H__
  40 
  41 #define HSOTG_REG(x)    (x)
  42 
  43 #define GOTGCTL                         HSOTG_REG(0x000)
  44 #define GOTGCTL_CHIRPEN                 BIT(27)
  45 #define GOTGCTL_MULT_VALID_BC_MASK      (0x1f << 22)
  46 #define GOTGCTL_MULT_VALID_BC_SHIFT     22
  47 #define GOTGCTL_OTGVER                  BIT(20)
  48 #define GOTGCTL_BSESVLD                 BIT(19)
  49 #define GOTGCTL_ASESVLD                 BIT(18)
  50 #define GOTGCTL_DBNC_SHORT              BIT(17)
  51 #define GOTGCTL_CONID_B                 BIT(16)
  52 #define GOTGCTL_DBNCE_FLTR_BYPASS       BIT(15)
  53 #define GOTGCTL_DEVHNPEN                BIT(11)
  54 #define GOTGCTL_HSTSETHNPEN             BIT(10)
  55 #define GOTGCTL_HNPREQ                  BIT(9)
  56 #define GOTGCTL_HSTNEGSCS               BIT(8)
  57 #define GOTGCTL_SESREQ                  BIT(1)
  58 #define GOTGCTL_SESREQSCS               BIT(0)
  59 
  60 #define GOTGINT                         HSOTG_REG(0x004)
  61 #define GOTGINT_DBNCE_DONE              BIT(19)
  62 #define GOTGINT_A_DEV_TOUT_CHG          BIT(18)
  63 #define GOTGINT_HST_NEG_DET             BIT(17)
  64 #define GOTGINT_HST_NEG_SUC_STS_CHNG    BIT(9)
  65 #define GOTGINT_SES_REQ_SUC_STS_CHNG    BIT(8)
  66 #define GOTGINT_SES_END_DET             BIT(2)
  67 
  68 #define GAHBCFG                         HSOTG_REG(0x008)
  69 #define GAHBCFG_AHB_SINGLE              BIT(23)
  70 #define GAHBCFG_NOTI_ALL_DMA_WRIT       BIT(22)
  71 #define GAHBCFG_REM_MEM_SUPP            BIT(21)
  72 #define GAHBCFG_P_TXF_EMP_LVL           BIT(8)
  73 #define GAHBCFG_NP_TXF_EMP_LVL          BIT(7)
  74 #define GAHBCFG_DMA_EN                  BIT(5)
  75 #define GAHBCFG_HBSTLEN_MASK            (0xf << 1)
  76 #define GAHBCFG_HBSTLEN_SHIFT           1
  77 #define GAHBCFG_HBSTLEN_SINGLE          0
  78 #define GAHBCFG_HBSTLEN_INCR            1
  79 #define GAHBCFG_HBSTLEN_INCR4           3
  80 #define GAHBCFG_HBSTLEN_INCR8           5
  81 #define GAHBCFG_HBSTLEN_INCR16          7
  82 #define GAHBCFG_GLBL_INTR_EN            BIT(0)
  83 #define GAHBCFG_CTRL_MASK               (GAHBCFG_P_TXF_EMP_LVL | \
  84                                          GAHBCFG_NP_TXF_EMP_LVL | \
  85                                          GAHBCFG_DMA_EN | \
  86                                          GAHBCFG_GLBL_INTR_EN)
  87 
  88 #define GUSBCFG                         HSOTG_REG(0x00C)
  89 #define GUSBCFG_FORCEDEVMODE            BIT(30)
  90 #define GUSBCFG_FORCEHOSTMODE           BIT(29)
  91 #define GUSBCFG_TXENDDELAY              BIT(28)
  92 #define GUSBCFG_ICTRAFFICPULLREMOVE     BIT(27)
  93 #define GUSBCFG_ICUSBCAP                BIT(26)
  94 #define GUSBCFG_ULPI_INT_PROT_DIS       BIT(25)
  95 #define GUSBCFG_INDICATORPASSTHROUGH    BIT(24)
  96 #define GUSBCFG_INDICATORCOMPLEMENT     BIT(23)
  97 #define GUSBCFG_TERMSELDLPULSE          BIT(22)
  98 #define GUSBCFG_ULPI_INT_VBUS_IND       BIT(21)
  99 #define GUSBCFG_ULPI_EXT_VBUS_DRV       BIT(20)
 100 #define GUSBCFG_ULPI_CLK_SUSP_M         BIT(19)
 101 #define GUSBCFG_ULPI_AUTO_RES           BIT(18)
 102 #define GUSBCFG_ULPI_FS_LS              BIT(17)
 103 #define GUSBCFG_OTG_UTMI_FS_SEL         BIT(16)
 104 #define GUSBCFG_PHY_LP_CLK_SEL          BIT(15)
 105 #define GUSBCFG_USBTRDTIM_MASK          (0xf << 10)
 106 #define GUSBCFG_USBTRDTIM_SHIFT         10
 107 #define GUSBCFG_HNPCAP                  BIT(9)
 108 #define GUSBCFG_SRPCAP                  BIT(8)
 109 #define GUSBCFG_DDRSEL                  BIT(7)
 110 #define GUSBCFG_PHYSEL                  BIT(6)
 111 #define GUSBCFG_FSINTF                  BIT(5)
 112 #define GUSBCFG_ULPI_UTMI_SEL           BIT(4)
 113 #define GUSBCFG_PHYIF16                 BIT(3)
 114 #define GUSBCFG_PHYIF8                  (0 << 3)
 115 #define GUSBCFG_TOUTCAL_MASK            (0x7 << 0)
 116 #define GUSBCFG_TOUTCAL_SHIFT           0
 117 #define GUSBCFG_TOUTCAL_LIMIT           0x7
 118 #define GUSBCFG_TOUTCAL(_x)             ((_x) << 0)
 119 
 120 #define GRSTCTL                         HSOTG_REG(0x010)
 121 #define GRSTCTL_AHBIDLE                 BIT(31)
 122 #define GRSTCTL_DMAREQ                  BIT(30)
 123 #define GRSTCTL_TXFNUM_MASK             (0x1f << 6)
 124 #define GRSTCTL_TXFNUM_SHIFT            6
 125 #define GRSTCTL_TXFNUM_LIMIT            0x1f
 126 #define GRSTCTL_TXFNUM(_x)              ((_x) << 6)
 127 #define GRSTCTL_TXFFLSH                 BIT(5)
 128 #define GRSTCTL_RXFFLSH                 BIT(4)
 129 #define GRSTCTL_IN_TKNQ_FLSH            BIT(3)
 130 #define GRSTCTL_FRMCNTRRST              BIT(2)
 131 #define GRSTCTL_HSFTRST                 BIT(1)
 132 #define GRSTCTL_CSFTRST                 BIT(0)
 133 
 134 #define GINTSTS                         HSOTG_REG(0x014)
 135 #define GINTMSK                         HSOTG_REG(0x018)
 136 #define GINTSTS_WKUPINT                 BIT(31)
 137 #define GINTSTS_SESSREQINT              BIT(30)
 138 #define GINTSTS_DISCONNINT              BIT(29)
 139 #define GINTSTS_CONIDSTSCHNG            BIT(28)
 140 #define GINTSTS_LPMTRANRCVD             BIT(27)
 141 #define GINTSTS_PTXFEMP                 BIT(26)
 142 #define GINTSTS_HCHINT                  BIT(25)
 143 #define GINTSTS_PRTINT                  BIT(24)
 144 #define GINTSTS_RESETDET                BIT(23)
 145 #define GINTSTS_FET_SUSP                BIT(22)
 146 #define GINTSTS_INCOMPL_IP              BIT(21)
 147 #define GINTSTS_INCOMPL_SOOUT           BIT(21)
 148 #define GINTSTS_INCOMPL_SOIN            BIT(20)
 149 #define GINTSTS_OEPINT                  BIT(19)
 150 #define GINTSTS_IEPINT                  BIT(18)
 151 #define GINTSTS_EPMIS                   BIT(17)
 152 #define GINTSTS_RESTOREDONE             BIT(16)
 153 #define GINTSTS_EOPF                    BIT(15)
 154 #define GINTSTS_ISOUTDROP               BIT(14)
 155 #define GINTSTS_ENUMDONE                BIT(13)
 156 #define GINTSTS_USBRST                  BIT(12)
 157 #define GINTSTS_USBSUSP                 BIT(11)
 158 #define GINTSTS_ERLYSUSP                BIT(10)
 159 #define GINTSTS_I2CINT                  BIT(9)
 160 #define GINTSTS_ULPI_CK_INT             BIT(8)
 161 #define GINTSTS_GOUTNAKEFF              BIT(7)
 162 #define GINTSTS_GINNAKEFF               BIT(6)
 163 #define GINTSTS_NPTXFEMP                BIT(5)
 164 #define GINTSTS_RXFLVL                  BIT(4)
 165 #define GINTSTS_SOF                     BIT(3)
 166 #define GINTSTS_OTGINT                  BIT(2)
 167 #define GINTSTS_MODEMIS                 BIT(1)
 168 #define GINTSTS_CURMODE_HOST            BIT(0)
 169 
 170 #define GRXSTSR                         HSOTG_REG(0x01C)
 171 #define GRXSTSP                         HSOTG_REG(0x020)
 172 #define GRXSTS_FN_MASK                  (0x7f << 25)
 173 #define GRXSTS_FN_SHIFT                 25
 174 #define GRXSTS_PKTSTS_MASK              (0xf << 17)
 175 #define GRXSTS_PKTSTS_SHIFT             17
 176 #define GRXSTS_PKTSTS_GLOBALOUTNAK      1
 177 #define GRXSTS_PKTSTS_OUTRX             2
 178 #define GRXSTS_PKTSTS_HCHIN             2
 179 #define GRXSTS_PKTSTS_OUTDONE           3
 180 #define GRXSTS_PKTSTS_HCHIN_XFER_COMP   3
 181 #define GRXSTS_PKTSTS_SETUPDONE         4
 182 #define GRXSTS_PKTSTS_DATATOGGLEERR     5
 183 #define GRXSTS_PKTSTS_SETUPRX           6
 184 #define GRXSTS_PKTSTS_HCHHALTED         7
 185 #define GRXSTS_HCHNUM_MASK              (0xf << 0)
 186 #define GRXSTS_HCHNUM_SHIFT             0
 187 #define GRXSTS_DPID_MASK                (0x3 << 15)
 188 #define GRXSTS_DPID_SHIFT               15
 189 #define GRXSTS_BYTECNT_MASK             (0x7ff << 4)
 190 #define GRXSTS_BYTECNT_SHIFT            4
 191 #define GRXSTS_EPNUM_MASK               (0xf << 0)
 192 #define GRXSTS_EPNUM_SHIFT              0
 193 
 194 #define GRXFSIZ                         HSOTG_REG(0x024)
 195 #define GRXFSIZ_DEPTH_MASK              (0xffff << 0)
 196 #define GRXFSIZ_DEPTH_SHIFT             0
 197 
 198 #define GNPTXFSIZ                       HSOTG_REG(0x028)
 199 /* Use FIFOSIZE_* constants to access this register */
 200 
 201 #define GNPTXSTS                        HSOTG_REG(0x02C)
 202 #define GNPTXSTS_NP_TXQ_TOP_MASK                (0x7f << 24)
 203 #define GNPTXSTS_NP_TXQ_TOP_SHIFT               24
 204 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK          (0xff << 16)
 205 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT         16
 206 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v)       (((_v) >> 16) & 0xff)
 207 #define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK          (0xffff << 0)
 208 #define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT         0
 209 #define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v)       (((_v) >> 0) & 0xffff)
 210 
 211 #define GI2CCTL                         HSOTG_REG(0x0030)
 212 #define GI2CCTL_BSYDNE                  BIT(31)
 213 #define GI2CCTL_RW                      BIT(30)
 214 #define GI2CCTL_I2CDATSE0               BIT(28)
 215 #define GI2CCTL_I2CDEVADDR_MASK         (0x3 << 26)
 216 #define GI2CCTL_I2CDEVADDR_SHIFT        26
 217 #define GI2CCTL_I2CSUSPCTL              BIT(25)
 218 #define GI2CCTL_ACK                     BIT(24)
 219 #define GI2CCTL_I2CEN                   BIT(23)
 220 #define GI2CCTL_ADDR_MASK               (0x7f << 16)
 221 #define GI2CCTL_ADDR_SHIFT              16
 222 #define GI2CCTL_REGADDR_MASK            (0xff << 8)
 223 #define GI2CCTL_REGADDR_SHIFT           8
 224 #define GI2CCTL_RWDATA_MASK             (0xff << 0)
 225 #define GI2CCTL_RWDATA_SHIFT            0
 226 
 227 #define GPVNDCTL                        HSOTG_REG(0x0034)
 228 #define GGPIO                           HSOTG_REG(0x0038)
 229 #define GGPIO_STM32_OTG_GCCFG_PWRDWN    BIT(16)
 230 
 231 #define GUID                            HSOTG_REG(0x003c)
 232 #define GSNPSID                         HSOTG_REG(0x0040)
 233 #define GHWCFG1                         HSOTG_REG(0x0044)
 234 #define GSNPSID_ID_MASK                 GENMASK(31, 16)
 235 
 236 #define GHWCFG2                         HSOTG_REG(0x0048)
 237 #define GHWCFG2_OTG_ENABLE_IC_USB               BIT(31)
 238 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK          (0x1f << 26)
 239 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT         26
 240 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK      (0x3 << 24)
 241 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT     24
 242 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK        (0x3 << 22)
 243 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT       22
 244 #define GHWCFG2_MULTI_PROC_INT                  BIT(20)
 245 #define GHWCFG2_DYNAMIC_FIFO                    BIT(19)
 246 #define GHWCFG2_PERIO_EP_SUPPORTED              BIT(18)
 247 #define GHWCFG2_NUM_HOST_CHAN_MASK              (0xf << 14)
 248 #define GHWCFG2_NUM_HOST_CHAN_SHIFT             14
 249 #define GHWCFG2_NUM_DEV_EP_MASK                 (0xf << 10)
 250 #define GHWCFG2_NUM_DEV_EP_SHIFT                10
 251 #define GHWCFG2_FS_PHY_TYPE_MASK                (0x3 << 8)
 252 #define GHWCFG2_FS_PHY_TYPE_SHIFT               8
 253 #define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED       0
 254 #define GHWCFG2_FS_PHY_TYPE_DEDICATED           1
 255 #define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI         2
 256 #define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI         3
 257 #define GHWCFG2_HS_PHY_TYPE_MASK                (0x3 << 6)
 258 #define GHWCFG2_HS_PHY_TYPE_SHIFT               6
 259 #define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED       0
 260 #define GHWCFG2_HS_PHY_TYPE_UTMI                1
 261 #define GHWCFG2_HS_PHY_TYPE_ULPI                2
 262 #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI           3
 263 #define GHWCFG2_POINT2POINT                     BIT(5)
 264 #define GHWCFG2_ARCHITECTURE_MASK               (0x3 << 3)
 265 #define GHWCFG2_ARCHITECTURE_SHIFT              3
 266 #define GHWCFG2_SLAVE_ONLY_ARCH                 0
 267 #define GHWCFG2_EXT_DMA_ARCH                    1
 268 #define GHWCFG2_INT_DMA_ARCH                    2
 269 #define GHWCFG2_OP_MODE_MASK                    (0x7 << 0)
 270 #define GHWCFG2_OP_MODE_SHIFT                   0
 271 #define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE         0
 272 #define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE        1
 273 #define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE      2
 274 #define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE      3
 275 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE   4
 276 #define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST        5
 277 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST     6
 278 #define GHWCFG2_OP_MODE_UNDEFINED               7
 279 
 280 #define GHWCFG3                         HSOTG_REG(0x004c)
 281 #define GHWCFG3_DFIFO_DEPTH_MASK                (0xffff << 16)
 282 #define GHWCFG3_DFIFO_DEPTH_SHIFT               16
 283 #define GHWCFG3_OTG_LPM_EN                      BIT(15)
 284 #define GHWCFG3_BC_SUPPORT                      BIT(14)
 285 #define GHWCFG3_OTG_ENABLE_HSIC                 BIT(13)
 286 #define GHWCFG3_ADP_SUPP                        BIT(12)
 287 #define GHWCFG3_SYNCH_RESET_TYPE                BIT(11)
 288 #define GHWCFG3_OPTIONAL_FEATURES               BIT(10)
 289 #define GHWCFG3_VENDOR_CTRL_IF                  BIT(9)
 290 #define GHWCFG3_I2C                             BIT(8)
 291 #define GHWCFG3_OTG_FUNC                        BIT(7)
 292 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK     (0x7 << 4)
 293 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT    4
 294 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK       (0xf << 0)
 295 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT      0
 296 
 297 #define GHWCFG4                         HSOTG_REG(0x0050)
 298 #define GHWCFG4_DESC_DMA_DYN                    BIT(31)
 299 #define GHWCFG4_DESC_DMA                        BIT(30)
 300 #define GHWCFG4_NUM_IN_EPS_MASK                 (0xf << 26)
 301 #define GHWCFG4_NUM_IN_EPS_SHIFT                26
 302 #define GHWCFG4_DED_FIFO_EN                     BIT(25)
 303 #define GHWCFG4_DED_FIFO_SHIFT          25
 304 #define GHWCFG4_SESSION_END_FILT_EN             BIT(24)
 305 #define GHWCFG4_B_VALID_FILT_EN                 BIT(23)
 306 #define GHWCFG4_A_VALID_FILT_EN                 BIT(22)
 307 #define GHWCFG4_VBUS_VALID_FILT_EN              BIT(21)
 308 #define GHWCFG4_IDDIG_FILT_EN                   BIT(20)
 309 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK       (0xf << 16)
 310 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT      16
 311 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK        (0x3 << 14)
 312 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT       14
 313 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8           0
 314 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16          1
 315 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16     2
 316 #define GHWCFG4_ACG_SUPPORTED                   BIT(12)
 317 #define GHWCFG4_IPG_ISOC_SUPPORTED              BIT(11)
 318 #define GHWCFG4_SERVICE_INTERVAL_SUPPORTED      BIT(10)
 319 #define GHWCFG4_XHIBER                          BIT(7)
 320 #define GHWCFG4_HIBER                           BIT(6)
 321 #define GHWCFG4_MIN_AHB_FREQ                    BIT(5)
 322 #define GHWCFG4_POWER_OPTIMIZ                   BIT(4)
 323 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK        (0xf << 0)
 324 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT       0
 325 
 326 #define GLPMCFG                         HSOTG_REG(0x0054)
 327 #define GLPMCFG_INVSELHSIC              BIT(31)
 328 #define GLPMCFG_HSICCON                 BIT(30)
 329 #define GLPMCFG_RSTRSLPSTS              BIT(29)
 330 #define GLPMCFG_ENBESL                  BIT(28)
 331 #define GLPMCFG_LPM_RETRYCNT_STS_MASK   (0x7 << 25)
 332 #define GLPMCFG_LPM_RETRYCNT_STS_SHIFT  25
 333 #define GLPMCFG_SNDLPM                  BIT(24)
 334 #define GLPMCFG_RETRY_CNT_MASK          (0x7 << 21)
 335 #define GLPMCFG_RETRY_CNT_SHIFT         21
 336 #define GLPMCFG_LPM_REJECT_CTRL_CONTROL BIT(21)
 337 #define GLPMCFG_LPM_ACCEPT_CTRL_ISOC    BIT(22)
 338 #define GLPMCFG_LPM_CHNL_INDX_MASK      (0xf << 17)
 339 #define GLPMCFG_LPM_CHNL_INDX_SHIFT     17
 340 #define GLPMCFG_L1RESUMEOK              BIT(16)
 341 #define GLPMCFG_SLPSTS                  BIT(15)
 342 #define GLPMCFG_COREL1RES_MASK          (0x3 << 13)
 343 #define GLPMCFG_COREL1RES_SHIFT         13
 344 #define GLPMCFG_HIRD_THRES_MASK         (0x1f << 8)
 345 #define GLPMCFG_HIRD_THRES_SHIFT        8
 346 #define GLPMCFG_HIRD_THRES_EN           (0x10 << 8)
 347 #define GLPMCFG_ENBLSLPM                BIT(7)
 348 #define GLPMCFG_BREMOTEWAKE             BIT(6)
 349 #define GLPMCFG_HIRD_MASK               (0xf << 2)
 350 #define GLPMCFG_HIRD_SHIFT              2
 351 #define GLPMCFG_APPL1RES                BIT(1)
 352 #define GLPMCFG_LPMCAP                  BIT(0)
 353 
 354 #define GPWRDN                          HSOTG_REG(0x0058)
 355 #define GPWRDN_MULT_VAL_ID_BC_MASK      (0x1f << 24)
 356 #define GPWRDN_MULT_VAL_ID_BC_SHIFT     24
 357 #define GPWRDN_ADP_INT                  BIT(23)
 358 #define GPWRDN_BSESSVLD                 BIT(22)
 359 #define GPWRDN_IDSTS                    BIT(21)
 360 #define GPWRDN_LINESTATE_MASK           (0x3 << 19)
 361 #define GPWRDN_LINESTATE_SHIFT          19
 362 #define GPWRDN_STS_CHGINT_MSK           BIT(18)
 363 #define GPWRDN_STS_CHGINT               BIT(17)
 364 #define GPWRDN_SRP_DET_MSK              BIT(16)
 365 #define GPWRDN_SRP_DET                  BIT(15)
 366 #define GPWRDN_CONNECT_DET_MSK          BIT(14)
 367 #define GPWRDN_CONNECT_DET              BIT(13)
 368 #define GPWRDN_DISCONN_DET_MSK          BIT(12)
 369 #define GPWRDN_DISCONN_DET              BIT(11)
 370 #define GPWRDN_RST_DET_MSK              BIT(10)
 371 #define GPWRDN_RST_DET                  BIT(9)
 372 #define GPWRDN_LNSTSCHG_MSK             BIT(8)
 373 #define GPWRDN_LNSTSCHG                 BIT(7)
 374 #define GPWRDN_DIS_VBUS                 BIT(6)
 375 #define GPWRDN_PWRDNSWTCH               BIT(5)
 376 #define GPWRDN_PWRDNRSTN                BIT(4)
 377 #define GPWRDN_PWRDNCLMP                BIT(3)
 378 #define GPWRDN_RESTORE                  BIT(2)
 379 #define GPWRDN_PMUACTV                  BIT(1)
 380 #define GPWRDN_PMUINTSEL                BIT(0)
 381 
 382 #define GDFIFOCFG                       HSOTG_REG(0x005c)
 383 #define GDFIFOCFG_EPINFOBASE_MASK       (0xffff << 16)
 384 #define GDFIFOCFG_EPINFOBASE_SHIFT      16
 385 #define GDFIFOCFG_GDFIFOCFG_MASK        (0xffff << 0)
 386 #define GDFIFOCFG_GDFIFOCFG_SHIFT       0
 387 
 388 #define ADPCTL                          HSOTG_REG(0x0060)
 389 #define ADPCTL_AR_MASK                  (0x3 << 27)
 390 #define ADPCTL_AR_SHIFT                 27
 391 #define ADPCTL_ADP_TMOUT_INT_MSK        BIT(26)
 392 #define ADPCTL_ADP_SNS_INT_MSK          BIT(25)
 393 #define ADPCTL_ADP_PRB_INT_MSK          BIT(24)
 394 #define ADPCTL_ADP_TMOUT_INT            BIT(23)
 395 #define ADPCTL_ADP_SNS_INT              BIT(22)
 396 #define ADPCTL_ADP_PRB_INT              BIT(21)
 397 #define ADPCTL_ADPENA                   BIT(20)
 398 #define ADPCTL_ADPRES                   BIT(19)
 399 #define ADPCTL_ENASNS                   BIT(18)
 400 #define ADPCTL_ENAPRB                   BIT(17)
 401 #define ADPCTL_RTIM_MASK                (0x7ff << 6)
 402 #define ADPCTL_RTIM_SHIFT               6
 403 #define ADPCTL_PRB_PER_MASK             (0x3 << 4)
 404 #define ADPCTL_PRB_PER_SHIFT            4
 405 #define ADPCTL_PRB_DELTA_MASK           (0x3 << 2)
 406 #define ADPCTL_PRB_DELTA_SHIFT          2
 407 #define ADPCTL_PRB_DSCHRG_MASK          (0x3 << 0)
 408 #define ADPCTL_PRB_DSCHRG_SHIFT         0
 409 
 410 #define GREFCLK                             HSOTG_REG(0x0064)
 411 #define GREFCLK_REFCLKPER_MASK              (0x1ffff << 15)
 412 #define GREFCLK_REFCLKPER_SHIFT             15
 413 #define GREFCLK_REF_CLK_MODE                BIT(14)
 414 #define GREFCLK_SOF_CNT_WKUP_ALERT_MASK     (0x3ff)
 415 #define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT    0
 416 
 417 #define GINTMSK2                        HSOTG_REG(0x0068)
 418 #define GINTMSK2_WKUP_ALERT_INT_MSK     BIT(0)
 419 
 420 #define GINTSTS2                        HSOTG_REG(0x006c)
 421 #define GINTSTS2_WKUP_ALERT_INT         BIT(0)
 422 
 423 #define HPTXFSIZ                        HSOTG_REG(0x100)
 424 /* Use FIFOSIZE_* constants to access this register */
 425 
 426 #define DPTXFSIZN(_a)                   HSOTG_REG(0x104 + (((_a) - 1) * 4))
 427 /* Use FIFOSIZE_* constants to access this register */
 428 
 429 /* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
 430 #define FIFOSIZE_DEPTH_MASK             (0xffff << 16)
 431 #define FIFOSIZE_DEPTH_SHIFT            16
 432 #define FIFOSIZE_STARTADDR_MASK         (0xffff << 0)
 433 #define FIFOSIZE_STARTADDR_SHIFT        0
 434 #define FIFOSIZE_DEPTH_GET(_x)          (((_x) >> 16) & 0xffff)
 435 
 436 /* Device mode registers */
 437 
 438 #define DCFG                            HSOTG_REG(0x800)
 439 #define DCFG_DESCDMA_EN                 BIT(23)
 440 #define DCFG_EPMISCNT_MASK              (0x1f << 18)
 441 #define DCFG_EPMISCNT_SHIFT             18
 442 #define DCFG_EPMISCNT_LIMIT             0x1f
 443 #define DCFG_EPMISCNT(_x)               ((_x) << 18)
 444 #define DCFG_IPG_ISOC_SUPPORDED         BIT(17)
 445 #define DCFG_PERFRINT_MASK              (0x3 << 11)
 446 #define DCFG_PERFRINT_SHIFT             11
 447 #define DCFG_PERFRINT_LIMIT             0x3
 448 #define DCFG_PERFRINT(_x)               ((_x) << 11)
 449 #define DCFG_DEVADDR_MASK               (0x7f << 4)
 450 #define DCFG_DEVADDR_SHIFT              4
 451 #define DCFG_DEVADDR_LIMIT              0x7f
 452 #define DCFG_DEVADDR(_x)                ((_x) << 4)
 453 #define DCFG_NZ_STS_OUT_HSHK            BIT(2)
 454 #define DCFG_DEVSPD_MASK                (0x3 << 0)
 455 #define DCFG_DEVSPD_SHIFT               0
 456 #define DCFG_DEVSPD_HS                  0
 457 #define DCFG_DEVSPD_FS                  1
 458 #define DCFG_DEVSPD_LS                  2
 459 #define DCFG_DEVSPD_FS48                3
 460 
 461 #define DCTL                            HSOTG_REG(0x804)
 462 #define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19)
 463 #define DCTL_PWRONPRGDONE               BIT(11)
 464 #define DCTL_CGOUTNAK                   BIT(10)
 465 #define DCTL_SGOUTNAK                   BIT(9)
 466 #define DCTL_CGNPINNAK                  BIT(8)
 467 #define DCTL_SGNPINNAK                  BIT(7)
 468 #define DCTL_TSTCTL_MASK                (0x7 << 4)
 469 #define DCTL_TSTCTL_SHIFT               4
 470 #define DCTL_GOUTNAKSTS                 BIT(3)
 471 #define DCTL_GNPINNAKSTS                BIT(2)
 472 #define DCTL_SFTDISCON                  BIT(1)
 473 #define DCTL_RMTWKUPSIG                 BIT(0)
 474 
 475 #define DSTS                            HSOTG_REG(0x808)
 476 #define DSTS_SOFFN_MASK                 (0x3fff << 8)
 477 #define DSTS_SOFFN_SHIFT                8
 478 #define DSTS_SOFFN_LIMIT                0x3fff
 479 #define DSTS_SOFFN(_x)                  ((_x) << 8)
 480 #define DSTS_ERRATICERR                 BIT(3)
 481 #define DSTS_ENUMSPD_MASK               (0x3 << 1)
 482 #define DSTS_ENUMSPD_SHIFT              1
 483 #define DSTS_ENUMSPD_HS                 0
 484 #define DSTS_ENUMSPD_FS                 1
 485 #define DSTS_ENUMSPD_LS                 2
 486 #define DSTS_ENUMSPD_FS48               3
 487 #define DSTS_SUSPSTS                    BIT(0)
 488 
 489 #define DIEPMSK                         HSOTG_REG(0x810)
 490 #define DIEPMSK_NAKMSK                  BIT(13)
 491 #define DIEPMSK_BNAININTRMSK            BIT(9)
 492 #define DIEPMSK_TXFIFOUNDRNMSK          BIT(8)
 493 #define DIEPMSK_TXFIFOEMPTY             BIT(7)
 494 #define DIEPMSK_INEPNAKEFFMSK           BIT(6)
 495 #define DIEPMSK_INTKNEPMISMSK           BIT(5)
 496 #define DIEPMSK_INTKNTXFEMPMSK          BIT(4)
 497 #define DIEPMSK_TIMEOUTMSK              BIT(3)
 498 #define DIEPMSK_AHBERRMSK               BIT(2)
 499 #define DIEPMSK_EPDISBLDMSK             BIT(1)
 500 #define DIEPMSK_XFERCOMPLMSK            BIT(0)
 501 
 502 #define DOEPMSK                         HSOTG_REG(0x814)
 503 #define DOEPMSK_BNAMSK                  BIT(9)
 504 #define DOEPMSK_BACK2BACKSETUP          BIT(6)
 505 #define DOEPMSK_STSPHSERCVDMSK          BIT(5)
 506 #define DOEPMSK_OUTTKNEPDISMSK          BIT(4)
 507 #define DOEPMSK_SETUPMSK                BIT(3)
 508 #define DOEPMSK_AHBERRMSK               BIT(2)
 509 #define DOEPMSK_EPDISBLDMSK             BIT(1)
 510 #define DOEPMSK_XFERCOMPLMSK            BIT(0)
 511 
 512 #define DAINT                           HSOTG_REG(0x818)
 513 #define DAINTMSK                        HSOTG_REG(0x81C)
 514 #define DAINT_OUTEP_SHIFT               16
 515 #define DAINT_OUTEP(_x)                 (1 << ((_x) + 16))
 516 #define DAINT_INEP(_x)                  (1 << (_x))
 517 
 518 #define DTKNQR1                         HSOTG_REG(0x820)
 519 #define DTKNQR2                         HSOTG_REG(0x824)
 520 #define DTKNQR3                         HSOTG_REG(0x830)
 521 #define DTKNQR4                         HSOTG_REG(0x834)
 522 #define DIEPEMPMSK                      HSOTG_REG(0x834)
 523 
 524 #define DVBUSDIS                        HSOTG_REG(0x828)
 525 #define DVBUSPULSE                      HSOTG_REG(0x82C)
 526 
 527 #define DIEPCTL0                        HSOTG_REG(0x900)
 528 #define DIEPCTL(_a)                     HSOTG_REG(0x900 + ((_a) * 0x20))
 529 
 530 #define DOEPCTL0                        HSOTG_REG(0xB00)
 531 #define DOEPCTL(_a)                     HSOTG_REG(0xB00 + ((_a) * 0x20))
 532 
 533 /* EP0 specialness:
 534  * bits[29..28] - reserved (no SetD0PID, SetD1PID)
 535  * bits[25..22] - should always be zero, this isn't a periodic endpoint
 536  * bits[10..0]  - MPS setting different for EP0
 537  */
 538 #define D0EPCTL_MPS_MASK                (0x3 << 0)
 539 #define D0EPCTL_MPS_SHIFT               0
 540 #define D0EPCTL_MPS_64                  0
 541 #define D0EPCTL_MPS_32                  1
 542 #define D0EPCTL_MPS_16                  2
 543 #define D0EPCTL_MPS_8                   3
 544 
 545 #define DXEPCTL_EPENA                   BIT(31)
 546 #define DXEPCTL_EPDIS                   BIT(30)
 547 #define DXEPCTL_SETD1PID                BIT(29)
 548 #define DXEPCTL_SETODDFR                BIT(29)
 549 #define DXEPCTL_SETD0PID                BIT(28)
 550 #define DXEPCTL_SETEVENFR               BIT(28)
 551 #define DXEPCTL_SNAK                    BIT(27)
 552 #define DXEPCTL_CNAK                    BIT(26)
 553 #define DXEPCTL_TXFNUM_MASK             (0xf << 22)
 554 #define DXEPCTL_TXFNUM_SHIFT            22
 555 #define DXEPCTL_TXFNUM_LIMIT            0xf
 556 #define DXEPCTL_TXFNUM(_x)              ((_x) << 22)
 557 #define DXEPCTL_STALL                   BIT(21)
 558 #define DXEPCTL_SNP                     BIT(20)
 559 #define DXEPCTL_EPTYPE_MASK             (0x3 << 18)
 560 #define DXEPCTL_EPTYPE_CONTROL          (0x0 << 18)
 561 #define DXEPCTL_EPTYPE_ISO              (0x1 << 18)
 562 #define DXEPCTL_EPTYPE_BULK             (0x2 << 18)
 563 #define DXEPCTL_EPTYPE_INTERRUPT        (0x3 << 18)
 564 
 565 #define DXEPCTL_NAKSTS                  BIT(17)
 566 #define DXEPCTL_DPID                    BIT(16)
 567 #define DXEPCTL_EOFRNUM                 BIT(16)
 568 #define DXEPCTL_USBACTEP                BIT(15)
 569 #define DXEPCTL_NEXTEP_MASK             (0xf << 11)
 570 #define DXEPCTL_NEXTEP_SHIFT            11
 571 #define DXEPCTL_NEXTEP_LIMIT            0xf
 572 #define DXEPCTL_NEXTEP(_x)              ((_x) << 11)
 573 #define DXEPCTL_MPS_MASK                (0x7ff << 0)
 574 #define DXEPCTL_MPS_SHIFT               0
 575 #define DXEPCTL_MPS_LIMIT               0x7ff
 576 #define DXEPCTL_MPS(_x)                 ((_x) << 0)
 577 
 578 #define DIEPINT(_a)                     HSOTG_REG(0x908 + ((_a) * 0x20))
 579 #define DOEPINT(_a)                     HSOTG_REG(0xB08 + ((_a) * 0x20))
 580 #define DXEPINT_SETUP_RCVD              BIT(15)
 581 #define DXEPINT_NYETINTRPT              BIT(14)
 582 #define DXEPINT_NAKINTRPT               BIT(13)
 583 #define DXEPINT_BBLEERRINTRPT           BIT(12)
 584 #define DXEPINT_PKTDRPSTS               BIT(11)
 585 #define DXEPINT_BNAINTR                 BIT(9)
 586 #define DXEPINT_TXFIFOUNDRN             BIT(8)
 587 #define DXEPINT_OUTPKTERR               BIT(8)
 588 #define DXEPINT_TXFEMP                  BIT(7)
 589 #define DXEPINT_INEPNAKEFF              BIT(6)
 590 #define DXEPINT_BACK2BACKSETUP          BIT(6)
 591 #define DXEPINT_INTKNEPMIS              BIT(5)
 592 #define DXEPINT_STSPHSERCVD             BIT(5)
 593 #define DXEPINT_INTKNTXFEMP             BIT(4)
 594 #define DXEPINT_OUTTKNEPDIS             BIT(4)
 595 #define DXEPINT_TIMEOUT                 BIT(3)
 596 #define DXEPINT_SETUP                   BIT(3)
 597 #define DXEPINT_AHBERR                  BIT(2)
 598 #define DXEPINT_EPDISBLD                BIT(1)
 599 #define DXEPINT_XFERCOMPL               BIT(0)
 600 
 601 #define DIEPTSIZ0                       HSOTG_REG(0x910)
 602 #define DIEPTSIZ0_PKTCNT_MASK           (0x3 << 19)
 603 #define DIEPTSIZ0_PKTCNT_SHIFT          19
 604 #define DIEPTSIZ0_PKTCNT_LIMIT          0x3
 605 #define DIEPTSIZ0_PKTCNT(_x)            ((_x) << 19)
 606 #define DIEPTSIZ0_XFERSIZE_MASK         (0x7f << 0)
 607 #define DIEPTSIZ0_XFERSIZE_SHIFT        0
 608 #define DIEPTSIZ0_XFERSIZE_LIMIT        0x7f
 609 #define DIEPTSIZ0_XFERSIZE(_x)          ((_x) << 0)
 610 
 611 #define DOEPTSIZ0                       HSOTG_REG(0xB10)
 612 #define DOEPTSIZ0_SUPCNT_MASK           (0x3 << 29)
 613 #define DOEPTSIZ0_SUPCNT_SHIFT          29
 614 #define DOEPTSIZ0_SUPCNT_LIMIT          0x3
 615 #define DOEPTSIZ0_SUPCNT(_x)            ((_x) << 29)
 616 #define DOEPTSIZ0_PKTCNT                BIT(19)
 617 #define DOEPTSIZ0_XFERSIZE_MASK         (0x7f << 0)
 618 #define DOEPTSIZ0_XFERSIZE_SHIFT        0
 619 
 620 #define DIEPTSIZ(_a)                    HSOTG_REG(0x910 + ((_a) * 0x20))
 621 #define DOEPTSIZ(_a)                    HSOTG_REG(0xB10 + ((_a) * 0x20))
 622 #define DXEPTSIZ_MC_MASK                (0x3 << 29)
 623 #define DXEPTSIZ_MC_SHIFT               29
 624 #define DXEPTSIZ_MC_LIMIT               0x3
 625 #define DXEPTSIZ_MC(_x)                 ((_x) << 29)
 626 #define DXEPTSIZ_PKTCNT_MASK            (0x3ff << 19)
 627 #define DXEPTSIZ_PKTCNT_SHIFT           19
 628 #define DXEPTSIZ_PKTCNT_LIMIT           0x3ff
 629 #define DXEPTSIZ_PKTCNT_GET(_v)         (((_v) >> 19) & 0x3ff)
 630 #define DXEPTSIZ_PKTCNT(_x)             ((_x) << 19)
 631 #define DXEPTSIZ_XFERSIZE_MASK          (0x7ffff << 0)
 632 #define DXEPTSIZ_XFERSIZE_SHIFT         0
 633 #define DXEPTSIZ_XFERSIZE_LIMIT         0x7ffff
 634 #define DXEPTSIZ_XFERSIZE_GET(_v)       (((_v) >> 0) & 0x7ffff)
 635 #define DXEPTSIZ_XFERSIZE(_x)           ((_x) << 0)
 636 
 637 #define DIEPDMA(_a)                     HSOTG_REG(0x914 + ((_a) * 0x20))
 638 #define DOEPDMA(_a)                     HSOTG_REG(0xB14 + ((_a) * 0x20))
 639 
 640 #define DTXFSTS(_a)                     HSOTG_REG(0x918 + ((_a) * 0x20))
 641 
 642 #define PCGCTL                          HSOTG_REG(0x0e00)
 643 #define PCGCTL_IF_DEV_MODE              BIT(31)
 644 #define PCGCTL_P2HD_PRT_SPD_MASK        (0x3 << 29)
 645 #define PCGCTL_P2HD_PRT_SPD_SHIFT       29
 646 #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK   (0x3 << 27)
 647 #define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT  27
 648 #define PCGCTL_MAC_DEV_ADDR_MASK        (0x7f << 20)
 649 #define PCGCTL_MAC_DEV_ADDR_SHIFT       20
 650 #define PCGCTL_MAX_TERMSEL              BIT(19)
 651 #define PCGCTL_MAX_XCVRSELECT_MASK      (0x3 << 17)
 652 #define PCGCTL_MAX_XCVRSELECT_SHIFT     17
 653 #define PCGCTL_PORT_POWER               BIT(16)
 654 #define PCGCTL_PRT_CLK_SEL_MASK         (0x3 << 14)
 655 #define PCGCTL_PRT_CLK_SEL_SHIFT        14
 656 #define PCGCTL_ESS_REG_RESTORED         BIT(13)
 657 #define PCGCTL_EXTND_HIBER_SWITCH       BIT(12)
 658 #define PCGCTL_EXTND_HIBER_PWRCLMP      BIT(11)
 659 #define PCGCTL_ENBL_EXTND_HIBER         BIT(10)
 660 #define PCGCTL_RESTOREMODE              BIT(9)
 661 #define PCGCTL_RESETAFTSUSP             BIT(8)
 662 #define PCGCTL_DEEP_SLEEP               BIT(7)
 663 #define PCGCTL_PHY_IN_SLEEP             BIT(6)
 664 #define PCGCTL_ENBL_SLEEP_GATING        BIT(5)
 665 #define PCGCTL_RSTPDWNMODULE            BIT(3)
 666 #define PCGCTL_PWRCLMP                  BIT(2)
 667 #define PCGCTL_GATEHCLK                 BIT(1)
 668 #define PCGCTL_STOPPCLK                 BIT(0)
 669 
 670 #define PCGCCTL1                        HSOTG_REG(0xe04)
 671 #define PCGCCTL1_TIMER                  (0x3 << 1)
 672 #define PCGCCTL1_GATEEN                 BIT(0)
 673 
 674 #define EPFIFO(_a)                      HSOTG_REG(0x1000 + ((_a) * 0x1000))
 675 
 676 /* Host Mode Registers */
 677 
 678 #define HCFG                            HSOTG_REG(0x0400)
 679 #define HCFG_MODECHTIMEN                BIT(31)
 680 #define HCFG_PERSCHEDENA                BIT(26)
 681 #define HCFG_FRLISTEN_MASK              (0x3 << 24)
 682 #define HCFG_FRLISTEN_SHIFT             24
 683 #define HCFG_FRLISTEN_8                         (0 << 24)
 684 #define FRLISTEN_8_SIZE                         8
 685 #define HCFG_FRLISTEN_16                        BIT(24)
 686 #define FRLISTEN_16_SIZE                        16
 687 #define HCFG_FRLISTEN_32                        (2 << 24)
 688 #define FRLISTEN_32_SIZE                        32
 689 #define HCFG_FRLISTEN_64                        (3 << 24)
 690 #define FRLISTEN_64_SIZE                        64
 691 #define HCFG_DESCDMA                    BIT(23)
 692 #define HCFG_RESVALID_MASK              (0xff << 8)
 693 #define HCFG_RESVALID_SHIFT             8
 694 #define HCFG_ENA32KHZ                   BIT(7)
 695 #define HCFG_FSLSSUPP                   BIT(2)
 696 #define HCFG_FSLSPCLKSEL_MASK           (0x3 << 0)
 697 #define HCFG_FSLSPCLKSEL_SHIFT          0
 698 #define HCFG_FSLSPCLKSEL_30_60_MHZ      0
 699 #define HCFG_FSLSPCLKSEL_48_MHZ         1
 700 #define HCFG_FSLSPCLKSEL_6_MHZ          2
 701 
 702 #define HFIR                            HSOTG_REG(0x0404)
 703 #define HFIR_FRINT_MASK                 (0xffff << 0)
 704 #define HFIR_FRINT_SHIFT                0
 705 #define HFIR_RLDCTRL                    BIT(16)
 706 
 707 #define HFNUM                           HSOTG_REG(0x0408)
 708 #define HFNUM_FRREM_MASK                (0xffff << 16)
 709 #define HFNUM_FRREM_SHIFT               16
 710 #define HFNUM_FRNUM_MASK                (0xffff << 0)
 711 #define HFNUM_FRNUM_SHIFT               0
 712 #define HFNUM_MAX_FRNUM                 0x3fff
 713 
 714 #define HPTXSTS                         HSOTG_REG(0x0410)
 715 #define TXSTS_QTOP_ODD                  BIT(31)
 716 #define TXSTS_QTOP_CHNEP_MASK           (0xf << 27)
 717 #define TXSTS_QTOP_CHNEP_SHIFT          27
 718 #define TXSTS_QTOP_TOKEN_MASK           (0x3 << 25)
 719 #define TXSTS_QTOP_TOKEN_SHIFT          25
 720 #define TXSTS_QTOP_TERMINATE            BIT(24)
 721 #define TXSTS_QSPCAVAIL_MASK            (0xff << 16)
 722 #define TXSTS_QSPCAVAIL_SHIFT           16
 723 #define TXSTS_FSPCAVAIL_MASK            (0xffff << 0)
 724 #define TXSTS_FSPCAVAIL_SHIFT           0
 725 
 726 #define HAINT                           HSOTG_REG(0x0414)
 727 #define HAINTMSK                        HSOTG_REG(0x0418)
 728 #define HFLBADDR                        HSOTG_REG(0x041c)
 729 
 730 #define HPRT0                           HSOTG_REG(0x0440)
 731 #define HPRT0_SPD_MASK                  (0x3 << 17)
 732 #define HPRT0_SPD_SHIFT                 17
 733 #define HPRT0_SPD_HIGH_SPEED            0
 734 #define HPRT0_SPD_FULL_SPEED            1
 735 #define HPRT0_SPD_LOW_SPEED             2
 736 #define HPRT0_TSTCTL_MASK               (0xf << 13)
 737 #define HPRT0_TSTCTL_SHIFT              13
 738 #define HPRT0_PWR                       BIT(12)
 739 #define HPRT0_LNSTS_MASK                (0x3 << 10)
 740 #define HPRT0_LNSTS_SHIFT               10
 741 #define HPRT0_RST                       BIT(8)
 742 #define HPRT0_SUSP                      BIT(7)
 743 #define HPRT0_RES                       BIT(6)
 744 #define HPRT0_OVRCURRCHG                BIT(5)
 745 #define HPRT0_OVRCURRACT                BIT(4)
 746 #define HPRT0_ENACHG                    BIT(3)
 747 #define HPRT0_ENA                       BIT(2)
 748 #define HPRT0_CONNDET                   BIT(1)
 749 #define HPRT0_CONNSTS                   BIT(0)
 750 
 751 #define HCCHAR(_ch)                     HSOTG_REG(0x0500 + 0x20 * (_ch))
 752 #define HCCHAR_CHENA                    BIT(31)
 753 #define HCCHAR_CHDIS                    BIT(30)
 754 #define HCCHAR_ODDFRM                   BIT(29)
 755 #define HCCHAR_DEVADDR_MASK             (0x7f << 22)
 756 #define HCCHAR_DEVADDR_SHIFT            22
 757 #define HCCHAR_MULTICNT_MASK            (0x3 << 20)
 758 #define HCCHAR_MULTICNT_SHIFT           20
 759 #define HCCHAR_EPTYPE_MASK              (0x3 << 18)
 760 #define HCCHAR_EPTYPE_SHIFT             18
 761 #define HCCHAR_LSPDDEV                  BIT(17)
 762 #define HCCHAR_EPDIR                    BIT(15)
 763 #define HCCHAR_EPNUM_MASK               (0xf << 11)
 764 #define HCCHAR_EPNUM_SHIFT              11
 765 #define HCCHAR_MPS_MASK                 (0x7ff << 0)
 766 #define HCCHAR_MPS_SHIFT                0
 767 
 768 #define HCSPLT(_ch)                     HSOTG_REG(0x0504 + 0x20 * (_ch))
 769 #define HCSPLT_SPLTENA                  BIT(31)
 770 #define HCSPLT_COMPSPLT                 BIT(16)
 771 #define HCSPLT_XACTPOS_MASK             (0x3 << 14)
 772 #define HCSPLT_XACTPOS_SHIFT            14
 773 #define HCSPLT_XACTPOS_MID              0
 774 #define HCSPLT_XACTPOS_END              1
 775 #define HCSPLT_XACTPOS_BEGIN            2
 776 #define HCSPLT_XACTPOS_ALL              3
 777 #define HCSPLT_HUBADDR_MASK             (0x7f << 7)
 778 #define HCSPLT_HUBADDR_SHIFT            7
 779 #define HCSPLT_PRTADDR_MASK             (0x7f << 0)
 780 #define HCSPLT_PRTADDR_SHIFT            0
 781 
 782 #define HCINT(_ch)                      HSOTG_REG(0x0508 + 0x20 * (_ch))
 783 #define HCINTMSK(_ch)                   HSOTG_REG(0x050c + 0x20 * (_ch))
 784 #define HCINTMSK_RESERVED14_31          (0x3ffff << 14)
 785 #define HCINTMSK_FRM_LIST_ROLL          BIT(13)
 786 #define HCINTMSK_XCS_XACT               BIT(12)
 787 #define HCINTMSK_BNA                    BIT(11)
 788 #define HCINTMSK_DATATGLERR             BIT(10)
 789 #define HCINTMSK_FRMOVRUN               BIT(9)
 790 #define HCINTMSK_BBLERR                 BIT(8)
 791 #define HCINTMSK_XACTERR                BIT(7)
 792 #define HCINTMSK_NYET                   BIT(6)
 793 #define HCINTMSK_ACK                    BIT(5)
 794 #define HCINTMSK_NAK                    BIT(4)
 795 #define HCINTMSK_STALL                  BIT(3)
 796 #define HCINTMSK_AHBERR                 BIT(2)
 797 #define HCINTMSK_CHHLTD                 BIT(1)
 798 #define HCINTMSK_XFERCOMPL              BIT(0)
 799 
 800 #define HCTSIZ(_ch)                     HSOTG_REG(0x0510 + 0x20 * (_ch))
 801 #define TSIZ_DOPNG                      BIT(31)
 802 #define TSIZ_SC_MC_PID_MASK             (0x3 << 29)
 803 #define TSIZ_SC_MC_PID_SHIFT            29
 804 #define TSIZ_SC_MC_PID_DATA0            0
 805 #define TSIZ_SC_MC_PID_DATA2            1
 806 #define TSIZ_SC_MC_PID_DATA1            2
 807 #define TSIZ_SC_MC_PID_MDATA            3
 808 #define TSIZ_SC_MC_PID_SETUP            3
 809 #define TSIZ_PKTCNT_MASK                (0x3ff << 19)
 810 #define TSIZ_PKTCNT_SHIFT               19
 811 #define TSIZ_NTD_MASK                   (0xff << 8)
 812 #define TSIZ_NTD_SHIFT                  8
 813 #define TSIZ_SCHINFO_MASK               (0xff << 0)
 814 #define TSIZ_SCHINFO_SHIFT              0
 815 #define TSIZ_XFERSIZE_MASK              (0x7ffff << 0)
 816 #define TSIZ_XFERSIZE_SHIFT             0
 817 
 818 #define HCDMA(_ch)                      HSOTG_REG(0x0514 + 0x20 * (_ch))
 819 
 820 #define HCDMAB(_ch)                     HSOTG_REG(0x051c + 0x20 * (_ch))
 821 
 822 #define HCFIFO(_ch)                     HSOTG_REG(0x1000 + 0x1000 * (_ch))
 823 
 824 /**
 825  * struct dwc2_dma_desc - DMA descriptor structure,
 826  * used for both host and gadget modes
 827  *
 828  * @status: DMA descriptor status quadlet
 829  * @buf:    DMA descriptor data buffer pointer
 830  *
 831  * DMA Descriptor structure contains two quadlets:
 832  * Status quadlet and Data buffer pointer.
 833  */
 834 struct dwc2_dma_desc {
 835         u32 status;
 836         u32 buf;
 837 } __packed;
 838 
 839 /* Host Mode DMA descriptor status quadlet */
 840 
 841 #define HOST_DMA_A                      BIT(31)
 842 #define HOST_DMA_STS_MASK               (0x3 << 28)
 843 #define HOST_DMA_STS_SHIFT              28
 844 #define HOST_DMA_STS_PKTERR             BIT(28)
 845 #define HOST_DMA_EOL                    BIT(26)
 846 #define HOST_DMA_IOC                    BIT(25)
 847 #define HOST_DMA_SUP                    BIT(24)
 848 #define HOST_DMA_ALT_QTD                BIT(23)
 849 #define HOST_DMA_QTD_OFFSET_MASK        (0x3f << 17)
 850 #define HOST_DMA_QTD_OFFSET_SHIFT       17
 851 #define HOST_DMA_ISOC_NBYTES_MASK       (0xfff << 0)
 852 #define HOST_DMA_ISOC_NBYTES_SHIFT      0
 853 #define HOST_DMA_NBYTES_MASK            (0x1ffff << 0)
 854 #define HOST_DMA_NBYTES_SHIFT           0
 855 #define HOST_DMA_NBYTES_LIMIT           131071
 856 
 857 /* Device Mode DMA descriptor status quadlet */
 858 
 859 #define DEV_DMA_BUFF_STS_MASK           (0x3 << 30)
 860 #define DEV_DMA_BUFF_STS_SHIFT          30
 861 #define DEV_DMA_BUFF_STS_HREADY         0
 862 #define DEV_DMA_BUFF_STS_DMABUSY        1
 863 #define DEV_DMA_BUFF_STS_DMADONE        2
 864 #define DEV_DMA_BUFF_STS_HBUSY          3
 865 #define DEV_DMA_STS_MASK                (0x3 << 28)
 866 #define DEV_DMA_STS_SHIFT               28
 867 #define DEV_DMA_STS_SUCC                0
 868 #define DEV_DMA_STS_BUFF_FLUSH          1
 869 #define DEV_DMA_STS_BUFF_ERR            3
 870 #define DEV_DMA_L                       BIT(27)
 871 #define DEV_DMA_SHORT                   BIT(26)
 872 #define DEV_DMA_IOC                     BIT(25)
 873 #define DEV_DMA_SR                      BIT(24)
 874 #define DEV_DMA_MTRF                    BIT(23)
 875 #define DEV_DMA_ISOC_PID_MASK           (0x3 << 23)
 876 #define DEV_DMA_ISOC_PID_SHIFT          23
 877 #define DEV_DMA_ISOC_PID_DATA0          0
 878 #define DEV_DMA_ISOC_PID_DATA2          1
 879 #define DEV_DMA_ISOC_PID_DATA1          2
 880 #define DEV_DMA_ISOC_PID_MDATA          3
 881 #define DEV_DMA_ISOC_FRNUM_MASK         (0x7ff << 12)
 882 #define DEV_DMA_ISOC_FRNUM_SHIFT        12
 883 #define DEV_DMA_ISOC_TX_NBYTES_MASK     (0xfff << 0)
 884 #define DEV_DMA_ISOC_TX_NBYTES_LIMIT    0xfff
 885 #define DEV_DMA_ISOC_RX_NBYTES_MASK     (0x7ff << 0)
 886 #define DEV_DMA_ISOC_RX_NBYTES_LIMIT    0x7ff
 887 #define DEV_DMA_ISOC_NBYTES_SHIFT       0
 888 #define DEV_DMA_NBYTES_MASK             (0xffff << 0)
 889 #define DEV_DMA_NBYTES_SHIFT            0
 890 #define DEV_DMA_NBYTES_LIMIT            0xffff
 891 
 892 #define MAX_DMA_DESC_NUM_GENERIC        64
 893 #define MAX_DMA_DESC_NUM_HS_ISOC        256
 894 
 895 #endif /* __DWC2_HW_H__ */

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