This source file includes following definitions.
- xhci_rcar_start_gen2
- xhci_rcar_is_gen2
- xhci_rcar_start
- xhci_rcar_download_firmware
- xhci_rcar_wait_for_pll_active
- xhci_rcar_init_quirk
- xhci_rcar_resume_quirk
1
2
3
4
5
6
7
8 #include <linux/firmware.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/of.h>
12 #include <linux/usb/phy.h>
13 #include <linux/sys_soc.h>
14
15 #include "xhci.h"
16 #include "xhci-plat.h"
17 #include "xhci-rcar.h"
18
19
20
21
22
23
24
25
26
27 MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V1);
28 MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V2);
29 MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3);
30
31
32 #define RCAR_USB3_AXH_STA 0x104
33 #define RCAR_USB3_INT_ENA 0x224
34 #define RCAR_USB3_DL_CTRL 0x250
35 #define RCAR_USB3_FW_DATA0 0x258
36
37 #define RCAR_USB3_LCLK 0xa44
38 #define RCAR_USB3_CONF1 0xa48
39 #define RCAR_USB3_CONF2 0xa5c
40 #define RCAR_USB3_CONF3 0xaa8
41 #define RCAR_USB3_RX_POL 0xab0
42 #define RCAR_USB3_TX_POL 0xab8
43
44
45
46 #define RCAR_USB3_AXH_STA_B3_PLL_ACTIVE 0x00010000
47 #define RCAR_USB3_AXH_STA_B2_PLL_ACTIVE 0x00000001
48 #define RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK (RCAR_USB3_AXH_STA_B3_PLL_ACTIVE | \
49 RCAR_USB3_AXH_STA_B2_PLL_ACTIVE)
50
51
52 #define RCAR_USB3_INT_XHC_ENA 0x00000001
53 #define RCAR_USB3_INT_PME_ENA 0x00000002
54 #define RCAR_USB3_INT_HSE_ENA 0x00000004
55 #define RCAR_USB3_INT_ENA_VAL (RCAR_USB3_INT_XHC_ENA | \
56 RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA)
57
58
59 #define RCAR_USB3_DL_CTRL_ENABLE 0x00000001
60 #define RCAR_USB3_DL_CTRL_FW_SUCCESS 0x00000010
61 #define RCAR_USB3_DL_CTRL_FW_SET_DATA0 0x00000100
62
63
64 #define RCAR_USB3_LCLK_ENA_VAL 0x01030001
65
66
67 #define RCAR_USB3_CONF1_VAL 0x00030204
68 #define RCAR_USB3_CONF2_VAL 0x00030300
69 #define RCAR_USB3_CONF3_VAL 0x13802007
70
71
72 #define RCAR_USB3_RX_POL_VAL BIT(21)
73 #define RCAR_USB3_TX_POL_VAL BIT(4)
74
75
76 #define RCAR_XHCI_FIRMWARE_V2 BIT(0)
77 #define RCAR_XHCI_FIRMWARE_V3 BIT(1)
78
79 static const struct soc_device_attribute rcar_quirks_match[] = {
80 {
81 .soc_id = "r8a7795", .revision = "ES1.*",
82 .data = (void *)RCAR_XHCI_FIRMWARE_V2,
83 },
84 { },
85 };
86
87 static void xhci_rcar_start_gen2(struct usb_hcd *hcd)
88 {
89
90 writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK);
91
92 writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1);
93 writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2);
94 writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3);
95
96 writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL);
97 writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL);
98 }
99
100 static int xhci_rcar_is_gen2(struct device *dev)
101 {
102 struct device_node *node = dev->of_node;
103
104 return of_device_is_compatible(node, "renesas,xhci-r8a7790") ||
105 of_device_is_compatible(node, "renesas,xhci-r8a7791") ||
106 of_device_is_compatible(node, "renesas,xhci-r8a7793") ||
107 of_device_is_compatible(node, "renesas,rcar-gen2-xhci");
108 }
109
110 void xhci_rcar_start(struct usb_hcd *hcd)
111 {
112 u32 temp;
113
114 if (hcd->regs != NULL) {
115
116 temp = readl(hcd->regs + RCAR_USB3_INT_ENA);
117 temp |= RCAR_USB3_INT_ENA_VAL;
118 writel(temp, hcd->regs + RCAR_USB3_INT_ENA);
119 if (xhci_rcar_is_gen2(hcd->self.controller))
120 xhci_rcar_start_gen2(hcd);
121 }
122 }
123
124 static int xhci_rcar_download_firmware(struct usb_hcd *hcd)
125 {
126 struct device *dev = hcd->self.controller;
127 void __iomem *regs = hcd->regs;
128 struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
129 const struct firmware *fw;
130 int retval, index, j, time;
131 int timeout = 10000;
132 u32 data, val, temp;
133 u32 quirks = 0;
134 const struct soc_device_attribute *attr;
135 const char *firmware_name;
136
137 attr = soc_device_match(rcar_quirks_match);
138 if (attr)
139 quirks = (uintptr_t)attr->data;
140
141 if (quirks & RCAR_XHCI_FIRMWARE_V2)
142 firmware_name = XHCI_RCAR_FIRMWARE_NAME_V2;
143 else if (quirks & RCAR_XHCI_FIRMWARE_V3)
144 firmware_name = XHCI_RCAR_FIRMWARE_NAME_V3;
145 else
146 firmware_name = priv->firmware_name;
147
148
149 retval = request_firmware(&fw, firmware_name, dev);
150 if (retval)
151 return retval;
152
153
154 temp = readl(regs + RCAR_USB3_DL_CTRL);
155 temp |= RCAR_USB3_DL_CTRL_ENABLE;
156 writel(temp, regs + RCAR_USB3_DL_CTRL);
157
158 for (index = 0; index < fw->size; index += 4) {
159
160 for (data = 0, j = 3; j >= 0; j--) {
161 if ((j + index) < fw->size)
162 data |= fw->data[index + j] << (8 * j);
163 }
164 writel(data, regs + RCAR_USB3_FW_DATA0);
165 temp = readl(regs + RCAR_USB3_DL_CTRL);
166 temp |= RCAR_USB3_DL_CTRL_FW_SET_DATA0;
167 writel(temp, regs + RCAR_USB3_DL_CTRL);
168
169 for (time = 0; time < timeout; time++) {
170 val = readl(regs + RCAR_USB3_DL_CTRL);
171 if ((val & RCAR_USB3_DL_CTRL_FW_SET_DATA0) == 0)
172 break;
173 udelay(1);
174 }
175 if (time == timeout) {
176 retval = -ETIMEDOUT;
177 break;
178 }
179 }
180
181 temp = readl(regs + RCAR_USB3_DL_CTRL);
182 temp &= ~RCAR_USB3_DL_CTRL_ENABLE;
183 writel(temp, regs + RCAR_USB3_DL_CTRL);
184
185 for (time = 0; time < timeout; time++) {
186 val = readl(regs + RCAR_USB3_DL_CTRL);
187 if (val & RCAR_USB3_DL_CTRL_FW_SUCCESS) {
188 retval = 0;
189 break;
190 }
191 udelay(1);
192 }
193 if (time == timeout)
194 retval = -ETIMEDOUT;
195
196 release_firmware(fw);
197
198 return retval;
199 }
200
201 static bool xhci_rcar_wait_for_pll_active(struct usb_hcd *hcd)
202 {
203 int timeout = 1000;
204 u32 val, mask = RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK;
205
206 while (timeout > 0) {
207 val = readl(hcd->regs + RCAR_USB3_AXH_STA);
208 if ((val & mask) == mask)
209 return true;
210 udelay(1);
211 timeout--;
212 }
213
214 return false;
215 }
216
217
218 int xhci_rcar_init_quirk(struct usb_hcd *hcd)
219 {
220
221 if (!hcd->regs)
222 return 0;
223
224 if (!xhci_rcar_wait_for_pll_active(hcd))
225 return -ETIMEDOUT;
226
227 return xhci_rcar_download_firmware(hcd);
228 }
229
230 int xhci_rcar_resume_quirk(struct usb_hcd *hcd)
231 {
232 int ret;
233
234 ret = xhci_rcar_download_firmware(hcd);
235 if (!ret)
236 xhci_rcar_start(hcd);
237
238 return ret;
239 }