1 // SPDX-License-Identifier: GPL-1.0+
2 /*
3 * OHCI HCD (Host Controller Driver) for USB.
4 *
5 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
6 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 *
8 * This file is licenced under the GPL.
9 */
10
11 #include <linux/irq.h>
12 #include <linux/slab.h>
13
14 static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
15 {
16 int last = urb_priv->length - 1;
17
18 if (last >= 0) {
19 int i;
20 struct td *td;
21
22 for (i = 0; i <= last; i++) {
23 td = urb_priv->td [i];
24 if (td)
25 td_free (hc, td);
26 }
27 }
28
29 list_del (&urb_priv->pending);
30 kfree (urb_priv);
31 }
32
33 /*-------------------------------------------------------------------------*/
34
35 /*
36 * URB goes back to driver, and isn't reissued.
37 * It's completely gone from HC data structures.
38 * PRECONDITION: ohci lock held, irqs blocked.
39 */
40 static void
41 finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
42 __releases(ohci->lock)
43 __acquires(ohci->lock)
44 {
45 struct device *dev = ohci_to_hcd(ohci)->self.controller;
46 struct usb_host_endpoint *ep = urb->ep;
47 struct urb_priv *urb_priv;
48
49 // ASSERT (urb->hcpriv != 0);
50
51 restart:
52 urb_free_priv (ohci, urb->hcpriv);
53 urb->hcpriv = NULL;
54 if (likely(status == -EINPROGRESS))
55 status = 0;
56
57 switch (usb_pipetype (urb->pipe)) {
58 case PIPE_ISOCHRONOUS:
59 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
60 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
61 if (quirk_amdiso(ohci))
62 usb_amd_quirk_pll_enable();
63 if (quirk_amdprefetch(ohci))
64 sb800_prefetch(dev, 0);
65 }
66 break;
67 case PIPE_INTERRUPT:
68 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
69 break;
70 }
71
72 /* urb->complete() can reenter this HCD */
73 usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
74 spin_unlock (&ohci->lock);
75 usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status);
76 spin_lock (&ohci->lock);
77
78 /* stop periodic dma if it's not needed */
79 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
80 && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
81 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
82 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
83 }
84
85 /*
86 * An isochronous URB that is sumitted too late won't have any TDs
87 * (marked by the fact that the td_cnt value is larger than the
88 * actual number of TDs). If the next URB on this endpoint is like
89 * that, give it back now.
90 */
91 if (!list_empty(&ep->urb_list)) {
92 urb = list_first_entry(&ep->urb_list, struct urb, urb_list);
93 urb_priv = urb->hcpriv;
94 if (urb_priv->td_cnt > urb_priv->length) {
95 status = 0;
96 goto restart;
97 }
98 }
99 }
100
101
102 /*-------------------------------------------------------------------------*
103 * ED handling functions
104 *-------------------------------------------------------------------------*/
105
106 /* search for the right schedule branch to use for a periodic ed.
107 * does some load balancing; returns the branch, or negative errno.
108 */
109 static int balance (struct ohci_hcd *ohci, int interval, int load)
110 {
111 int i, branch = -ENOSPC;
112
113 /* iso periods can be huge; iso tds specify frame numbers */
114 if (interval > NUM_INTS)
115 interval = NUM_INTS;
116
117 /* search for the least loaded schedule branch of that period
118 * that has enough bandwidth left unreserved.
119 */
120 for (i = 0; i < interval ; i++) {
121 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
122 int j;
123
124 /* usb 1.1 says 90% of one frame */
125 for (j = i; j < NUM_INTS; j += interval) {
126 if ((ohci->load [j] + load) > 900)
127 break;
128 }
129 if (j < NUM_INTS)
130 continue;
131 branch = i;
132 }
133 }
134 return branch;
135 }
136
137 /*-------------------------------------------------------------------------*/
138
139 /* both iso and interrupt requests have periods; this routine puts them
140 * into the schedule tree in the apppropriate place. most iso devices use
141 * 1msec periods, but that's not required.
142 */
143 static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
144 {
145 unsigned i;
146
147 ohci_dbg(ohci, "link %sed %p branch %d [%dus.], interval %d\n",
148 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
149 ed, ed->branch, ed->load, ed->interval);
150
151 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
152 struct ed **prev = &ohci->periodic [i];
153 __hc32 *prev_p = &ohci->hcca->int_table [i];
154 struct ed *here = *prev;
155
156 /* sorting each branch by period (slow before fast)
157 * lets us share the faster parts of the tree.
158 * (plus maybe: put interrupt eds before iso)
159 */
160 while (here && ed != here) {
161 if (ed->interval > here->interval)
162 break;
163 prev = &here->ed_next;
164 prev_p = &here->hwNextED;
165 here = *prev;
166 }
167 if (ed != here) {
168 ed->ed_next = here;
169 if (here)
170 ed->hwNextED = *prev_p;
171 wmb ();
172 *prev = ed;
173 *prev_p = cpu_to_hc32(ohci, ed->dma);
174 wmb();
175 }
176 ohci->load [i] += ed->load;
177 }
178 ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
179 }
180
181 /* link an ed into one of the HC chains */
182
183 static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
184 {
185 int branch;
186
187 ed->ed_prev = NULL;
188 ed->ed_next = NULL;
189 ed->hwNextED = 0;
190 wmb ();
191
192 /* we care about rm_list when setting CLE/BLE in case the HC was at
193 * work on some TD when CLE/BLE was turned off, and isn't quiesced
194 * yet. finish_unlinks() restarts as needed, some upcoming INTR_SF.
195 *
196 * control and bulk EDs are doubly linked (ed_next, ed_prev), but
197 * periodic ones are singly linked (ed_next). that's because the
198 * periodic schedule encodes a tree like figure 3-5 in the ohci
199 * spec: each qh can have several "previous" nodes, and the tree
200 * doesn't have unused/idle descriptors.
201 */
202 switch (ed->type) {
203 case PIPE_CONTROL:
204 if (ohci->ed_controltail == NULL) {
205 WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
206 ohci_writel (ohci, ed->dma,
207 &ohci->regs->ed_controlhead);
208 } else {
209 ohci->ed_controltail->ed_next = ed;
210 ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
211 ed->dma);
212 }
213 ed->ed_prev = ohci->ed_controltail;
214 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
215 wmb();
216 ohci->hc_control |= OHCI_CTRL_CLE;
217 ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
218 ohci_writel (ohci, ohci->hc_control,
219 &ohci->regs->control);
220 }
221 ohci->ed_controltail = ed;
222 break;
223
224 case PIPE_BULK:
225 if (ohci->ed_bulktail == NULL) {
226 WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
227 ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
228 } else {
229 ohci->ed_bulktail->ed_next = ed;
230 ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
231 ed->dma);
232 }
233 ed->ed_prev = ohci->ed_bulktail;
234 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
235 wmb();
236 ohci->hc_control |= OHCI_CTRL_BLE;
237 ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
238 ohci_writel (ohci, ohci->hc_control,
239 &ohci->regs->control);
240 }
241 ohci->ed_bulktail = ed;
242 break;
243
244 // case PIPE_INTERRUPT:
245 // case PIPE_ISOCHRONOUS:
246 default:
247 branch = balance (ohci, ed->interval, ed->load);
248 if (branch < 0) {
249 ohci_dbg (ohci,
250 "ERR %d, interval %d msecs, load %d\n",
251 branch, ed->interval, ed->load);
252 // FIXME if there are TDs queued, fail them!
253 return branch;
254 }
255 ed->branch = branch;
256 periodic_link (ohci, ed);
257 }
258
259 /* the HC may not see the schedule updates yet, but if it does
260 * then they'll be properly ordered.
261 */
262
263 ed->state = ED_OPER;
264 return 0;
265 }
266
267 /*-------------------------------------------------------------------------*/
268
269 /* scan the periodic table to find and unlink this ED */
270 static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
271 {
272 int i;
273
274 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
275 struct ed *temp;
276 struct ed **prev = &ohci->periodic [i];
277 __hc32 *prev_p = &ohci->hcca->int_table [i];
278
279 while (*prev && (temp = *prev) != ed) {
280 prev_p = &temp->hwNextED;
281 prev = &temp->ed_next;
282 }
283 if (*prev) {
284 *prev_p = ed->hwNextED;
285 *prev = ed->ed_next;
286 }
287 ohci->load [i] -= ed->load;
288 }
289 ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
290
291 ohci_dbg(ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
292 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
293 ed, ed->branch, ed->load, ed->interval);
294 }
295
296 /* unlink an ed from one of the HC chains.
297 * just the link to the ed is unlinked.
298 * the link from the ed still points to another operational ed or 0
299 * so the HC can eventually finish the processing of the unlinked ed
300 * (assuming it already started that, which needn't be true).
301 *
302 * ED_UNLINK is a transient state: the HC may still see this ED, but soon
303 * it won't. ED_SKIP means the HC will finish its current transaction,
304 * but won't start anything new. The TD queue may still grow; device
305 * drivers don't know about this HCD-internal state.
306 *
307 * When the HC can't see the ED, something changes ED_UNLINK to one of:
308 *
309 * - ED_OPER: when there's any request queued, the ED gets rescheduled
310 * immediately. HC should be working on them.
311 *
312 * - ED_IDLE: when there's no TD queue or the HC isn't running.
313 *
314 * When finish_unlinks() runs later, after SOF interrupt, it will often
315 * complete one or more URB unlinks before making that state change.
316 */
317 static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
318 {
319 ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
320 wmb ();
321 ed->state = ED_UNLINK;
322
323 /* To deschedule something from the control or bulk list, just
324 * clear CLE/BLE and wait. There's no safe way to scrub out list
325 * head/current registers until later, and "later" isn't very
326 * tightly specified. Figure 6-5 and Section 6.4.2.2 show how
327 * the HC is reading the ED queues (while we modify them).
328 *
329 * For now, ed_schedule() is "later". It might be good paranoia
330 * to scrub those registers in finish_unlinks(), in case of bugs
331 * that make the HC try to use them.
332 */
333 switch (ed->type) {
334 case PIPE_CONTROL:
335 /* remove ED from the HC's list: */
336 if (ed->ed_prev == NULL) {
337 if (!ed->hwNextED) {
338 ohci->hc_control &= ~OHCI_CTRL_CLE;
339 ohci_writel (ohci, ohci->hc_control,
340 &ohci->regs->control);
341 // a ohci_readl() later syncs CLE with the HC
342 } else
343 ohci_writel (ohci,
344 hc32_to_cpup (ohci, &ed->hwNextED),
345 &ohci->regs->ed_controlhead);
346 } else {
347 ed->ed_prev->ed_next = ed->ed_next;
348 ed->ed_prev->hwNextED = ed->hwNextED;
349 }
350 /* remove ED from the HCD's list: */
351 if (ohci->ed_controltail == ed) {
352 ohci->ed_controltail = ed->ed_prev;
353 if (ohci->ed_controltail)
354 ohci->ed_controltail->ed_next = NULL;
355 } else if (ed->ed_next) {
356 ed->ed_next->ed_prev = ed->ed_prev;
357 }
358 break;
359
360 case PIPE_BULK:
361 /* remove ED from the HC's list: */
362 if (ed->ed_prev == NULL) {
363 if (!ed->hwNextED) {
364 ohci->hc_control &= ~OHCI_CTRL_BLE;
365 ohci_writel (ohci, ohci->hc_control,
366 &ohci->regs->control);
367 // a ohci_readl() later syncs BLE with the HC
368 } else
369 ohci_writel (ohci,
370 hc32_to_cpup (ohci, &ed->hwNextED),
371 &ohci->regs->ed_bulkhead);
372 } else {
373 ed->ed_prev->ed_next = ed->ed_next;
374 ed->ed_prev->hwNextED = ed->hwNextED;
375 }
376 /* remove ED from the HCD's list: */
377 if (ohci->ed_bulktail == ed) {
378 ohci->ed_bulktail = ed->ed_prev;
379 if (ohci->ed_bulktail)
380 ohci->ed_bulktail->ed_next = NULL;
381 } else if (ed->ed_next) {
382 ed->ed_next->ed_prev = ed->ed_prev;
383 }
384 break;
385
386 // case PIPE_INTERRUPT:
387 // case PIPE_ISOCHRONOUS:
388 default:
389 periodic_unlink (ohci, ed);
390 break;
391 }
392 }
393
394
395 /*-------------------------------------------------------------------------*/
396
397 /* get and maybe (re)init an endpoint. init _should_ be done only as part
398 * of enumeration, usb_set_configuration() or usb_set_interface().
399 */
400 static struct ed *ed_get (
401 struct ohci_hcd *ohci,
402 struct usb_host_endpoint *ep,
403 struct usb_device *udev,
404 unsigned int pipe,
405 int interval
406 ) {
407 struct ed *ed;
408 unsigned long flags;
409
410 spin_lock_irqsave (&ohci->lock, flags);
411
412 ed = ep->hcpriv;
413 if (!ed) {
414 struct td *td;
415 int is_out;
416 u32 info;
417
418 ed = ed_alloc (ohci, GFP_ATOMIC);
419 if (!ed) {
420 /* out of memory */
421 goto done;
422 }
423
424 /* dummy td; end of td list for ed */
425 td = td_alloc (ohci, GFP_ATOMIC);
426 if (!td) {
427 /* out of memory */
428 ed_free (ohci, ed);
429 ed = NULL;
430 goto done;
431 }
432 ed->dummy = td;
433 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
434 ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */
435 ed->state = ED_IDLE;
436
437 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
438
439 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
440 * succeeds ... otherwise we wouldn't need "pipe".
441 */
442 info = usb_pipedevice (pipe);
443 ed->type = usb_pipetype(pipe);
444
445 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
446 info |= usb_endpoint_maxp(&ep->desc) << 16;
447 if (udev->speed == USB_SPEED_LOW)
448 info |= ED_LOWSPEED;
449 /* only control transfers store pids in tds */
450 if (ed->type != PIPE_CONTROL) {
451 info |= is_out ? ED_OUT : ED_IN;
452 if (ed->type != PIPE_BULK) {
453 /* periodic transfers... */
454 if (ed->type == PIPE_ISOCHRONOUS)
455 info |= ED_ISO;
456 else if (interval > 32) /* iso can be bigger */
457 interval = 32;
458 ed->interval = interval;
459 ed->load = usb_calc_bus_time (
460 udev->speed, !is_out,
461 ed->type == PIPE_ISOCHRONOUS,
462 usb_endpoint_maxp(&ep->desc))
463 / 1000;
464 }
465 }
466 ed->hwINFO = cpu_to_hc32(ohci, info);
467
468 ep->hcpriv = ed;
469 }
470
471 done:
472 spin_unlock_irqrestore (&ohci->lock, flags);
473 return ed;
474 }
475
476 /*-------------------------------------------------------------------------*/
477
478 /* request unlinking of an endpoint from an operational HC.
479 * put the ep on the rm_list
480 * real work is done at the next start frame (SF) hardware interrupt
481 * caller guarantees HCD is running, so hardware access is safe,
482 * and that ed->state is ED_OPER
483 */
484 static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
485 {
486 ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
487 ed_deschedule (ohci, ed);
488
489 /* rm_list is just singly linked, for simplicity */
490 ed->ed_next = ohci->ed_rm_list;
491 ed->ed_prev = NULL;
492 ohci->ed_rm_list = ed;
493
494 /* enable SOF interrupt */
495 ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
496 ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
497 // flush those writes, and get latest HCCA contents
498 (void) ohci_readl (ohci, &ohci->regs->control);
499
500 /* SF interrupt might get delayed; record the frame counter value that
501 * indicates when the HC isn't looking at it, so concurrent unlinks
502 * behave. frame_no wraps every 2^16 msec, and changes right before
503 * SF is triggered.
504 */
505 ed->tick = ohci_frame_no(ohci) + 1;
506
507 }
508
509 /*-------------------------------------------------------------------------*
510 * TD handling functions
511 *-------------------------------------------------------------------------*/
512
513 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
514
515 static void
516 td_fill (struct ohci_hcd *ohci, u32 info,
517 dma_addr_t data, int len,
518 struct urb *urb, int index)
519 {
520 struct td *td, *td_pt;
521 struct urb_priv *urb_priv = urb->hcpriv;
522 int is_iso = info & TD_ISO;
523 int hash;
524
525 // ASSERT (index < urb_priv->length);
526
527 /* aim for only one interrupt per urb. mostly applies to control
528 * and iso; other urbs rarely need more than one TD per urb.
529 * this way, only final tds (or ones with an error) cause IRQs.
530 * at least immediately; use DI=6 in case any control request is
531 * tempted to die part way through. (and to force the hc to flush
532 * its donelist soonish, even on unlink paths.)
533 *
534 * NOTE: could delay interrupts even for the last TD, and get fewer
535 * interrupts ... increasing per-urb latency by sharing interrupts.
536 * Drivers that queue bulk urbs may request that behavior.
537 */
538 if (index != (urb_priv->length - 1)
539 || (urb->transfer_flags & URB_NO_INTERRUPT))
540 info |= TD_DI_SET (6);
541
542 /* use this td as the next dummy */
543 td_pt = urb_priv->td [index];
544
545 /* fill the old dummy TD */
546 td = urb_priv->td [index] = urb_priv->ed->dummy;
547 urb_priv->ed->dummy = td_pt;
548
549 td->ed = urb_priv->ed;
550 td->next_dl_td = NULL;
551 td->index = index;
552 td->urb = urb;
553 td->data_dma = data;
554 if (!len)
555 data = 0;
556
557 td->hwINFO = cpu_to_hc32 (ohci, info);
558 if (is_iso) {
559 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
560 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
561 (data & 0x0FFF) | 0xE000);
562 } else {
563 td->hwCBP = cpu_to_hc32 (ohci, data);
564 }
565 if (data)
566 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
567 else
568 td->hwBE = 0;
569 td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
570
571 /* append to queue */
572 list_add_tail (&td->td_list, &td->ed->td_list);
573
574 /* hash it for later reverse mapping */
575 hash = TD_HASH_FUNC (td->td_dma);
576 td->td_hash = ohci->td_hash [hash];
577 ohci->td_hash [hash] = td;
578
579 /* HC might read the TD (or cachelines) right away ... */
580 wmb ();
581 td->ed->hwTailP = td->hwNextTD;
582 }
583
584 /*-------------------------------------------------------------------------*/
585
586 /* Prepare all TDs of a transfer, and queue them onto the ED.
587 * Caller guarantees HC is active.
588 * Usually the ED is already on the schedule, so TDs might be
589 * processed as soon as they're queued.
590 */
591 static void td_submit_urb (
592 struct ohci_hcd *ohci,
593 struct urb *urb
594 ) {
595 struct urb_priv *urb_priv = urb->hcpriv;
596 struct device *dev = ohci_to_hcd(ohci)->self.controller;
597 dma_addr_t data;
598 int data_len = urb->transfer_buffer_length;
599 int cnt = 0;
600 u32 info = 0;
601 int is_out = usb_pipeout (urb->pipe);
602 int periodic = 0;
603 int i, this_sg_len, n;
604 struct scatterlist *sg;
605
606 /* OHCI handles the bulk/interrupt data toggles itself. We just
607 * use the device toggle bits for resetting, and rely on the fact
608 * that resetting toggle is meaningless if the endpoint is active.
609 */
610 if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
611 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
612 is_out, 1);
613 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
614 }
615
616 list_add (&urb_priv->pending, &ohci->pending);
617
618 i = urb->num_mapped_sgs;
619 if (data_len > 0 && i > 0) {
620 sg = urb->sg;
621 data = sg_dma_address(sg);
622
623 /*
624 * urb->transfer_buffer_length may be smaller than the
625 * size of the scatterlist (or vice versa)
626 */
627 this_sg_len = min_t(int, sg_dma_len(sg), data_len);
628 } else {
629 sg = NULL;
630 if (data_len)
631 data = urb->transfer_dma;
632 else
633 data = 0;
634 this_sg_len = data_len;
635 }
636
637 /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
638 * using TD_CC_GET, as well as by seeing them on the done list.
639 * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
640 */
641 switch (urb_priv->ed->type) {
642
643 /* Bulk and interrupt are identical except for where in the schedule
644 * their EDs live.
645 */
646 case PIPE_INTERRUPT:
647 /* ... and periodic urbs have extra accounting */
648 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
649 && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
650 /* FALLTHROUGH */
651 case PIPE_BULK:
652 info = is_out
653 ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
654 : TD_T_TOGGLE | TD_CC | TD_DP_IN;
655 /* TDs _could_ transfer up to 8K each */
656 for (;;) {
657 n = min(this_sg_len, 4096);
658
659 /* maybe avoid ED halt on final TD short read */
660 if (n >= data_len || (i == 1 && n >= this_sg_len)) {
661 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
662 info |= TD_R;
663 }
664 td_fill(ohci, info, data, n, urb, cnt);
665 this_sg_len -= n;
666 data_len -= n;
667 data += n;
668 cnt++;
669
670 if (this_sg_len <= 0) {
671 if (--i <= 0 || data_len <= 0)
672 break;
673 sg = sg_next(sg);
674 data = sg_dma_address(sg);
675 this_sg_len = min_t(int, sg_dma_len(sg),
676 data_len);
677 }
678 }
679 if ((urb->transfer_flags & URB_ZERO_PACKET)
680 && cnt < urb_priv->length) {
681 td_fill (ohci, info, 0, 0, urb, cnt);
682 cnt++;
683 }
684 /* maybe kickstart bulk list */
685 if (urb_priv->ed->type == PIPE_BULK) {
686 wmb ();
687 ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
688 }
689 break;
690
691 /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
692 * any DATA phase works normally, and the STATUS ack is special.
693 */
694 case PIPE_CONTROL:
695 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
696 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
697 if (data_len > 0) {
698 info = TD_CC | TD_R | TD_T_DATA1;
699 info |= is_out ? TD_DP_OUT : TD_DP_IN;
700 /* NOTE: mishandles transfers >8K, some >4K */
701 td_fill (ohci, info, data, data_len, urb, cnt++);
702 }
703 info = (is_out || data_len == 0)
704 ? TD_CC | TD_DP_IN | TD_T_DATA1
705 : TD_CC | TD_DP_OUT | TD_T_DATA1;
706 td_fill (ohci, info, data, 0, urb, cnt++);
707 /* maybe kickstart control list */
708 wmb ();
709 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
710 break;
711
712 /* ISO has no retransmit, so no toggle; and it uses special TDs.
713 * Each TD could handle multiple consecutive frames (interval 1);
714 * we could often reduce the number of TDs here.
715 */
716 case PIPE_ISOCHRONOUS:
717 for (cnt = urb_priv->td_cnt; cnt < urb->number_of_packets;
718 cnt++) {
719 int frame = urb->start_frame;
720
721 // FIXME scheduling should handle frame counter
722 // roll-around ... exotic case (and OHCI has
723 // a 2^16 iso range, vs other HCs max of 2^10)
724 frame += cnt * urb->interval;
725 frame &= 0xffff;
726 td_fill (ohci, TD_CC | TD_ISO | frame,
727 data + urb->iso_frame_desc [cnt].offset,
728 urb->iso_frame_desc [cnt].length, urb, cnt);
729 }
730 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
731 if (quirk_amdiso(ohci))
732 usb_amd_quirk_pll_disable();
733 if (quirk_amdprefetch(ohci))
734 sb800_prefetch(dev, 1);
735 }
736 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
737 && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
738 break;
739 }
740
741 /* start periodic dma if needed */
742 if (periodic) {
743 wmb ();
744 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
745 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
746 }
747
748 // ASSERT (urb_priv->length == cnt);
749 }
750
751 /*-------------------------------------------------------------------------*
752 * Done List handling functions
753 *-------------------------------------------------------------------------*/
754
755 /* calculate transfer length/status and update the urb */
756 static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td)
757 {
758 u32 tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
759 int cc = 0;
760 int status = -EINPROGRESS;
761
762 list_del (&td->td_list);
763
764 /* ISO ... drivers see per-TD length/status */
765 if (tdINFO & TD_ISO) {
766 u16 tdPSW = ohci_hwPSW(ohci, td, 0);
767 int dlen = 0;
768
769 /* NOTE: assumes FC in tdINFO == 0, and that
770 * only the first of 0..MAXPSW psws is used.
771 */
772
773 cc = (tdPSW >> 12) & 0xF;
774 if (tdINFO & TD_CC) /* hc didn't touch? */
775 return status;
776
777 if (usb_pipeout (urb->pipe))
778 dlen = urb->iso_frame_desc [td->index].length;
779 else {
780 /* short reads are always OK for ISO */
781 if (cc == TD_DATAUNDERRUN)
782 cc = TD_CC_NOERROR;
783 dlen = tdPSW & 0x3ff;
784 }
785 urb->actual_length += dlen;
786 urb->iso_frame_desc [td->index].actual_length = dlen;
787 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
788
789 if (cc != TD_CC_NOERROR)
790 ohci_dbg(ohci,
791 "urb %p iso td %p (%d) len %d cc %d\n",
792 urb, td, 1 + td->index, dlen, cc);
793
794 /* BULK, INT, CONTROL ... drivers see aggregate length/status,
795 * except that "setup" bytes aren't counted and "short" transfers
796 * might not be reported as errors.
797 */
798 } else {
799 int type = usb_pipetype (urb->pipe);
800 u32 tdBE = hc32_to_cpup (ohci, &td->hwBE);
801
802 cc = TD_CC_GET (tdINFO);
803
804 /* update packet status if needed (short is normally ok) */
805 if (cc == TD_DATAUNDERRUN
806 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
807 cc = TD_CC_NOERROR;
808 if (cc != TD_CC_NOERROR && cc < 0x0E)
809 status = cc_to_error[cc];
810
811 /* count all non-empty packets except control SETUP packet */
812 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
813 if (td->hwCBP == 0)
814 urb->actual_length += tdBE - td->data_dma + 1;
815 else
816 urb->actual_length +=
817 hc32_to_cpup (ohci, &td->hwCBP)
818 - td->data_dma;
819 }
820
821 if (cc != TD_CC_NOERROR && cc < 0x0E)
822 ohci_dbg(ohci,
823 "urb %p td %p (%d) cc %d, len=%d/%d\n",
824 urb, td, 1 + td->index, cc,
825 urb->actual_length,
826 urb->transfer_buffer_length);
827 }
828 return status;
829 }
830
831 /*-------------------------------------------------------------------------*/
832
833 static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc)
834 {
835 struct urb *urb = td->urb;
836 urb_priv_t *urb_priv = urb->hcpriv;
837 struct ed *ed = td->ed;
838 struct list_head *tmp = td->td_list.next;
839 __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
840
841 /* clear ed halt; this is the td that caused it, but keep it inactive
842 * until its urb->complete() has a chance to clean up.
843 */
844 ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
845 wmb ();
846 ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
847
848 /* Get rid of all later tds from this urb. We don't have
849 * to be careful: no errors and nothing was transferred.
850 * Also patch the ed so it looks as if those tds completed normally.
851 */
852 while (tmp != &ed->td_list) {
853 struct td *next;
854
855 next = list_entry (tmp, struct td, td_list);
856 tmp = next->td_list.next;
857
858 if (next->urb != urb)
859 break;
860
861 /* NOTE: if multi-td control DATA segments get supported,
862 * this urb had one of them, this td wasn't the last td
863 * in that segment (TD_R clear), this ed halted because
864 * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
865 * then we need to leave the control STATUS packet queued
866 * and clear ED_SKIP.
867 */
868
869 list_del(&next->td_list);
870 urb_priv->td_cnt++;
871 ed->hwHeadP = next->hwNextTD | toggle;
872 }
873
874 /* help for troubleshooting: report anything that
875 * looks odd ... that doesn't include protocol stalls
876 * (or maybe some other things)
877 */
878 switch (cc) {
879 case TD_DATAUNDERRUN:
880 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
881 break;
882 /* fallthrough */
883 case TD_CC_STALL:
884 if (usb_pipecontrol (urb->pipe))
885 break;
886 /* fallthrough */
887 default:
888 ohci_dbg (ohci,
889 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
890 urb, urb->dev->devpath,
891 usb_pipeendpoint (urb->pipe),
892 usb_pipein (urb->pipe) ? "in" : "out",
893 hc32_to_cpu (ohci, td->hwINFO),
894 cc, cc_to_error [cc]);
895 }
896 }
897
898 /* Add a TD to the done list */
899 static void add_to_done_list(struct ohci_hcd *ohci, struct td *td)
900 {
901 struct td *td2, *td_prev;
902 struct ed *ed;
903
904 if (td->next_dl_td)
905 return; /* Already on the list */
906
907 /* Add all the TDs going back until we reach one that's on the list */
908 ed = td->ed;
909 td2 = td_prev = td;
910 list_for_each_entry_continue_reverse(td2, &ed->td_list, td_list) {
911 if (td2->next_dl_td)
912 break;
913 td2->next_dl_td = td_prev;
914 td_prev = td2;
915 }
916
917 if (ohci->dl_end)
918 ohci->dl_end->next_dl_td = td_prev;
919 else
920 ohci->dl_start = td_prev;
921
922 /*
923 * Make td->next_dl_td point to td itself, to mark the fact
924 * that td is on the done list.
925 */
926 ohci->dl_end = td->next_dl_td = td;
927
928 /* Did we just add the latest pending TD? */
929 td2 = ed->pending_td;
930 if (td2 && td2->next_dl_td)
931 ed->pending_td = NULL;
932 }
933
934 /* Get the entries on the hardware done queue and put them on our list */
935 static void update_done_list(struct ohci_hcd *ohci)
936 {
937 u32 td_dma;
938 struct td *td = NULL;
939
940 td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
941 ohci->hcca->done_head = 0;
942 wmb();
943
944 /* get TD from hc's singly linked list, and
945 * add to ours. ed->td_list changes later.
946 */
947 while (td_dma) {
948 int cc;
949
950 td = dma_to_td (ohci, td_dma);
951 if (!td) {
952 ohci_err (ohci, "bad entry %8x\n", td_dma);
953 break;
954 }
955
956 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
957 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
958
959 /* Non-iso endpoints can halt on error; un-halt,
960 * and dequeue any other TDs from this urb.
961 * No other TD could have caused the halt.
962 */
963 if (cc != TD_CC_NOERROR
964 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
965 ed_halted(ohci, td, cc);
966
967 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
968 add_to_done_list(ohci, td);
969 }
970 }
971
972 /*-------------------------------------------------------------------------*/
973
974 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
975 static void finish_unlinks(struct ohci_hcd *ohci)
976 {
977 unsigned tick = ohci_frame_no(ohci);
978 struct ed *ed, **last;
979
980 rescan_all:
981 for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
982 struct list_head *entry, *tmp;
983 int completed, modified;
984 __hc32 *prev;
985
986 /* only take off EDs that the HC isn't using, accounting for
987 * frame counter wraps and EDs with partially retired TDs
988 */
989 if (likely(ohci->rh_state == OHCI_RH_RUNNING) &&
990 tick_before(tick, ed->tick)) {
991 skip_ed:
992 last = &ed->ed_next;
993 continue;
994 }
995 if (!list_empty(&ed->td_list)) {
996 struct td *td;
997 u32 head;
998
999 td = list_first_entry(&ed->td_list, struct td, td_list);
1000
1001 /* INTR_WDH may need to clean up first */
1002 head = hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK;
1003 if (td->td_dma != head &&
1004 ohci->rh_state == OHCI_RH_RUNNING)
1005 goto skip_ed;
1006
1007 /* Don't mess up anything already on the done list */
1008 if (td->next_dl_td)
1009 goto skip_ed;
1010 }
1011
1012 /* ED's now officially unlinked, hc doesn't see */
1013 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
1014 ed->hwNextED = 0;
1015 wmb();
1016 ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE);
1017
1018 /* reentrancy: if we drop the schedule lock, someone might
1019 * have modified this list. normally it's just prepending
1020 * entries (which we'd ignore), but paranoia won't hurt.
1021 */
1022 *last = ed->ed_next;
1023 ed->ed_next = NULL;
1024 modified = 0;
1025
1026 /* unlink urbs as requested, but rescan the list after
1027 * we call a completion since it might have unlinked
1028 * another (earlier) urb
1029 *
1030 * When we get here, the HC doesn't see this ed. But it
1031 * must not be rescheduled until all completed URBs have
1032 * been given back to the driver.
1033 */
1034 rescan_this:
1035 completed = 0;
1036 prev = &ed->hwHeadP;
1037 list_for_each_safe (entry, tmp, &ed->td_list) {
1038 struct td *td;
1039 struct urb *urb;
1040 urb_priv_t *urb_priv;
1041 __hc32 savebits;
1042 u32 tdINFO;
1043
1044 td = list_entry (entry, struct td, td_list);
1045 urb = td->urb;
1046 urb_priv = td->urb->hcpriv;
1047
1048 if (!urb->unlinked) {
1049 prev = &td->hwNextTD;
1050 continue;
1051 }
1052
1053 /* patch pointer hc uses */
1054 savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
1055 *prev = td->hwNextTD | savebits;
1056
1057 /* If this was unlinked, the TD may not have been
1058 * retired ... so manually save the data toggle.
1059 * The controller ignores the value we save for
1060 * control and ISO endpoints.
1061 */
1062 tdINFO = hc32_to_cpup(ohci, &td->hwINFO);
1063 if ((tdINFO & TD_T) == TD_T_DATA0)
1064 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C);
1065 else if ((tdINFO & TD_T) == TD_T_DATA1)
1066 ed->hwHeadP |= cpu_to_hc32(ohci, ED_C);
1067
1068 /* HC may have partly processed this TD */
1069 td_done (ohci, urb, td);
1070 urb_priv->td_cnt++;
1071
1072 /* if URB is done, clean up */
1073 if (urb_priv->td_cnt >= urb_priv->length) {
1074 modified = completed = 1;
1075 finish_urb(ohci, urb, 0);
1076 }
1077 }
1078 if (completed && !list_empty (&ed->td_list))
1079 goto rescan_this;
1080
1081 /*
1082 * If no TDs are queued, ED is now idle.
1083 * Otherwise, if the HC is running, reschedule.
1084 * If the HC isn't running, add ED back to the
1085 * start of the list for later processing.
1086 */
1087 if (list_empty(&ed->td_list)) {
1088 ed->state = ED_IDLE;
1089 list_del(&ed->in_use_list);
1090 } else if (ohci->rh_state == OHCI_RH_RUNNING) {
1091 ed_schedule(ohci, ed);
1092 } else {
1093 ed->ed_next = ohci->ed_rm_list;
1094 ohci->ed_rm_list = ed;
1095 /* Don't loop on the same ED */
1096 if (last == &ohci->ed_rm_list)
1097 last = &ed->ed_next;
1098 }
1099
1100 if (modified)
1101 goto rescan_all;
1102 }
1103
1104 /* maybe reenable control and bulk lists */
1105 if (ohci->rh_state == OHCI_RH_RUNNING && !ohci->ed_rm_list) {
1106 u32 command = 0, control = 0;
1107
1108 if (ohci->ed_controltail) {
1109 command |= OHCI_CLF;
1110 if (quirk_zfmicro(ohci))
1111 mdelay(1);
1112 if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1113 control |= OHCI_CTRL_CLE;
1114 ohci_writel (ohci, 0,
1115 &ohci->regs->ed_controlcurrent);
1116 }
1117 }
1118 if (ohci->ed_bulktail) {
1119 command |= OHCI_BLF;
1120 if (quirk_zfmicro(ohci))
1121 mdelay(1);
1122 if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1123 control |= OHCI_CTRL_BLE;
1124 ohci_writel (ohci, 0,
1125 &ohci->regs->ed_bulkcurrent);
1126 }
1127 }
1128
1129 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1130 if (control) {
1131 ohci->hc_control |= control;
1132 if (quirk_zfmicro(ohci))
1133 mdelay(1);
1134 ohci_writel (ohci, ohci->hc_control,
1135 &ohci->regs->control);
1136 }
1137 if (command) {
1138 if (quirk_zfmicro(ohci))
1139 mdelay(1);
1140 ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1141 }
1142 }
1143 }
1144
1145
1146
1147 /*-------------------------------------------------------------------------*/
1148
1149 /* Take back a TD from the host controller */
1150 static void takeback_td(struct ohci_hcd *ohci, struct td *td)
1151 {
1152 struct urb *urb = td->urb;
1153 urb_priv_t *urb_priv = urb->hcpriv;
1154 struct ed *ed = td->ed;
1155 int status;
1156
1157 /* update URB's length and status from TD */
1158 status = td_done(ohci, urb, td);
1159 urb_priv->td_cnt++;
1160
1161 /* If all this urb's TDs are done, call complete() */
1162 if (urb_priv->td_cnt >= urb_priv->length)
1163 finish_urb(ohci, urb, status);
1164
1165 /* clean schedule: unlink EDs that are no longer busy */
1166 if (list_empty(&ed->td_list)) {
1167 if (ed->state == ED_OPER)
1168 start_ed_unlink(ohci, ed);
1169
1170 /* ... reenabling halted EDs only after fault cleanup */
1171 } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
1172 == cpu_to_hc32(ohci, ED_SKIP)) {
1173 td = list_entry(ed->td_list.next, struct td, td_list);
1174 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
1175 ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
1176 /* ... hc may need waking-up */
1177 switch (ed->type) {
1178 case PIPE_CONTROL:
1179 ohci_writel(ohci, OHCI_CLF,
1180 &ohci->regs->cmdstatus);
1181 break;
1182 case PIPE_BULK:
1183 ohci_writel(ohci, OHCI_BLF,
1184 &ohci->regs->cmdstatus);
1185 break;
1186 }
1187 }
1188 }
1189 }
1190
1191 /*
1192 * Process normal completions (error or success) and clean the schedules.
1193 *
1194 * This is the main path for handing urbs back to drivers. The only other
1195 * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
1196 * instead of scanning the (re-reversed) donelist as this does.
1197 */
1198 static void process_done_list(struct ohci_hcd *ohci)
1199 {
1200 struct td *td;
1201
1202 while (ohci->dl_start) {
1203 td = ohci->dl_start;
1204 if (td == ohci->dl_end)
1205 ohci->dl_start = ohci->dl_end = NULL;
1206 else
1207 ohci->dl_start = td->next_dl_td;
1208
1209 takeback_td(ohci, td);
1210 }
1211 }
1212
1213 /*
1214 * TD takeback and URB giveback must be single-threaded.
1215 * This routine takes care of it all.
1216 */
1217 static void ohci_work(struct ohci_hcd *ohci)
1218 {
1219 if (ohci->working) {
1220 ohci->restart_work = 1;
1221 return;
1222 }
1223 ohci->working = 1;
1224
1225 restart:
1226 process_done_list(ohci);
1227 if (ohci->ed_rm_list)
1228 finish_unlinks(ohci);
1229
1230 if (ohci->restart_work) {
1231 ohci->restart_work = 0;
1232 goto restart;
1233 }
1234 ohci->working = 0;
1235 }