This source file includes following definitions.
- hcd_to_uhci
- uhci_to_hcd
- uhci_is_aspeed
- uhci_readl
- uhci_writel
- uhci_readw
- uhci_writew
- uhci_readb
- uhci_writeb
- uhci_aspeed_reg
- uhci_readl
- uhci_writel
- uhci_readw
- uhci_writew
- uhci_readb
- uhci_writeb
- cpu_to_hc32
- hc32_to_cpu
- cpu_to_hc32
- hc32_to_cpu
1
2 #ifndef __LINUX_UHCI_HCD_H
3 #define __LINUX_UHCI_HCD_H
4
5 #include <linux/list.h>
6 #include <linux/usb.h>
7 #include <linux/clk.h>
8
9 #define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
10 #define PIPE_DEVEP_MASK 0x0007ff00
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16
17
18 #define USBCMD 0
19 #define USBCMD_RS 0x0001
20 #define USBCMD_HCRESET 0x0002
21 #define USBCMD_GRESET 0x0004
22 #define USBCMD_EGSM 0x0008
23 #define USBCMD_FGR 0x0010
24 #define USBCMD_SWDBG 0x0020
25 #define USBCMD_CF 0x0040
26 #define USBCMD_MAXP 0x0080
27
28
29 #define USBSTS 2
30 #define USBSTS_USBINT 0x0001
31 #define USBSTS_ERROR 0x0002
32 #define USBSTS_RD 0x0004
33 #define USBSTS_HSE 0x0008
34 #define USBSTS_HCPE 0x0010
35
36 #define USBSTS_HCH 0x0020
37
38
39 #define USBINTR 4
40 #define USBINTR_TIMEOUT 0x0001
41 #define USBINTR_RESUME 0x0002
42 #define USBINTR_IOC 0x0004
43 #define USBINTR_SP 0x0008
44
45 #define USBFRNUM 6
46 #define USBFLBASEADD 8
47 #define USBSOF 12
48 #define USBSOF_DEFAULT 64
49
50
51 #define USBPORTSC1 16
52 #define USBPORTSC2 18
53 #define USBPORTSC3 20
54 #define USBPORTSC4 22
55 #define USBPORTSC_CCS 0x0001
56
57 #define USBPORTSC_CSC 0x0002
58 #define USBPORTSC_PE 0x0004
59 #define USBPORTSC_PEC 0x0008
60 #define USBPORTSC_DPLUS 0x0010
61 #define USBPORTSC_DMINUS 0x0020
62 #define USBPORTSC_RD 0x0040
63 #define USBPORTSC_RES1 0x0080
64 #define USBPORTSC_LSDA 0x0100
65 #define USBPORTSC_PR 0x0200
66
67 #define USBPORTSC_OC 0x0400
68 #define USBPORTSC_OCC 0x0800
69 #define USBPORTSC_SUSP 0x1000
70 #define USBPORTSC_RES2 0x2000
71 #define USBPORTSC_RES3 0x4000
72 #define USBPORTSC_RES4 0x8000
73
74
75 #define USBLEGSUP 0xc0
76 #define USBLEGSUP_DEFAULT 0x2000
77 #define USBLEGSUP_RWC 0x8f00
78 #define USBLEGSUP_RO 0x5040
79
80
81 #define USBRES_INTEL 0xc4
82 #define USBPORT1EN 0x01
83 #define USBPORT2EN 0x02
84
85 #define UHCI_PTR_BITS(uhci) cpu_to_hc32((uhci), 0x000F)
86 #define UHCI_PTR_TERM(uhci) cpu_to_hc32((uhci), 0x0001)
87 #define UHCI_PTR_QH(uhci) cpu_to_hc32((uhci), 0x0002)
88 #define UHCI_PTR_DEPTH(uhci) cpu_to_hc32((uhci), 0x0004)
89 #define UHCI_PTR_BREADTH(uhci) cpu_to_hc32((uhci), 0x0000)
90
91 #define UHCI_NUMFRAMES 1024
92 #define UHCI_MAX_SOF_NUMBER 2047
93 #define CAN_SCHEDULE_FRAMES 1000
94
95 #define MAX_PHASE 32
96
97
98
99 #define FSBR_OFF_DELAY msecs_to_jiffies(10)
100
101
102 #define QH_WAIT_TIMEOUT msecs_to_jiffies(200)
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112
113 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC
114 typedef __u32 __bitwise __hc32;
115 typedef __u16 __bitwise __hc16;
116 #else
117 #define __hc32 __le32
118 #define __hc16 __le16
119 #endif
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144
145 #define QH_STATE_IDLE 1
146 #define QH_STATE_UNLINKING 2
147
148
149 #define QH_STATE_ACTIVE 3
150
151 struct uhci_qh {
152
153 __hc32 link;
154 __hc32 element;
155
156
157 dma_addr_t dma_handle;
158
159 struct list_head node;
160 struct usb_host_endpoint *hep;
161 struct usb_device *udev;
162 struct list_head queue;
163 struct uhci_td *dummy_td;
164 struct uhci_td *post_td;
165
166 struct usb_iso_packet_descriptor *iso_packet_desc;
167
168 unsigned long advance_jiffies;
169 unsigned int unlink_frame;
170 unsigned int period;
171 short phase;
172 short load;
173 unsigned int iso_frame;
174
175 int state;
176 int type;
177 int skel;
178
179 unsigned int initial_toggle:1;
180 unsigned int needs_fixup:1;
181 unsigned int is_stopped:1;
182 unsigned int wait_expired:1;
183 unsigned int bandwidth_reserved:1;
184
185 } __attribute__((aligned(16)));
186
187
188
189
190
191 #define qh_element(qh) READ_ONCE((qh)->element)
192
193 #define LINK_TO_QH(uhci, qh) (UHCI_PTR_QH((uhci)) | \
194 cpu_to_hc32((uhci), (qh)->dma_handle))
195
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202
203
204 #define TD_CTRL_SPD (1 << 29)
205 #define TD_CTRL_C_ERR_MASK (3 << 27)
206 #define TD_CTRL_C_ERR_SHIFT 27
207 #define TD_CTRL_LS (1 << 26)
208 #define TD_CTRL_IOS (1 << 25)
209 #define TD_CTRL_IOC (1 << 24)
210 #define TD_CTRL_ACTIVE (1 << 23)
211 #define TD_CTRL_STALLED (1 << 22)
212 #define TD_CTRL_DBUFERR (1 << 21)
213 #define TD_CTRL_BABBLE (1 << 20)
214 #define TD_CTRL_NAK (1 << 19)
215 #define TD_CTRL_CRCTIMEO (1 << 18)
216 #define TD_CTRL_BITSTUFF (1 << 17)
217 #define TD_CTRL_ACTLEN_MASK 0x7FF
218
219 #define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT)
220 #define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000)
221 #define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \
222 TD_CTRL_ACTLEN_MASK)
223
224
225
226
227 #define td_token(uhci, td) hc32_to_cpu((uhci), (td)->token)
228 #define TD_TOKEN_DEVADDR_SHIFT 8
229 #define TD_TOKEN_TOGGLE_SHIFT 19
230 #define TD_TOKEN_TOGGLE (1 << 19)
231 #define TD_TOKEN_EXPLEN_SHIFT 21
232 #define TD_TOKEN_EXPLEN_MASK 0x7FF
233 #define TD_TOKEN_PID_MASK 0xFF
234
235 #define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
236 TD_TOKEN_EXPLEN_SHIFT)
237
238 #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
239 1) & TD_TOKEN_EXPLEN_MASK)
240 #define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
241 #define uhci_endpoint(token) (((token) >> 15) & 0xf)
242 #define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
243 #define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
244 #define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK)
245 #define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN)
246 #define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN)
247
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257
258 struct uhci_td {
259
260 __hc32 link;
261 __hc32 status;
262 __hc32 token;
263 __hc32 buffer;
264
265
266 dma_addr_t dma_handle;
267
268 struct list_head list;
269
270 int frame;
271 struct list_head fl_list;
272 } __attribute__((aligned(16)));
273
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276
277
278 #define td_status(uhci, td) hc32_to_cpu((uhci), \
279 READ_ONCE((td)->status))
280
281 #define LINK_TO_TD(uhci, td) (cpu_to_hc32((uhci), (td)->dma_handle))
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329 #define UHCI_NUM_SKELQH 11
330 #define SKEL_UNLINK 0
331 #define skel_unlink_qh skelqh[SKEL_UNLINK]
332 #define SKEL_ISO 1
333 #define skel_iso_qh skelqh[SKEL_ISO]
334
335 #define SKEL_INDEX(exponent) (9 - exponent)
336 #define SKEL_ASYNC 9
337 #define skel_async_qh skelqh[SKEL_ASYNC]
338 #define SKEL_TERM 10
339 #define skel_term_qh skelqh[SKEL_TERM]
340
341
342 #define SKEL_LS_CONTROL 20
343 #define SKEL_FS_CONTROL 21
344 #define SKEL_FSBR SKEL_FS_CONTROL
345 #define SKEL_BULK 22
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360
361 enum uhci_rh_state {
362
363
364 UHCI_RH_RESET,
365 UHCI_RH_SUSPENDED,
366
367 UHCI_RH_AUTO_STOPPED,
368 UHCI_RH_RESUMING,
369
370
371
372 UHCI_RH_SUSPENDING,
373
374
375
376 UHCI_RH_RUNNING,
377 UHCI_RH_RUNNING_NODEVS,
378 };
379
380
381
382
383 struct uhci_hcd {
384
385
386 struct dentry *dentry;
387
388
389 unsigned long io_addr;
390
391
392 void __iomem *regs;
393
394 struct dma_pool *qh_pool;
395 struct dma_pool *td_pool;
396
397 struct uhci_td *term_td;
398 struct uhci_qh *skelqh[UHCI_NUM_SKELQH];
399 struct uhci_qh *next_qh;
400
401 spinlock_t lock;
402
403 dma_addr_t frame_dma_handle;
404 __hc32 *frame;
405 void **frame_cpu;
406
407 enum uhci_rh_state rh_state;
408 unsigned long auto_stop_time;
409
410 unsigned int frame_number;
411 unsigned int is_stopped;
412 #define UHCI_IS_STOPPED 9999
413 unsigned int last_iso_frame;
414 unsigned int cur_iso_frame;
415
416 unsigned int scan_in_progress:1;
417 unsigned int need_rescan:1;
418 unsigned int dead:1;
419 unsigned int RD_enable:1;
420
421
422 unsigned int is_initialized:1;
423 unsigned int fsbr_is_on:1;
424 unsigned int fsbr_is_wanted:1;
425 unsigned int fsbr_expiring:1;
426
427 struct timer_list fsbr_timer;
428
429
430 unsigned int oc_low:1;
431 unsigned int wait_for_hp:1;
432 unsigned int big_endian_mmio:1;
433 unsigned int big_endian_desc:1;
434 unsigned int is_aspeed:1;
435
436
437 unsigned long port_c_suspend;
438 unsigned long resuming_ports;
439 unsigned long ports_timeout;
440
441 struct list_head idle_qh_list;
442
443 int rh_numports;
444
445 wait_queue_head_t waitqh;
446 int num_waiting;
447
448 int total_load;
449 short load[MAX_PHASE];
450
451 struct clk *clk;
452
453
454 void (*reset_hc) (struct uhci_hcd *uhci);
455 int (*check_and_reset_hc) (struct uhci_hcd *uhci);
456
457 void (*configure_hc) (struct uhci_hcd *uhci);
458
459 int (*resume_detect_interrupts_are_broken) (struct uhci_hcd *uhci);
460
461 int (*global_suspend_mode_is_broken) (struct uhci_hcd *uhci);
462 };
463
464
465 static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
466 {
467 return (struct uhci_hcd *) (hcd->hcd_priv);
468 }
469 static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
470 {
471 return container_of((void *) uhci, struct usb_hcd, hcd_priv);
472 }
473
474 #define uhci_dev(u) (uhci_to_hcd(u)->self.controller)
475
476
477 #define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1)))
478
479
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481
482
483 struct urb_priv {
484 struct list_head node;
485
486 struct urb *urb;
487
488 struct uhci_qh *qh;
489 struct list_head td_list;
490
491 unsigned fsbr:1;
492 };
493
494
495
496
497 #define PCI_VENDOR_ID_GENESYS 0x17a0
498 #define PCI_DEVICE_ID_GL880S_UHCI 0x8083
499
500
501 static inline bool uhci_is_aspeed(const struct uhci_hcd *uhci)
502 {
503 return IS_ENABLED(CONFIG_USB_UHCI_ASPEED) && uhci->is_aspeed;
504 }
505
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509
510
511
512 #ifndef CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC
513
514 static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
515 {
516 return inl(uhci->io_addr + reg);
517 }
518
519 static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
520 {
521 outl(val, uhci->io_addr + reg);
522 }
523
524 static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
525 {
526 return inw(uhci->io_addr + reg);
527 }
528
529 static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
530 {
531 outw(val, uhci->io_addr + reg);
532 }
533
534 static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
535 {
536 return inb(uhci->io_addr + reg);
537 }
538
539 static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
540 {
541 outb(val, uhci->io_addr + reg);
542 }
543
544 #else
545
546 #ifdef CONFIG_USB_PCI
547
548 #define uhci_has_pci_registers(u) ((u)->io_addr != 0)
549 #else
550
551 #define uhci_has_pci_registers(u) 0
552 #endif
553
554 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
555
556 #define uhci_big_endian_mmio(u) ((u)->big_endian_mmio)
557 #else
558 #define uhci_big_endian_mmio(u) 0
559 #endif
560
561 static inline int uhci_aspeed_reg(unsigned int reg)
562 {
563 switch (reg) {
564 case USBCMD:
565 return 00;
566 case USBSTS:
567 return 0x04;
568 case USBINTR:
569 return 0x08;
570 case USBFRNUM:
571 return 0x80;
572 case USBFLBASEADD:
573 return 0x0c;
574 case USBSOF:
575 return 0x84;
576 case USBPORTSC1:
577 return 0x88;
578 case USBPORTSC2:
579 return 0x8c;
580 case USBPORTSC3:
581 return 0x90;
582 case USBPORTSC4:
583 return 0x94;
584 default:
585 pr_warn("UHCI: Unsupported register 0x%02x on Aspeed\n", reg);
586
587 return 0x10;
588 }
589 }
590
591 static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
592 {
593 if (uhci_has_pci_registers(uhci))
594 return inl(uhci->io_addr + reg);
595 else if (uhci_is_aspeed(uhci))
596 return readl(uhci->regs + uhci_aspeed_reg(reg));
597 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
598 else if (uhci_big_endian_mmio(uhci))
599 return readl_be(uhci->regs + reg);
600 #endif
601 else
602 return readl(uhci->regs + reg);
603 }
604
605 static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
606 {
607 if (uhci_has_pci_registers(uhci))
608 outl(val, uhci->io_addr + reg);
609 else if (uhci_is_aspeed(uhci))
610 writel(val, uhci->regs + uhci_aspeed_reg(reg));
611 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
612 else if (uhci_big_endian_mmio(uhci))
613 writel_be(val, uhci->regs + reg);
614 #endif
615 else
616 writel(val, uhci->regs + reg);
617 }
618
619 static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
620 {
621 if (uhci_has_pci_registers(uhci))
622 return inw(uhci->io_addr + reg);
623 else if (uhci_is_aspeed(uhci))
624 return readl(uhci->regs + uhci_aspeed_reg(reg));
625 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
626 else if (uhci_big_endian_mmio(uhci))
627 return readw_be(uhci->regs + reg);
628 #endif
629 else
630 return readw(uhci->regs + reg);
631 }
632
633 static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
634 {
635 if (uhci_has_pci_registers(uhci))
636 outw(val, uhci->io_addr + reg);
637 else if (uhci_is_aspeed(uhci))
638 writel(val, uhci->regs + uhci_aspeed_reg(reg));
639 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
640 else if (uhci_big_endian_mmio(uhci))
641 writew_be(val, uhci->regs + reg);
642 #endif
643 else
644 writew(val, uhci->regs + reg);
645 }
646
647 static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
648 {
649 if (uhci_has_pci_registers(uhci))
650 return inb(uhci->io_addr + reg);
651 else if (uhci_is_aspeed(uhci))
652 return readl(uhci->regs + uhci_aspeed_reg(reg));
653 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
654 else if (uhci_big_endian_mmio(uhci))
655 return readb_be(uhci->regs + reg);
656 #endif
657 else
658 return readb(uhci->regs + reg);
659 }
660
661 static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
662 {
663 if (uhci_has_pci_registers(uhci))
664 outb(val, uhci->io_addr + reg);
665 else if (uhci_is_aspeed(uhci))
666 writel(val, uhci->regs + uhci_aspeed_reg(reg));
667 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
668 else if (uhci_big_endian_mmio(uhci))
669 writeb_be(val, uhci->regs + reg);
670 #endif
671 else
672 writeb(val, uhci->regs + reg);
673 }
674 #endif
675
676
677
678
679
680
681
682 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC
683 #define uhci_big_endian_desc(u) ((u)->big_endian_desc)
684
685
686 static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x)
687 {
688 return uhci_big_endian_desc(uhci)
689 ? (__force __hc32)cpu_to_be32(x)
690 : (__force __hc32)cpu_to_le32(x);
691 }
692
693
694 static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x)
695 {
696 return uhci_big_endian_desc(uhci)
697 ? be32_to_cpu((__force __be32)x)
698 : le32_to_cpu((__force __le32)x);
699 }
700
701 #else
702
703 static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x)
704 {
705 return cpu_to_le32(x);
706 }
707
708
709 static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x)
710 {
711 return le32_to_cpu(x);
712 }
713 #endif
714
715 #endif