drivers/usb/host/xhci-pci.c

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This source file includes following definitions.
xhci_pci_reinit
xhci_pci_quirks
xhci_pme_acpi_rtd3_enable
xhci_pme_acpi_rtd3_enable
xhci_pci_setup
xhci_pci_probe
xhci_pci_remove
xhci_ssic_port_unused_quirk
xhci_pme_quirk
xhci_pci_suspend
xhci_pci_resume
xhci_pci_shutdown
xhci_pci_init
xhci_pci_exit
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10 
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15 
  16 #include "xhci.h"
  17 #include "xhci-trace.h"
  18 
  19 #define SSIC_PORT_NUM           2
  20 #define SSIC_PORT_CFG2          0x880c
  21 #define SSIC_PORT_CFG2_OFFSET   0x30
  22 #define PROG_DONE               (1 << 30)
  23 #define SSIC_PORT_UNUSED        (1 << 31)
  24 
  25 /* Device for a quirk */
  26 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  30 
  31 #define PCI_VENDOR_ID_ETRON             0x1b6f
  32 #define PCI_DEVICE_ID_EJ168             0x7023
  33 
  34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  42 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  44 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI        0x15b5
  45 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI        0x15b6
  46 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI      0x15db
  47 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI      0x15d4
  48 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI         0x15e9
  49 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI         0x15ec
  50 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI         0x15f0
  51 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI               0x8a13
  52 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  53 
  54 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  55 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  56 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  57 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  58 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  59 
  60 static const char hcd_name[] = "xhci_hcd";
  61 
  62 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  63 
  64 static int xhci_pci_setup(struct usb_hcd *hcd);
  65 
  66 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  67         .reset = xhci_pci_setup,
  68 };
  69 
  70 /* called after powerup, by probe or system-pm "wakeup" */
  71 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  72 {
  73         /*
  74          * TODO: Implement finding debug ports later.
  75          * TODO: see if there are any quirks that need to be added to handle
  76          * new extended capabilities.
  77          */
  78 
  79         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  80         if (!pci_set_mwi(pdev))
  81                 xhci_dbg(xhci, "MWI active\n");
  82 
  83         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  84         return 0;
  85 }
  86 
  87 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  88 {
  89         struct pci_dev          *pdev = to_pci_dev(dev);
  90 
  91         /* Look for vendor-specific quirks */
  92         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  93                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  94                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  95                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  96                                 pdev->revision == 0x0) {
  97                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  98                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  99                                 "QUIRK: Fresco Logic xHC needs configure"
 100                                 " endpoint cmd after reset endpoint");
 101                 }
 102                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 103                                 pdev->revision == 0x4) {
 104                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 105                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 106                                 "QUIRK: Fresco Logic xHC revision %u"
 107                                 "must be suspended extra slowly",
 108                                 pdev->revision);
 109                 }
 110                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 111                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 112                 /* Fresco Logic confirms: all revisions of this chip do not
 113                  * support MSI, even though some of them claim to in their PCI
 114                  * capabilities.
 115                  */
 116                 xhci->quirks |= XHCI_BROKEN_MSI;
 117                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 118                                 "QUIRK: Fresco Logic revision %u "
 119                                 "has broken MSI implementation",
 120                                 pdev->revision);
 121                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 122         }
 123 
 124         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 125                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 126                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 127 
 128         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 129                 xhci->quirks |= XHCI_NEC_HOST;
 130 
 131         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 132                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 133 
 134         /* AMD PLL quirk */
 135         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
 136                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 137 
 138         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 139                 (pdev->device == 0x145c ||
 140                  pdev->device == 0x15e0 ||
 141                  pdev->device == 0x15e1 ||
 142                  pdev->device == 0x43bb))
 143                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 144 
 145         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 146             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 147                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 148 
 149         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 150                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 151 
 152         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 153                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 154                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 155                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 156                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 157                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 158 
 159         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 160                 xhci->quirks |= XHCI_LPM_SUPPORT;
 161                 xhci->quirks |= XHCI_INTEL_HOST;
 162                 xhci->quirks |= XHCI_AVOID_BEI;
 163         }
 164         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 165                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 166                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 167                 xhci->limit_active_eps = 64;
 168                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 169                 /*
 170                  * PPT desktop boards DH77EB and DH77DF will power back on after
 171                  * a few seconds of being shutdown.  The fix for this is to
 172                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 173                  * DMI information to find those particular boards (since each
 174                  * vendor will change the board name), so we have to key off all
 175                  * PPT chipsets.
 176                  */
 177                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 178         }
 179         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 180                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 181                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 182                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 183                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 184         }
 185         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 186                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 187                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 188                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 189                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 190                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 191                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 192                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 193                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 194                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 195         }
 196         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 197             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 198                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 199         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 200             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 201              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 202              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 203                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 204         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 205             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 206              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 207              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 208              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 209              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 210                 xhci->quirks |= XHCI_MISSING_CAS;
 211 
 212         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 213             (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
 214              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
 215              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
 216              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
 217              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
 218              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
 219              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
 220              pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI))
 221                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 222 
 223         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 224                         pdev->device == PCI_DEVICE_ID_EJ168) {
 225                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 226                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 227                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 228         }
 229         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 230             pdev->device == 0x0014) {
 231                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 232                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 233         }
 234         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 235             pdev->device == 0x0015) {
 236                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 237                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 238         }
 239         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 240                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 241 
 242         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 243         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 244                         pdev->device == 0x3432)
 245                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 246 
 247         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 248                         pdev->device == 0x1042)
 249                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 250         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 251                         pdev->device == 0x1142)
 252                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 253 
 254         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 255                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 256                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 257 
 258         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 259                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 260 
 261         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 262              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 263              pdev->device == 0x9026)
 264                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 265 
 266         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 267                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 268                                 "QUIRK: Resetting on resume");
 269 }
 270 
 271 #ifdef CONFIG_ACPI
 272 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 273 {
 274         static const guid_t intel_dsm_guid =
 275                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 276                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 277         union acpi_object *obj;
 278 
 279         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 280                                 NULL);
 281         ACPI_FREE(obj);
 282 }
 283 #else
 284 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 285 #endif /* CONFIG_ACPI */
 286 
 287 /* called during probe() after chip reset completes */
 288 static int xhci_pci_setup(struct usb_hcd *hcd)
 289 {
 290         struct xhci_hcd         *xhci;
 291         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 292         int                     retval;
 293 
 294         xhci = hcd_to_xhci(hcd);
 295         if (!xhci->sbrn)
 296                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 297 
 298         /* imod_interval is the interrupt moderation value in nanoseconds. */
 299         xhci->imod_interval = 40000;
 300 
 301         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 302         if (retval)
 303                 return retval;
 304 
 305         if (!usb_hcd_is_primary_hcd(hcd))
 306                 return 0;
 307 
 308         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 309                 xhci_pme_acpi_rtd3_enable(pdev);
 310 
 311         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 312 
 313         /* Find any debug ports */
 314         return xhci_pci_reinit(xhci, pdev);
 315 }
 316 
 317 /*
 318  * We need to register our own PCI probe function (instead of the USB core's
 319  * function) in order to create a second roothub under xHCI.
 320  */
 321 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 322 {
 323         int retval;
 324         struct xhci_hcd *xhci;
 325         struct hc_driver *driver;
 326         struct usb_hcd *hcd;
 327 
 328         driver = (struct hc_driver *)id->driver_data;
 329 
 330         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 331         pm_runtime_get_noresume(&dev->dev);
 332 
 333         /* Register the USB 2.0 roothub.
 334          * FIXME: USB core must know to register the USB 2.0 roothub first.
 335          * This is sort of silly, because we could just set the HCD driver flags
 336          * to say USB 2.0, but I'm not sure what the implications would be in
 337          * the other parts of the HCD code.
 338          */
 339         retval = usb_hcd_pci_probe(dev, id);
 340 
 341         if (retval)
 342                 goto put_runtime_pm;
 343 
 344         /* USB 2.0 roothub is stored in the PCI device now. */
 345         hcd = dev_get_drvdata(&dev->dev);
 346         xhci = hcd_to_xhci(hcd);
 347         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 348                                 pci_name(dev), hcd);
 349         if (!xhci->shared_hcd) {
 350                 retval = -ENOMEM;
 351                 goto dealloc_usb2_hcd;
 352         }
 353 
 354         retval = xhci_ext_cap_init(xhci);
 355         if (retval)
 356                 goto put_usb3_hcd;
 357 
 358         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 359                         IRQF_SHARED);
 360         if (retval)
 361                 goto put_usb3_hcd;
 362         /* Roothub already marked as USB 3.0 speed */
 363 
 364         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 365                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 366                 xhci->shared_hcd->can_do_streams = 1;
 367 
 368         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 369         pm_runtime_put_noidle(&dev->dev);
 370 
 371         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 372                 pm_runtime_allow(&dev->dev);
 373 
 374         return 0;
 375 
 376 put_usb3_hcd:
 377         usb_put_hcd(xhci->shared_hcd);
 378 dealloc_usb2_hcd:
 379         usb_hcd_pci_remove(dev);
 380 put_runtime_pm:
 381         pm_runtime_put_noidle(&dev->dev);
 382         return retval;
 383 }
 384 
 385 static void xhci_pci_remove(struct pci_dev *dev)
 386 {
 387         struct xhci_hcd *xhci;
 388 
 389         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 390         xhci->xhc_state |= XHCI_STATE_REMOVING;
 391 
 392         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 393                 pm_runtime_forbid(&dev->dev);
 394 
 395         if (xhci->shared_hcd) {
 396                 usb_remove_hcd(xhci->shared_hcd);
 397                 usb_put_hcd(xhci->shared_hcd);
 398                 xhci->shared_hcd = NULL;
 399         }
 400 
 401         /* Workaround for spurious wakeups at shutdown with HSW */
 402         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 403                 pci_set_power_state(dev, PCI_D3hot);
 404 
 405         usb_hcd_pci_remove(dev);
 406 }
 407 
 408 #ifdef CONFIG_PM
 409 /*
 410  * In some Intel xHCI controllers, in order to get D3 working,
 411  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 412  * SSIC PORT need to be marked as "unused" before putting xHCI
 413  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 414  * Without this change, xHCI might not enter D3 state.
 415  */
 416 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 417 {
 418         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 419         u32 val;
 420         void __iomem *reg;
 421         int i;
 422 
 423         for (i = 0; i < SSIC_PORT_NUM; i++) {
 424                 reg = (void __iomem *) xhci->cap_regs +
 425                                 SSIC_PORT_CFG2 +
 426                                 i * SSIC_PORT_CFG2_OFFSET;
 427 
 428                 /* Notify SSIC that SSIC profile programming is not done. */
 429                 val = readl(reg) & ~PROG_DONE;
 430                 writel(val, reg);
 431 
 432                 /* Mark SSIC port as unused(suspend) or used(resume) */
 433                 val = readl(reg);
 434                 if (suspend)
 435                         val |= SSIC_PORT_UNUSED;
 436                 else
 437                         val &= ~SSIC_PORT_UNUSED;
 438                 writel(val, reg);
 439 
 440                 /* Notify SSIC that SSIC profile programming is done */
 441                 val = readl(reg) | PROG_DONE;
 442                 writel(val, reg);
 443                 readl(reg);
 444         }
 445 }
 446 
 447 /*
 448  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 449  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 450  */
 451 static void xhci_pme_quirk(struct usb_hcd *hcd)
 452 {
 453         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 454         void __iomem *reg;
 455         u32 val;
 456 
 457         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 458         val = readl(reg);
 459         writel(val | BIT(28), reg);
 460         readl(reg);
 461 }
 462 
 463 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 464 {
 465         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 466         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 467         int                     ret;
 468 
 469         /*
 470          * Systems with the TI redriver that loses port status change events
 471          * need to have the registers polled during D3, so avoid D3cold.
 472          */
 473         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 474                 pci_d3cold_disable(pdev);
 475 
 476         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 477                 xhci_pme_quirk(hcd);
 478 
 479         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 480                 xhci_ssic_port_unused_quirk(hcd, true);
 481 
 482         ret = xhci_suspend(xhci, do_wakeup);
 483         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 484                 xhci_ssic_port_unused_quirk(hcd, false);
 485 
 486         return ret;
 487 }
 488 
 489 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 490 {
 491         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 492         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 493         int                     retval = 0;
 494 
 495         /* The BIOS on systems with the Intel Panther Point chipset may or may
 496          * not support xHCI natively.  That means that during system resume, it
 497          * may switch the ports back to EHCI so that users can use their
 498          * keyboard to select a kernel from GRUB after resume from hibernate.
 499          *
 500          * The BIOS is supposed to remember whether the OS had xHCI ports
 501          * enabled before resume, and switch the ports back to xHCI when the
 502          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 503          * writers.
 504          *
 505          * Unconditionally switch the ports back to xHCI after a system resume.
 506          * It should not matter whether the EHCI or xHCI controller is
 507          * resumed first. It's enough to do the switchover in xHCI because
 508          * USB core won't notice anything as the hub driver doesn't start
 509          * running again until after all the devices (including both EHCI and
 510          * xHCI host controllers) have been resumed.
 511          */
 512 
 513         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 514                 usb_enable_intel_xhci_ports(pdev);
 515 
 516         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 517                 xhci_ssic_port_unused_quirk(hcd, false);
 518 
 519         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 520                 xhci_pme_quirk(hcd);
 521 
 522         retval = xhci_resume(xhci, hibernated);
 523         return retval;
 524 }
 525 
 526 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 527 {
 528         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 529         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 530 
 531         xhci_shutdown(hcd);
 532 
 533         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 534         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 535                 pci_set_power_state(pdev, PCI_D3hot);
 536 }
 537 #endif /* CONFIG_PM */
 538 
 539 /*-------------------------------------------------------------------------*/
 540 
 541 /* PCI driver selection metadata; PCI hotplugging uses this */
 542 static const struct pci_device_id pci_ids[] = { {
 543         /* handle any USB 3.0 xHCI controller */
 544         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 545         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 546         },
 547         { /* end: all zeroes */ }
 548 };
 549 MODULE_DEVICE_TABLE(pci, pci_ids);
 550 
 551 /* pci driver glue; this is a "new style" PCI driver module */
 552 static struct pci_driver xhci_pci_driver = {
 553         .name =         (char *) hcd_name,
 554         .id_table =     pci_ids,
 555 
 556         .probe =        xhci_pci_probe,
 557         .remove =       xhci_pci_remove,
 558         /* suspend and resume implemented later */
 559 
 560         .shutdown =     usb_hcd_pci_shutdown,
 561 #ifdef CONFIG_PM
 562         .driver = {
 563                 .pm = &usb_hcd_pci_pm_ops
 564         },
 565 #endif
 566 };
 567 
 568 static int __init xhci_pci_init(void)
 569 {
 570         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 571 #ifdef CONFIG_PM
 572         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 573         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 574         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 575 #endif
 576         return pci_register_driver(&xhci_pci_driver);
 577 }
 578 module_init(xhci_pci_init);
 579 
 580 static void __exit xhci_pci_exit(void)
 581 {
 582         pci_unregister_driver(&xhci_pci_driver);
 583 }
 584 module_exit(xhci_pci_exit);
 585 
 586 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 587 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/usb/host/xhci-pci.c

DEFINITIONS
