drivers/usb/host/xhci-hub.c

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This source file includes following definitions.
xhci_create_usb3_bos_desc
xhci_common_hub_descriptor
xhci_usb2_hub_descriptor
xhci_usb3_hub_descriptor
xhci_hub_descriptor
xhci_port_speed
xhci_port_state_to_neutral
xhci_find_slot_id_by_port
xhci_stop_device
xhci_ring_device
xhci_disable_port
xhci_clear_port_change_bit
xhci_get_rhub
xhci_set_port_power
xhci_port_set_test_mode
xhci_enter_test_mode
xhci_exit_test_mode
xhci_set_link_state
xhci_set_remote_wake_mask
xhci_test_and_clear_bit
xhci_hub_report_usb3_link_state
xhci_del_comp_mod_timer
xhci_handle_usb2_port_link_resume
xhci_get_ext_port_status
xhci_get_usb3_port_status
xhci_get_usb2_port_status
xhci_get_port_status
xhci_hub_control
xhci_hub_status_data
xhci_bus_suspend
xhci_port_missing_cas_quirk
xhci_bus_resume
xhci_get_resuming_ports
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10 
  11 
  12 #include <linux/slab.h>
  13 #include <asm/unaligned.h>
  14 
  15 #include "xhci.h"
  16 #include "xhci-trace.h"
  17 
  18 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  19 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  20                          PORT_RC | PORT_PLC | PORT_PE)
  21 
  22 /* USB 3 BOS descriptor and a capability descriptors, combined.
  23  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  24  */
  25 static u8 usb_bos_descriptor [] = {
  26         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  27         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  28         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  29         0x1,                            /*  __u8 bNumDeviceCaps */
  30         /* First device capability, SuperSpeed */
  31         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  32         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  33         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  34         0x00,                           /* bmAttributes, LTM off by default */
  35         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  36         0x03,                           /* bFunctionalitySupport,
  37                                            USB 3.0 speed only */
  38         0x00,                           /* bU1DevExitLat, set later. */
  39         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  40         /* Second device capability, SuperSpeedPlus */
  41         0x1c,                           /* bLength 28, will be adjusted later */
  42         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  43         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  44         0x00,                           /* bReserved 0 */
  45         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  46         0x01, 0x00,                     /* wFunctionalitySupport */
  47         0x00, 0x00,                     /* wReserved 0 */
  48         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  49         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  50         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  51         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  52         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  53 };
  54 
  55 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  56                                      u16 wLength)
  57 {
  58         struct xhci_port_cap *port_cap = NULL;
  59         int i, ssa_count;
  60         u32 temp;
  61         u16 desc_size, ssp_cap_size, ssa_size = 0;
  62         bool usb3_1 = false;
  63 
  64         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  65         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  66 
  67         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  68         for (i = 0; i < xhci->num_port_caps; i++) {
  69                 if (xhci->port_caps[i].maj_rev == 0x03 &&
  70                     xhci->port_caps[i].min_rev >= 0x01) {
  71                         usb3_1 = true;
  72                         port_cap = &xhci->port_caps[i];
  73                         break;
  74                 }
  75         }
  76 
  77         if (usb3_1) {
  78                 /* does xhci provide a PSI table for SSA speed attributes? */
  79                 if (port_cap->psi_count) {
  80                         /* two SSA entries for each unique PSI ID, RX and TX */
  81                         ssa_count = port_cap->psi_uid_count * 2;
  82                         ssa_size = ssa_count * sizeof(u32);
  83                         ssp_cap_size -= 16; /* skip copying the default SSA */
  84                 }
  85                 desc_size += ssp_cap_size;
  86         }
  87         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  88 
  89         if (usb3_1) {
  90                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  91                 buf[4] += 1;
  92                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  93         }
  94 
  95         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  96                 return wLength;
  97 
  98         /* Indicate whether the host has LTM support. */
  99         temp = readl(&xhci->cap_regs->hcc_params);
 100         if (HCC_LTC(temp))
 101                 buf[8] |= USB_LTM_SUPPORT;
 102 
 103         /* Set the U1 and U2 exit latencies. */
 104         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 105                 temp = readl(&xhci->cap_regs->hcs_params3);
 106                 buf[12] = HCS_U1_LATENCY(temp);
 107                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 108         }
 109 
 110         /* If PSI table exists, add the custom speed attributes from it */
 111         if (usb3_1 && port_cap->psi_count) {
 112                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 113                 int offset;
 114 
 115                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 116 
 117                 if (wLength < desc_size)
 118                         return wLength;
 119                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 120 
 121                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 122                 bm_attrib = (ssa_count - 1) & 0x1f;
 123                 bm_attrib |= (port_cap->psi_uid_count - 1) << 5;
 124                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 125 
 126                 if (wLength < desc_size + ssa_size)
 127                         return wLength;
 128                 /*
 129                  * Create the Sublink Speed Attributes (SSA) array.
 130                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 131                  * but link type bits 7:6 differ for values 01b and 10b.
 132                  * xhci has also only one PSI entry for a symmetric link when
 133                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 134                  */
 135                 offset = desc_size;
 136                 for (i = 0; i < port_cap->psi_count; i++) {
 137                         psi = port_cap->psi[i];
 138                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 139                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
 140                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
 141 
 142                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 143                         for (; psi_exp < 3; psi_exp++)
 144                                 psi_mant /= 1000;
 145                         if (psi_mant >= 10)
 146                                 psi |= BIT(14);
 147 
 148                         if ((psi & PLT_MASK) == PLT_SYM) {
 149                         /* Symmetric, create SSA RX and TX from one PSI entry */
 150                                 put_unaligned_le32(psi, &buf[offset]);
 151                                 psi |= 1 << 7;  /* turn entry to TX */
 152                                 offset += 4;
 153                                 if (offset >= desc_size + ssa_size)
 154                                         return desc_size + ssa_size;
 155                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 156                                 /* Asymetric RX, flip bits 7:6 for SSA */
 157                                 psi ^= PLT_MASK;
 158                         }
 159                         put_unaligned_le32(psi, &buf[offset]);
 160                         offset += 4;
 161                         if (offset >= desc_size + ssa_size)
 162                                 return desc_size + ssa_size;
 163                 }
 164         }
 165         /* ssa_size is 0 for other than usb 3.1 hosts */
 166         return desc_size + ssa_size;
 167 }
 168 
 169 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 170                 struct usb_hub_descriptor *desc, int ports)
 171 {
 172         u16 temp;
 173 
 174         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
 175         desc->bHubContrCurrent = 0;
 176 
 177         desc->bNbrPorts = ports;
 178         temp = 0;
 179         /* Bits 1:0 - support per-port power switching, or power always on */
 180         if (HCC_PPC(xhci->hcc_params))
 181                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 182         else
 183                 temp |= HUB_CHAR_NO_LPSM;
 184         /* Bit  2 - root hubs are not part of a compound device */
 185         /* Bits 4:3 - individual port over current protection */
 186         temp |= HUB_CHAR_INDV_PORT_OCPM;
 187         /* Bits 6:5 - no TTs in root ports */
 188         /* Bit  7 - no port indicators */
 189         desc->wHubCharacteristics = cpu_to_le16(temp);
 190 }
 191 
 192 /* Fill in the USB 2.0 roothub descriptor */
 193 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 194                 struct usb_hub_descriptor *desc)
 195 {
 196         int ports;
 197         u16 temp;
 198         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 199         u32 portsc;
 200         unsigned int i;
 201         struct xhci_hub *rhub;
 202 
 203         rhub = &xhci->usb2_rhub;
 204         ports = rhub->num_ports;
 205         xhci_common_hub_descriptor(xhci, desc, ports);
 206         desc->bDescriptorType = USB_DT_HUB;
 207         temp = 1 + (ports / 8);
 208         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 209 
 210         /* The Device Removable bits are reported on a byte granularity.
 211          * If the port doesn't exist within that byte, the bit is set to 0.
 212          */
 213         memset(port_removable, 0, sizeof(port_removable));
 214         for (i = 0; i < ports; i++) {
 215                 portsc = readl(rhub->ports[i]->addr);
 216                 /* If a device is removable, PORTSC reports a 0, same as in the
 217                  * hub descriptor DeviceRemovable bits.
 218                  */
 219                 if (portsc & PORT_DEV_REMOVE)
 220                         /* This math is hairy because bit 0 of DeviceRemovable
 221                          * is reserved, and bit 1 is for port 1, etc.
 222                          */
 223                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 224         }
 225 
 226         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 227          * ports on it.  The USB 2.0 specification says that there are two
 228          * variable length fields at the end of the hub descriptor:
 229          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 230          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 231          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 232          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 233          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 234          * set of ports that actually exist.
 235          */
 236         memset(desc->u.hs.DeviceRemovable, 0xff,
 237                         sizeof(desc->u.hs.DeviceRemovable));
 238         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 239                         sizeof(desc->u.hs.PortPwrCtrlMask));
 240 
 241         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 242                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 243                                 sizeof(__u8));
 244 }
 245 
 246 /* Fill in the USB 3.0 roothub descriptor */
 247 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 248                 struct usb_hub_descriptor *desc)
 249 {
 250         int ports;
 251         u16 port_removable;
 252         u32 portsc;
 253         unsigned int i;
 254         struct xhci_hub *rhub;
 255 
 256         rhub = &xhci->usb3_rhub;
 257         ports = rhub->num_ports;
 258         xhci_common_hub_descriptor(xhci, desc, ports);
 259         desc->bDescriptorType = USB_DT_SS_HUB;
 260         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 261 
 262         /* header decode latency should be zero for roothubs,
 263          * see section 4.23.5.2.
 264          */
 265         desc->u.ss.bHubHdrDecLat = 0;
 266         desc->u.ss.wHubDelay = 0;
 267 
 268         port_removable = 0;
 269         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 270         for (i = 0; i < ports; i++) {
 271                 portsc = readl(rhub->ports[i]->addr);
 272                 if (portsc & PORT_DEV_REMOVE)
 273                         port_removable |= 1 << (i + 1);
 274         }
 275 
 276         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 277 }
 278 
 279 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 280                 struct usb_hub_descriptor *desc)
 281 {
 282 
 283         if (hcd->speed >= HCD_USB3)
 284                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 285         else
 286                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 287 
 288 }
 289 
 290 static unsigned int xhci_port_speed(unsigned int port_status)
 291 {
 292         if (DEV_LOWSPEED(port_status))
 293                 return USB_PORT_STAT_LOW_SPEED;
 294         if (DEV_HIGHSPEED(port_status))
 295                 return USB_PORT_STAT_HIGH_SPEED;
 296         /*
 297          * FIXME: Yes, we should check for full speed, but the core uses that as
 298          * a default in portspeed() in usb/core/hub.c (which is the only place
 299          * USB_PORT_STAT_*_SPEED is used).
 300          */
 301         return 0;
 302 }
 303 
 304 /*
 305  * These bits are Read Only (RO) and should be saved and written to the
 306  * registers: 0, 3, 10:13, 30
 307  * connect status, over-current status, port speed, and device removable.
 308  * connect status and port speed are also sticky - meaning they're in
 309  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 310  */
 311 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 312 /*
 313  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 314  * bits 5:8, 9, 14:15, 25:27
 315  * link state, port power, port indicator state, "wake on" enable state
 316  */
 317 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 318 /*
 319  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 320  * bit 4 (port reset)
 321  */
 322 #define XHCI_PORT_RW1S  ((1<<4))
 323 /*
 324  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 325  * bits 1, 17, 18, 19, 20, 21, 22, 23
 326  * port enable/disable, and
 327  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 328  * over-current, reset, link state, and L1 change
 329  */
 330 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 331 /*
 332  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 333  * latched in
 334  */
 335 #define XHCI_PORT_RW    ((1<<16))
 336 /*
 337  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 338  * bits 2, 24, 28:31
 339  */
 340 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 341 
 342 /*
 343  * Given a port state, this function returns a value that would result in the
 344  * port being in the same state, if the value was written to the port status
 345  * control register.
 346  * Save Read Only (RO) bits and save read/write bits where
 347  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 348  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 349  */
 350 u32 xhci_port_state_to_neutral(u32 state)
 351 {
 352         /* Save read-only status and port state */
 353         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 354 }
 355 
 356 /*
 357  * find slot id based on port number.
 358  * @port: The one-based port number from one of the two split roothubs.
 359  */
 360 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 361                 u16 port)
 362 {
 363         int slot_id;
 364         int i;
 365         enum usb_device_speed speed;
 366 
 367         slot_id = 0;
 368         for (i = 0; i < MAX_HC_SLOTS; i++) {
 369                 if (!xhci->devs[i] || !xhci->devs[i]->udev)
 370                         continue;
 371                 speed = xhci->devs[i]->udev->speed;
 372                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 373                                 && xhci->devs[i]->fake_port == port) {
 374                         slot_id = i;
 375                         break;
 376                 }
 377         }
 378 
 379         return slot_id;
 380 }
 381 
 382 /*
 383  * Stop device
 384  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 385  * to complete.
 386  * suspend will set to 1, if suspend bit need to set in command.
 387  */
 388 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 389 {
 390         struct xhci_virt_device *virt_dev;
 391         struct xhci_command *cmd;
 392         unsigned long flags;
 393         int ret;
 394         int i;
 395 
 396         ret = 0;
 397         virt_dev = xhci->devs[slot_id];
 398         if (!virt_dev)
 399                 return -ENODEV;
 400 
 401         trace_xhci_stop_device(virt_dev);
 402 
 403         cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
 404         if (!cmd)
 405                 return -ENOMEM;
 406 
 407         spin_lock_irqsave(&xhci->lock, flags);
 408         for (i = LAST_EP_INDEX; i > 0; i--) {
 409                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 410                         struct xhci_ep_ctx *ep_ctx;
 411                         struct xhci_command *command;
 412 
 413                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 414 
 415                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 416                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 417                                 continue;
 418 
 419                         command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
 420                         if (!command) {
 421                                 spin_unlock_irqrestore(&xhci->lock, flags);
 422                                 ret = -ENOMEM;
 423                                 goto cmd_cleanup;
 424                         }
 425 
 426                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 427                                                        i, suspend);
 428                         if (ret) {
 429                                 spin_unlock_irqrestore(&xhci->lock, flags);
 430                                 xhci_free_command(xhci, command);
 431                                 goto cmd_cleanup;
 432                         }
 433                 }
 434         }
 435         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 436         if (ret) {
 437                 spin_unlock_irqrestore(&xhci->lock, flags);
 438                 goto cmd_cleanup;
 439         }
 440 
 441         xhci_ring_cmd_db(xhci);
 442         spin_unlock_irqrestore(&xhci->lock, flags);
 443 
 444         /* Wait for last stop endpoint command to finish */
 445         wait_for_completion(cmd->completion);
 446 
 447         if (cmd->status == COMP_COMMAND_ABORTED ||
 448             cmd->status == COMP_COMMAND_RING_STOPPED) {
 449                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 450                 ret = -ETIME;
 451         }
 452 
 453 cmd_cleanup:
 454         xhci_free_command(xhci, cmd);
 455         return ret;
 456 }
 457 
 458 /*
 459  * Ring device, it rings the all doorbells unconditionally.
 460  */
 461 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 462 {
 463         int i, s;
 464         struct xhci_virt_ep *ep;
 465 
 466         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 467                 ep = &xhci->devs[slot_id]->eps[i];
 468 
 469                 if (ep->ep_state & EP_HAS_STREAMS) {
 470                         for (s = 1; s < ep->stream_info->num_streams; s++)
 471                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 472                 } else if (ep->ring && ep->ring->dequeue) {
 473                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 474                 }
 475         }
 476 
 477         return;
 478 }
 479 
 480 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 481                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 482 {
 483         /* Don't allow the USB core to disable SuperSpeed ports. */
 484         if (hcd->speed >= HCD_USB3) {
 485                 xhci_dbg(xhci, "Ignoring request to disable "
 486                                 "SuperSpeed port.\n");
 487                 return;
 488         }
 489 
 490         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 491                 xhci_dbg(xhci,
 492                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 493                 return;
 494         }
 495 
 496         /* Write 1 to disable the port */
 497         writel(port_status | PORT_PE, addr);
 498         port_status = readl(addr);
 499         xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
 500                  hcd->self.busnum, wIndex + 1, port_status);
 501 }
 502 
 503 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 504                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 505 {
 506         char *port_change_bit;
 507         u32 status;
 508 
 509         switch (wValue) {
 510         case USB_PORT_FEAT_C_RESET:
 511                 status = PORT_RC;
 512                 port_change_bit = "reset";
 513                 break;
 514         case USB_PORT_FEAT_C_BH_PORT_RESET:
 515                 status = PORT_WRC;
 516                 port_change_bit = "warm(BH) reset";
 517                 break;
 518         case USB_PORT_FEAT_C_CONNECTION:
 519                 status = PORT_CSC;
 520                 port_change_bit = "connect";
 521                 break;
 522         case USB_PORT_FEAT_C_OVER_CURRENT:
 523                 status = PORT_OCC;
 524                 port_change_bit = "over-current";
 525                 break;
 526         case USB_PORT_FEAT_C_ENABLE:
 527                 status = PORT_PEC;
 528                 port_change_bit = "enable/disable";
 529                 break;
 530         case USB_PORT_FEAT_C_SUSPEND:
 531                 status = PORT_PLC;
 532                 port_change_bit = "suspend/resume";
 533                 break;
 534         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 535                 status = PORT_PLC;
 536                 port_change_bit = "link state";
 537                 break;
 538         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 539                 status = PORT_CEC;
 540                 port_change_bit = "config error";
 541                 break;
 542         default:
 543                 /* Should never happen */
 544                 return;
 545         }
 546         /* Change bits are all write 1 to clear */
 547         writel(port_status | status, addr);
 548         port_status = readl(addr);
 549 
 550         xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
 551                  wIndex + 1, port_change_bit, port_status);
 552 }
 553 
 554 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
 555 {
 556         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 557 
 558         if (hcd->speed >= HCD_USB3)
 559                 return &xhci->usb3_rhub;
 560         return &xhci->usb2_rhub;
 561 }
 562 
 563 /*
 564  * xhci_set_port_power() must be called with xhci->lock held.
 565  * It will release and re-aquire the lock while calling ACPI
 566  * method.
 567  */
 568 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 569                                 u16 index, bool on, unsigned long *flags)
 570 {
 571         struct xhci_hub *rhub;
 572         struct xhci_port *port;
 573         u32 temp;
 574 
 575         rhub = xhci_get_rhub(hcd);
 576         port = rhub->ports[index];
 577         temp = readl(port->addr);
 578 
 579         xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
 580                  hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp);
 581 
 582         temp = xhci_port_state_to_neutral(temp);
 583 
 584         if (on) {
 585                 /* Power on */
 586                 writel(temp | PORT_POWER, port->addr);
 587                 readl(port->addr);
 588         } else {
 589                 /* Power off */
 590                 writel(temp & ~PORT_POWER, port->addr);
 591         }
 592 
 593         spin_unlock_irqrestore(&xhci->lock, *flags);
 594         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 595                                         index);
 596         if (temp)
 597                 usb_acpi_set_power_state(hcd->self.root_hub,
 598                         index, on);
 599         spin_lock_irqsave(&xhci->lock, *flags);
 600 }
 601 
 602 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 603         u16 test_mode, u16 wIndex)
 604 {
 605         u32 temp;
 606         struct xhci_port *port;
 607 
 608         /* xhci only supports test mode for usb2 ports */
 609         port = xhci->usb2_rhub.ports[wIndex];
 610         temp = readl(port->addr + PORTPMSC);
 611         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 612         writel(temp, port->addr + PORTPMSC);
 613         xhci->test_mode = test_mode;
 614         if (test_mode == TEST_FORCE_EN)
 615                 xhci_start(xhci);
 616 }
 617 
 618 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 619                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 620 {
 621         int i, retval;
 622 
 623         /* Disable all Device Slots */
 624         xhci_dbg(xhci, "Disable all slots\n");
 625         spin_unlock_irqrestore(&xhci->lock, *flags);
 626         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 627                 if (!xhci->devs[i])
 628                         continue;
 629 
 630                 retval = xhci_disable_slot(xhci, i);
 631                 if (retval)
 632                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 633                                  i, retval);
 634         }
 635         spin_lock_irqsave(&xhci->lock, *flags);
 636         /* Put all ports to the Disable state by clear PP */
 637         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 638         /* Power off USB3 ports*/
 639         for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
 640                 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
 641         /* Power off USB2 ports*/
 642         for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
 643                 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
 644         /* Stop the controller */
 645         xhci_dbg(xhci, "Stop controller\n");
 646         retval = xhci_halt(xhci);
 647         if (retval)
 648                 return retval;
 649         /* Disable runtime PM for test mode */
 650         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 651         /* Set PORTPMSC.PTC field to enter selected test mode */
 652         /* Port is selected by wIndex. port_id = wIndex + 1 */
 653         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 654                                         test_mode, wIndex + 1);
 655         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 656         return retval;
 657 }
 658 
 659 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 660 {
 661         int retval;
 662 
 663         if (!xhci->test_mode) {
 664                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 665                 return 0;
 666         }
 667         if (xhci->test_mode == TEST_FORCE_EN &&
 668                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 669                 retval = xhci_halt(xhci);
 670                 if (retval)
 671                         return retval;
 672         }
 673         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 674         xhci->test_mode = 0;
 675         return xhci_reset(xhci);
 676 }
 677 
 678 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
 679                          u32 link_state)
 680 {
 681         u32 temp;
 682         u32 portsc;
 683 
 684         portsc = readl(port->addr);
 685         temp = xhci_port_state_to_neutral(portsc);
 686         temp &= ~PORT_PLS_MASK;
 687         temp |= PORT_LINK_STROBE | link_state;
 688         writel(temp, port->addr);
 689 
 690         xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
 691                  port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
 692                  portsc, temp);
 693 }
 694 
 695 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 696                                       struct xhci_port *port, u16 wake_mask)
 697 {
 698         u32 temp;
 699 
 700         temp = readl(port->addr);
 701         temp = xhci_port_state_to_neutral(temp);
 702 
 703         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 704                 temp |= PORT_WKCONN_E;
 705         else
 706                 temp &= ~PORT_WKCONN_E;
 707 
 708         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 709                 temp |= PORT_WKDISC_E;
 710         else
 711                 temp &= ~PORT_WKDISC_E;
 712 
 713         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 714                 temp |= PORT_WKOC_E;
 715         else
 716                 temp &= ~PORT_WKOC_E;
 717 
 718         writel(temp, port->addr);
 719 }
 720 
 721 /* Test and clear port RWC bit */
 722 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
 723                              u32 port_bit)
 724 {
 725         u32 temp;
 726 
 727         temp = readl(port->addr);
 728         if (temp & port_bit) {
 729                 temp = xhci_port_state_to_neutral(temp);
 730                 temp |= port_bit;
 731                 writel(temp, port->addr);
 732         }
 733 }
 734 
 735 /* Updates Link Status for super Speed port */
 736 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 737                 u32 *status, u32 status_reg)
 738 {
 739         u32 pls = status_reg & PORT_PLS_MASK;
 740 
 741         /* resume state is a xHCI internal state.
 742          * Do not report it to usb core, instead, pretend to be U3,
 743          * thus usb core knows it's not ready for transfer
 744          */
 745         if (pls == XDEV_RESUME) {
 746                 *status |= USB_SS_PORT_LS_U3;
 747                 return;
 748         }
 749 
 750         /* When the CAS bit is set then warm reset
 751          * should be performed on port
 752          */
 753         if (status_reg & PORT_CAS) {
 754                 /* The CAS bit can be set while the port is
 755                  * in any link state.
 756                  * Only roothubs have CAS bit, so we
 757                  * pretend to be in compliance mode
 758                  * unless we're already in compliance
 759                  * or the inactive state.
 760                  */
 761                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 762                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 763                         pls = USB_SS_PORT_LS_COMP_MOD;
 764                 }
 765                 /* Return also connection bit -
 766                  * hub state machine resets port
 767                  * when this bit is set.
 768                  */
 769                 pls |= USB_PORT_STAT_CONNECTION;
 770         } else {
 771                 /*
 772                  * If CAS bit isn't set but the Port is already at
 773                  * Compliance Mode, fake a connection so the USB core
 774                  * notices the Compliance state and resets the port.
 775                  * This resolves an issue generated by the SN65LVPE502CP
 776                  * in which sometimes the port enters compliance mode
 777                  * caused by a delay on the host-device negotiation.
 778                  */
 779                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 780                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 781                         pls |= USB_PORT_STAT_CONNECTION;
 782         }
 783 
 784         /* update status field */
 785         *status |= pls;
 786 }
 787 
 788 /*
 789  * Function for Compliance Mode Quirk.
 790  *
 791  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 792  * the compliance mode timer is deleted. A port won't enter
 793  * compliance mode if it has previously entered U0.
 794  */
 795 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 796                                     u16 wIndex)
 797 {
 798         u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
 799         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 800 
 801         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 802                 return;
 803 
 804         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 805                 xhci->port_status_u0 |= 1 << wIndex;
 806                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 807                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 808                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 809                                 "All USB3 ports have entered U0 already!");
 810                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 811                                 "Compliance Mode Recovery Timer Deleted.");
 812                 }
 813         }
 814 }
 815 
 816 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
 817                                              u32 *status, u32 portsc,
 818                                              unsigned long *flags)
 819 {
 820         struct xhci_bus_state *bus_state;
 821         struct xhci_hcd *xhci;
 822         struct usb_hcd *hcd;
 823         int slot_id;
 824         u32 wIndex;
 825 
 826         hcd = port->rhub->hcd;
 827         bus_state = &port->rhub->bus_state;
 828         xhci = hcd_to_xhci(hcd);
 829         wIndex = port->hcd_portnum;
 830 
 831         if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
 832                 *status = 0xffffffff;
 833                 return -EINVAL;
 834         }
 835         /* did port event handler already start resume timing? */
 836         if (!bus_state->resume_done[wIndex]) {
 837                 /* If not, maybe we are in a host initated resume? */
 838                 if (test_bit(wIndex, &bus_state->resuming_ports)) {
 839                         /* Host initated resume doesn't time the resume
 840                          * signalling using resume_done[].
 841                          * It manually sets RESUME state, sleeps 20ms
 842                          * and sets U0 state. This should probably be
 843                          * changed, but not right now.
 844                          */
 845                 } else {
 846                         /* port resume was discovered now and here,
 847                          * start resume timing
 848                          */
 849                         unsigned long timeout = jiffies +
 850                                 msecs_to_jiffies(USB_RESUME_TIMEOUT);
 851 
 852                         set_bit(wIndex, &bus_state->resuming_ports);
 853                         bus_state->resume_done[wIndex] = timeout;
 854                         mod_timer(&hcd->rh_timer, timeout);
 855                         usb_hcd_start_port_resume(&hcd->self, wIndex);
 856                 }
 857         /* Has resume been signalled for USB_RESUME_TIME yet? */
 858         } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) {
 859                 int time_left;
 860 
 861                 xhci_dbg(xhci, "resume USB2 port %d-%d\n",
 862                          hcd->self.busnum, wIndex + 1);
 863 
 864                 bus_state->resume_done[wIndex] = 0;
 865                 clear_bit(wIndex, &bus_state->resuming_ports);
 866 
 867                 set_bit(wIndex, &bus_state->rexit_ports);
 868 
 869                 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
 870                 xhci_set_link_state(xhci, port, XDEV_U0);
 871 
 872                 spin_unlock_irqrestore(&xhci->lock, *flags);
 873                 time_left = wait_for_completion_timeout(
 874                         &bus_state->rexit_done[wIndex],
 875                         msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
 876                 spin_lock_irqsave(&xhci->lock, *flags);
 877 
 878                 if (time_left) {
 879                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 880                                                             wIndex + 1);
 881                         if (!slot_id) {
 882                                 xhci_dbg(xhci, "slot_id is zero\n");
 883                                 *status = 0xffffffff;
 884                                 return -ENODEV;
 885                         }
 886                         xhci_ring_device(xhci, slot_id);
 887                 } else {
 888                         int port_status = readl(port->addr);
 889 
 890                         xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
 891                                   hcd->self.busnum, wIndex + 1, port_status);
 892                         *status |= USB_PORT_STAT_SUSPEND;
 893                         clear_bit(wIndex, &bus_state->rexit_ports);
 894                 }
 895 
 896                 usb_hcd_end_port_resume(&hcd->self, wIndex);
 897                 bus_state->port_c_suspend |= 1 << wIndex;
 898                 bus_state->suspended_ports &= ~(1 << wIndex);
 899         } else {
 900                 /*
 901                  * The resume has been signaling for less than
 902                  * USB_RESUME_TIME. Report the port status as SUSPEND,
 903                  * let the usbcore check port status again and clear
 904                  * resume signaling later.
 905                  */
 906                 *status |= USB_PORT_STAT_SUSPEND;
 907         }
 908         return 0;
 909 }
 910 
 911 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 912 {
 913         u32 ext_stat = 0;
 914         int speed_id;
 915 
 916         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 917         speed_id = DEV_PORT_SPEED(raw_port_status);
 918         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 919         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 920 
 921         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 922         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 923 
 924         return ext_stat;
 925 }
 926 
 927 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
 928                                       u32 portsc)
 929 {
 930         struct xhci_bus_state *bus_state;
 931         struct xhci_hcd *xhci;
 932         struct usb_hcd *hcd;
 933         u32 link_state;
 934         u32 portnum;
 935 
 936         bus_state = &port->rhub->bus_state;
 937         xhci = hcd_to_xhci(port->rhub->hcd);
 938         hcd = port->rhub->hcd;
 939         link_state = portsc & PORT_PLS_MASK;
 940         portnum = port->hcd_portnum;
 941 
 942         /* USB3 specific wPortChange bits
 943          *
 944          * Port link change with port in resume state should not be
 945          * reported to usbcore, as this is an internal state to be
 946          * handled by xhci driver. Reporting PLC to usbcore may
 947          * cause usbcore clearing PLC first and port change event
 948          * irq won't be generated.
 949          */
 950 
 951         if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
 952                 *status |= USB_PORT_STAT_C_LINK_STATE << 16;
 953         if (portsc & PORT_WRC)
 954                 *status |= USB_PORT_STAT_C_BH_RESET << 16;
 955         if (portsc & PORT_CEC)
 956                 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 957 
 958         /* USB3 specific wPortStatus bits */
 959         if (portsc & PORT_POWER) {
 960                 *status |= USB_SS_PORT_STAT_POWER;
 961                 /* link state handling */
 962                 if (link_state == XDEV_U0)
 963                         bus_state->suspended_ports &= ~(1 << portnum);
 964         }
 965 
 966         /* remote wake resume signaling complete */
 967         if (bus_state->port_remote_wakeup & (1 << portnum) &&
 968             link_state != XDEV_RESUME &&
 969             link_state != XDEV_RECOVERY) {
 970                 bus_state->port_remote_wakeup &= ~(1 << portnum);
 971                 usb_hcd_end_port_resume(&hcd->self, portnum);
 972         }
 973 
 974         xhci_hub_report_usb3_link_state(xhci, status, portsc);
 975         xhci_del_comp_mod_timer(xhci, portsc, portnum);
 976 }
 977 
 978 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
 979                                       u32 portsc, unsigned long *flags)
 980 {
 981         struct xhci_bus_state *bus_state;
 982         u32 link_state;
 983         u32 portnum;
 984         int ret;
 985 
 986         bus_state = &port->rhub->bus_state;
 987         link_state = portsc & PORT_PLS_MASK;
 988         portnum = port->hcd_portnum;
 989 
 990         /* USB2 wPortStatus bits */
 991         if (portsc & PORT_POWER) {
 992                 *status |= USB_PORT_STAT_POWER;
 993 
 994                 /* link state is only valid if port is powered */
 995                 if (link_state == XDEV_U3)
 996                         *status |= USB_PORT_STAT_SUSPEND;
 997                 if (link_state == XDEV_U2)
 998                         *status |= USB_PORT_STAT_L1;
 999                 if (link_state == XDEV_U0) {
1000                         bus_state->resume_done[portnum] = 0;
1001                         clear_bit(portnum, &bus_state->resuming_ports);
1002                         if (bus_state->suspended_ports & (1 << portnum)) {
1003                                 bus_state->suspended_ports &= ~(1 << portnum);
1004                                 bus_state->port_c_suspend |= 1 << portnum;
1005                         }
1006                 }
1007                 if (link_state == XDEV_RESUME) {
1008                         ret = xhci_handle_usb2_port_link_resume(port, status,
1009                                                                 portsc, flags);
1010                         if (ret)
1011                                 return;
1012                 }
1013         }
1014 }
1015 
1016 /*
1017  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1018  * 3.0 hubs use.
1019  *
1020  * Possible side effects:
1021  *  - Mark a port as being done with device resume,
1022  *    and ring the endpoint doorbells.
1023  *  - Stop the Synopsys redriver Compliance Mode polling.
1024  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
1025  */
1026 static u32 xhci_get_port_status(struct usb_hcd *hcd,
1027                 struct xhci_bus_state *bus_state,
1028         u16 wIndex, u32 raw_port_status,
1029                 unsigned long *flags)
1030         __releases(&xhci->lock)
1031         __acquires(&xhci->lock)
1032 {
1033         u32 status = 0;
1034         struct xhci_hub *rhub;
1035         struct xhci_port *port;
1036 
1037         rhub = xhci_get_rhub(hcd);
1038         port = rhub->ports[wIndex];
1039 
1040         /* common wPortChange bits */
1041         if (raw_port_status & PORT_CSC)
1042                 status |= USB_PORT_STAT_C_CONNECTION << 16;
1043         if (raw_port_status & PORT_PEC)
1044                 status |= USB_PORT_STAT_C_ENABLE << 16;
1045         if ((raw_port_status & PORT_OCC))
1046                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1047         if ((raw_port_status & PORT_RC))
1048                 status |= USB_PORT_STAT_C_RESET << 16;
1049 
1050         /* common wPortStatus bits */
1051         if (raw_port_status & PORT_CONNECT) {
1052                 status |= USB_PORT_STAT_CONNECTION;
1053                 status |= xhci_port_speed(raw_port_status);
1054         }
1055         if (raw_port_status & PORT_PE)
1056                 status |= USB_PORT_STAT_ENABLE;
1057         if (raw_port_status & PORT_OC)
1058                 status |= USB_PORT_STAT_OVERCURRENT;
1059         if (raw_port_status & PORT_RESET)
1060                 status |= USB_PORT_STAT_RESET;
1061 
1062         /* USB2 and USB3 specific bits, including Port Link State */
1063         if (hcd->speed >= HCD_USB3)
1064                 xhci_get_usb3_port_status(port, &status, raw_port_status);
1065         else
1066                 xhci_get_usb2_port_status(port, &status, raw_port_status,
1067                                           flags);
1068         /*
1069          * Clear stale usb2 resume signalling variables in case port changed
1070          * state during resume signalling. For example on error
1071          */
1072         if ((bus_state->resume_done[wIndex] ||
1073              test_bit(wIndex, &bus_state->resuming_ports)) &&
1074             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
1075             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
1076                 bus_state->resume_done[wIndex] = 0;
1077                 clear_bit(wIndex, &bus_state->resuming_ports);
1078                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1079         }
1080 
1081         if (bus_state->port_c_suspend & (1 << wIndex))
1082                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1083 
1084         return status;
1085 }
1086 
1087 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1088                 u16 wIndex, char *buf, u16 wLength)
1089 {
1090         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1091         int max_ports;
1092         unsigned long flags;
1093         u32 temp, status;
1094         int retval = 0;
1095         int slot_id;
1096         struct xhci_bus_state *bus_state;
1097         u16 link_state = 0;
1098         u16 wake_mask = 0;
1099         u16 timeout = 0;
1100         u16 test_mode = 0;
1101         struct xhci_hub *rhub;
1102         struct xhci_port **ports;
1103 
1104         rhub = xhci_get_rhub(hcd);
1105         ports = rhub->ports;
1106         max_ports = rhub->num_ports;
1107         bus_state = &rhub->bus_state;
1108 
1109         spin_lock_irqsave(&xhci->lock, flags);
1110         switch (typeReq) {
1111         case GetHubStatus:
1112                 /* No power source, over-current reported per port */
1113                 memset(buf, 0, 4);
1114                 break;
1115         case GetHubDescriptor:
1116                 /* Check to make sure userspace is asking for the USB 3.0 hub
1117                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1118                  * endpoint, like external hubs do.
1119                  */
1120                 if (hcd->speed >= HCD_USB3 &&
1121                                 (wLength < USB_DT_SS_HUB_SIZE ||
1122                                  wValue != (USB_DT_SS_HUB << 8))) {
1123                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1124                                         "USB 3.0 roothub.\n");
1125                         goto error;
1126                 }
1127                 xhci_hub_descriptor(hcd, xhci,
1128                                 (struct usb_hub_descriptor *) buf);
1129                 break;
1130         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1131                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1132                         goto error;
1133 
1134                 if (hcd->speed < HCD_USB3)
1135                         goto error;
1136 
1137                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1138                 spin_unlock_irqrestore(&xhci->lock, flags);
1139                 return retval;
1140         case GetPortStatus:
1141                 if (!wIndex || wIndex > max_ports)
1142                         goto error;
1143                 wIndex--;
1144                 temp = readl(ports[wIndex]->addr);
1145                 if (temp == ~(u32)0) {
1146                         xhci_hc_died(xhci);
1147                         retval = -ENODEV;
1148                         break;
1149                 }
1150                 trace_xhci_get_port_status(wIndex, temp);
1151                 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1152                                               &flags);
1153                 if (status == 0xffffffff)
1154                         goto error;
1155 
1156                 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1157                          hcd->self.busnum, wIndex + 1, temp, status);
1158 
1159                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1160                 /* if USB 3.1 extended port status return additional 4 bytes */
1161                 if (wValue == 0x02) {
1162                         u32 port_li;
1163 
1164                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1165                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1166                                 retval = -EINVAL;
1167                                 break;
1168                         }
1169                         port_li = readl(ports[wIndex]->addr + PORTLI);
1170                         status = xhci_get_ext_port_status(temp, port_li);
1171                         put_unaligned_le32(status, &buf[4]);
1172                 }
1173                 break;
1174         case SetPortFeature:
1175                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1176                         link_state = (wIndex & 0xff00) >> 3;
1177                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1178                         wake_mask = wIndex & 0xff00;
1179                 if (wValue == USB_PORT_FEAT_TEST)
1180                         test_mode = (wIndex & 0xff00) >> 8;
1181                 /* The MSB of wIndex is the U1/U2 timeout */
1182                 timeout = (wIndex & 0xff00) >> 8;
1183                 wIndex &= 0xff;
1184                 if (!wIndex || wIndex > max_ports)
1185                         goto error;
1186                 wIndex--;
1187                 temp = readl(ports[wIndex]->addr);
1188                 if (temp == ~(u32)0) {
1189                         xhci_hc_died(xhci);
1190                         retval = -ENODEV;
1191                         break;
1192                 }
1193                 temp = xhci_port_state_to_neutral(temp);
1194                 /* FIXME: What new port features do we need to support? */
1195                 switch (wValue) {
1196                 case USB_PORT_FEAT_SUSPEND:
1197                         temp = readl(ports[wIndex]->addr);
1198                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1199                                 /* Resume the port to U0 first */
1200                                 xhci_set_link_state(xhci, ports[wIndex],
1201                                                         XDEV_U0);
1202                                 spin_unlock_irqrestore(&xhci->lock, flags);
1203                                 msleep(10);
1204                                 spin_lock_irqsave(&xhci->lock, flags);
1205                         }
1206                         /* In spec software should not attempt to suspend
1207                          * a port unless the port reports that it is in the
1208                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1209                          */
1210                         temp = readl(ports[wIndex]->addr);
1211                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1212                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1213                                 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1214                                           hcd->self.busnum, wIndex + 1);
1215                                 goto error;
1216                         }
1217 
1218                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1219                                         wIndex + 1);
1220                         if (!slot_id) {
1221                                 xhci_warn(xhci, "slot_id is zero\n");
1222                                 goto error;
1223                         }
1224                         /* unlock to execute stop endpoint commands */
1225                         spin_unlock_irqrestore(&xhci->lock, flags);
1226                         xhci_stop_device(xhci, slot_id, 1);
1227                         spin_lock_irqsave(&xhci->lock, flags);
1228 
1229                         xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
1230 
1231                         spin_unlock_irqrestore(&xhci->lock, flags);
1232                         msleep(10); /* wait device to enter */
1233                         spin_lock_irqsave(&xhci->lock, flags);
1234 
1235                         temp = readl(ports[wIndex]->addr);
1236                         bus_state->suspended_ports |= 1 << wIndex;
1237                         break;
1238                 case USB_PORT_FEAT_LINK_STATE:
1239                         temp = readl(ports[wIndex]->addr);
1240                         /* Disable port */
1241                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1242                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1243                                 temp = xhci_port_state_to_neutral(temp);
1244                                 /*
1245                                  * Clear all change bits, so that we get a new
1246                                  * connection event.
1247                                  */
1248                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1249                                         PORT_OCC | PORT_RC | PORT_PLC |
1250                                         PORT_CEC;
1251                                 writel(temp | PORT_PE, ports[wIndex]->addr);
1252                                 temp = readl(ports[wIndex]->addr);
1253                                 break;
1254                         }
1255 
1256                         /* Put link in RxDetect (enable port) */
1257                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1258                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1259                                 xhci_set_link_state(xhci, ports[wIndex],
1260                                                         link_state);
1261                                 temp = readl(ports[wIndex]->addr);
1262                                 break;
1263                         }
1264 
1265                         /*
1266                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1267                          * root hub port's transition to compliance mode upon
1268                          * detecting LFPS timeout may be controlled by an
1269                          * Compliance Transition Enabled (CTE) flag (not
1270                          * software visible). This flag is set by writing 0xA
1271                          * to PORTSC PLS field which will allow transition to
1272                          * compliance mode the next time LFPS timeout is
1273                          * encountered. A warm reset will clear it.
1274                          *
1275                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1276                          * flag is set, otherwise, the compliance substate is
1277                          * automatically entered as on 1.0 and prior.
1278                          */
1279                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1280                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1281                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1282                                         break;
1283                                 }
1284 
1285                                 if ((temp & PORT_CONNECT)) {
1286                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1287                                         goto error;
1288                                 }
1289 
1290                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1291                                                 wIndex);
1292                                 xhci_set_link_state(xhci, ports[wIndex],
1293                                                 link_state);
1294 
1295                                 temp = readl(ports[wIndex]->addr);
1296                                 break;
1297                         }
1298                         /* Port must be enabled */
1299                         if (!(temp & PORT_PE)) {
1300                                 retval = -ENODEV;
1301                                 break;
1302                         }
1303                         /* Can't set port link state above '3' (U3) */
1304                         if (link_state > USB_SS_PORT_LS_U3) {
1305                                 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1306                                          wIndex, link_state);
1307                                 goto error;
1308                         }
1309 
1310                         /*
1311                          * set link to U0, steps depend on current link state.
1312                          * U3: set link to U0 and wait for u3exit completion.
1313                          * U1/U2:  no PLC complete event, only set link to U0.
1314                          * Resume/Recovery: device initiated U0, only wait for
1315                          * completion
1316                          */
1317                         if (link_state == USB_SS_PORT_LS_U0) {
1318                                 u32 pls = temp & PORT_PLS_MASK;
1319                                 bool wait_u0 = false;
1320 
1321                                 /* already in U0 */
1322                                 if (pls == XDEV_U0)
1323                                         break;
1324                                 if (pls == XDEV_U3 ||
1325                                     pls == XDEV_RESUME ||
1326                                     pls == XDEV_RECOVERY) {
1327                                         wait_u0 = true;
1328                                         reinit_completion(&bus_state->u3exit_done[wIndex]);
1329                                 }
1330                                 if (pls <= XDEV_U3) /* U1, U2, U3 */
1331                                         xhci_set_link_state(xhci, ports[wIndex],
1332                                                             USB_SS_PORT_LS_U0);
1333                                 if (!wait_u0) {
1334                                         if (pls > XDEV_U3)
1335                                                 goto error;
1336                                         break;
1337                                 }
1338                                 spin_unlock_irqrestore(&xhci->lock, flags);
1339                                 if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex],
1340                                                                  msecs_to_jiffies(100)))
1341                                         xhci_dbg(xhci, "missing U0 port change event for port %d\n",
1342                                                  wIndex);
1343                                 spin_lock_irqsave(&xhci->lock, flags);
1344                                 temp = readl(ports[wIndex]->addr);
1345                                 break;
1346                         }
1347 
1348                         if (link_state == USB_SS_PORT_LS_U3) {
1349                                 int retries = 16;
1350                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1351                                                 wIndex + 1);
1352                                 if (slot_id) {
1353                                         /* unlock to execute stop endpoint
1354                                          * commands */
1355                                         spin_unlock_irqrestore(&xhci->lock,
1356                                                                 flags);
1357                                         xhci_stop_device(xhci, slot_id, 1);
1358                                         spin_lock_irqsave(&xhci->lock, flags);
1359                                 }
1360                                 xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3);
1361                                 spin_unlock_irqrestore(&xhci->lock, flags);
1362                                 while (retries--) {
1363                                         usleep_range(4000, 8000);
1364                                         temp = readl(ports[wIndex]->addr);
1365                                         if ((temp & PORT_PLS_MASK) == XDEV_U3)
1366                                                 break;
1367                                 }
1368                                 spin_lock_irqsave(&xhci->lock, flags);
1369                                 temp = readl(ports[wIndex]->addr);
1370                                 bus_state->suspended_ports |= 1 << wIndex;
1371                         }
1372                         break;
1373                 case USB_PORT_FEAT_POWER:
1374                         /*
1375                          * Turn on ports, even if there isn't per-port switching.
1376                          * HC will report connect events even before this is set.
1377                          * However, hub_wq will ignore the roothub events until
1378                          * the roothub is registered.
1379                          */
1380                         xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1381                         break;
1382                 case USB_PORT_FEAT_RESET:
1383                         temp = (temp | PORT_RESET);
1384                         writel(temp, ports[wIndex]->addr);
1385 
1386                         temp = readl(ports[wIndex]->addr);
1387                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1388                         break;
1389                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1390                         xhci_set_remote_wake_mask(xhci, ports[wIndex],
1391                                                   wake_mask);
1392                         temp = readl(ports[wIndex]->addr);
1393                         xhci_dbg(xhci, "set port remote wake mask, "
1394                                         "actual port %d status  = 0x%x\n",
1395                                         wIndex, temp);
1396                         break;
1397                 case USB_PORT_FEAT_BH_PORT_RESET:
1398                         temp |= PORT_WR;
1399                         writel(temp, ports[wIndex]->addr);
1400                         temp = readl(ports[wIndex]->addr);
1401                         break;
1402                 case USB_PORT_FEAT_U1_TIMEOUT:
1403                         if (hcd->speed < HCD_USB3)
1404                                 goto error;
1405                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1406                         temp &= ~PORT_U1_TIMEOUT_MASK;
1407                         temp |= PORT_U1_TIMEOUT(timeout);
1408                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1409                         break;
1410                 case USB_PORT_FEAT_U2_TIMEOUT:
1411                         if (hcd->speed < HCD_USB3)
1412                                 goto error;
1413                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1414                         temp &= ~PORT_U2_TIMEOUT_MASK;
1415                         temp |= PORT_U2_TIMEOUT(timeout);
1416                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1417                         break;
1418                 case USB_PORT_FEAT_TEST:
1419                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1420                         if (hcd->speed != HCD_USB2)
1421                                 goto error;
1422                         if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1423                                 goto error;
1424                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1425                                                       &flags);
1426                         break;
1427                 default:
1428                         goto error;
1429                 }
1430                 /* unblock any posted writes */
1431                 temp = readl(ports[wIndex]->addr);
1432                 break;
1433         case ClearPortFeature:
1434                 if (!wIndex || wIndex > max_ports)
1435                         goto error;
1436                 wIndex--;
1437                 temp = readl(ports[wIndex]->addr);
1438                 if (temp == ~(u32)0) {
1439                         xhci_hc_died(xhci);
1440                         retval = -ENODEV;
1441                         break;
1442                 }
1443                 /* FIXME: What new port features do we need to support? */
1444                 temp = xhci_port_state_to_neutral(temp);
1445                 switch (wValue) {
1446                 case USB_PORT_FEAT_SUSPEND:
1447                         temp = readl(ports[wIndex]->addr);
1448                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1449                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1450                         if (temp & PORT_RESET)
1451                                 goto error;
1452                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1453                                 if ((temp & PORT_PE) == 0)
1454                                         goto error;
1455 
1456                                 set_bit(wIndex, &bus_state->resuming_ports);
1457                                 usb_hcd_start_port_resume(&hcd->self, wIndex);
1458                                 xhci_set_link_state(xhci, ports[wIndex],
1459                                                     XDEV_RESUME);
1460                                 spin_unlock_irqrestore(&xhci->lock, flags);
1461                                 msleep(USB_RESUME_TIMEOUT);
1462                                 spin_lock_irqsave(&xhci->lock, flags);
1463                                 xhci_set_link_state(xhci, ports[wIndex],
1464                                                         XDEV_U0);
1465                                 clear_bit(wIndex, &bus_state->resuming_ports);
1466                                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1467                         }
1468                         bus_state->port_c_suspend |= 1 << wIndex;
1469 
1470                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1471                                         wIndex + 1);
1472                         if (!slot_id) {
1473                                 xhci_dbg(xhci, "slot_id is zero\n");
1474                                 goto error;
1475                         }
1476                         xhci_ring_device(xhci, slot_id);
1477                         break;
1478                 case USB_PORT_FEAT_C_SUSPEND:
1479                         bus_state->port_c_suspend &= ~(1 << wIndex);
1480                         /* fall through */
1481                 case USB_PORT_FEAT_C_RESET:
1482                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1483                 case USB_PORT_FEAT_C_CONNECTION:
1484                 case USB_PORT_FEAT_C_OVER_CURRENT:
1485                 case USB_PORT_FEAT_C_ENABLE:
1486                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1487                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1488                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1489                                         ports[wIndex]->addr, temp);
1490                         break;
1491                 case USB_PORT_FEAT_ENABLE:
1492                         xhci_disable_port(hcd, xhci, wIndex,
1493                                         ports[wIndex]->addr, temp);
1494                         break;
1495                 case USB_PORT_FEAT_POWER:
1496                         xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1497                         break;
1498                 case USB_PORT_FEAT_TEST:
1499                         retval = xhci_exit_test_mode(xhci);
1500                         break;
1501                 default:
1502                         goto error;
1503                 }
1504                 break;
1505         default:
1506 error:
1507                 /* "stall" on error */
1508                 retval = -EPIPE;
1509         }
1510         spin_unlock_irqrestore(&xhci->lock, flags);
1511         return retval;
1512 }
1513 
1514 /*
1515  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1516  * Ports are 0-indexed from the HCD point of view,
1517  * and 1-indexed from the USB core pointer of view.
1518  *
1519  * Note that the status change bits will be cleared as soon as a port status
1520  * change event is generated, so we use the saved status from that event.
1521  */
1522 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1523 {
1524         unsigned long flags;
1525         u32 temp, status;
1526         u32 mask;
1527         int i, retval;
1528         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1529         int max_ports;
1530         struct xhci_bus_state *bus_state;
1531         bool reset_change = false;
1532         struct xhci_hub *rhub;
1533         struct xhci_port **ports;
1534 
1535         rhub = xhci_get_rhub(hcd);
1536         ports = rhub->ports;
1537         max_ports = rhub->num_ports;
1538         bus_state = &rhub->bus_state;
1539 
1540         /* Initial status is no changes */
1541         retval = (max_ports + 8) / 8;
1542         memset(buf, 0, retval);
1543 
1544         /*
1545          * Inform the usbcore about resume-in-progress by returning
1546          * a non-zero value even if there are no status changes.
1547          */
1548         status = bus_state->resuming_ports;
1549 
1550         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1551 
1552         spin_lock_irqsave(&xhci->lock, flags);
1553         /* For each port, did anything change?  If so, set that bit in buf. */
1554         for (i = 0; i < max_ports; i++) {
1555                 temp = readl(ports[i]->addr);
1556                 if (temp == ~(u32)0) {
1557                         xhci_hc_died(xhci);
1558                         retval = -ENODEV;
1559                         break;
1560                 }
1561                 trace_xhci_hub_status_data(i, temp);
1562 
1563                 if ((temp & mask) != 0 ||
1564                         (bus_state->port_c_suspend & 1 << i) ||
1565                         (bus_state->resume_done[i] && time_after_eq(
1566                             jiffies, bus_state->resume_done[i]))) {
1567                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1568                         status = 1;
1569                 }
1570                 if ((temp & PORT_RC))
1571                         reset_change = true;
1572                 if (temp & PORT_OC)
1573                         status = 1;
1574         }
1575         if (!status && !reset_change) {
1576                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1577                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1578         }
1579         spin_unlock_irqrestore(&xhci->lock, flags);
1580         return status ? retval : 0;
1581 }
1582 
1583 #ifdef CONFIG_PM
1584 
1585 int xhci_bus_suspend(struct usb_hcd *hcd)
1586 {
1587         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1588         int max_ports, port_index;
1589         struct xhci_bus_state *bus_state;
1590         unsigned long flags;
1591         struct xhci_hub *rhub;
1592         struct xhci_port **ports;
1593         u32 portsc_buf[USB_MAXCHILDREN];
1594         bool wake_enabled;
1595 
1596         rhub = xhci_get_rhub(hcd);
1597         ports = rhub->ports;
1598         max_ports = rhub->num_ports;
1599         bus_state = &rhub->bus_state;
1600         wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1601 
1602         spin_lock_irqsave(&xhci->lock, flags);
1603 
1604         if (wake_enabled) {
1605                 if (bus_state->resuming_ports ||        /* USB2 */
1606                     bus_state->port_remote_wakeup) {    /* USB3 */
1607                         spin_unlock_irqrestore(&xhci->lock, flags);
1608                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1609                         return -EBUSY;
1610                 }
1611         }
1612         /*
1613          * Prepare ports for suspend, but don't write anything before all ports
1614          * are checked and we know bus suspend can proceed
1615          */
1616         bus_state->bus_suspended = 0;
1617         port_index = max_ports;
1618         while (port_index--) {
1619                 u32 t1, t2;
1620                 int retries = 10;
1621 retry:
1622                 t1 = readl(ports[port_index]->addr);
1623                 t2 = xhci_port_state_to_neutral(t1);
1624                 portsc_buf[port_index] = 0;
1625 
1626                 /*
1627                  * Give a USB3 port in link training time to finish, but don't
1628                  * prevent suspend as port might be stuck
1629                  */
1630                 if ((hcd->speed >= HCD_USB3) && retries-- &&
1631                     (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1632                         spin_unlock_irqrestore(&xhci->lock, flags);
1633                         msleep(XHCI_PORT_POLLING_LFPS_TIME);
1634                         spin_lock_irqsave(&xhci->lock, flags);
1635                         xhci_dbg(xhci, "port %d polling in bus suspend, waiting\n",
1636                                  port_index);
1637                         goto retry;
1638                 }
1639                 /* bail out if port detected a over-current condition */
1640                 if (t1 & PORT_OC) {
1641                         bus_state->bus_suspended = 0;
1642                         spin_unlock_irqrestore(&xhci->lock, flags);
1643                         xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n");
1644                         return -EBUSY;
1645                 }
1646                 /* suspend ports in U0, or bail out for new connect changes */
1647                 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1648                         if ((t1 & PORT_CSC) && wake_enabled) {
1649                                 bus_state->bus_suspended = 0;
1650                                 spin_unlock_irqrestore(&xhci->lock, flags);
1651                                 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1652                                 return -EBUSY;
1653                         }
1654                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1655                         t2 &= ~PORT_PLS_MASK;
1656                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1657                         set_bit(port_index, &bus_state->bus_suspended);
1658                 }
1659                 /* USB core sets remote wake mask for USB 3.0 hubs,
1660                  * including the USB 3.0 roothub, but only if CONFIG_PM
1661                  * is enabled, so also enable remote wake here.
1662                  */
1663                 if (wake_enabled) {
1664                         if (t1 & PORT_CONNECT) {
1665                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1666                                 t2 &= ~PORT_WKCONN_E;
1667                         } else {
1668                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1669                                 t2 &= ~PORT_WKDISC_E;
1670                         }
1671 
1672                         if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1673                             (hcd->speed < HCD_USB3)) {
1674                                 if (usb_amd_pt_check_port(hcd->self.controller,
1675                                                           port_index))
1676                                         t2 &= ~PORT_WAKE_BITS;
1677                         }
1678                 } else
1679                         t2 &= ~PORT_WAKE_BITS;
1680 
1681                 t1 = xhci_port_state_to_neutral(t1);
1682                 if (t1 != t2)
1683                         portsc_buf[port_index] = t2;
1684         }
1685 
1686         /* write port settings, stopping and suspending ports if needed */
1687         port_index = max_ports;
1688         while (port_index--) {
1689                 if (!portsc_buf[port_index])
1690                         continue;
1691                 if (test_bit(port_index, &bus_state->bus_suspended)) {
1692                         int slot_id;
1693 
1694                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1695                                                             port_index + 1);
1696                         if (slot_id) {
1697                                 spin_unlock_irqrestore(&xhci->lock, flags);
1698                                 xhci_stop_device(xhci, slot_id, 1);
1699                                 spin_lock_irqsave(&xhci->lock, flags);
1700                         }
1701                 }
1702                 writel(portsc_buf[port_index], ports[port_index]->addr);
1703         }
1704         hcd->state = HC_STATE_SUSPENDED;
1705         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1706         spin_unlock_irqrestore(&xhci->lock, flags);
1707         return 0;
1708 }
1709 
1710 /*
1711  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1712  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1713  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1714  */
1715 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1716 {
1717         u32 portsc;
1718 
1719         portsc = readl(port->addr);
1720 
1721         /* if any of these are set we are not stuck */
1722         if (portsc & (PORT_CONNECT | PORT_CAS))
1723                 return false;
1724 
1725         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1726             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1727                 return false;
1728 
1729         /* clear wakeup/change bits, and do a warm port reset */
1730         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1731         portsc |= PORT_WR;
1732         writel(portsc, port->addr);
1733         /* flush write */
1734         readl(port->addr);
1735         return true;
1736 }
1737 
1738 int xhci_bus_resume(struct usb_hcd *hcd)
1739 {
1740         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1741         struct xhci_bus_state *bus_state;
1742         unsigned long flags;
1743         int max_ports, port_index;
1744         int slot_id;
1745         int sret;
1746         u32 next_state;
1747         u32 temp, portsc;
1748         struct xhci_hub *rhub;
1749         struct xhci_port **ports;
1750 
1751         rhub = xhci_get_rhub(hcd);
1752         ports = rhub->ports;
1753         max_ports = rhub->num_ports;
1754         bus_state = &rhub->bus_state;
1755 
1756         if (time_before(jiffies, bus_state->next_statechange))
1757                 msleep(5);
1758 
1759         spin_lock_irqsave(&xhci->lock, flags);
1760         if (!HCD_HW_ACCESSIBLE(hcd)) {
1761                 spin_unlock_irqrestore(&xhci->lock, flags);
1762                 return -ESHUTDOWN;
1763         }
1764 
1765         /* delay the irqs */
1766         temp = readl(&xhci->op_regs->command);
1767         temp &= ~CMD_EIE;
1768         writel(temp, &xhci->op_regs->command);
1769 
1770         /* bus specific resume for ports we suspended at bus_suspend */
1771         if (hcd->speed >= HCD_USB3)
1772                 next_state = XDEV_U0;
1773         else
1774                 next_state = XDEV_RESUME;
1775 
1776         port_index = max_ports;
1777         while (port_index--) {
1778                 portsc = readl(ports[port_index]->addr);
1779 
1780                 /* warm reset CAS limited ports stuck in polling/compliance */
1781                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1782                     (hcd->speed >= HCD_USB3) &&
1783                     xhci_port_missing_cas_quirk(ports[port_index])) {
1784                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1785                         clear_bit(port_index, &bus_state->bus_suspended);
1786                         continue;
1787                 }
1788                 /* resume if we suspended the link, and it is still suspended */
1789                 if (test_bit(port_index, &bus_state->bus_suspended))
1790                         switch (portsc & PORT_PLS_MASK) {
1791                         case XDEV_U3:
1792                                 portsc = xhci_port_state_to_neutral(portsc);
1793                                 portsc &= ~PORT_PLS_MASK;
1794                                 portsc |= PORT_LINK_STROBE | next_state;
1795                                 break;
1796                         case XDEV_RESUME:
1797                                 /* resume already initiated */
1798                                 break;
1799                         default:
1800                                 /* not in a resumeable state, ignore it */
1801                                 clear_bit(port_index,
1802                                           &bus_state->bus_suspended);
1803                                 break;
1804                         }
1805                 /* disable wake for all ports, write new link state if needed */
1806                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1807                 writel(portsc, ports[port_index]->addr);
1808         }
1809 
1810         /* USB2 specific resume signaling delay and U0 link state transition */
1811         if (hcd->speed < HCD_USB3) {
1812                 if (bus_state->bus_suspended) {
1813                         spin_unlock_irqrestore(&xhci->lock, flags);
1814                         msleep(USB_RESUME_TIMEOUT);
1815                         spin_lock_irqsave(&xhci->lock, flags);
1816                 }
1817                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1818                                  BITS_PER_LONG) {
1819                         /* Clear PLC to poll it later for U0 transition */
1820                         xhci_test_and_clear_bit(xhci, ports[port_index],
1821                                                 PORT_PLC);
1822                         xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1823                 }
1824         }
1825 
1826         /* poll for U0 link state complete, both USB2 and USB3 */
1827         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1828                 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1829                                       PORT_PLC, 10 * 1000);
1830                 if (sret) {
1831                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1832                                   port_index);
1833                         continue;
1834                 }
1835                 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1836                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1837                 if (slot_id)
1838                         xhci_ring_device(xhci, slot_id);
1839         }
1840         (void) readl(&xhci->op_regs->command);
1841 
1842         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1843         /* re-enable irqs */
1844         temp = readl(&xhci->op_regs->command);
1845         temp |= CMD_EIE;
1846         writel(temp, &xhci->op_regs->command);
1847         temp = readl(&xhci->op_regs->command);
1848 
1849         spin_unlock_irqrestore(&xhci->lock, flags);
1850         return 0;
1851 }
1852 
1853 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1854 {
1855         struct xhci_hub *rhub = xhci_get_rhub(hcd);
1856 
1857         /* USB3 port wakeups are reported via usb_wakeup_notification() */
1858         return rhub->bus_state.resuming_ports;  /* USB2 ports only */
1859 }
1860 
1861 #endif  /* CONFIG_PM */
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root/drivers/usb/host/xhci-hub.c

DEFINITIONS
