This source file includes following definitions.
- hcd_to_ehci
- ehci_to_hcd
- ehci_port_speed
- ehci_readl
- imx28_ehci_writel
- imx28_ehci_writel
- ehci_writel
- set_ohci_hcfs
- set_ohci_hcfs
- cpu_to_hc32
- hc32_to_cpu
- hc32_to_cpup
- cpu_to_hc32
- hc32_to_cpu
- hc32_to_cpup
1
2
3
4
5
6 #ifndef __LINUX_EHCI_HCD_H
7 #define __LINUX_EHCI_HCD_H
8
9
10
11
12
13
14
15
16
17
18
19 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
20 typedef __u32 __bitwise __hc32;
21 typedef __u16 __bitwise __hc16;
22 #else
23 #define __hc32 __le32
24 #define __hc16 __le16
25 #endif
26
27
28 #ifdef CONFIG_DYNAMIC_DEBUG
29 #define EHCI_STATS
30 #endif
31
32 struct ehci_stats {
33
34 unsigned long normal;
35 unsigned long error;
36 unsigned long iaa;
37 unsigned long lost_iaa;
38
39
40 unsigned long complete;
41 unsigned long unlink;
42 };
43
44
45
46
47
48 struct ehci_per_sched {
49 struct usb_device *udev;
50 struct usb_host_endpoint *ep;
51 struct list_head ps_list;
52 u16 tt_usecs;
53 u16 cs_mask;
54 u16 period;
55 u16 phase;
56 u8 bw_phase;
57
58 u8 phase_uf;
59 u8 usecs, c_usecs;
60 u8 bw_uperiod;
61
62 u8 bw_period;
63 };
64 #define NO_FRAME 29999
65
66
67
68
69
70
71
72
73
74
75
76 #define EHCI_MAX_ROOT_PORTS 15
77
78
79
80
81
82 enum ehci_rh_state {
83 EHCI_RH_HALTED,
84 EHCI_RH_SUSPENDED,
85 EHCI_RH_RUNNING,
86 EHCI_RH_STOPPING
87 };
88
89
90
91
92
93
94 enum ehci_hrtimer_event {
95 EHCI_HRTIMER_POLL_ASS,
96 EHCI_HRTIMER_POLL_PSS,
97 EHCI_HRTIMER_POLL_DEAD,
98 EHCI_HRTIMER_UNLINK_INTR,
99 EHCI_HRTIMER_FREE_ITDS,
100 EHCI_HRTIMER_ACTIVE_UNLINK,
101 EHCI_HRTIMER_START_UNLINK_INTR,
102 EHCI_HRTIMER_ASYNC_UNLINKS,
103 EHCI_HRTIMER_IAA_WATCHDOG,
104 EHCI_HRTIMER_DISABLE_PERIODIC,
105 EHCI_HRTIMER_DISABLE_ASYNC,
106 EHCI_HRTIMER_IO_WATCHDOG,
107 EHCI_HRTIMER_NUM_EVENTS
108 };
109 #define EHCI_HRTIMER_NO_EVENT 99
110
111 struct ehci_hcd {
112
113 enum ehci_hrtimer_event next_hrtimer_event;
114 unsigned enabled_hrtimer_events;
115 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
116 struct hrtimer hrtimer;
117
118 int PSS_poll_count;
119 int ASS_poll_count;
120 int died_poll_count;
121
122
123 struct ehci_caps __iomem *caps;
124 struct ehci_regs __iomem *regs;
125 struct ehci_dbg_port __iomem *debug;
126
127 __u32 hcs_params;
128 spinlock_t lock;
129 enum ehci_rh_state rh_state;
130
131
132 bool scanning:1;
133 bool need_rescan:1;
134 bool intr_unlinking:1;
135 bool iaa_in_progress:1;
136 bool async_unlinking:1;
137 bool shutdown:1;
138 struct ehci_qh *qh_scan_next;
139
140
141 struct ehci_qh *async;
142 struct ehci_qh *dummy;
143 struct list_head async_unlink;
144 struct list_head async_idle;
145 unsigned async_unlink_cycle;
146 unsigned async_count;
147 __hc32 old_current;
148 __hc32 old_token;
149
150
151 #define DEFAULT_I_TDPS 1024
152 unsigned periodic_size;
153 __hc32 *periodic;
154 dma_addr_t periodic_dma;
155 struct list_head intr_qh_list;
156 unsigned i_thresh;
157
158 union ehci_shadow *pshadow;
159 struct list_head intr_unlink_wait;
160 struct list_head intr_unlink;
161 unsigned intr_unlink_wait_cycle;
162 unsigned intr_unlink_cycle;
163 unsigned now_frame;
164 unsigned last_iso_frame;
165 unsigned intr_count;
166 unsigned isoc_count;
167 unsigned periodic_count;
168 unsigned uframe_periodic_max;
169
170
171
172 struct list_head cached_itd_list;
173 struct ehci_itd *last_itd_to_free;
174 struct list_head cached_sitd_list;
175 struct ehci_sitd *last_sitd_to_free;
176
177
178 unsigned long reset_done[EHCI_MAX_ROOT_PORTS];
179
180
181 unsigned long bus_suspended;
182
183 unsigned long companion_ports;
184
185 unsigned long owned_ports;
186
187 unsigned long port_c_suspend;
188
189 unsigned long suspended_ports;
190
191 unsigned long resuming_ports;
192
193
194
195 struct dma_pool *qh_pool;
196 struct dma_pool *qtd_pool;
197 struct dma_pool *itd_pool;
198 struct dma_pool *sitd_pool;
199
200 unsigned random_frame;
201 unsigned long next_statechange;
202 ktime_t last_periodic_enable;
203 u32 command;
204
205
206 unsigned no_selective_suspend:1;
207 unsigned has_fsl_port_bug:1;
208 unsigned has_fsl_hs_errata:1;
209 unsigned has_fsl_susp_errata:1;
210 unsigned big_endian_mmio:1;
211 unsigned big_endian_desc:1;
212 unsigned big_endian_capbase:1;
213 unsigned has_amcc_usb23:1;
214 unsigned need_io_watchdog:1;
215 unsigned amd_pll_fix:1;
216 unsigned use_dummy_qh:1;
217 unsigned has_synopsys_hc_bug:1;
218 unsigned frame_index_bug:1;
219 unsigned need_oc_pp_cycle:1;
220 unsigned imx28_write_fix:1;
221
222
223 #define OHCI_CTRL_HCFS (3 << 6)
224 #define OHCI_USB_OPER (2 << 6)
225 #define OHCI_USB_SUSPEND (3 << 6)
226
227 #define OHCI_HCCTRL_OFFSET 0x4
228 #define OHCI_HCCTRL_LEN 0x4
229 __hc32 *ohci_hcctrl_reg;
230 unsigned has_hostpc:1;
231 unsigned has_tdi_phy_lpm:1;
232 unsigned has_ppcd:1;
233 u8 sbrn;
234
235
236 #ifdef EHCI_STATS
237 struct ehci_stats stats;
238 # define INCR(x) ((x)++)
239 #else
240 # define INCR(x) do {} while (0)
241 #endif
242
243
244 #ifdef CONFIG_DYNAMIC_DEBUG
245 struct dentry *debug_dir;
246 #endif
247
248
249 #define EHCI_BANDWIDTH_SIZE 64
250 #define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3)
251 u8 bandwidth[EHCI_BANDWIDTH_SIZE];
252
253 u8 tt_budget[EHCI_BANDWIDTH_SIZE];
254
255 struct list_head tt_list;
256
257
258 unsigned long priv[0] __aligned(sizeof(s64));
259 };
260
261
262 static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd)
263 {
264 return (struct ehci_hcd *) (hcd->hcd_priv);
265 }
266 static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)
267 {
268 return container_of((void *) ehci, struct usb_hcd, hcd_priv);
269 }
270
271
272
273 #include <linux/usb/ehci_def.h>
274
275
276
277 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
278
279
280
281
282
283
284
285
286
287 struct ehci_qtd {
288
289 __hc32 hw_next;
290 __hc32 hw_alt_next;
291 __hc32 hw_token;
292 #define QTD_TOGGLE (1 << 31)
293 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
294 #define QTD_IOC (1 << 15)
295 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
296 #define QTD_PID(tok) (((tok)>>8) & 0x3)
297 #define QTD_STS_ACTIVE (1 << 7)
298 #define QTD_STS_HALT (1 << 6)
299 #define QTD_STS_DBE (1 << 5)
300 #define QTD_STS_BABBLE (1 << 4)
301 #define QTD_STS_XACT (1 << 3)
302 #define QTD_STS_MMF (1 << 2)
303 #define QTD_STS_STS (1 << 1)
304 #define QTD_STS_PING (1 << 0)
305
306 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
307 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
308 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
309
310 __hc32 hw_buf[5];
311 __hc32 hw_buf_hi[5];
312
313
314 dma_addr_t qtd_dma;
315 struct list_head qtd_list;
316 struct urb *urb;
317 size_t length;
318 } __aligned(32);
319
320
321 #define QTD_MASK(ehci) cpu_to_hc32(ehci, ~0x1f)
322
323 #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
324
325
326
327
328 #define Q_NEXT_TYPE(ehci, dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
329
330
331
332
333
334
335
336
337
338 #define Q_TYPE_ITD (0 << 1)
339 #define Q_TYPE_QH (1 << 1)
340 #define Q_TYPE_SITD (2 << 1)
341 #define Q_TYPE_FSTN (3 << 1)
342
343
344 #define QH_NEXT(ehci, dma) \
345 (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
346
347
348 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1)
349
350
351
352
353
354
355
356
357
358 union ehci_shadow {
359 struct ehci_qh *qh;
360 struct ehci_itd *itd;
361 struct ehci_sitd *sitd;
362 struct ehci_fstn *fstn;
363 __hc32 *hw_next;
364 void *ptr;
365 };
366
367
368
369
370
371
372
373
374
375
376
377
378 struct ehci_qh_hw {
379 __hc32 hw_next;
380 __hc32 hw_info1;
381 #define QH_CONTROL_EP (1 << 27)
382 #define QH_HEAD (1 << 15)
383 #define QH_TOGGLE_CTL (1 << 14)
384 #define QH_HIGH_SPEED (2 << 12)
385 #define QH_LOW_SPEED (1 << 12)
386 #define QH_FULL_SPEED (0 << 12)
387 #define QH_INACTIVATE (1 << 7)
388 __hc32 hw_info2;
389 #define QH_SMASK 0x000000ff
390 #define QH_CMASK 0x0000ff00
391 #define QH_HUBADDR 0x007f0000
392 #define QH_HUBPORT 0x3f800000
393 #define QH_MULT 0xc0000000
394 __hc32 hw_current;
395
396
397 __hc32 hw_qtd_next;
398 __hc32 hw_alt_next;
399 __hc32 hw_token;
400 __hc32 hw_buf[5];
401 __hc32 hw_buf_hi[5];
402 } __aligned(32);
403
404 struct ehci_qh {
405 struct ehci_qh_hw *hw;
406
407 dma_addr_t qh_dma;
408 union ehci_shadow qh_next;
409 struct list_head qtd_list;
410 struct list_head intr_node;
411 struct ehci_qtd *dummy;
412 struct list_head unlink_node;
413 struct ehci_per_sched ps;
414
415 unsigned unlink_cycle;
416
417 u8 qh_state;
418 #define QH_STATE_LINKED 1
419 #define QH_STATE_UNLINK 2
420 #define QH_STATE_IDLE 3
421 #define QH_STATE_UNLINK_WAIT 4
422 #define QH_STATE_COMPLETING 5
423
424 u8 xacterrs;
425 #define QH_XACTERR_MAX 32
426
427 u8 unlink_reason;
428 #define QH_UNLINK_HALTED 0x01
429 #define QH_UNLINK_SHORT_READ 0x02
430 #define QH_UNLINK_DUMMY_OVERLAY 0x04
431 #define QH_UNLINK_SHUTDOWN 0x08
432 #define QH_UNLINK_QUEUE_EMPTY 0x10
433 #define QH_UNLINK_REQUESTED 0x20
434
435 u8 gap_uf;
436
437 unsigned is_out:1;
438 unsigned clearing_tt:1;
439 unsigned dequeue_during_giveback:1;
440 unsigned should_be_inactive:1;
441 };
442
443
444
445
446 struct ehci_iso_packet {
447
448 u64 bufp;
449 __hc32 transaction;
450 u8 cross;
451
452 u32 buf1;
453 };
454
455
456
457
458
459 struct ehci_iso_sched {
460 struct list_head td_list;
461 unsigned span;
462 unsigned first_packet;
463 struct ehci_iso_packet packet[0];
464 };
465
466
467
468
469
470 struct ehci_iso_stream {
471
472 struct ehci_qh_hw *hw;
473
474 u8 bEndpointAddress;
475 u8 highspeed;
476 struct list_head td_list;
477 struct list_head free_list;
478
479
480 struct ehci_per_sched ps;
481 unsigned next_uframe;
482 __hc32 splits;
483
484
485
486
487 u16 uperiod;
488 u16 maxp;
489 unsigned bandwidth;
490
491
492 __hc32 buf0;
493 __hc32 buf1;
494 __hc32 buf2;
495
496
497 __hc32 address;
498 };
499
500
501
502
503
504
505
506
507
508 struct ehci_itd {
509
510 __hc32 hw_next;
511 __hc32 hw_transaction[8];
512 #define EHCI_ISOC_ACTIVE (1<<31)
513 #define EHCI_ISOC_BUF_ERR (1<<30)
514 #define EHCI_ISOC_BABBLE (1<<29)
515 #define EHCI_ISOC_XACTERR (1<<28)
516 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
517 #define EHCI_ITD_IOC (1 << 15)
518
519 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
520
521 __hc32 hw_bufp[7];
522 __hc32 hw_bufp_hi[7];
523
524
525 dma_addr_t itd_dma;
526 union ehci_shadow itd_next;
527
528 struct urb *urb;
529 struct ehci_iso_stream *stream;
530 struct list_head itd_list;
531
532
533 unsigned frame;
534 unsigned pg;
535 unsigned index[8];
536 } __aligned(32);
537
538
539
540
541
542
543
544
545
546 struct ehci_sitd {
547
548 __hc32 hw_next;
549
550 __hc32 hw_fullspeed_ep;
551 __hc32 hw_uframe;
552 __hc32 hw_results;
553 #define SITD_IOC (1 << 31)
554 #define SITD_PAGE (1 << 30)
555 #define SITD_LENGTH(x) (((x) >> 16) & 0x3ff)
556 #define SITD_STS_ACTIVE (1 << 7)
557 #define SITD_STS_ERR (1 << 6)
558 #define SITD_STS_DBE (1 << 5)
559 #define SITD_STS_BABBLE (1 << 4)
560 #define SITD_STS_XACT (1 << 3)
561 #define SITD_STS_MMF (1 << 2)
562 #define SITD_STS_STS (1 << 1)
563
564 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
565
566 __hc32 hw_buf[2];
567 __hc32 hw_backpointer;
568 __hc32 hw_buf_hi[2];
569
570
571 dma_addr_t sitd_dma;
572 union ehci_shadow sitd_next;
573
574 struct urb *urb;
575 struct ehci_iso_stream *stream;
576 struct list_head sitd_list;
577 unsigned frame;
578 unsigned index;
579 } __aligned(32);
580
581
582
583
584
585
586
587
588
589
590
591
592 struct ehci_fstn {
593 __hc32 hw_next;
594 __hc32 hw_prev;
595
596
597 dma_addr_t fstn_dma;
598 union ehci_shadow fstn_next;
599 } __aligned(32);
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621 struct ehci_tt {
622 u16 bandwidth[EHCI_BANDWIDTH_FRAMES];
623
624 struct list_head tt_list;
625 struct list_head ps_list;
626 struct usb_tt *usb_tt;
627 int tt_port;
628 };
629
630
631
632
633
634 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
635 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
636
637 #define ehci_prepare_ports_for_controller_resume(ehci) \
638 ehci_adjust_port_wakeup_flags(ehci, false, false)
639
640
641
642 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
643
644
645
646
647
648
649
650
651 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
652
653
654 static inline unsigned int
655 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
656 {
657 if (ehci_is_TDI(ehci)) {
658 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
659 case 0:
660 return 0;
661 case 1:
662 return USB_PORT_STAT_LOW_SPEED;
663 case 2:
664 default:
665 return USB_PORT_STAT_HIGH_SPEED;
666 }
667 }
668 return USB_PORT_STAT_HIGH_SPEED;
669 }
670
671 #else
672
673 #define ehci_is_TDI(e) (0)
674
675 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
676 #endif
677
678
679
680 #ifdef CONFIG_PPC_83xx
681
682
683
684 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
685 #else
686 #define ehci_has_fsl_portno_bug(e) (0)
687 #endif
688
689 #define PORTSC_FSL_PFSC 24
690
691 #if defined(CONFIG_PPC_85xx)
692
693
694
695 #define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata)
696 #else
697 #define ehci_has_fsl_hs_errata(e) (0)
698 #endif
699
700
701
702
703
704
705 #define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata)
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
722 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
723 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
724 #else
725 #define ehci_big_endian_mmio(e) 0
726 #define ehci_big_endian_capbase(e) 0
727 #endif
728
729
730
731
732
733 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
734 #define readl_be(addr) __raw_readl((__force unsigned *)addr)
735 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
736 #endif
737
738 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
739 __u32 __iomem *regs)
740 {
741 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
742 return ehci_big_endian_mmio(ehci) ?
743 readl_be(regs) :
744 readl(regs);
745 #else
746 return readl(regs);
747 #endif
748 }
749
750 #ifdef CONFIG_SOC_IMX28
751 static inline void imx28_ehci_writel(const unsigned int val,
752 volatile __u32 __iomem *addr)
753 {
754 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
755 }
756 #else
757 static inline void imx28_ehci_writel(const unsigned int val,
758 volatile __u32 __iomem *addr)
759 {
760 }
761 #endif
762 static inline void ehci_writel(const struct ehci_hcd *ehci,
763 const unsigned int val, __u32 __iomem *regs)
764 {
765 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
766 ehci_big_endian_mmio(ehci) ?
767 writel_be(val, regs) :
768 writel(val, regs);
769 #else
770 if (ehci->imx28_write_fix)
771 imx28_ehci_writel(val, regs);
772 else
773 writel(val, regs);
774 #endif
775 }
776
777
778
779
780
781
782 #ifdef CONFIG_44x
783 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
784 {
785 u32 hc_control;
786
787 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
788 if (operational)
789 hc_control |= OHCI_USB_OPER;
790 else
791 hc_control |= OHCI_USB_SUSPEND;
792
793 writel_be(hc_control, ehci->ohci_hcctrl_reg);
794 (void) readl_be(ehci->ohci_hcctrl_reg);
795 }
796 #else
797 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
798 { }
799 #endif
800
801
802
803
804
805
806
807
808
809
810 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
811 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
812
813
814 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
815 {
816 return ehci_big_endian_desc(ehci)
817 ? (__force __hc32)cpu_to_be32(x)
818 : (__force __hc32)cpu_to_le32(x);
819 }
820
821
822 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
823 {
824 return ehci_big_endian_desc(ehci)
825 ? be32_to_cpu((__force __be32)x)
826 : le32_to_cpu((__force __le32)x);
827 }
828
829 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
830 {
831 return ehci_big_endian_desc(ehci)
832 ? be32_to_cpup((__force __be32 *)x)
833 : le32_to_cpup((__force __le32 *)x);
834 }
835
836 #else
837
838
839 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
840 {
841 return cpu_to_le32(x);
842 }
843
844
845 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
846 {
847 return le32_to_cpu(x);
848 }
849
850 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
851 {
852 return le32_to_cpup(x);
853 }
854
855 #endif
856
857
858
859 #define ehci_dbg(ehci, fmt, args...) \
860 dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
861 #define ehci_err(ehci, fmt, args...) \
862 dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
863 #define ehci_info(ehci, fmt, args...) \
864 dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
865 #define ehci_warn(ehci, fmt, args...) \
866 dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
867
868
869
870
871
872 struct ehci_driver_overrides {
873 size_t extra_priv_size;
874 int (*reset)(struct usb_hcd *hcd);
875 int (*port_power)(struct usb_hcd *hcd,
876 int portnum, bool enable);
877 };
878
879 extern void ehci_init_driver(struct hc_driver *drv,
880 const struct ehci_driver_overrides *over);
881 extern int ehci_setup(struct usb_hcd *hcd);
882 extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
883 u32 mask, u32 done, int usec);
884 extern int ehci_reset(struct ehci_hcd *ehci);
885
886 extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
887 extern int ehci_resume(struct usb_hcd *hcd, bool force_reset);
888 extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
889 bool suspending, bool do_wakeup);
890
891 extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
892 u16 wIndex, char *buf, u16 wLength);
893
894 #endif