drivers/usb/mtu3/mtu3

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This source file includes following definitions.
ep_fifo_alloc
ep_fifo_free
mtu3_ss_func_set
mtu3_hs_softconn_set
mtu3_device_enable
mtu3_device_disable
mtu3_device_reset
mtu3_intr_disable
mtu3_intr_status_clear
mtu3_intr_enable
mtu3_ep_reset
mtu3_ep_stall_set
mtu3_dev_on_off
mtu3_start
mtu3_stop
mtu3_config_ep
mtu3_deconfig_ep
get_ep_fifo_config
mtu3_ep0_setup
mtu3_mem_alloc
mtu3_mem_free
mtu3_set_speed
mtu3_regs_init
mtu3_link_isr
mtu3_u3_ltssm_isr
mtu3_u2_common_isr
mtu3_irq
mtu3_hw_init
mtu3_hw_exit
mtu3_set_dma_mask
ssusb_gadget_init
ssusb_gadget_exit
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * mtu3_core.c - hardware access layer and gadget init/exit of
   4  *                     MediaTek usb3 Dual-Role Controller Driver
   5  *
   6  * Copyright (C) 2016 MediaTek Inc.
   7  *
   8  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
   9  */
  10 
  11 #include <linux/dma-mapping.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_irq.h>
  16 #include <linux/platform_device.h>
  17 
  18 #include "mtu3.h"
  19 #include "mtu3_dr.h"
  20 #include "mtu3_debug.h"
  21 #include "mtu3_trace.h"
  22 
  23 static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
  24 {
  25         struct mtu3_fifo_info *fifo = mep->fifo;
  26         u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT);
  27         u32 start_bit;
  28 
  29         /* ensure that @mep->fifo_seg_size is power of two */
  30         num_bits = roundup_pow_of_two(num_bits);
  31         if (num_bits > fifo->limit)
  32                 return -EINVAL;
  33 
  34         mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT;
  35         num_bits = num_bits * (mep->slot + 1);
  36         start_bit = bitmap_find_next_zero_area(fifo->bitmap,
  37                         fifo->limit, 0, num_bits, 0);
  38         if (start_bit >= fifo->limit)
  39                 return -EOVERFLOW;
  40 
  41         bitmap_set(fifo->bitmap, start_bit, num_bits);
  42         mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT;
  43         mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit;
  44 
  45         dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n",
  46                 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
  47 
  48         return mep->fifo_addr;
  49 }
  50 
  51 static void ep_fifo_free(struct mtu3_ep *mep)
  52 {
  53         struct mtu3_fifo_info *fifo = mep->fifo;
  54         u32 addr = mep->fifo_addr;
  55         u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT;
  56         u32 start_bit;
  57 
  58         if (unlikely(addr < fifo->base || bits > fifo->limit))
  59                 return;
  60 
  61         start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT;
  62         bitmap_clear(fifo->bitmap, start_bit, bits);
  63         mep->fifo_size = 0;
  64         mep->fifo_seg_size = 0;
  65 
  66         dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n",
  67                 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
  68 }
  69 
  70 /* enable/disable U3D SS function */
  71 static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
  72 {
  73         /* If usb3_en==0, LTSSM will go to SS.Disable state */
  74         if (enable)
  75                 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
  76         else
  77                 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
  78 
  79         dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
  80 }
  81 
  82 /* set/clear U3D HS device soft connect */
  83 static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
  84 {
  85         if (enable) {
  86                 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
  87                         SOFT_CONN | SUSPENDM_ENABLE);
  88         } else {
  89                 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
  90                         SOFT_CONN | SUSPENDM_ENABLE);
  91         }
  92         dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
  93 }
  94 
  95 /* only port0 of U2/U3 supports device mode */
  96 static int mtu3_device_enable(struct mtu3 *mtu)
  97 {
  98         void __iomem *ibase = mtu->ippc_base;
  99         u32 check_clk = 0;
 100 
 101         mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
 102 
 103         if (mtu->is_u3_ip) {
 104                 check_clk = SSUSB_U3_MAC_RST_B_STS;
 105                 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
 106                         (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
 107                         SSUSB_U3_PORT_HOST_SEL));
 108         }
 109         mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
 110                 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
 111                 SSUSB_U2_PORT_HOST_SEL));
 112 
 113         if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
 114                 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
 115                 if (mtu->is_u3_ip)
 116                         mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
 117                                      SSUSB_U3_PORT_DUAL_MODE);
 118         }
 119 
 120         return ssusb_check_clocks(mtu->ssusb, check_clk);
 121 }
 122 
 123 static void mtu3_device_disable(struct mtu3 *mtu)
 124 {
 125         void __iomem *ibase = mtu->ippc_base;
 126 
 127         if (mtu->is_u3_ip)
 128                 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
 129                         (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
 130 
 131         mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
 132                 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
 133 
 134         if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
 135                 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
 136 
 137         mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
 138 }
 139 
 140 /* reset U3D's device module. */
 141 static void mtu3_device_reset(struct mtu3 *mtu)
 142 {
 143         void __iomem *ibase = mtu->ippc_base;
 144 
 145         mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
 146         udelay(1);
 147         mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
 148 }
 149 
 150 /* disable all interrupts */
 151 static void mtu3_intr_disable(struct mtu3 *mtu)
 152 {
 153         void __iomem *mbase = mtu->mac_base;
 154 
 155         /* Disable level 1 interrupts */
 156         mtu3_writel(mbase, U3D_LV1IECR, ~0x0);
 157         /* Disable endpoint interrupts */
 158         mtu3_writel(mbase, U3D_EPIECR, ~0x0);
 159 }
 160 
 161 static void mtu3_intr_status_clear(struct mtu3 *mtu)
 162 {
 163         void __iomem *mbase = mtu->mac_base;
 164 
 165         /* Clear EP0 and Tx/Rx EPn interrupts status */
 166         mtu3_writel(mbase, U3D_EPISR, ~0x0);
 167         /* Clear U2 USB common interrupts status */
 168         mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
 169         /* Clear U3 LTSSM interrupts status */
 170         mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
 171         /* Clear speed change interrupt status */
 172         mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
 173 }
 174 
 175 /* enable system global interrupt */
 176 static void mtu3_intr_enable(struct mtu3 *mtu)
 177 {
 178         void __iomem *mbase = mtu->mac_base;
 179         u32 value;
 180 
 181         /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */
 182         value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
 183         mtu3_writel(mbase, U3D_LV1IESR, value);
 184 
 185         /* Enable U2 common USB interrupts */
 186         value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
 187         mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
 188 
 189         if (mtu->is_u3_ip) {
 190                 /* Enable U3 LTSSM interrupts */
 191                 value = HOT_RST_INTR | WARM_RST_INTR |
 192                         ENTER_U3_INTR | EXIT_U3_INTR;
 193                 mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
 194         }
 195 
 196         /* Enable QMU interrupts. */
 197         value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
 198                         RXQ_LENERR_INT | RXQ_ZLPERR_INT;
 199         mtu3_writel(mbase, U3D_QIESR1, value);
 200 
 201         /* Enable speed change interrupt */
 202         mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
 203 }
 204 
 205 /* reset: u2 - data toggle, u3 - SeqN, flow control status etc */
 206 static void mtu3_ep_reset(struct mtu3_ep *mep)
 207 {
 208         struct mtu3 *mtu = mep->mtu;
 209         u32 rst_bit = EP_RST(mep->is_in, mep->epnum);
 210 
 211         mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit);
 212         mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit);
 213 }
 214 
 215 /* set/clear the stall and toggle bits for non-ep0 */
 216 void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
 217 {
 218         struct mtu3 *mtu = mep->mtu;
 219         void __iomem *mbase = mtu->mac_base;
 220         u8 epnum = mep->epnum;
 221         u32 csr;
 222 
 223         if (mep->is_in) {       /* TX */
 224                 csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
 225                 if (set)
 226                         csr |= TX_SENDSTALL;
 227                 else
 228                         csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
 229                 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
 230         } else {        /* RX */
 231                 csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
 232                 if (set)
 233                         csr |= RX_SENDSTALL;
 234                 else
 235                         csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
 236                 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
 237         }
 238 
 239         if (!set) {
 240                 mtu3_ep_reset(mep);
 241                 mep->flags &= ~MTU3_EP_STALL;
 242         } else {
 243                 mep->flags |= MTU3_EP_STALL;
 244         }
 245 
 246         dev_dbg(mtu->dev, "%s: %s\n", mep->name,
 247                 set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
 248 }
 249 
 250 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
 251 {
 252         if (mtu->is_u3_ip && mtu->max_speed >= USB_SPEED_SUPER)
 253                 mtu3_ss_func_set(mtu, is_on);
 254         else
 255                 mtu3_hs_softconn_set(mtu, is_on);
 256 
 257         dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
 258                 usb_speed_string(mtu->max_speed), is_on ? "+" : "-");
 259 }
 260 
 261 void mtu3_start(struct mtu3 *mtu)
 262 {
 263         void __iomem *mbase = mtu->mac_base;
 264 
 265         dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
 266                 mtu3_readl(mbase, U3D_DEVICE_CONTROL));
 267 
 268         mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
 269 
 270         /*
 271          * When disable U2 port, USB2_CSR's register will be reset to
 272          * default value after re-enable it again(HS is enabled by default).
 273          * So if force mac to work as FS, disable HS function.
 274          */
 275         if (mtu->max_speed == USB_SPEED_FULL)
 276                 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
 277 
 278         /* Initialize the default interrupts */
 279         mtu3_intr_enable(mtu);
 280         mtu->is_active = 1;
 281 
 282         if (mtu->softconnect)
 283                 mtu3_dev_on_off(mtu, 1);
 284 }
 285 
 286 void mtu3_stop(struct mtu3 *mtu)
 287 {
 288         dev_dbg(mtu->dev, "%s\n", __func__);
 289 
 290         mtu3_intr_disable(mtu);
 291         mtu3_intr_status_clear(mtu);
 292 
 293         if (mtu->softconnect)
 294                 mtu3_dev_on_off(mtu, 0);
 295 
 296         mtu->is_active = 0;
 297         mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
 298 }
 299 
 300 /* for non-ep0 */
 301 int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
 302                         int interval, int burst, int mult)
 303 {
 304         void __iomem *mbase = mtu->mac_base;
 305         bool gen2cp = mtu->gen2cp;
 306         int epnum = mep->epnum;
 307         u32 csr0, csr1, csr2;
 308         int fifo_sgsz, fifo_addr;
 309         int num_pkts;
 310 
 311         fifo_addr = ep_fifo_alloc(mep, mep->maxp);
 312         if (fifo_addr < 0) {
 313                 dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
 314                 return -ENOMEM;
 315         }
 316         fifo_sgsz = ilog2(mep->fifo_seg_size);
 317         dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
 318                 mep->fifo_seg_size, mep->fifo_size);
 319 
 320         if (mep->is_in) {
 321                 csr0 = TX_TXMAXPKTSZ(mep->maxp);
 322                 csr0 |= TX_DMAREQEN;
 323 
 324                 num_pkts = (burst + 1) * (mult + 1) - 1;
 325                 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
 326                 csr1 |= TX_MAX_PKT(gen2cp, num_pkts) | TX_MULT(gen2cp, mult);
 327 
 328                 csr2 = TX_FIFOADDR(fifo_addr >> 4);
 329                 csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
 330 
 331                 switch (mep->type) {
 332                 case USB_ENDPOINT_XFER_BULK:
 333                         csr1 |= TX_TYPE(TYPE_BULK);
 334                         break;
 335                 case USB_ENDPOINT_XFER_ISOC:
 336                         csr1 |= TX_TYPE(TYPE_ISO);
 337                         csr2 |= TX_BINTERVAL(interval);
 338                         break;
 339                 case USB_ENDPOINT_XFER_INT:
 340                         csr1 |= TX_TYPE(TYPE_INT);
 341                         csr2 |= TX_BINTERVAL(interval);
 342                         break;
 343                 }
 344 
 345                 /* Enable QMU Done interrupt */
 346                 mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
 347 
 348                 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
 349                 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
 350                 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
 351 
 352                 dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
 353                         epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
 354                         mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
 355                         mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
 356         } else {
 357                 csr0 = RX_RXMAXPKTSZ(mep->maxp);
 358                 csr0 |= RX_DMAREQEN;
 359 
 360                 num_pkts = (burst + 1) * (mult + 1) - 1;
 361                 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
 362                 csr1 |= RX_MAX_PKT(gen2cp, num_pkts) | RX_MULT(gen2cp, mult);
 363 
 364                 csr2 = RX_FIFOADDR(fifo_addr >> 4);
 365                 csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
 366 
 367                 switch (mep->type) {
 368                 case USB_ENDPOINT_XFER_BULK:
 369                         csr1 |= RX_TYPE(TYPE_BULK);
 370                         break;
 371                 case USB_ENDPOINT_XFER_ISOC:
 372                         csr1 |= RX_TYPE(TYPE_ISO);
 373                         csr2 |= RX_BINTERVAL(interval);
 374                         break;
 375                 case USB_ENDPOINT_XFER_INT:
 376                         csr1 |= RX_TYPE(TYPE_INT);
 377                         csr2 |= RX_BINTERVAL(interval);
 378                         break;
 379                 }
 380 
 381                 /*Enable QMU Done interrupt */
 382                 mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
 383 
 384                 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
 385                 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
 386                 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
 387 
 388                 dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
 389                         epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
 390                         mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
 391                         mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
 392         }
 393 
 394         dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
 395         dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
 396                 __func__, mep->name, mep->fifo_addr, mep->fifo_size,
 397                 fifo_sgsz, mep->fifo_seg_size);
 398 
 399         return 0;
 400 }
 401 
 402 /* for non-ep0 */
 403 void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
 404 {
 405         void __iomem *mbase = mtu->mac_base;
 406         int epnum = mep->epnum;
 407 
 408         if (mep->is_in) {
 409                 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
 410                 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
 411                 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
 412                 mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
 413         } else {
 414                 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
 415                 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
 416                 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
 417                 mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
 418         }
 419 
 420         mtu3_ep_reset(mep);
 421         ep_fifo_free(mep);
 422 
 423         dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
 424 }
 425 
 426 /*
 427  * Two scenarios:
 428  * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs
 429  *      are separated;
 430  * 2. when supports only HS, the fifo is shared for all EPs, and
 431  *      the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate
 432  *      the total fifo size of non-ep0, and ep0's is fixed to 64B,
 433  *      so the total fifo size is 64B + @EPNTXFFSZ;
 434  *      Due to the first 64B should be reserved for EP0, non-ep0's fifo
 435  *      starts from offset 64 and are divided into two equal parts for
 436  *      TX or RX EPs for simplification.
 437  */
 438 static void get_ep_fifo_config(struct mtu3 *mtu)
 439 {
 440         struct mtu3_fifo_info *tx_fifo;
 441         struct mtu3_fifo_info *rx_fifo;
 442         u32 fifosize;
 443 
 444         if (mtu->is_u3_ip) {
 445                 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
 446                 tx_fifo = &mtu->tx_fifo;
 447                 tx_fifo->base = 0;
 448                 tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
 449                 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
 450 
 451                 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
 452                 rx_fifo = &mtu->rx_fifo;
 453                 rx_fifo->base = 0;
 454                 rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
 455                 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
 456                 mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
 457         } else {
 458                 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
 459                 tx_fifo = &mtu->tx_fifo;
 460                 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
 461                 tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1;
 462                 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
 463 
 464                 rx_fifo = &mtu->rx_fifo;
 465                 rx_fifo->base =
 466                         tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT;
 467                 rx_fifo->limit = tx_fifo->limit;
 468                 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
 469                 mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
 470         }
 471 
 472         dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
 473                 __func__, tx_fifo->base, tx_fifo->limit,
 474                 rx_fifo->base, rx_fifo->limit);
 475 }
 476 
 477 void mtu3_ep0_setup(struct mtu3 *mtu)
 478 {
 479         u32 maxpacket = mtu->g.ep0->maxpacket;
 480         u32 csr;
 481 
 482         dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
 483 
 484         csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
 485         csr &= ~EP0_MAXPKTSZ_MSK;
 486         csr |= EP0_MAXPKTSZ(maxpacket);
 487         csr &= EP0_W1C_BITS;
 488         mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
 489 
 490         /* Enable EP0 interrupt */
 491         mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR | SETUPENDISR);
 492 }
 493 
 494 static int mtu3_mem_alloc(struct mtu3 *mtu)
 495 {
 496         void __iomem *mbase = mtu->mac_base;
 497         struct mtu3_ep *ep_array;
 498         int in_ep_num, out_ep_num;
 499         u32 cap_epinfo;
 500         int ret;
 501         int i;
 502 
 503         cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
 504         in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
 505         out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
 506 
 507         dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
 508                  mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
 509                  mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
 510 
 511         /* one for ep0, another is reserved */
 512         mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
 513         ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
 514         if (ep_array == NULL)
 515                 return -ENOMEM;
 516 
 517         mtu->ep_array = ep_array;
 518         mtu->in_eps = ep_array;
 519         mtu->out_eps = &ep_array[mtu->num_eps];
 520         /* ep0 uses in_eps[0], out_eps[0] is reserved */
 521         mtu->ep0 = mtu->in_eps;
 522         mtu->ep0->mtu = mtu;
 523         mtu->ep0->epnum = 0;
 524 
 525         for (i = 1; i < mtu->num_eps; i++) {
 526                 struct mtu3_ep *mep = mtu->in_eps + i;
 527 
 528                 mep->fifo = &mtu->tx_fifo;
 529                 mep = mtu->out_eps + i;
 530                 mep->fifo = &mtu->rx_fifo;
 531         }
 532 
 533         get_ep_fifo_config(mtu);
 534 
 535         ret = mtu3_qmu_init(mtu);
 536         if (ret)
 537                 kfree(mtu->ep_array);
 538 
 539         return ret;
 540 }
 541 
 542 static void mtu3_mem_free(struct mtu3 *mtu)
 543 {
 544         mtu3_qmu_exit(mtu);
 545         kfree(mtu->ep_array);
 546 }
 547 
 548 static void mtu3_set_speed(struct mtu3 *mtu)
 549 {
 550         void __iomem *mbase = mtu->mac_base;
 551 
 552         if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
 553                 mtu->max_speed = USB_SPEED_HIGH;
 554 
 555         if (mtu->max_speed == USB_SPEED_FULL) {
 556                 /* disable U3 SS function */
 557                 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
 558                 /* disable HS function */
 559                 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
 560         } else if (mtu->max_speed == USB_SPEED_HIGH) {
 561                 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
 562                 /* HS/FS detected by HW */
 563                 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
 564         } else if (mtu->max_speed == USB_SPEED_SUPER) {
 565                 mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
 566                              SSUSB_U3_PORT_SSP_SPEED);
 567         }
 568 
 569         dev_info(mtu->dev, "max_speed: %s\n",
 570                 usb_speed_string(mtu->max_speed));
 571 }
 572 
 573 static void mtu3_regs_init(struct mtu3 *mtu)
 574 {
 575 
 576         void __iomem *mbase = mtu->mac_base;
 577 
 578         /* be sure interrupts are disabled before registration of ISR */
 579         mtu3_intr_disable(mtu);
 580         mtu3_intr_status_clear(mtu);
 581 
 582         if (mtu->is_u3_ip) {
 583                 /* disable LGO_U1/U2 by default */
 584                 mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
 585                                 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
 586                 /* enable accept LGO_U1/U2 link command from host */
 587                 mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
 588                                 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE);
 589                 /* device responses to u3_exit from host automatically */
 590                 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
 591                 /* automatically build U2 link when U3 detect fail */
 592                 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
 593                 /* auto clear SOFT_CONN when clear USB3_EN if work as HS */
 594                 mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
 595         }
 596 
 597         mtu3_set_speed(mtu);
 598 
 599         /* delay about 0.1us from detecting reset to send chirp-K */
 600         mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
 601         /* U2/U3 detected by HW */
 602         mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
 603         /* vbus detected by HW */
 604         mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
 605         /* enable automatical HWRW from L1 */
 606         mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE);
 607 
 608         /* use new QMU format when HW version >= 0x1003 */
 609         if (mtu->gen2cp)
 610                 mtu3_writel(mbase, U3D_QFCR, ~0x0);
 611 }
 612 
 613 static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
 614 {
 615         void __iomem *mbase = mtu->mac_base;
 616         enum usb_device_speed udev_speed;
 617         u32 maxpkt = 64;
 618         u32 link;
 619         u32 speed;
 620 
 621         link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
 622         link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
 623         mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */
 624         dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
 625 
 626         if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
 627                 return IRQ_NONE;
 628 
 629         speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
 630 
 631         switch (speed) {
 632         case MTU3_SPEED_FULL:
 633                 udev_speed = USB_SPEED_FULL;
 634                 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
 635                 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
 636                                 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
 637                 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
 638                                 LPM_BESL_STALL | LPM_BESLD_STALL);
 639                 break;
 640         case MTU3_SPEED_HIGH:
 641                 udev_speed = USB_SPEED_HIGH;
 642                 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
 643                 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
 644                                 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
 645                 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
 646                                 LPM_BESL_STALL | LPM_BESLD_STALL);
 647                 break;
 648         case MTU3_SPEED_SUPER:
 649                 udev_speed = USB_SPEED_SUPER;
 650                 maxpkt = 512;
 651                 break;
 652         case MTU3_SPEED_SUPER_PLUS:
 653                 udev_speed = USB_SPEED_SUPER_PLUS;
 654                 maxpkt = 512;
 655                 break;
 656         default:
 657                 udev_speed = USB_SPEED_UNKNOWN;
 658                 break;
 659         }
 660         dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
 661         mtu3_dbg_trace(mtu->dev, "link speed %s",
 662                        usb_speed_string(udev_speed));
 663 
 664         mtu->g.speed = udev_speed;
 665         mtu->g.ep0->maxpacket = maxpkt;
 666         mtu->ep0_state = MU3D_EP0_STATE_SETUP;
 667 
 668         if (udev_speed == USB_SPEED_UNKNOWN)
 669                 mtu3_gadget_disconnect(mtu);
 670         else
 671                 mtu3_ep0_setup(mtu);
 672 
 673         return IRQ_HANDLED;
 674 }
 675 
 676 static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
 677 {
 678         void __iomem *mbase = mtu->mac_base;
 679         u32 ltssm;
 680 
 681         ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
 682         ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
 683         mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
 684         dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
 685         trace_mtu3_u3_ltssm_isr(ltssm);
 686 
 687         if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
 688                 mtu3_gadget_reset(mtu);
 689 
 690         if (ltssm & VBUS_FALL_INTR) {
 691                 mtu3_ss_func_set(mtu, false);
 692                 mtu3_gadget_reset(mtu);
 693         }
 694 
 695         if (ltssm & VBUS_RISE_INTR)
 696                 mtu3_ss_func_set(mtu, true);
 697 
 698         if (ltssm & EXIT_U3_INTR)
 699                 mtu3_gadget_resume(mtu);
 700 
 701         if (ltssm & ENTER_U3_INTR)
 702                 mtu3_gadget_suspend(mtu);
 703 
 704         return IRQ_HANDLED;
 705 }
 706 
 707 static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
 708 {
 709         void __iomem *mbase = mtu->mac_base;
 710         u32 u2comm;
 711 
 712         u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
 713         u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
 714         mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
 715         dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
 716         trace_mtu3_u2_common_isr(u2comm);
 717 
 718         if (u2comm & SUSPEND_INTR)
 719                 mtu3_gadget_suspend(mtu);
 720 
 721         if (u2comm & RESUME_INTR)
 722                 mtu3_gadget_resume(mtu);
 723 
 724         if (u2comm & RESET_INTR)
 725                 mtu3_gadget_reset(mtu);
 726 
 727         return IRQ_HANDLED;
 728 }
 729 
 730 static irqreturn_t mtu3_irq(int irq, void *data)
 731 {
 732         struct mtu3 *mtu = (struct mtu3 *)data;
 733         unsigned long flags;
 734         u32 level1;
 735 
 736         spin_lock_irqsave(&mtu->lock, flags);
 737 
 738         /* U3D_LV1ISR is RU */
 739         level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
 740         level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
 741 
 742         if (level1 & EP_CTRL_INTR)
 743                 mtu3_link_isr(mtu);
 744 
 745         if (level1 & MAC2_INTR)
 746                 mtu3_u2_common_isr(mtu);
 747 
 748         if (level1 & MAC3_INTR)
 749                 mtu3_u3_ltssm_isr(mtu);
 750 
 751         if (level1 & BMU_INTR)
 752                 mtu3_ep0_isr(mtu);
 753 
 754         if (level1 & QMU_INTR)
 755                 mtu3_qmu_isr(mtu);
 756 
 757         spin_unlock_irqrestore(&mtu->lock, flags);
 758 
 759         return IRQ_HANDLED;
 760 }
 761 
 762 static int mtu3_hw_init(struct mtu3 *mtu)
 763 {
 764         u32 value;
 765         int ret;
 766 
 767         value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_TRUNK_VERS);
 768         mtu->hw_version = IP_TRUNK_VERS(value);
 769         mtu->gen2cp = !!(mtu->hw_version >= MTU3_TRUNK_VERS_1003);
 770 
 771         value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
 772         mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(value);
 773 
 774         dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
 775                 mtu->is_u3_ip ? "U3" : "U2");
 776 
 777         mtu3_device_reset(mtu);
 778 
 779         ret = mtu3_device_enable(mtu);
 780         if (ret) {
 781                 dev_err(mtu->dev, "device enable failed %d\n", ret);
 782                 return ret;
 783         }
 784 
 785         ret = mtu3_mem_alloc(mtu);
 786         if (ret)
 787                 return -ENOMEM;
 788 
 789         mtu3_regs_init(mtu);
 790 
 791         return 0;
 792 }
 793 
 794 static void mtu3_hw_exit(struct mtu3 *mtu)
 795 {
 796         mtu3_device_disable(mtu);
 797         mtu3_mem_free(mtu);
 798 }
 799 
 800 /**
 801  * we set 32-bit DMA mask by default, here check whether the controller
 802  * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
 803  */
 804 static int mtu3_set_dma_mask(struct mtu3 *mtu)
 805 {
 806         struct device *dev = mtu->dev;
 807         bool is_36bit = false;
 808         int ret = 0;
 809         u32 value;
 810 
 811         value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
 812         if (value & DMA_ADDR_36BIT) {
 813                 is_36bit = true;
 814                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
 815                 /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
 816                 if (ret) {
 817                         is_36bit = false;
 818                         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
 819                 }
 820         }
 821         dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
 822 
 823         return ret;
 824 }
 825 
 826 int ssusb_gadget_init(struct ssusb_mtk *ssusb)
 827 {
 828         struct device *dev = ssusb->dev;
 829         struct platform_device *pdev = to_platform_device(dev);
 830         struct mtu3 *mtu = NULL;
 831         struct resource *res;
 832         int ret = -ENOMEM;
 833 
 834         mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
 835         if (mtu == NULL)
 836                 return -ENOMEM;
 837 
 838         mtu->irq = platform_get_irq(pdev, 0);
 839         if (mtu->irq < 0)
 840                 return mtu->irq;
 841         dev_info(dev, "irq %d\n", mtu->irq);
 842 
 843         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
 844         mtu->mac_base = devm_ioremap_resource(dev, res);
 845         if (IS_ERR(mtu->mac_base)) {
 846                 dev_err(dev, "error mapping memory for dev mac\n");
 847                 return PTR_ERR(mtu->mac_base);
 848         }
 849 
 850         spin_lock_init(&mtu->lock);
 851         mtu->dev = dev;
 852         mtu->ippc_base = ssusb->ippc_base;
 853         ssusb->mac_base = mtu->mac_base;
 854         ssusb->u3d = mtu;
 855         mtu->ssusb = ssusb;
 856         mtu->max_speed = usb_get_maximum_speed(dev);
 857 
 858         /* check the max_speed parameter */
 859         switch (mtu->max_speed) {
 860         case USB_SPEED_FULL:
 861         case USB_SPEED_HIGH:
 862         case USB_SPEED_SUPER:
 863         case USB_SPEED_SUPER_PLUS:
 864                 break;
 865         default:
 866                 dev_err(dev, "invalid max_speed: %s\n",
 867                         usb_speed_string(mtu->max_speed));
 868                 /* fall through */
 869         case USB_SPEED_UNKNOWN:
 870                 /* default as SSP */
 871                 mtu->max_speed = USB_SPEED_SUPER_PLUS;
 872                 break;
 873         }
 874 
 875         dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
 876                 mtu->mac_base, mtu->ippc_base);
 877 
 878         ret = mtu3_hw_init(mtu);
 879         if (ret) {
 880                 dev_err(dev, "mtu3 hw init failed:%d\n", ret);
 881                 return ret;
 882         }
 883 
 884         ret = mtu3_set_dma_mask(mtu);
 885         if (ret) {
 886                 dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
 887                 goto dma_mask_err;
 888         }
 889 
 890         ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
 891         if (ret) {
 892                 dev_err(dev, "request irq %d failed!\n", mtu->irq);
 893                 goto irq_err;
 894         }
 895 
 896         device_init_wakeup(dev, true);
 897 
 898         ret = mtu3_gadget_setup(mtu);
 899         if (ret) {
 900                 dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
 901                 goto gadget_err;
 902         }
 903 
 904         /* init as host mode, power down device IP for power saving */
 905         if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
 906                 mtu3_stop(mtu);
 907 
 908         ssusb_dev_debugfs_init(ssusb);
 909 
 910         dev_dbg(dev, " %s() done...\n", __func__);
 911 
 912         return 0;
 913 
 914 gadget_err:
 915         device_init_wakeup(dev, false);
 916 
 917 dma_mask_err:
 918 irq_err:
 919         mtu3_hw_exit(mtu);
 920         ssusb->u3d = NULL;
 921         dev_err(dev, " %s() fail...\n", __func__);
 922 
 923         return ret;
 924 }
 925 
 926 void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
 927 {
 928         struct mtu3 *mtu = ssusb->u3d;
 929 
 930         mtu3_gadget_cleanup(mtu);
 931         device_init_wakeup(ssusb->dev, false);
 932         mtu3_hw_exit(mtu);
 933 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/usb/mtu3/mtu3_core.c

DEFINITIONS
