root/drivers/usb/dwc3/core.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. dwc3_is_usb3
  2. dwc3_is_usb31
  3. dwc3_host_init
  4. dwc3_host_exit
  5. dwc3_gadget_init
  6. dwc3_gadget_exit
  7. dwc3_gadget_set_test_mode
  8. dwc3_gadget_get_link_state
  9. dwc3_gadget_set_link_state
  10. dwc3_send_gadget_ep_cmd
  11. dwc3_send_gadget_generic_command
  12. dwc3_drd_init
  13. dwc3_drd_exit
  14. dwc3_otg_init
  15. dwc3_otg_exit
  16. dwc3_otg_update
  17. dwc3_otg_host_init
  18. dwc3_gadget_suspend
  19. dwc3_gadget_resume
  20. dwc3_gadget_process_pending_events
  21. dwc3_ulpi_init
  22. dwc3_ulpi_exit
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * core.h - DesignWare USB3 DRD Core Header
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10 
  11 #ifndef __DRIVERS_USB_DWC3_CORE_H
  12 #define __DRIVERS_USB_DWC3_CORE_H
  13 
  14 #include <linux/device.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/ioport.h>
  17 #include <linux/list.h>
  18 #include <linux/bitops.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/mm.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/wait.h>
  23 #include <linux/workqueue.h>
  24 
  25 #include <linux/usb/ch9.h>
  26 #include <linux/usb/gadget.h>
  27 #include <linux/usb/otg.h>
  28 #include <linux/ulpi/interface.h>
  29 
  30 #include <linux/phy/phy.h>
  31 
  32 #define DWC3_MSG_MAX    500
  33 
  34 /* Global constants */
  35 #define DWC3_PULL_UP_TIMEOUT    500     /* ms */
  36 #define DWC3_BOUNCE_SIZE        1024    /* size of a superspeed bulk */
  37 #define DWC3_EP0_SETUP_SIZE     512
  38 #define DWC3_ENDPOINTS_NUM      32
  39 #define DWC3_XHCI_RESOURCES_NUM 2
  40 #define DWC3_ISOC_MAX_RETRIES   5
  41 
  42 #define DWC3_SCRATCHBUF_SIZE    4096    /* each buffer is assumed to be 4KiB */
  43 #define DWC3_EVENT_BUFFERS_SIZE 4096
  44 #define DWC3_EVENT_TYPE_MASK    0xfe
  45 
  46 #define DWC3_EVENT_TYPE_DEV     0
  47 #define DWC3_EVENT_TYPE_CARKIT  3
  48 #define DWC3_EVENT_TYPE_I2C     4
  49 
  50 #define DWC3_DEVICE_EVENT_DISCONNECT            0
  51 #define DWC3_DEVICE_EVENT_RESET                 1
  52 #define DWC3_DEVICE_EVENT_CONNECT_DONE          2
  53 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE    3
  54 #define DWC3_DEVICE_EVENT_WAKEUP                4
  55 #define DWC3_DEVICE_EVENT_HIBER_REQ             5
  56 #define DWC3_DEVICE_EVENT_EOPF                  6
  57 #define DWC3_DEVICE_EVENT_SOF                   7
  58 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR         9
  59 #define DWC3_DEVICE_EVENT_CMD_CMPL              10
  60 #define DWC3_DEVICE_EVENT_OVERFLOW              11
  61 
  62 /* Controller's role while using the OTG block */
  63 #define DWC3_OTG_ROLE_IDLE      0
  64 #define DWC3_OTG_ROLE_HOST      1
  65 #define DWC3_OTG_ROLE_DEVICE    2
  66 
  67 #define DWC3_GEVNTCOUNT_MASK    0xfffc
  68 #define DWC3_GEVNTCOUNT_EHB     BIT(31)
  69 #define DWC3_GSNPSID_MASK       0xffff0000
  70 #define DWC3_GSNPSREV_MASK      0xffff
  71 
  72 /* DWC3 registers memory space boundries */
  73 #define DWC3_XHCI_REGS_START            0x0
  74 #define DWC3_XHCI_REGS_END              0x7fff
  75 #define DWC3_GLOBALS_REGS_START         0xc100
  76 #define DWC3_GLOBALS_REGS_END           0xc6ff
  77 #define DWC3_DEVICE_REGS_START          0xc700
  78 #define DWC3_DEVICE_REGS_END            0xcbff
  79 #define DWC3_OTG_REGS_START             0xcc00
  80 #define DWC3_OTG_REGS_END               0xccff
  81 
  82 /* Global Registers */
  83 #define DWC3_GSBUSCFG0          0xc100
  84 #define DWC3_GSBUSCFG1          0xc104
  85 #define DWC3_GTXTHRCFG          0xc108
  86 #define DWC3_GRXTHRCFG          0xc10c
  87 #define DWC3_GCTL               0xc110
  88 #define DWC3_GEVTEN             0xc114
  89 #define DWC3_GSTS               0xc118
  90 #define DWC3_GUCTL1             0xc11c
  91 #define DWC3_GSNPSID            0xc120
  92 #define DWC3_GGPIO              0xc124
  93 #define DWC3_GUID               0xc128
  94 #define DWC3_GUCTL              0xc12c
  95 #define DWC3_GBUSERRADDR0       0xc130
  96 #define DWC3_GBUSERRADDR1       0xc134
  97 #define DWC3_GPRTBIMAP0         0xc138
  98 #define DWC3_GPRTBIMAP1         0xc13c
  99 #define DWC3_GHWPARAMS0         0xc140
 100 #define DWC3_GHWPARAMS1         0xc144
 101 #define DWC3_GHWPARAMS2         0xc148
 102 #define DWC3_GHWPARAMS3         0xc14c
 103 #define DWC3_GHWPARAMS4         0xc150
 104 #define DWC3_GHWPARAMS5         0xc154
 105 #define DWC3_GHWPARAMS6         0xc158
 106 #define DWC3_GHWPARAMS7         0xc15c
 107 #define DWC3_GDBGFIFOSPACE      0xc160
 108 #define DWC3_GDBGLTSSM          0xc164
 109 #define DWC3_GDBGBMU            0xc16c
 110 #define DWC3_GDBGLSPMUX         0xc170
 111 #define DWC3_GDBGLSP            0xc174
 112 #define DWC3_GDBGEPINFO0        0xc178
 113 #define DWC3_GDBGEPINFO1        0xc17c
 114 #define DWC3_GPRTBIMAP_HS0      0xc180
 115 #define DWC3_GPRTBIMAP_HS1      0xc184
 116 #define DWC3_GPRTBIMAP_FS0      0xc188
 117 #define DWC3_GPRTBIMAP_FS1      0xc18c
 118 #define DWC3_GUCTL2             0xc19c
 119 
 120 #define DWC3_VER_NUMBER         0xc1a0
 121 #define DWC3_VER_TYPE           0xc1a4
 122 
 123 #define DWC3_GUSB2PHYCFG(n)     (0xc200 + ((n) * 0x04))
 124 #define DWC3_GUSB2I2CCTL(n)     (0xc240 + ((n) * 0x04))
 125 
 126 #define DWC3_GUSB2PHYACC(n)     (0xc280 + ((n) * 0x04))
 127 
 128 #define DWC3_GUSB3PIPECTL(n)    (0xc2c0 + ((n) * 0x04))
 129 
 130 #define DWC3_GTXFIFOSIZ(n)      (0xc300 + ((n) * 0x04))
 131 #define DWC3_GRXFIFOSIZ(n)      (0xc380 + ((n) * 0x04))
 132 
 133 #define DWC3_GEVNTADRLO(n)      (0xc400 + ((n) * 0x10))
 134 #define DWC3_GEVNTADRHI(n)      (0xc404 + ((n) * 0x10))
 135 #define DWC3_GEVNTSIZ(n)        (0xc408 + ((n) * 0x10))
 136 #define DWC3_GEVNTCOUNT(n)      (0xc40c + ((n) * 0x10))
 137 
 138 #define DWC3_GHWPARAMS8         0xc600
 139 #define DWC3_GFLADJ             0xc630
 140 
 141 /* Device Registers */
 142 #define DWC3_DCFG               0xc700
 143 #define DWC3_DCTL               0xc704
 144 #define DWC3_DEVTEN             0xc708
 145 #define DWC3_DSTS               0xc70c
 146 #define DWC3_DGCMDPAR           0xc710
 147 #define DWC3_DGCMD              0xc714
 148 #define DWC3_DALEPENA           0xc720
 149 
 150 #define DWC3_DEP_BASE(n)        (0xc800 + ((n) * 0x10))
 151 #define DWC3_DEPCMDPAR2         0x00
 152 #define DWC3_DEPCMDPAR1         0x04
 153 #define DWC3_DEPCMDPAR0         0x08
 154 #define DWC3_DEPCMD             0x0c
 155 
 156 #define DWC3_DEV_IMOD(n)        (0xca00 + ((n) * 0x4))
 157 
 158 /* OTG Registers */
 159 #define DWC3_OCFG               0xcc00
 160 #define DWC3_OCTL               0xcc04
 161 #define DWC3_OEVT               0xcc08
 162 #define DWC3_OEVTEN             0xcc0C
 163 #define DWC3_OSTS               0xcc10
 164 
 165 /* Bit fields */
 166 
 167 /* Global SoC Bus Configuration INCRx Register 0 */
 168 #define DWC3_GSBUSCFG0_INCR256BRSTENA   (1 << 7) /* INCR256 burst */
 169 #define DWC3_GSBUSCFG0_INCR128BRSTENA   (1 << 6) /* INCR128 burst */
 170 #define DWC3_GSBUSCFG0_INCR64BRSTENA    (1 << 5) /* INCR64 burst */
 171 #define DWC3_GSBUSCFG0_INCR32BRSTENA    (1 << 4) /* INCR32 burst */
 172 #define DWC3_GSBUSCFG0_INCR16BRSTENA    (1 << 3) /* INCR16 burst */
 173 #define DWC3_GSBUSCFG0_INCR8BRSTENA     (1 << 2) /* INCR8 burst */
 174 #define DWC3_GSBUSCFG0_INCR4BRSTENA     (1 << 1) /* INCR4 burst */
 175 #define DWC3_GSBUSCFG0_INCRBRSTENA      (1 << 0) /* undefined length enable */
 176 #define DWC3_GSBUSCFG0_INCRBRST_MASK    0xff
 177 
 178 /* Global Debug LSP MUX Select */
 179 #define DWC3_GDBGLSPMUX_ENDBC           BIT(15) /* Host only */
 180 #define DWC3_GDBGLSPMUX_HOSTSELECT(n)   ((n) & 0x3fff)
 181 #define DWC3_GDBGLSPMUX_DEVSELECT(n)    (((n) & 0xf) << 4)
 182 #define DWC3_GDBGLSPMUX_EPSELECT(n)     ((n) & 0xf)
 183 
 184 /* Global Debug Queue/FIFO Space Available Register */
 185 #define DWC3_GDBGFIFOSPACE_NUM(n)       ((n) & 0x1f)
 186 #define DWC3_GDBGFIFOSPACE_TYPE(n)      (((n) << 5) & 0x1e0)
 187 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
 188 
 189 #define DWC3_TXFIFO             0
 190 #define DWC3_RXFIFO             1
 191 #define DWC3_TXREQQ             2
 192 #define DWC3_RXREQQ             3
 193 #define DWC3_RXINFOQ            4
 194 #define DWC3_PSTATQ             5
 195 #define DWC3_DESCFETCHQ         6
 196 #define DWC3_EVENTQ             7
 197 #define DWC3_AUXEVENTQ          8
 198 
 199 /* Global RX Threshold Configuration Register */
 200 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
 201 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
 202 #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
 203 
 204 /* Global RX Threshold Configuration Register for DWC_usb31 only */
 205 #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n)       (((n) & 0x1f) << 16)
 206 #define DWC31_GRXTHRCFG_RXPKTCNT(n)             (((n) & 0x1f) << 21)
 207 #define DWC31_GRXTHRCFG_PKTCNTSEL               BIT(26)
 208 #define DWC31_RXTHRNUMPKTSEL_HS_PRD             BIT(15)
 209 #define DWC31_RXTHRNUMPKT_HS_PRD(n)             (((n) & 0x3) << 13)
 210 #define DWC31_RXTHRNUMPKTSEL_PRD                BIT(10)
 211 #define DWC31_RXTHRNUMPKT_PRD(n)                (((n) & 0x1f) << 5)
 212 #define DWC31_MAXRXBURSTSIZE_PRD(n)             ((n) & 0x1f)
 213 
 214 /* Global TX Threshold Configuration Register for DWC_usb31 only */
 215 #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n)       (((n) & 0x1f) << 16)
 216 #define DWC31_GTXTHRCFG_TXPKTCNT(n)             (((n) & 0x1f) << 21)
 217 #define DWC31_GTXTHRCFG_PKTCNTSEL               BIT(26)
 218 #define DWC31_TXTHRNUMPKTSEL_HS_PRD             BIT(15)
 219 #define DWC31_TXTHRNUMPKT_HS_PRD(n)             (((n) & 0x3) << 13)
 220 #define DWC31_TXTHRNUMPKTSEL_PRD                BIT(10)
 221 #define DWC31_TXTHRNUMPKT_PRD(n)                (((n) & 0x1f) << 5)
 222 #define DWC31_MAXTXBURSTSIZE_PRD(n)             ((n) & 0x1f)
 223 
 224 /* Global Configuration Register */
 225 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
 226 #define DWC3_GCTL_U2RSTECN      BIT(16)
 227 #define DWC3_GCTL_RAMCLKSEL(x)  (((x) & DWC3_GCTL_CLK_MASK) << 6)
 228 #define DWC3_GCTL_CLK_BUS       (0)
 229 #define DWC3_GCTL_CLK_PIPE      (1)
 230 #define DWC3_GCTL_CLK_PIPEHALF  (2)
 231 #define DWC3_GCTL_CLK_MASK      (3)
 232 
 233 #define DWC3_GCTL_PRTCAP(n)     (((n) & (3 << 12)) >> 12)
 234 #define DWC3_GCTL_PRTCAPDIR(n)  ((n) << 12)
 235 #define DWC3_GCTL_PRTCAP_HOST   1
 236 #define DWC3_GCTL_PRTCAP_DEVICE 2
 237 #define DWC3_GCTL_PRTCAP_OTG    3
 238 
 239 #define DWC3_GCTL_CORESOFTRESET         BIT(11)
 240 #define DWC3_GCTL_SOFITPSYNC            BIT(10)
 241 #define DWC3_GCTL_SCALEDOWN(n)          ((n) << 4)
 242 #define DWC3_GCTL_SCALEDOWN_MASK        DWC3_GCTL_SCALEDOWN(3)
 243 #define DWC3_GCTL_DISSCRAMBLE           BIT(3)
 244 #define DWC3_GCTL_U2EXIT_LFPS           BIT(2)
 245 #define DWC3_GCTL_GBLHIBERNATIONEN      BIT(1)
 246 #define DWC3_GCTL_DSBLCLKGTNG           BIT(0)
 247 
 248 /* Global User Control Register */
 249 #define DWC3_GUCTL_HSTINAUTORETRY       BIT(14)
 250 
 251 /* Global User Control 1 Register */
 252 #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
 253 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS      BIT(28)
 254 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW   BIT(24)
 255 
 256 /* Global Status Register */
 257 #define DWC3_GSTS_OTG_IP        BIT(10)
 258 #define DWC3_GSTS_BC_IP         BIT(9)
 259 #define DWC3_GSTS_ADP_IP        BIT(8)
 260 #define DWC3_GSTS_HOST_IP       BIT(7)
 261 #define DWC3_GSTS_DEVICE_IP     BIT(6)
 262 #define DWC3_GSTS_CSR_TIMEOUT   BIT(5)
 263 #define DWC3_GSTS_BUS_ERR_ADDR_VLD      BIT(4)
 264 #define DWC3_GSTS_CURMOD(n)     ((n) & 0x3)
 265 #define DWC3_GSTS_CURMOD_DEVICE 0
 266 #define DWC3_GSTS_CURMOD_HOST   1
 267 
 268 /* Global USB2 PHY Configuration Register */
 269 #define DWC3_GUSB2PHYCFG_PHYSOFTRST     BIT(31)
 270 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS      BIT(30)
 271 #define DWC3_GUSB2PHYCFG_SUSPHY         BIT(6)
 272 #define DWC3_GUSB2PHYCFG_ULPI_UTMI      BIT(4)
 273 #define DWC3_GUSB2PHYCFG_ENBLSLPM       BIT(8)
 274 #define DWC3_GUSB2PHYCFG_PHYIF(n)       (n << 3)
 275 #define DWC3_GUSB2PHYCFG_PHYIF_MASK     DWC3_GUSB2PHYCFG_PHYIF(1)
 276 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n)   (n << 10)
 277 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
 278 #define USBTRDTIM_UTMI_8_BIT            9
 279 #define USBTRDTIM_UTMI_16_BIT           5
 280 #define UTMI_PHYIF_16_BIT               1
 281 #define UTMI_PHYIF_8_BIT                0
 282 
 283 /* Global USB2 PHY Vendor Control Register */
 284 #define DWC3_GUSB2PHYACC_NEWREGREQ      BIT(25)
 285 #define DWC3_GUSB2PHYACC_BUSY           BIT(23)
 286 #define DWC3_GUSB2PHYACC_WRITE          BIT(22)
 287 #define DWC3_GUSB2PHYACC_ADDR(n)        (n << 16)
 288 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
 289 #define DWC3_GUSB2PHYACC_DATA(n)        (n & 0xff)
 290 
 291 /* Global USB3 PIPE Control Register */
 292 #define DWC3_GUSB3PIPECTL_PHYSOFTRST    BIT(31)
 293 #define DWC3_GUSB3PIPECTL_U2SSINP3OK    BIT(29)
 294 #define DWC3_GUSB3PIPECTL_DISRXDETINP3  BIT(28)
 295 #define DWC3_GUSB3PIPECTL_UX_EXIT_PX    BIT(27)
 296 #define DWC3_GUSB3PIPECTL_REQP1P2P3     BIT(24)
 297 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n)   ((n) << 19)
 298 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
 299 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN   DWC3_GUSB3PIPECTL_DEP1P2P3(1)
 300 #define DWC3_GUSB3PIPECTL_DEPOCHANGE    BIT(18)
 301 #define DWC3_GUSB3PIPECTL_SUSPHY        BIT(17)
 302 #define DWC3_GUSB3PIPECTL_LFPSFILT      BIT(9)
 303 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL   BIT(8)
 304 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
 305 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n)   ((n) << 1)
 306 
 307 /* Global TX Fifo Size Register */
 308 #define DWC31_GTXFIFOSIZ_TXFRAMNUM      BIT(15)         /* DWC_usb31 only */
 309 #define DWC31_GTXFIFOSIZ_TXFDEF(n)      ((n) & 0x7fff)  /* DWC_usb31 only */
 310 #define DWC3_GTXFIFOSIZ_TXFDEF(n)       ((n) & 0xffff)
 311 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n)    ((n) & 0xffff0000)
 312 
 313 /* Global RX Fifo Size Register */
 314 #define DWC31_GRXFIFOSIZ_RXFDEP(n)      ((n) & 0x7fff)  /* DWC_usb31 only */
 315 #define DWC3_GRXFIFOSIZ_RXFDEP(n)       ((n) & 0xffff)
 316 
 317 /* Global Event Size Registers */
 318 #define DWC3_GEVNTSIZ_INTMASK           BIT(31)
 319 #define DWC3_GEVNTSIZ_SIZE(n)           ((n) & 0xffff)
 320 
 321 /* Global HWPARAMS0 Register */
 322 #define DWC3_GHWPARAMS0_MODE(n)         ((n) & 0x3)
 323 #define DWC3_GHWPARAMS0_MODE_GADGET     0
 324 #define DWC3_GHWPARAMS0_MODE_HOST       1
 325 #define DWC3_GHWPARAMS0_MODE_DRD        2
 326 #define DWC3_GHWPARAMS0_MBUS_TYPE(n)    (((n) >> 3) & 0x7)
 327 #define DWC3_GHWPARAMS0_SBUS_TYPE(n)    (((n) >> 6) & 0x3)
 328 #define DWC3_GHWPARAMS0_MDWIDTH(n)      (((n) >> 8) & 0xff)
 329 #define DWC3_GHWPARAMS0_SDWIDTH(n)      (((n) >> 16) & 0xff)
 330 #define DWC3_GHWPARAMS0_AWIDTH(n)       (((n) >> 24) & 0xff)
 331 
 332 /* Global HWPARAMS1 Register */
 333 #define DWC3_GHWPARAMS1_EN_PWROPT(n)    (((n) & (3 << 24)) >> 24)
 334 #define DWC3_GHWPARAMS1_EN_PWROPT_NO    0
 335 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK   1
 336 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB   2
 337 #define DWC3_GHWPARAMS1_PWROPT(n)       ((n) << 24)
 338 #define DWC3_GHWPARAMS1_PWROPT_MASK     DWC3_GHWPARAMS1_PWROPT(3)
 339 #define DWC3_GHWPARAMS1_ENDBC           BIT(31)
 340 
 341 /* Global HWPARAMS3 Register */
 342 #define DWC3_GHWPARAMS3_SSPHY_IFC(n)            ((n) & 3)
 343 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS           0
 344 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1          1
 345 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2          2 /* DWC_usb31 only */
 346 #define DWC3_GHWPARAMS3_HSPHY_IFC(n)            (((n) & (3 << 2)) >> 2)
 347 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS           0
 348 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI          1
 349 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI          2
 350 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI     3
 351 #define DWC3_GHWPARAMS3_FSPHY_IFC(n)            (((n) & (3 << 4)) >> 4)
 352 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS           0
 353 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA           1
 354 
 355 /* Global HWPARAMS4 Register */
 356 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n)    (((n) & (0x0f << 13)) >> 13)
 357 #define DWC3_MAX_HIBER_SCRATCHBUFS              15
 358 
 359 /* Global HWPARAMS6 Register */
 360 #define DWC3_GHWPARAMS6_BCSUPPORT               BIT(14)
 361 #define DWC3_GHWPARAMS6_OTG3SUPPORT             BIT(13)
 362 #define DWC3_GHWPARAMS6_ADPSUPPORT              BIT(12)
 363 #define DWC3_GHWPARAMS6_HNPSUPPORT              BIT(11)
 364 #define DWC3_GHWPARAMS6_SRPSUPPORT              BIT(10)
 365 #define DWC3_GHWPARAMS6_EN_FPGA                 BIT(7)
 366 
 367 /* Global HWPARAMS7 Register */
 368 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n)   ((n) & 0xffff)
 369 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n)   (((n) >> 16) & 0xffff)
 370 
 371 /* Global Frame Length Adjustment Register */
 372 #define DWC3_GFLADJ_30MHZ_SDBND_SEL             BIT(7)
 373 #define DWC3_GFLADJ_30MHZ_MASK                  0x3f
 374 
 375 /* Global User Control Register 2 */
 376 #define DWC3_GUCTL2_RST_ACTBITLATER             BIT(14)
 377 
 378 /* Device Configuration Register */
 379 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
 380 #define DWC3_DCFG_DEVADDR_MASK  DWC3_DCFG_DEVADDR(0x7f)
 381 
 382 #define DWC3_DCFG_SPEED_MASK    (7 << 0)
 383 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0)  /* DWC_usb31 only */
 384 #define DWC3_DCFG_SUPERSPEED    (4 << 0)
 385 #define DWC3_DCFG_HIGHSPEED     (0 << 0)
 386 #define DWC3_DCFG_FULLSPEED     BIT(0)
 387 #define DWC3_DCFG_LOWSPEED      (2 << 0)
 388 
 389 #define DWC3_DCFG_NUMP_SHIFT    17
 390 #define DWC3_DCFG_NUMP(n)       (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
 391 #define DWC3_DCFG_NUMP_MASK     (0x1f << DWC3_DCFG_NUMP_SHIFT)
 392 #define DWC3_DCFG_LPM_CAP       BIT(22)
 393 
 394 /* Device Control Register */
 395 #define DWC3_DCTL_RUN_STOP      BIT(31)
 396 #define DWC3_DCTL_CSFTRST       BIT(30)
 397 #define DWC3_DCTL_LSFTRST       BIT(29)
 398 
 399 #define DWC3_DCTL_HIRD_THRES_MASK       (0x1f << 24)
 400 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
 401 
 402 #define DWC3_DCTL_APPL1RES      BIT(23)
 403 
 404 /* These apply for core versions 1.87a and earlier */
 405 #define DWC3_DCTL_TRGTULST_MASK         (0x0f << 17)
 406 #define DWC3_DCTL_TRGTULST(n)           ((n) << 17)
 407 #define DWC3_DCTL_TRGTULST_U2           (DWC3_DCTL_TRGTULST(2))
 408 #define DWC3_DCTL_TRGTULST_U3           (DWC3_DCTL_TRGTULST(3))
 409 #define DWC3_DCTL_TRGTULST_SS_DIS       (DWC3_DCTL_TRGTULST(4))
 410 #define DWC3_DCTL_TRGTULST_RX_DET       (DWC3_DCTL_TRGTULST(5))
 411 #define DWC3_DCTL_TRGTULST_SS_INACT     (DWC3_DCTL_TRGTULST(6))
 412 
 413 /* These apply for core versions 1.94a and later */
 414 #define DWC3_DCTL_NYET_THRES(n)         (((n) & 0xf) << 20)
 415 
 416 #define DWC3_DCTL_KEEP_CONNECT          BIT(19)
 417 #define DWC3_DCTL_L1_HIBER_EN           BIT(18)
 418 #define DWC3_DCTL_CRS                   BIT(17)
 419 #define DWC3_DCTL_CSS                   BIT(16)
 420 
 421 #define DWC3_DCTL_INITU2ENA             BIT(12)
 422 #define DWC3_DCTL_ACCEPTU2ENA           BIT(11)
 423 #define DWC3_DCTL_INITU1ENA             BIT(10)
 424 #define DWC3_DCTL_ACCEPTU1ENA           BIT(9)
 425 #define DWC3_DCTL_TSTCTRL_MASK          (0xf << 1)
 426 
 427 #define DWC3_DCTL_ULSTCHNGREQ_MASK      (0x0f << 5)
 428 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
 429 
 430 #define DWC3_DCTL_ULSTCHNG_NO_ACTION    (DWC3_DCTL_ULSTCHNGREQ(0))
 431 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED  (DWC3_DCTL_ULSTCHNGREQ(4))
 432 #define DWC3_DCTL_ULSTCHNG_RX_DETECT    (DWC3_DCTL_ULSTCHNGREQ(5))
 433 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE  (DWC3_DCTL_ULSTCHNGREQ(6))
 434 #define DWC3_DCTL_ULSTCHNG_RECOVERY     (DWC3_DCTL_ULSTCHNGREQ(8))
 435 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE   (DWC3_DCTL_ULSTCHNGREQ(10))
 436 #define DWC3_DCTL_ULSTCHNG_LOOPBACK     (DWC3_DCTL_ULSTCHNGREQ(11))
 437 
 438 /* Device Event Enable Register */
 439 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN   BIT(12)
 440 #define DWC3_DEVTEN_EVNTOVERFLOWEN      BIT(11)
 441 #define DWC3_DEVTEN_CMDCMPLTEN          BIT(10)
 442 #define DWC3_DEVTEN_ERRTICERREN         BIT(9)
 443 #define DWC3_DEVTEN_SOFEN               BIT(7)
 444 #define DWC3_DEVTEN_EOPFEN              BIT(6)
 445 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
 446 #define DWC3_DEVTEN_WKUPEVTEN           BIT(4)
 447 #define DWC3_DEVTEN_ULSTCNGEN           BIT(3)
 448 #define DWC3_DEVTEN_CONNECTDONEEN       BIT(2)
 449 #define DWC3_DEVTEN_USBRSTEN            BIT(1)
 450 #define DWC3_DEVTEN_DISCONNEVTEN        BIT(0)
 451 
 452 /* Device Status Register */
 453 #define DWC3_DSTS_DCNRD                 BIT(29)
 454 
 455 /* This applies for core versions 1.87a and earlier */
 456 #define DWC3_DSTS_PWRUPREQ              BIT(24)
 457 
 458 /* These apply for core versions 1.94a and later */
 459 #define DWC3_DSTS_RSS                   BIT(25)
 460 #define DWC3_DSTS_SSS                   BIT(24)
 461 
 462 #define DWC3_DSTS_COREIDLE              BIT(23)
 463 #define DWC3_DSTS_DEVCTRLHLT            BIT(22)
 464 
 465 #define DWC3_DSTS_USBLNKST_MASK         (0x0f << 18)
 466 #define DWC3_DSTS_USBLNKST(n)           (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
 467 
 468 #define DWC3_DSTS_RXFIFOEMPTY           BIT(17)
 469 
 470 #define DWC3_DSTS_SOFFN_MASK            (0x3fff << 3)
 471 #define DWC3_DSTS_SOFFN(n)              (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
 472 
 473 #define DWC3_DSTS_CONNECTSPD            (7 << 0)
 474 
 475 #define DWC3_DSTS_SUPERSPEED_PLUS       (5 << 0) /* DWC_usb31 only */
 476 #define DWC3_DSTS_SUPERSPEED            (4 << 0)
 477 #define DWC3_DSTS_HIGHSPEED             (0 << 0)
 478 #define DWC3_DSTS_FULLSPEED             BIT(0)
 479 #define DWC3_DSTS_LOWSPEED              (2 << 0)
 480 
 481 /* Device Generic Command Register */
 482 #define DWC3_DGCMD_SET_LMP              0x01
 483 #define DWC3_DGCMD_SET_PERIODIC_PAR     0x02
 484 #define DWC3_DGCMD_XMIT_FUNCTION        0x03
 485 
 486 /* These apply for core versions 1.94a and later */
 487 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO       0x04
 488 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI       0x05
 489 
 490 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH  0x09
 491 #define DWC3_DGCMD_ALL_FIFO_FLUSH       0x0a
 492 #define DWC3_DGCMD_SET_ENDPOINT_NRDY    0x0c
 493 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
 494 
 495 #define DWC3_DGCMD_STATUS(n)            (((n) >> 12) & 0x0F)
 496 #define DWC3_DGCMD_CMDACT               BIT(10)
 497 #define DWC3_DGCMD_CMDIOC               BIT(8)
 498 
 499 /* Device Generic Command Parameter Register */
 500 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT       BIT(0)
 501 #define DWC3_DGCMDPAR_FIFO_NUM(n)               ((n) << 0)
 502 #define DWC3_DGCMDPAR_RX_FIFO                   (0 << 5)
 503 #define DWC3_DGCMDPAR_TX_FIFO                   BIT(5)
 504 #define DWC3_DGCMDPAR_LOOPBACK_DIS              (0 << 0)
 505 #define DWC3_DGCMDPAR_LOOPBACK_ENA              BIT(0)
 506 
 507 /* Device Endpoint Command Register */
 508 #define DWC3_DEPCMD_PARAM_SHIFT         16
 509 #define DWC3_DEPCMD_PARAM(x)            ((x) << DWC3_DEPCMD_PARAM_SHIFT)
 510 #define DWC3_DEPCMD_GET_RSC_IDX(x)      (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
 511 #define DWC3_DEPCMD_STATUS(x)           (((x) >> 12) & 0x0F)
 512 #define DWC3_DEPCMD_HIPRI_FORCERM       BIT(11)
 513 #define DWC3_DEPCMD_CLEARPENDIN         BIT(11)
 514 #define DWC3_DEPCMD_CMDACT              BIT(10)
 515 #define DWC3_DEPCMD_CMDIOC              BIT(8)
 516 
 517 #define DWC3_DEPCMD_DEPSTARTCFG         (0x09 << 0)
 518 #define DWC3_DEPCMD_ENDTRANSFER         (0x08 << 0)
 519 #define DWC3_DEPCMD_UPDATETRANSFER      (0x07 << 0)
 520 #define DWC3_DEPCMD_STARTTRANSFER       (0x06 << 0)
 521 #define DWC3_DEPCMD_CLEARSTALL          (0x05 << 0)
 522 #define DWC3_DEPCMD_SETSTALL            (0x04 << 0)
 523 /* This applies for core versions 1.90a and earlier */
 524 #define DWC3_DEPCMD_GETSEQNUMBER        (0x03 << 0)
 525 /* This applies for core versions 1.94a and later */
 526 #define DWC3_DEPCMD_GETEPSTATE          (0x03 << 0)
 527 #define DWC3_DEPCMD_SETTRANSFRESOURCE   (0x02 << 0)
 528 #define DWC3_DEPCMD_SETEPCONFIG         (0x01 << 0)
 529 
 530 #define DWC3_DEPCMD_CMD(x)              ((x) & 0xf)
 531 
 532 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
 533 #define DWC3_DALEPENA_EP(n)             BIT(n)
 534 
 535 #define DWC3_DEPCMD_TYPE_CONTROL        0
 536 #define DWC3_DEPCMD_TYPE_ISOC           1
 537 #define DWC3_DEPCMD_TYPE_BULK           2
 538 #define DWC3_DEPCMD_TYPE_INTR           3
 539 
 540 #define DWC3_DEV_IMOD_COUNT_SHIFT       16
 541 #define DWC3_DEV_IMOD_COUNT_MASK        (0xffff << 16)
 542 #define DWC3_DEV_IMOD_INTERVAL_SHIFT    0
 543 #define DWC3_DEV_IMOD_INTERVAL_MASK     (0xffff << 0)
 544 
 545 /* OTG Configuration Register */
 546 #define DWC3_OCFG_DISPWRCUTTOFF         BIT(5)
 547 #define DWC3_OCFG_HIBDISMASK            BIT(4)
 548 #define DWC3_OCFG_SFTRSTMASK            BIT(3)
 549 #define DWC3_OCFG_OTGVERSION            BIT(2)
 550 #define DWC3_OCFG_HNPCAP                BIT(1)
 551 #define DWC3_OCFG_SRPCAP                BIT(0)
 552 
 553 /* OTG CTL Register */
 554 #define DWC3_OCTL_OTG3GOERR             BIT(7)
 555 #define DWC3_OCTL_PERIMODE              BIT(6)
 556 #define DWC3_OCTL_PRTPWRCTL             BIT(5)
 557 #define DWC3_OCTL_HNPREQ                BIT(4)
 558 #define DWC3_OCTL_SESREQ                BIT(3)
 559 #define DWC3_OCTL_TERMSELIDPULSE        BIT(2)
 560 #define DWC3_OCTL_DEVSETHNPEN           BIT(1)
 561 #define DWC3_OCTL_HSTSETHNPEN           BIT(0)
 562 
 563 /* OTG Event Register */
 564 #define DWC3_OEVT_DEVICEMODE            BIT(31)
 565 #define DWC3_OEVT_XHCIRUNSTPSET         BIT(27)
 566 #define DWC3_OEVT_DEVRUNSTPSET          BIT(26)
 567 #define DWC3_OEVT_HIBENTRY              BIT(25)
 568 #define DWC3_OEVT_CONIDSTSCHNG          BIT(24)
 569 #define DWC3_OEVT_HRRCONFNOTIF          BIT(23)
 570 #define DWC3_OEVT_HRRINITNOTIF          BIT(22)
 571 #define DWC3_OEVT_ADEVIDLE              BIT(21)
 572 #define DWC3_OEVT_ADEVBHOSTEND          BIT(20)
 573 #define DWC3_OEVT_ADEVHOST              BIT(19)
 574 #define DWC3_OEVT_ADEVHNPCHNG           BIT(18)
 575 #define DWC3_OEVT_ADEVSRPDET            BIT(17)
 576 #define DWC3_OEVT_ADEVSESSENDDET        BIT(16)
 577 #define DWC3_OEVT_BDEVBHOSTEND          BIT(11)
 578 #define DWC3_OEVT_BDEVHNPCHNG           BIT(10)
 579 #define DWC3_OEVT_BDEVSESSVLDDET        BIT(9)
 580 #define DWC3_OEVT_BDEVVBUSCHNG          BIT(8)
 581 #define DWC3_OEVT_BSESSVLD              BIT(3)
 582 #define DWC3_OEVT_HSTNEGSTS             BIT(2)
 583 #define DWC3_OEVT_SESREQSTS             BIT(1)
 584 #define DWC3_OEVT_ERROR                 BIT(0)
 585 
 586 /* OTG Event Enable Register */
 587 #define DWC3_OEVTEN_XHCIRUNSTPSETEN     BIT(27)
 588 #define DWC3_OEVTEN_DEVRUNSTPSETEN      BIT(26)
 589 #define DWC3_OEVTEN_HIBENTRYEN          BIT(25)
 590 #define DWC3_OEVTEN_CONIDSTSCHNGEN      BIT(24)
 591 #define DWC3_OEVTEN_HRRCONFNOTIFEN      BIT(23)
 592 #define DWC3_OEVTEN_HRRINITNOTIFEN      BIT(22)
 593 #define DWC3_OEVTEN_ADEVIDLEEN          BIT(21)
 594 #define DWC3_OEVTEN_ADEVBHOSTENDEN      BIT(20)
 595 #define DWC3_OEVTEN_ADEVHOSTEN          BIT(19)
 596 #define DWC3_OEVTEN_ADEVHNPCHNGEN       BIT(18)
 597 #define DWC3_OEVTEN_ADEVSRPDETEN        BIT(17)
 598 #define DWC3_OEVTEN_ADEVSESSENDDETEN    BIT(16)
 599 #define DWC3_OEVTEN_BDEVBHOSTENDEN      BIT(11)
 600 #define DWC3_OEVTEN_BDEVHNPCHNGEN       BIT(10)
 601 #define DWC3_OEVTEN_BDEVSESSVLDDETEN    BIT(9)
 602 #define DWC3_OEVTEN_BDEVVBUSCHNGEN      BIT(8)
 603 
 604 /* OTG Status Register */
 605 #define DWC3_OSTS_DEVRUNSTP             BIT(13)
 606 #define DWC3_OSTS_XHCIRUNSTP            BIT(12)
 607 #define DWC3_OSTS_PERIPHERALSTATE       BIT(4)
 608 #define DWC3_OSTS_XHCIPRTPOWER          BIT(3)
 609 #define DWC3_OSTS_BSESVLD               BIT(2)
 610 #define DWC3_OSTS_VBUSVLD               BIT(1)
 611 #define DWC3_OSTS_CONIDSTS              BIT(0)
 612 
 613 /* Structures */
 614 
 615 struct dwc3_trb;
 616 
 617 /**
 618  * struct dwc3_event_buffer - Software event buffer representation
 619  * @buf: _THE_ buffer
 620  * @cache: The buffer cache used in the threaded interrupt
 621  * @length: size of this buffer
 622  * @lpos: event offset
 623  * @count: cache of last read event count register
 624  * @flags: flags related to this event buffer
 625  * @dma: dma_addr_t
 626  * @dwc: pointer to DWC controller
 627  */
 628 struct dwc3_event_buffer {
 629         void                    *buf;
 630         void                    *cache;
 631         unsigned                length;
 632         unsigned int            lpos;
 633         unsigned int            count;
 634         unsigned int            flags;
 635 
 636 #define DWC3_EVENT_PENDING      BIT(0)
 637 
 638         dma_addr_t              dma;
 639 
 640         struct dwc3             *dwc;
 641 };
 642 
 643 #define DWC3_EP_FLAG_STALLED    BIT(0)
 644 #define DWC3_EP_FLAG_WEDGED     BIT(1)
 645 
 646 #define DWC3_EP_DIRECTION_TX    true
 647 #define DWC3_EP_DIRECTION_RX    false
 648 
 649 #define DWC3_TRB_NUM            256
 650 
 651 /**
 652  * struct dwc3_ep - device side endpoint representation
 653  * @endpoint: usb endpoint
 654  * @cancelled_list: list of cancelled requests for this endpoint
 655  * @pending_list: list of pending requests for this endpoint
 656  * @started_list: list of started requests on this endpoint
 657  * @regs: pointer to first endpoint register
 658  * @trb_pool: array of transaction buffers
 659  * @trb_pool_dma: dma address of @trb_pool
 660  * @trb_enqueue: enqueue 'pointer' into TRB array
 661  * @trb_dequeue: dequeue 'pointer' into TRB array
 662  * @dwc: pointer to DWC controller
 663  * @saved_state: ep state saved during hibernation
 664  * @flags: endpoint flags (wedged, stalled, ...)
 665  * @number: endpoint number (1 - 15)
 666  * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
 667  * @resource_index: Resource transfer index
 668  * @frame_number: set to the frame number we want this transfer to start (ISOC)
 669  * @interval: the interval on which the ISOC transfer is started
 670  * @name: a human readable name e.g. ep1out-bulk
 671  * @direction: true for TX, false for RX
 672  * @stream_capable: true when streams are enabled
 673  * @combo_num: the test combination BIT[15:14] of the frame number to test
 674  *              isochronous START TRANSFER command failure workaround
 675  * @start_cmd_status: the status of testing START TRANSFER command with
 676  *              combo_num = 'b00
 677  */
 678 struct dwc3_ep {
 679         struct usb_ep           endpoint;
 680         struct list_head        cancelled_list;
 681         struct list_head        pending_list;
 682         struct list_head        started_list;
 683 
 684         void __iomem            *regs;
 685 
 686         struct dwc3_trb         *trb_pool;
 687         dma_addr_t              trb_pool_dma;
 688         struct dwc3             *dwc;
 689 
 690         u32                     saved_state;
 691         unsigned                flags;
 692 #define DWC3_EP_ENABLED         BIT(0)
 693 #define DWC3_EP_STALL           BIT(1)
 694 #define DWC3_EP_WEDGE           BIT(2)
 695 #define DWC3_EP_TRANSFER_STARTED BIT(3)
 696 #define DWC3_EP_END_TRANSFER_PENDING BIT(4)
 697 #define DWC3_EP_PENDING_REQUEST BIT(5)
 698 #define DWC3_EP_DELAY_START     BIT(6)
 699 
 700         /* This last one is specific to EP0 */
 701 #define DWC3_EP0_DIR_IN         BIT(31)
 702 
 703         /*
 704          * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
 705          * use a u8 type here. If anybody decides to increase number of TRBs to
 706          * anything larger than 256 - I can't see why people would want to do
 707          * this though - then this type needs to be changed.
 708          *
 709          * By using u8 types we ensure that our % operator when incrementing
 710          * enqueue and dequeue get optimized away by the compiler.
 711          */
 712         u8                      trb_enqueue;
 713         u8                      trb_dequeue;
 714 
 715         u8                      number;
 716         u8                      type;
 717         u8                      resource_index;
 718         u32                     frame_number;
 719         u32                     interval;
 720 
 721         char                    name[20];
 722 
 723         unsigned                direction:1;
 724         unsigned                stream_capable:1;
 725 
 726         /* For isochronous START TRANSFER workaround only */
 727         u8                      combo_num;
 728         int                     start_cmd_status;
 729 };
 730 
 731 enum dwc3_phy {
 732         DWC3_PHY_UNKNOWN = 0,
 733         DWC3_PHY_USB3,
 734         DWC3_PHY_USB2,
 735 };
 736 
 737 enum dwc3_ep0_next {
 738         DWC3_EP0_UNKNOWN = 0,
 739         DWC3_EP0_COMPLETE,
 740         DWC3_EP0_NRDY_DATA,
 741         DWC3_EP0_NRDY_STATUS,
 742 };
 743 
 744 enum dwc3_ep0_state {
 745         EP0_UNCONNECTED         = 0,
 746         EP0_SETUP_PHASE,
 747         EP0_DATA_PHASE,
 748         EP0_STATUS_PHASE,
 749 };
 750 
 751 enum dwc3_link_state {
 752         /* In SuperSpeed */
 753         DWC3_LINK_STATE_U0              = 0x00, /* in HS, means ON */
 754         DWC3_LINK_STATE_U1              = 0x01,
 755         DWC3_LINK_STATE_U2              = 0x02, /* in HS, means SLEEP */
 756         DWC3_LINK_STATE_U3              = 0x03, /* in HS, means SUSPEND */
 757         DWC3_LINK_STATE_SS_DIS          = 0x04,
 758         DWC3_LINK_STATE_RX_DET          = 0x05, /* in HS, means Early Suspend */
 759         DWC3_LINK_STATE_SS_INACT        = 0x06,
 760         DWC3_LINK_STATE_POLL            = 0x07,
 761         DWC3_LINK_STATE_RECOV           = 0x08,
 762         DWC3_LINK_STATE_HRESET          = 0x09,
 763         DWC3_LINK_STATE_CMPLY           = 0x0a,
 764         DWC3_LINK_STATE_LPBK            = 0x0b,
 765         DWC3_LINK_STATE_RESET           = 0x0e,
 766         DWC3_LINK_STATE_RESUME          = 0x0f,
 767         DWC3_LINK_STATE_MASK            = 0x0f,
 768 };
 769 
 770 /* TRB Length, PCM and Status */
 771 #define DWC3_TRB_SIZE_MASK      (0x00ffffff)
 772 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
 773 #define DWC3_TRB_SIZE_PCM1(n)   (((n) & 0x03) << 24)
 774 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
 775 
 776 #define DWC3_TRBSTS_OK                  0
 777 #define DWC3_TRBSTS_MISSED_ISOC         1
 778 #define DWC3_TRBSTS_SETUP_PENDING       2
 779 #define DWC3_TRB_STS_XFER_IN_PROG       4
 780 
 781 /* TRB Control */
 782 #define DWC3_TRB_CTRL_HWO               BIT(0)
 783 #define DWC3_TRB_CTRL_LST               BIT(1)
 784 #define DWC3_TRB_CTRL_CHN               BIT(2)
 785 #define DWC3_TRB_CTRL_CSP               BIT(3)
 786 #define DWC3_TRB_CTRL_TRBCTL(n)         (((n) & 0x3f) << 4)
 787 #define DWC3_TRB_CTRL_ISP_IMI           BIT(10)
 788 #define DWC3_TRB_CTRL_IOC               BIT(11)
 789 #define DWC3_TRB_CTRL_SID_SOFN(n)       (((n) & 0xffff) << 14)
 790 #define DWC3_TRB_CTRL_GET_SID_SOFN(n)   (((n) & (0xffff << 14)) >> 14)
 791 
 792 #define DWC3_TRBCTL_TYPE(n)             ((n) & (0x3f << 4))
 793 #define DWC3_TRBCTL_NORMAL              DWC3_TRB_CTRL_TRBCTL(1)
 794 #define DWC3_TRBCTL_CONTROL_SETUP       DWC3_TRB_CTRL_TRBCTL(2)
 795 #define DWC3_TRBCTL_CONTROL_STATUS2     DWC3_TRB_CTRL_TRBCTL(3)
 796 #define DWC3_TRBCTL_CONTROL_STATUS3     DWC3_TRB_CTRL_TRBCTL(4)
 797 #define DWC3_TRBCTL_CONTROL_DATA        DWC3_TRB_CTRL_TRBCTL(5)
 798 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST   DWC3_TRB_CTRL_TRBCTL(6)
 799 #define DWC3_TRBCTL_ISOCHRONOUS         DWC3_TRB_CTRL_TRBCTL(7)
 800 #define DWC3_TRBCTL_LINK_TRB            DWC3_TRB_CTRL_TRBCTL(8)
 801 
 802 /**
 803  * struct dwc3_trb - transfer request block (hw format)
 804  * @bpl: DW0-3
 805  * @bph: DW4-7
 806  * @size: DW8-B
 807  * @ctrl: DWC-F
 808  */
 809 struct dwc3_trb {
 810         u32             bpl;
 811         u32             bph;
 812         u32             size;
 813         u32             ctrl;
 814 } __packed;
 815 
 816 /**
 817  * struct dwc3_hwparams - copy of HWPARAMS registers
 818  * @hwparams0: GHWPARAMS0
 819  * @hwparams1: GHWPARAMS1
 820  * @hwparams2: GHWPARAMS2
 821  * @hwparams3: GHWPARAMS3
 822  * @hwparams4: GHWPARAMS4
 823  * @hwparams5: GHWPARAMS5
 824  * @hwparams6: GHWPARAMS6
 825  * @hwparams7: GHWPARAMS7
 826  * @hwparams8: GHWPARAMS8
 827  */
 828 struct dwc3_hwparams {
 829         u32     hwparams0;
 830         u32     hwparams1;
 831         u32     hwparams2;
 832         u32     hwparams3;
 833         u32     hwparams4;
 834         u32     hwparams5;
 835         u32     hwparams6;
 836         u32     hwparams7;
 837         u32     hwparams8;
 838 };
 839 
 840 /* HWPARAMS0 */
 841 #define DWC3_MODE(n)            ((n) & 0x7)
 842 
 843 #define DWC3_MDWIDTH(n)         (((n) & 0xff00) >> 8)
 844 
 845 /* HWPARAMS1 */
 846 #define DWC3_NUM_INT(n)         (((n) & (0x3f << 15)) >> 15)
 847 
 848 /* HWPARAMS3 */
 849 #define DWC3_NUM_IN_EPS_MASK    (0x1f << 18)
 850 #define DWC3_NUM_EPS_MASK       (0x3f << 12)
 851 #define DWC3_NUM_EPS(p)         (((p)->hwparams3 &              \
 852                         (DWC3_NUM_EPS_MASK)) >> 12)
 853 #define DWC3_NUM_IN_EPS(p)      (((p)->hwparams3 &              \
 854                         (DWC3_NUM_IN_EPS_MASK)) >> 18)
 855 
 856 /* HWPARAMS7 */
 857 #define DWC3_RAM1_DEPTH(n)      ((n) & 0xffff)
 858 
 859 /**
 860  * struct dwc3_request - representation of a transfer request
 861  * @request: struct usb_request to be transferred
 862  * @list: a list_head used for request queueing
 863  * @dep: struct dwc3_ep owning this request
 864  * @sg: pointer to first incomplete sg
 865  * @start_sg: pointer to the sg which should be queued next
 866  * @num_pending_sgs: counter to pending sgs
 867  * @num_queued_sgs: counter to the number of sgs which already got queued
 868  * @remaining: amount of data remaining
 869  * @status: internal dwc3 request status tracking
 870  * @epnum: endpoint number to which this request refers
 871  * @trb: pointer to struct dwc3_trb
 872  * @trb_dma: DMA address of @trb
 873  * @num_trbs: number of TRBs used by this request
 874  * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP
 875  *      or unaligned OUT)
 876  * @direction: IN or OUT direction flag
 877  * @mapped: true when request has been dma-mapped
 878  */
 879 struct dwc3_request {
 880         struct usb_request      request;
 881         struct list_head        list;
 882         struct dwc3_ep          *dep;
 883         struct scatterlist      *sg;
 884         struct scatterlist      *start_sg;
 885 
 886         unsigned                num_pending_sgs;
 887         unsigned int            num_queued_sgs;
 888         unsigned                remaining;
 889 
 890         unsigned int            status;
 891 #define DWC3_REQUEST_STATUS_QUEUED      0
 892 #define DWC3_REQUEST_STATUS_STARTED     1
 893 #define DWC3_REQUEST_STATUS_CANCELLED   2
 894 #define DWC3_REQUEST_STATUS_COMPLETED   3
 895 #define DWC3_REQUEST_STATUS_UNKNOWN     -1
 896 
 897         u8                      epnum;
 898         struct dwc3_trb         *trb;
 899         dma_addr_t              trb_dma;
 900 
 901         unsigned                num_trbs;
 902 
 903         unsigned                needs_extra_trb:1;
 904         unsigned                direction:1;
 905         unsigned                mapped:1;
 906 };
 907 
 908 /*
 909  * struct dwc3_scratchpad_array - hibernation scratchpad array
 910  * (format defined by hw)
 911  */
 912 struct dwc3_scratchpad_array {
 913         __le64  dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
 914 };
 915 
 916 /**
 917  * struct dwc3 - representation of our controller
 918  * @drd_work: workqueue used for role swapping
 919  * @ep0_trb: trb which is used for the ctrl_req
 920  * @bounce: address of bounce buffer
 921  * @scratchbuf: address of scratch buffer
 922  * @setup_buf: used while precessing STD USB requests
 923  * @ep0_trb_addr: dma address of @ep0_trb
 924  * @bounce_addr: dma address of @bounce
 925  * @ep0_usb_req: dummy req used while handling STD USB requests
 926  * @scratch_addr: dma address of scratchbuf
 927  * @ep0_in_setup: one control transfer is completed and enter setup phase
 928  * @lock: for synchronizing
 929  * @dev: pointer to our struct device
 930  * @sysdev: pointer to the DMA-capable device
 931  * @xhci: pointer to our xHCI child
 932  * @xhci_resources: struct resources for our @xhci child
 933  * @ev_buf: struct dwc3_event_buffer pointer
 934  * @eps: endpoint array
 935  * @gadget: device side representation of the peripheral controller
 936  * @gadget_driver: pointer to the gadget driver
 937  * @clks: array of clocks
 938  * @num_clks: number of clocks
 939  * @reset: reset control
 940  * @regs: base address for our registers
 941  * @regs_size: address space size
 942  * @fladj: frame length adjustment
 943  * @irq_gadget: peripheral controller's IRQ number
 944  * @otg_irq: IRQ number for OTG IRQs
 945  * @current_otg_role: current role of operation while using the OTG block
 946  * @desired_otg_role: desired role of operation while using the OTG block
 947  * @otg_restart_host: flag that OTG controller needs to restart host
 948  * @nr_scratch: number of scratch buffers
 949  * @u1u2: only used on revisions <1.83a for workaround
 950  * @maximum_speed: maximum speed requested (mainly for testing purposes)
 951  * @revision: revision register contents
 952  * @version_type: VERSIONTYPE register contents, a sub release of a revision
 953  * @dr_mode: requested mode of operation
 954  * @current_dr_role: current role of operation when in dual-role mode
 955  * @desired_dr_role: desired role of operation when in dual-role mode
 956  * @edev: extcon handle
 957  * @edev_nb: extcon notifier
 958  * @hsphy_mode: UTMI phy mode, one of following:
 959  *              - USBPHY_INTERFACE_MODE_UTMI
 960  *              - USBPHY_INTERFACE_MODE_UTMIW
 961  * @usb2_phy: pointer to USB2 PHY
 962  * @usb3_phy: pointer to USB3 PHY
 963  * @usb2_generic_phy: pointer to USB2 PHY
 964  * @usb3_generic_phy: pointer to USB3 PHY
 965  * @phys_ready: flag to indicate that PHYs are ready
 966  * @ulpi: pointer to ulpi interface
 967  * @ulpi_ready: flag to indicate that ULPI is initialized
 968  * @u2sel: parameter from Set SEL request.
 969  * @u2pel: parameter from Set SEL request.
 970  * @u1sel: parameter from Set SEL request.
 971  * @u1pel: parameter from Set SEL request.
 972  * @num_eps: number of endpoints
 973  * @ep0_next_event: hold the next expected event
 974  * @ep0state: state of endpoint zero
 975  * @link_state: link state
 976  * @speed: device speed (super, high, full, low)
 977  * @hwparams: copy of hwparams registers
 978  * @root: debugfs root folder pointer
 979  * @regset: debugfs pointer to regdump file
 980  * @dbg_lsp_select: current debug lsp mux register selection
 981  * @test_mode: true when we're entering a USB test mode
 982  * @test_mode_nr: test feature selector
 983  * @lpm_nyet_threshold: LPM NYET response threshold
 984  * @hird_threshold: HIRD threshold
 985  * @rx_thr_num_pkt_prd: periodic ESS receive packet count
 986  * @rx_max_burst_prd: max periodic ESS receive burst size
 987  * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
 988  * @tx_max_burst_prd: max periodic ESS transmit burst size
 989  * @hsphy_interface: "utmi" or "ulpi"
 990  * @connected: true when we're connected to a host, false otherwise
 991  * @delayed_status: true when gadget driver asks for delayed status
 992  * @ep0_bounced: true when we used bounce buffer
 993  * @ep0_expect_in: true when we expect a DATA IN transfer
 994  * @has_hibernation: true when dwc3 was configured with Hibernation
 995  * @sysdev_is_parent: true when dwc3 device has a parent driver
 996  * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
 997  *                      there's now way for software to detect this in runtime.
 998  * @is_utmi_l1_suspend: the core asserts output signal
 999  *      0       - utmi_sleep_n
1000  *      1       - utmi_l1_suspend_n
1001  * @is_fpga: true when we are using the FPGA board
1002  * @pending_events: true when we have pending IRQs to be handled
1003  * @pullups_connected: true when Run/Stop bit is set
1004  * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
1005  * @three_stage_setup: set if we perform a three phase setup
1006  * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is
1007  *                      not needed for DWC_usb31 version 1.70a-ea06 and below
1008  * @usb3_lpm_capable: set if hadrware supports Link Power Management
1009  * @usb2_lpm_disable: set to disable usb2 lpm
1010  * @disable_scramble_quirk: set if we enable the disable scramble quirk
1011  * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
1012  * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
1013  * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
1014  * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
1015  * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
1016  * @lfps_filter_quirk: set if we enable LFPS filter quirk
1017  * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
1018  * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
1019  * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
1020  * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
1021  *                      disabling the suspend signal to the PHY.
1022  * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled.
1023  * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled.
1024  * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
1025  * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
1026  *                      in GUSB2PHYCFG, specify that USB2 PHY doesn't
1027  *                      provide a free-running PHY clock.
1028  * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
1029  *                      change quirk.
1030  * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
1031  *                      check during HS transmit.
1032  * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
1033  *                      instances in park mode.
1034  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
1035  * @tx_de_emphasis: Tx de-emphasis value
1036  *      0       - -6dB de-emphasis
1037  *      1       - -3.5dB de-emphasis
1038  *      2       - No de-emphasis
1039  *      3       - Reserved
1040  * @dis_metastability_quirk: set to disable metastability quirk.
1041  * @imod_interval: set the interrupt moderation interval in 250ns
1042  *                 increments or 0 to disable.
1043  */
1044 struct dwc3 {
1045         struct work_struct      drd_work;
1046         struct dwc3_trb         *ep0_trb;
1047         void                    *bounce;
1048         void                    *scratchbuf;
1049         u8                      *setup_buf;
1050         dma_addr_t              ep0_trb_addr;
1051         dma_addr_t              bounce_addr;
1052         dma_addr_t              scratch_addr;
1053         struct dwc3_request     ep0_usb_req;
1054         struct completion       ep0_in_setup;
1055 
1056         /* device lock */
1057         spinlock_t              lock;
1058 
1059         struct device           *dev;
1060         struct device           *sysdev;
1061 
1062         struct platform_device  *xhci;
1063         struct resource         xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1064 
1065         struct dwc3_event_buffer *ev_buf;
1066         struct dwc3_ep          *eps[DWC3_ENDPOINTS_NUM];
1067 
1068         struct usb_gadget       gadget;
1069         struct usb_gadget_driver *gadget_driver;
1070 
1071         struct clk_bulk_data    *clks;
1072         int                     num_clks;
1073 
1074         struct reset_control    *reset;
1075 
1076         struct usb_phy          *usb2_phy;
1077         struct usb_phy          *usb3_phy;
1078 
1079         struct phy              *usb2_generic_phy;
1080         struct phy              *usb3_generic_phy;
1081 
1082         bool                    phys_ready;
1083 
1084         struct ulpi             *ulpi;
1085         bool                    ulpi_ready;
1086 
1087         void __iomem            *regs;
1088         size_t                  regs_size;
1089 
1090         enum usb_dr_mode        dr_mode;
1091         u32                     current_dr_role;
1092         u32                     desired_dr_role;
1093         struct extcon_dev       *edev;
1094         struct notifier_block   edev_nb;
1095         enum usb_phy_interface  hsphy_mode;
1096 
1097         u32                     fladj;
1098         u32                     irq_gadget;
1099         u32                     otg_irq;
1100         u32                     current_otg_role;
1101         u32                     desired_otg_role;
1102         bool                    otg_restart_host;
1103         u32                     nr_scratch;
1104         u32                     u1u2;
1105         u32                     maximum_speed;
1106 
1107         /*
1108          * All 3.1 IP version constants are greater than the 3.0 IP
1109          * version constants. This works for most version checks in
1110          * dwc3. However, in the future, this may not apply as
1111          * features may be developed on newer versions of the 3.0 IP
1112          * that are not in the 3.1 IP.
1113          */
1114         u32                     revision;
1115 
1116 #define DWC3_REVISION_173A      0x5533173a
1117 #define DWC3_REVISION_175A      0x5533175a
1118 #define DWC3_REVISION_180A      0x5533180a
1119 #define DWC3_REVISION_183A      0x5533183a
1120 #define DWC3_REVISION_185A      0x5533185a
1121 #define DWC3_REVISION_187A      0x5533187a
1122 #define DWC3_REVISION_188A      0x5533188a
1123 #define DWC3_REVISION_190A      0x5533190a
1124 #define DWC3_REVISION_194A      0x5533194a
1125 #define DWC3_REVISION_200A      0x5533200a
1126 #define DWC3_REVISION_202A      0x5533202a
1127 #define DWC3_REVISION_210A      0x5533210a
1128 #define DWC3_REVISION_220A      0x5533220a
1129 #define DWC3_REVISION_230A      0x5533230a
1130 #define DWC3_REVISION_240A      0x5533240a
1131 #define DWC3_REVISION_250A      0x5533250a
1132 #define DWC3_REVISION_260A      0x5533260a
1133 #define DWC3_REVISION_270A      0x5533270a
1134 #define DWC3_REVISION_280A      0x5533280a
1135 #define DWC3_REVISION_290A      0x5533290a
1136 #define DWC3_REVISION_300A      0x5533300a
1137 #define DWC3_REVISION_310A      0x5533310a
1138 #define DWC3_REVISION_330A      0x5533330a
1139 
1140 /*
1141  * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
1142  * just so dwc31 revisions are always larger than dwc3.
1143  */
1144 #define DWC3_REVISION_IS_DWC31          0x80000000
1145 #define DWC3_USB31_REVISION_110A        (0x3131302a | DWC3_REVISION_IS_DWC31)
1146 #define DWC3_USB31_REVISION_120A        (0x3132302a | DWC3_REVISION_IS_DWC31)
1147 #define DWC3_USB31_REVISION_160A        (0x3136302a | DWC3_REVISION_IS_DWC31)
1148 #define DWC3_USB31_REVISION_170A        (0x3137302a | DWC3_REVISION_IS_DWC31)
1149 #define DWC3_USB31_REVISION_180A        (0x3138302a | DWC3_REVISION_IS_DWC31)
1150 #define DWC3_USB31_REVISION_190A        (0x3139302a | DWC3_REVISION_IS_DWC31)
1151 
1152         u32                     version_type;
1153 
1154 #define DWC31_VERSIONTYPE_EA01          0x65613031
1155 #define DWC31_VERSIONTYPE_EA02          0x65613032
1156 #define DWC31_VERSIONTYPE_EA03          0x65613033
1157 #define DWC31_VERSIONTYPE_EA04          0x65613034
1158 #define DWC31_VERSIONTYPE_EA05          0x65613035
1159 #define DWC31_VERSIONTYPE_EA06          0x65613036
1160 
1161         enum dwc3_ep0_next      ep0_next_event;
1162         enum dwc3_ep0_state     ep0state;
1163         enum dwc3_link_state    link_state;
1164 
1165         u16                     u2sel;
1166         u16                     u2pel;
1167         u8                      u1sel;
1168         u8                      u1pel;
1169 
1170         u8                      speed;
1171 
1172         u8                      num_eps;
1173 
1174         struct dwc3_hwparams    hwparams;
1175         struct dentry           *root;
1176         struct debugfs_regset32 *regset;
1177 
1178         u32                     dbg_lsp_select;
1179 
1180         u8                      test_mode;
1181         u8                      test_mode_nr;
1182         u8                      lpm_nyet_threshold;
1183         u8                      hird_threshold;
1184         u8                      rx_thr_num_pkt_prd;
1185         u8                      rx_max_burst_prd;
1186         u8                      tx_thr_num_pkt_prd;
1187         u8                      tx_max_burst_prd;
1188 
1189         const char              *hsphy_interface;
1190 
1191         unsigned                connected:1;
1192         unsigned                delayed_status:1;
1193         unsigned                ep0_bounced:1;
1194         unsigned                ep0_expect_in:1;
1195         unsigned                has_hibernation:1;
1196         unsigned                sysdev_is_parent:1;
1197         unsigned                has_lpm_erratum:1;
1198         unsigned                is_utmi_l1_suspend:1;
1199         unsigned                is_fpga:1;
1200         unsigned                pending_events:1;
1201         unsigned                pullups_connected:1;
1202         unsigned                setup_packet_pending:1;
1203         unsigned                three_stage_setup:1;
1204         unsigned                dis_start_transfer_quirk:1;
1205         unsigned                usb3_lpm_capable:1;
1206         unsigned                usb2_lpm_disable:1;
1207 
1208         unsigned                disable_scramble_quirk:1;
1209         unsigned                u2exit_lfps_quirk:1;
1210         unsigned                u2ss_inp3_quirk:1;
1211         unsigned                req_p1p2p3_quirk:1;
1212         unsigned                del_p1p2p3_quirk:1;
1213         unsigned                del_phy_power_chg_quirk:1;
1214         unsigned                lfps_filter_quirk:1;
1215         unsigned                rx_detect_poll_quirk:1;
1216         unsigned                dis_u3_susphy_quirk:1;
1217         unsigned                dis_u2_susphy_quirk:1;
1218         unsigned                dis_enblslpm_quirk:1;
1219         unsigned                dis_u1_entry_quirk:1;
1220         unsigned                dis_u2_entry_quirk:1;
1221         unsigned                dis_rxdet_inp3_quirk:1;
1222         unsigned                dis_u2_freeclk_exists_quirk:1;
1223         unsigned                dis_del_phy_power_chg_quirk:1;
1224         unsigned                dis_tx_ipgap_linecheck_quirk:1;
1225         unsigned                parkmode_disable_ss_quirk:1;
1226 
1227         unsigned                tx_de_emphasis_quirk:1;
1228         unsigned                tx_de_emphasis:2;
1229 
1230         unsigned                dis_metastability_quirk:1;
1231 
1232         u16                     imod_interval;
1233 };
1234 
1235 #define INCRX_BURST_MODE 0
1236 #define INCRX_UNDEF_LENGTH_BURST_MODE 1
1237 
1238 #define work_to_dwc(w)          (container_of((w), struct dwc3, drd_work))
1239 
1240 /* -------------------------------------------------------------------------- */
1241 
1242 struct dwc3_event_type {
1243         u32     is_devspec:1;
1244         u32     type:7;
1245         u32     reserved8_31:24;
1246 } __packed;
1247 
1248 #define DWC3_DEPEVT_XFERCOMPLETE        0x01
1249 #define DWC3_DEPEVT_XFERINPROGRESS      0x02
1250 #define DWC3_DEPEVT_XFERNOTREADY        0x03
1251 #define DWC3_DEPEVT_RXTXFIFOEVT         0x04
1252 #define DWC3_DEPEVT_STREAMEVT           0x06
1253 #define DWC3_DEPEVT_EPCMDCMPLT          0x07
1254 
1255 /**
1256  * struct dwc3_event_depvt - Device Endpoint Events
1257  * @one_bit: indicates this is an endpoint event (not used)
1258  * @endpoint_number: number of the endpoint
1259  * @endpoint_event: The event we have:
1260  *      0x00    - Reserved
1261  *      0x01    - XferComplete
1262  *      0x02    - XferInProgress
1263  *      0x03    - XferNotReady
1264  *      0x04    - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1265  *      0x05    - Reserved
1266  *      0x06    - StreamEvt
1267  *      0x07    - EPCmdCmplt
1268  * @reserved11_10: Reserved, don't use.
1269  * @status: Indicates the status of the event. Refer to databook for
1270  *      more information.
1271  * @parameters: Parameters of the current event. Refer to databook for
1272  *      more information.
1273  */
1274 struct dwc3_event_depevt {
1275         u32     one_bit:1;
1276         u32     endpoint_number:5;
1277         u32     endpoint_event:4;
1278         u32     reserved11_10:2;
1279         u32     status:4;
1280 
1281 /* Within XferNotReady */
1282 #define DEPEVT_STATUS_TRANSFER_ACTIVE   BIT(3)
1283 
1284 /* Within XferComplete or XferInProgress */
1285 #define DEPEVT_STATUS_BUSERR    BIT(0)
1286 #define DEPEVT_STATUS_SHORT     BIT(1)
1287 #define DEPEVT_STATUS_IOC       BIT(2)
1288 #define DEPEVT_STATUS_LST       BIT(3) /* XferComplete */
1289 #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */
1290 
1291 /* Stream event only */
1292 #define DEPEVT_STREAMEVT_FOUND          1
1293 #define DEPEVT_STREAMEVT_NOTFOUND       2
1294 
1295 /* Control-only Status */
1296 #define DEPEVT_STATUS_CONTROL_DATA      1
1297 #define DEPEVT_STATUS_CONTROL_STATUS    2
1298 #define DEPEVT_STATUS_CONTROL_PHASE(n)  ((n) & 3)
1299 
1300 /* In response to Start Transfer */
1301 #define DEPEVT_TRANSFER_NO_RESOURCE     1
1302 #define DEPEVT_TRANSFER_BUS_EXPIRY      2
1303 
1304         u32     parameters:16;
1305 
1306 /* For Command Complete Events */
1307 #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1308 } __packed;
1309 
1310 /**
1311  * struct dwc3_event_devt - Device Events
1312  * @one_bit: indicates this is a non-endpoint event (not used)
1313  * @device_event: indicates it's a device event. Should read as 0x00
1314  * @type: indicates the type of device event.
1315  *      0       - DisconnEvt
1316  *      1       - USBRst
1317  *      2       - ConnectDone
1318  *      3       - ULStChng
1319  *      4       - WkUpEvt
1320  *      5       - Reserved
1321  *      6       - EOPF
1322  *      7       - SOF
1323  *      8       - Reserved
1324  *      9       - ErrticErr
1325  *      10      - CmdCmplt
1326  *      11      - EvntOverflow
1327  *      12      - VndrDevTstRcved
1328  * @reserved15_12: Reserved, not used
1329  * @event_info: Information about this event
1330  * @reserved31_25: Reserved, not used
1331  */
1332 struct dwc3_event_devt {
1333         u32     one_bit:1;
1334         u32     device_event:7;
1335         u32     type:4;
1336         u32     reserved15_12:4;
1337         u32     event_info:9;
1338         u32     reserved31_25:7;
1339 } __packed;
1340 
1341 /**
1342  * struct dwc3_event_gevt - Other Core Events
1343  * @one_bit: indicates this is a non-endpoint event (not used)
1344  * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1345  * @phy_port_number: self-explanatory
1346  * @reserved31_12: Reserved, not used.
1347  */
1348 struct dwc3_event_gevt {
1349         u32     one_bit:1;
1350         u32     device_event:7;
1351         u32     phy_port_number:4;
1352         u32     reserved31_12:20;
1353 } __packed;
1354 
1355 /**
1356  * union dwc3_event - representation of Event Buffer contents
1357  * @raw: raw 32-bit event
1358  * @type: the type of the event
1359  * @depevt: Device Endpoint Event
1360  * @devt: Device Event
1361  * @gevt: Global Event
1362  */
1363 union dwc3_event {
1364         u32                             raw;
1365         struct dwc3_event_type          type;
1366         struct dwc3_event_depevt        depevt;
1367         struct dwc3_event_devt          devt;
1368         struct dwc3_event_gevt          gevt;
1369 };
1370 
1371 /**
1372  * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1373  * parameters
1374  * @param2: third parameter
1375  * @param1: second parameter
1376  * @param0: first parameter
1377  */
1378 struct dwc3_gadget_ep_cmd_params {
1379         u32     param2;
1380         u32     param1;
1381         u32     param0;
1382 };
1383 
1384 /*
1385  * DWC3 Features to be used as Driver Data
1386  */
1387 
1388 #define DWC3_HAS_PERIPHERAL             BIT(0)
1389 #define DWC3_HAS_XHCI                   BIT(1)
1390 #define DWC3_HAS_OTG                    BIT(3)
1391 
1392 /* prototypes */
1393 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1394 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1395 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1396 
1397 /* check whether we are on the DWC_usb3 core */
1398 static inline bool dwc3_is_usb3(struct dwc3 *dwc)
1399 {
1400         return !(dwc->revision & DWC3_REVISION_IS_DWC31);
1401 }
1402 
1403 /* check whether we are on the DWC_usb31 core */
1404 static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1405 {
1406         return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1407 }
1408 
1409 bool dwc3_has_imod(struct dwc3 *dwc);
1410 
1411 int dwc3_event_buffers_setup(struct dwc3 *dwc);
1412 void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1413 
1414 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1415 int dwc3_host_init(struct dwc3 *dwc);
1416 void dwc3_host_exit(struct dwc3 *dwc);
1417 #else
1418 static inline int dwc3_host_init(struct dwc3 *dwc)
1419 { return 0; }
1420 static inline void dwc3_host_exit(struct dwc3 *dwc)
1421 { }
1422 #endif
1423 
1424 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1425 int dwc3_gadget_init(struct dwc3 *dwc);
1426 void dwc3_gadget_exit(struct dwc3 *dwc);
1427 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1428 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1429 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1430 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1431                 struct dwc3_gadget_ep_cmd_params *params);
1432 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1433 #else
1434 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1435 { return 0; }
1436 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1437 { }
1438 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1439 { return 0; }
1440 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1441 { return 0; }
1442 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1443                 enum dwc3_link_state state)
1444 { return 0; }
1445 
1446 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1447                 struct dwc3_gadget_ep_cmd_params *params)
1448 { return 0; }
1449 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1450                 int cmd, u32 param)
1451 { return 0; }
1452 #endif
1453 
1454 #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1455 int dwc3_drd_init(struct dwc3 *dwc);
1456 void dwc3_drd_exit(struct dwc3 *dwc);
1457 void dwc3_otg_init(struct dwc3 *dwc);
1458 void dwc3_otg_exit(struct dwc3 *dwc);
1459 void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1460 void dwc3_otg_host_init(struct dwc3 *dwc);
1461 #else
1462 static inline int dwc3_drd_init(struct dwc3 *dwc)
1463 { return 0; }
1464 static inline void dwc3_drd_exit(struct dwc3 *dwc)
1465 { }
1466 static inline void dwc3_otg_init(struct dwc3 *dwc)
1467 { }
1468 static inline void dwc3_otg_exit(struct dwc3 *dwc)
1469 { }
1470 static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1471 { }
1472 static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1473 { }
1474 #endif
1475 
1476 /* power management interface */
1477 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1478 int dwc3_gadget_suspend(struct dwc3 *dwc);
1479 int dwc3_gadget_resume(struct dwc3 *dwc);
1480 void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1481 #else
1482 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1483 {
1484         return 0;
1485 }
1486 
1487 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1488 {
1489         return 0;
1490 }
1491 
1492 static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1493 {
1494 }
1495 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1496 
1497 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1498 int dwc3_ulpi_init(struct dwc3 *dwc);
1499 void dwc3_ulpi_exit(struct dwc3 *dwc);
1500 #else
1501 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1502 { return 0; }
1503 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1504 { }
1505 #endif
1506 
1507 #endif /* __DRIVERS_USB_DWC3_CORE_H */
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