drivers/usb/dwc3/core.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
dwc3_get_dr_mode
dwc3_set_prtcap
__dwc3_set_mode
dwc3_set_mode
dwc3_core_fifo_space
dwc3_core_soft_reset
dwc3_frame_length_adjustment
dwc3_free_one_event_buffer
dwc3_alloc_one_event_buffer
dwc3_free_event_buffers
dwc3_alloc_event_buffers
dwc3_event_buffers_setup
dwc3_event_buffers_cleanup
dwc3_alloc_scratch_buffers
dwc3_setup_scratch_buffers
dwc3_free_scratch_buffers
dwc3_core_num_eps
dwc3_cache_hwparams
dwc3_core_ulpi_init
dwc3_phy_setup
dwc3_core_exit
dwc3_core_is_valid
dwc3_core_setup_global_control
dwc3_set_incr_burst_type
dwc3_core_init
dwc3_core_get_phy
dwc3_core_init_mode
dwc3_core_exit_mode
dwc3_get_properties
dwc3_has_imod
dwc3_check_params
dwc3_probe
dwc3_remove
dwc3_core_init_for_resume
dwc3_suspend_common
dwc3_resume_common
dwc3_runtime_checks
dwc3_runtime_suspend
dwc3_runtime_resume
dwc3_runtime_idle
dwc3_suspend
dwc3_resume
   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10 
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/acpi.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/reset.h>
  29 
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32 #include <linux/usb/of.h>
  33 #include <linux/usb/otg.h>
  34 
  35 #include "core.h"
  36 #include "gadget.h"
  37 #include "io.h"
  38 
  39 #include "debug.h"
  40 
  41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  42 
  43 /**
  44  * dwc3_get_dr_mode - Validates and sets dr_mode
  45  * @dwc: pointer to our context structure
  46  */
  47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  48 {
  49         enum usb_dr_mode mode;
  50         struct device *dev = dwc->dev;
  51         unsigned int hw_mode;
  52 
  53         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  54                 dwc->dr_mode = USB_DR_MODE_OTG;
  55 
  56         mode = dwc->dr_mode;
  57         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  58 
  59         switch (hw_mode) {
  60         case DWC3_GHWPARAMS0_MODE_GADGET:
  61                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  62                         dev_err(dev,
  63                                 "Controller does not support host mode.\n");
  64                         return -EINVAL;
  65                 }
  66                 mode = USB_DR_MODE_PERIPHERAL;
  67                 break;
  68         case DWC3_GHWPARAMS0_MODE_HOST:
  69                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  70                         dev_err(dev,
  71                                 "Controller does not support device mode.\n");
  72                         return -EINVAL;
  73                 }
  74                 mode = USB_DR_MODE_HOST;
  75                 break;
  76         default:
  77                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  78                         mode = USB_DR_MODE_HOST;
  79                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  80                         mode = USB_DR_MODE_PERIPHERAL;
  81 
  82                 /*
  83                  * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
  84                  * mode. If the controller supports DRD but the dr_mode is not
  85                  * specified or set to OTG, then set the mode to peripheral.
  86                  */
  87                 if (mode == USB_DR_MODE_OTG &&
  88                     dwc->revision >= DWC3_REVISION_330A)
  89                         mode = USB_DR_MODE_PERIPHERAL;
  90         }
  91 
  92         if (mode != dwc->dr_mode) {
  93                 dev_warn(dev,
  94                          "Configuration mismatch. dr_mode forced to %s\n",
  95                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  96 
  97                 dwc->dr_mode = mode;
  98         }
  99 
 100         return 0;
 101 }
 102 
 103 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 104 {
 105         u32 reg;
 106 
 107         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 108         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 109         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 110         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 111 
 112         dwc->current_dr_role = mode;
 113 }
 114 
 115 static void __dwc3_set_mode(struct work_struct *work)
 116 {
 117         struct dwc3 *dwc = work_to_dwc(work);
 118         unsigned long flags;
 119         int ret;
 120 
 121         if (dwc->dr_mode != USB_DR_MODE_OTG)
 122                 return;
 123 
 124         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 125                 dwc3_otg_update(dwc, 0);
 126 
 127         if (!dwc->desired_dr_role)
 128                 return;
 129 
 130         if (dwc->desired_dr_role == dwc->current_dr_role)
 131                 return;
 132 
 133         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 134                 return;
 135 
 136         switch (dwc->current_dr_role) {
 137         case DWC3_GCTL_PRTCAP_HOST:
 138                 dwc3_host_exit(dwc);
 139                 break;
 140         case DWC3_GCTL_PRTCAP_DEVICE:
 141                 dwc3_gadget_exit(dwc);
 142                 dwc3_event_buffers_cleanup(dwc);
 143                 break;
 144         case DWC3_GCTL_PRTCAP_OTG:
 145                 dwc3_otg_exit(dwc);
 146                 spin_lock_irqsave(&dwc->lock, flags);
 147                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 148                 spin_unlock_irqrestore(&dwc->lock, flags);
 149                 dwc3_otg_update(dwc, 1);
 150                 break;
 151         default:
 152                 break;
 153         }
 154 
 155         spin_lock_irqsave(&dwc->lock, flags);
 156 
 157         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 158 
 159         spin_unlock_irqrestore(&dwc->lock, flags);
 160 
 161         switch (dwc->desired_dr_role) {
 162         case DWC3_GCTL_PRTCAP_HOST:
 163                 ret = dwc3_host_init(dwc);
 164                 if (ret) {
 165                         dev_err(dwc->dev, "failed to initialize host\n");
 166                 } else {
 167                         if (dwc->usb2_phy)
 168                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 169                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 170                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 171                 }
 172                 break;
 173         case DWC3_GCTL_PRTCAP_DEVICE:
 174                 dwc3_event_buffers_setup(dwc);
 175 
 176                 if (dwc->usb2_phy)
 177                         otg_set_vbus(dwc->usb2_phy->otg, false);
 178                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 179                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 180 
 181                 ret = dwc3_gadget_init(dwc);
 182                 if (ret)
 183                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 184                 break;
 185         case DWC3_GCTL_PRTCAP_OTG:
 186                 dwc3_otg_init(dwc);
 187                 dwc3_otg_update(dwc, 0);
 188                 break;
 189         default:
 190                 break;
 191         }
 192 
 193 }
 194 
 195 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 196 {
 197         unsigned long flags;
 198 
 199         spin_lock_irqsave(&dwc->lock, flags);
 200         dwc->desired_dr_role = mode;
 201         spin_unlock_irqrestore(&dwc->lock, flags);
 202 
 203         queue_work(system_freezable_wq, &dwc->drd_work);
 204 }
 205 
 206 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 207 {
 208         struct dwc3             *dwc = dep->dwc;
 209         u32                     reg;
 210 
 211         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 212                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 213                         DWC3_GDBGFIFOSPACE_TYPE(type));
 214 
 215         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 216 
 217         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 218 }
 219 
 220 /**
 221  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 222  * @dwc: pointer to our context structure
 223  */
 224 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 225 {
 226         u32             reg;
 227         int             retries = 1000;
 228         int             ret;
 229 
 230         usb_phy_init(dwc->usb2_phy);
 231         usb_phy_init(dwc->usb3_phy);
 232         ret = phy_init(dwc->usb2_generic_phy);
 233         if (ret < 0)
 234                 return ret;
 235 
 236         ret = phy_init(dwc->usb3_generic_phy);
 237         if (ret < 0) {
 238                 phy_exit(dwc->usb2_generic_phy);
 239                 return ret;
 240         }
 241 
 242         /*
 243          * We're resetting only the device side because, if we're in host mode,
 244          * XHCI driver will reset the host block. If dwc3 was configured for
 245          * host-only mode, then we can return early.
 246          */
 247         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 248                 return 0;
 249 
 250         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 251         reg |= DWC3_DCTL_CSFTRST;
 252         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 253 
 254         /*
 255          * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
 256          * is cleared only after all the clocks are synchronized. This can
 257          * take a little more than 50ms. Set the polling rate at 20ms
 258          * for 10 times instead.
 259          */
 260         if (dwc3_is_usb31(dwc) && dwc->revision >= DWC3_USB31_REVISION_190A)
 261                 retries = 10;
 262 
 263         do {
 264                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 265                 if (!(reg & DWC3_DCTL_CSFTRST))
 266                         goto done;
 267 
 268                 if (dwc3_is_usb31(dwc) &&
 269                     dwc->revision >= DWC3_USB31_REVISION_190A)
 270                         msleep(20);
 271                 else
 272                         udelay(1);
 273         } while (--retries);
 274 
 275         phy_exit(dwc->usb3_generic_phy);
 276         phy_exit(dwc->usb2_generic_phy);
 277 
 278         return -ETIMEDOUT;
 279 
 280 done:
 281         /*
 282          * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
 283          * is cleared, we must wait at least 50ms before accessing the PHY
 284          * domain (synchronization delay).
 285          */
 286         if (dwc3_is_usb31(dwc) && dwc->revision <= DWC3_USB31_REVISION_180A)
 287                 msleep(50);
 288 
 289         return 0;
 290 }
 291 
 292 static const struct clk_bulk_data dwc3_core_clks[] = {
 293         { .id = "ref" },
 294         { .id = "bus_early" },
 295         { .id = "suspend" },
 296 };
 297 
 298 /*
 299  * dwc3_frame_length_adjustment - Adjusts frame length if required
 300  * @dwc3: Pointer to our controller context structure
 301  */
 302 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 303 {
 304         u32 reg;
 305         u32 dft;
 306 
 307         if (dwc->revision < DWC3_REVISION_250A)
 308                 return;
 309 
 310         if (dwc->fladj == 0)
 311                 return;
 312 
 313         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 314         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 315         if (dft != dwc->fladj) {
 316                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 317                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 318                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 319         }
 320 }
 321 
 322 /**
 323  * dwc3_free_one_event_buffer - Frees one event buffer
 324  * @dwc: Pointer to our controller context structure
 325  * @evt: Pointer to event buffer to be freed
 326  */
 327 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 328                 struct dwc3_event_buffer *evt)
 329 {
 330         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 331 }
 332 
 333 /**
 334  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 335  * @dwc: Pointer to our controller context structure
 336  * @length: size of the event buffer
 337  *
 338  * Returns a pointer to the allocated event buffer structure on success
 339  * otherwise ERR_PTR(errno).
 340  */
 341 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 342                 unsigned length)
 343 {
 344         struct dwc3_event_buffer        *evt;
 345 
 346         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 347         if (!evt)
 348                 return ERR_PTR(-ENOMEM);
 349 
 350         evt->dwc        = dwc;
 351         evt->length     = length;
 352         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 353         if (!evt->cache)
 354                 return ERR_PTR(-ENOMEM);
 355 
 356         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 357                         &evt->dma, GFP_KERNEL);
 358         if (!evt->buf)
 359                 return ERR_PTR(-ENOMEM);
 360 
 361         return evt;
 362 }
 363 
 364 /**
 365  * dwc3_free_event_buffers - frees all allocated event buffers
 366  * @dwc: Pointer to our controller context structure
 367  */
 368 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 369 {
 370         struct dwc3_event_buffer        *evt;
 371 
 372         evt = dwc->ev_buf;
 373         if (evt)
 374                 dwc3_free_one_event_buffer(dwc, evt);
 375 }
 376 
 377 /**
 378  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 379  * @dwc: pointer to our controller context structure
 380  * @length: size of event buffer
 381  *
 382  * Returns 0 on success otherwise negative errno. In the error case, dwc
 383  * may contain some buffers allocated but not all which were requested.
 384  */
 385 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 386 {
 387         struct dwc3_event_buffer *evt;
 388 
 389         evt = dwc3_alloc_one_event_buffer(dwc, length);
 390         if (IS_ERR(evt)) {
 391                 dev_err(dwc->dev, "can't allocate event buffer\n");
 392                 return PTR_ERR(evt);
 393         }
 394         dwc->ev_buf = evt;
 395 
 396         return 0;
 397 }
 398 
 399 /**
 400  * dwc3_event_buffers_setup - setup our allocated event buffers
 401  * @dwc: pointer to our controller context structure
 402  *
 403  * Returns 0 on success otherwise negative errno.
 404  */
 405 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 406 {
 407         struct dwc3_event_buffer        *evt;
 408 
 409         evt = dwc->ev_buf;
 410         evt->lpos = 0;
 411         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 412                         lower_32_bits(evt->dma));
 413         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 414                         upper_32_bits(evt->dma));
 415         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 416                         DWC3_GEVNTSIZ_SIZE(evt->length));
 417         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 418 
 419         return 0;
 420 }
 421 
 422 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 423 {
 424         struct dwc3_event_buffer        *evt;
 425 
 426         evt = dwc->ev_buf;
 427 
 428         evt->lpos = 0;
 429 
 430         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 431         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 432         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 433                         | DWC3_GEVNTSIZ_SIZE(0));
 434         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 435 }
 436 
 437 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 438 {
 439         if (!dwc->has_hibernation)
 440                 return 0;
 441 
 442         if (!dwc->nr_scratch)
 443                 return 0;
 444 
 445         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 446                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 447         if (!dwc->scratchbuf)
 448                 return -ENOMEM;
 449 
 450         return 0;
 451 }
 452 
 453 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 454 {
 455         dma_addr_t scratch_addr;
 456         u32 param;
 457         int ret;
 458 
 459         if (!dwc->has_hibernation)
 460                 return 0;
 461 
 462         if (!dwc->nr_scratch)
 463                 return 0;
 464 
 465          /* should never fall here */
 466         if (!WARN_ON(dwc->scratchbuf))
 467                 return 0;
 468 
 469         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 470                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 471                         DMA_BIDIRECTIONAL);
 472         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 473                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 474                 ret = -EFAULT;
 475                 goto err0;
 476         }
 477 
 478         dwc->scratch_addr = scratch_addr;
 479 
 480         param = lower_32_bits(scratch_addr);
 481 
 482         ret = dwc3_send_gadget_generic_command(dwc,
 483                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 484         if (ret < 0)
 485                 goto err1;
 486 
 487         param = upper_32_bits(scratch_addr);
 488 
 489         ret = dwc3_send_gadget_generic_command(dwc,
 490                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 491         if (ret < 0)
 492                 goto err1;
 493 
 494         return 0;
 495 
 496 err1:
 497         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 498                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 499 
 500 err0:
 501         return ret;
 502 }
 503 
 504 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 505 {
 506         if (!dwc->has_hibernation)
 507                 return;
 508 
 509         if (!dwc->nr_scratch)
 510                 return;
 511 
 512          /* should never fall here */
 513         if (!WARN_ON(dwc->scratchbuf))
 514                 return;
 515 
 516         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 517                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 518         kfree(dwc->scratchbuf);
 519 }
 520 
 521 static void dwc3_core_num_eps(struct dwc3 *dwc)
 522 {
 523         struct dwc3_hwparams    *parms = &dwc->hwparams;
 524 
 525         dwc->num_eps = DWC3_NUM_EPS(parms);
 526 }
 527 
 528 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 529 {
 530         struct dwc3_hwparams    *parms = &dwc->hwparams;
 531 
 532         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 533         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 534         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 535         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 536         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 537         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 538         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 539         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 540         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 541 }
 542 
 543 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 544 {
 545         int intf;
 546         int ret = 0;
 547 
 548         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 549 
 550         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 551             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 552              dwc->hsphy_interface &&
 553              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 554                 ret = dwc3_ulpi_init(dwc);
 555 
 556         return ret;
 557 }
 558 
 559 /**
 560  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 561  * @dwc: Pointer to our controller context structure
 562  *
 563  * Returns 0 on success. The USB PHY interfaces are configured but not
 564  * initialized. The PHY interfaces and the PHYs get initialized together with
 565  * the core in dwc3_core_init.
 566  */
 567 static int dwc3_phy_setup(struct dwc3 *dwc)
 568 {
 569         u32 reg;
 570 
 571         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 572 
 573         /*
 574          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 575          * PHYs. Also, this bit is not supposed to be used in normal operation.
 576          */
 577         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 578 
 579         /*
 580          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 581          * to '0' during coreConsultant configuration. So default value
 582          * will be '0' when the core is reset. Application needs to set it
 583          * to '1' after the core initialization is completed.
 584          */
 585         if (dwc->revision > DWC3_REVISION_194A)
 586                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 587 
 588         if (dwc->u2ss_inp3_quirk)
 589                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 590 
 591         if (dwc->dis_rxdet_inp3_quirk)
 592                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 593 
 594         if (dwc->req_p1p2p3_quirk)
 595                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 596 
 597         if (dwc->del_p1p2p3_quirk)
 598                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 599 
 600         if (dwc->del_phy_power_chg_quirk)
 601                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 602 
 603         if (dwc->lfps_filter_quirk)
 604                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 605 
 606         if (dwc->rx_detect_poll_quirk)
 607                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 608 
 609         if (dwc->tx_de_emphasis_quirk)
 610                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 611 
 612         if (dwc->dis_u3_susphy_quirk)
 613                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 614 
 615         if (dwc->dis_del_phy_power_chg_quirk)
 616                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 617 
 618         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 619 
 620         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 621 
 622         /* Select the HS PHY interface */
 623         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 624         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 625                 if (dwc->hsphy_interface &&
 626                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 627                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 628                         break;
 629                 } else if (dwc->hsphy_interface &&
 630                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 631                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 632                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 633                 } else {
 634                         /* Relying on default value. */
 635                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 636                                 break;
 637                 }
 638                 /* FALLTHROUGH */
 639         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 640                 /* FALLTHROUGH */
 641         default:
 642                 break;
 643         }
 644 
 645         switch (dwc->hsphy_mode) {
 646         case USBPHY_INTERFACE_MODE_UTMI:
 647                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 648                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 649                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 650                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 651                 break;
 652         case USBPHY_INTERFACE_MODE_UTMIW:
 653                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 654                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 655                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 656                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 657                 break;
 658         default:
 659                 break;
 660         }
 661 
 662         /*
 663          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 664          * '0' during coreConsultant configuration. So default value will
 665          * be '0' when the core is reset. Application needs to set it to
 666          * '1' after the core initialization is completed.
 667          */
 668         if (dwc->revision > DWC3_REVISION_194A)
 669                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 670 
 671         if (dwc->dis_u2_susphy_quirk)
 672                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 673 
 674         if (dwc->dis_enblslpm_quirk)
 675                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 676         else
 677                 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 678 
 679         if (dwc->dis_u2_freeclk_exists_quirk)
 680                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 681 
 682         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 683 
 684         return 0;
 685 }
 686 
 687 static void dwc3_core_exit(struct dwc3 *dwc)
 688 {
 689         dwc3_event_buffers_cleanup(dwc);
 690 
 691         usb_phy_shutdown(dwc->usb2_phy);
 692         usb_phy_shutdown(dwc->usb3_phy);
 693         phy_exit(dwc->usb2_generic_phy);
 694         phy_exit(dwc->usb3_generic_phy);
 695 
 696         usb_phy_set_suspend(dwc->usb2_phy, 1);
 697         usb_phy_set_suspend(dwc->usb3_phy, 1);
 698         phy_power_off(dwc->usb2_generic_phy);
 699         phy_power_off(dwc->usb3_generic_phy);
 700         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
 701         reset_control_assert(dwc->reset);
 702 }
 703 
 704 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 705 {
 706         u32 reg;
 707 
 708         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 709 
 710         /* This should read as U3 followed by revision number */
 711         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 712                 /* Detected DWC_usb3 IP */
 713                 dwc->revision = reg;
 714         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 715                 /* Detected DWC_usb31 IP */
 716                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 717                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 718                 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
 719         } else {
 720                 return false;
 721         }
 722 
 723         return true;
 724 }
 725 
 726 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 727 {
 728         u32 hwparams4 = dwc->hwparams.hwparams4;
 729         u32 reg;
 730 
 731         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 732         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 733 
 734         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 735         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 736                 /**
 737                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 738                  * issue which would cause xHCI compliance tests to fail.
 739                  *
 740                  * Because of that we cannot enable clock gating on such
 741                  * configurations.
 742                  *
 743                  * Refers to:
 744                  *
 745                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 746                  * SOF/ITP Mode Used
 747                  */
 748                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 749                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 750                                 (dwc->revision >= DWC3_REVISION_210A &&
 751                                 dwc->revision <= DWC3_REVISION_250A))
 752                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 753                 else
 754                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 755                 break;
 756         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 757                 /* enable hibernation here */
 758                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 759 
 760                 /*
 761                  * REVISIT Enabling this bit so that host-mode hibernation
 762                  * will work. Device-mode hibernation is not yet implemented.
 763                  */
 764                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 765                 break;
 766         default:
 767                 /* nothing */
 768                 break;
 769         }
 770 
 771         /* check if current dwc3 is on simulation board */
 772         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 773                 dev_info(dwc->dev, "Running with FPGA optimizations\n");
 774                 dwc->is_fpga = true;
 775         }
 776 
 777         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 778                         "disable_scramble cannot be used on non-FPGA builds\n");
 779 
 780         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 781                 reg |= DWC3_GCTL_DISSCRAMBLE;
 782         else
 783                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 784 
 785         if (dwc->u2exit_lfps_quirk)
 786                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 787 
 788         /*
 789          * WORKAROUND: DWC3 revisions <1.90a have a bug
 790          * where the device can fail to connect at SuperSpeed
 791          * and falls back to high-speed mode which causes
 792          * the device to enter a Connect/Disconnect loop
 793          */
 794         if (dwc->revision < DWC3_REVISION_190A)
 795                 reg |= DWC3_GCTL_U2RSTECN;
 796 
 797         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 798 }
 799 
 800 static int dwc3_core_get_phy(struct dwc3 *dwc);
 801 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 802 
 803 /* set global incr burst type configuration registers */
 804 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 805 {
 806         struct device *dev = dwc->dev;
 807         /* incrx_mode : for INCR burst type. */
 808         bool incrx_mode;
 809         /* incrx_size : for size of INCRX burst. */
 810         u32 incrx_size;
 811         u32 *vals;
 812         u32 cfg;
 813         int ntype;
 814         int ret;
 815         int i;
 816 
 817         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 818 
 819         /*
 820          * Handle property "snps,incr-burst-type-adjustment".
 821          * Get the number of value from this property:
 822          * result <= 0, means this property is not supported.
 823          * result = 1, means INCRx burst mode supported.
 824          * result > 1, means undefined length burst mode supported.
 825          */
 826         ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
 827         if (ntype <= 0)
 828                 return;
 829 
 830         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 831         if (!vals) {
 832                 dev_err(dev, "Error to get memory\n");
 833                 return;
 834         }
 835 
 836         /* Get INCR burst type, and parse it */
 837         ret = device_property_read_u32_array(dev,
 838                         "snps,incr-burst-type-adjustment", vals, ntype);
 839         if (ret) {
 840                 kfree(vals);
 841                 dev_err(dev, "Error to get property\n");
 842                 return;
 843         }
 844 
 845         incrx_size = *vals;
 846 
 847         if (ntype > 1) {
 848                 /* INCRX (undefined length) burst mode */
 849                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 850                 for (i = 1; i < ntype; i++) {
 851                         if (vals[i] > incrx_size)
 852                                 incrx_size = vals[i];
 853                 }
 854         } else {
 855                 /* INCRX burst mode */
 856                 incrx_mode = INCRX_BURST_MODE;
 857         }
 858 
 859         kfree(vals);
 860 
 861         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 862         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 863         if (incrx_mode)
 864                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 865         switch (incrx_size) {
 866         case 256:
 867                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 868                 break;
 869         case 128:
 870                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 871                 break;
 872         case 64:
 873                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 874                 break;
 875         case 32:
 876                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 877                 break;
 878         case 16:
 879                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 880                 break;
 881         case 8:
 882                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 883                 break;
 884         case 4:
 885                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 886                 break;
 887         case 1:
 888                 break;
 889         default:
 890                 dev_err(dev, "Invalid property\n");
 891                 break;
 892         }
 893 
 894         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 895 }
 896 
 897 /**
 898  * dwc3_core_init - Low-level initialization of DWC3 Core
 899  * @dwc: Pointer to our controller context structure
 900  *
 901  * Returns 0 on success otherwise negative errno.
 902  */
 903 static int dwc3_core_init(struct dwc3 *dwc)
 904 {
 905         u32                     reg;
 906         int                     ret;
 907 
 908         /*
 909          * Write Linux Version Code to our GUID register so it's easy to figure
 910          * out which kernel version a bug was found.
 911          */
 912         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 913 
 914         /* Handle USB2.0-only core configuration */
 915         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 916                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 917                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 918                         dwc->maximum_speed = USB_SPEED_HIGH;
 919         }
 920 
 921         ret = dwc3_phy_setup(dwc);
 922         if (ret)
 923                 goto err0;
 924 
 925         if (!dwc->ulpi_ready) {
 926                 ret = dwc3_core_ulpi_init(dwc);
 927                 if (ret)
 928                         goto err0;
 929                 dwc->ulpi_ready = true;
 930         }
 931 
 932         if (!dwc->phys_ready) {
 933                 ret = dwc3_core_get_phy(dwc);
 934                 if (ret)
 935                         goto err0a;
 936                 dwc->phys_ready = true;
 937         }
 938 
 939         ret = dwc3_core_soft_reset(dwc);
 940         if (ret)
 941                 goto err0a;
 942 
 943         dwc3_core_setup_global_control(dwc);
 944         dwc3_core_num_eps(dwc);
 945 
 946         ret = dwc3_setup_scratch_buffers(dwc);
 947         if (ret)
 948                 goto err1;
 949 
 950         /* Adjust Frame Length */
 951         dwc3_frame_length_adjustment(dwc);
 952 
 953         dwc3_set_incr_burst_type(dwc);
 954 
 955         usb_phy_set_suspend(dwc->usb2_phy, 0);
 956         usb_phy_set_suspend(dwc->usb3_phy, 0);
 957         ret = phy_power_on(dwc->usb2_generic_phy);
 958         if (ret < 0)
 959                 goto err2;
 960 
 961         ret = phy_power_on(dwc->usb3_generic_phy);
 962         if (ret < 0)
 963                 goto err3;
 964 
 965         ret = dwc3_event_buffers_setup(dwc);
 966         if (ret) {
 967                 dev_err(dwc->dev, "failed to setup event buffers\n");
 968                 goto err4;
 969         }
 970 
 971         /*
 972          * ENDXFER polling is available on version 3.10a and later of
 973          * the DWC_usb3 controller. It is NOT available in the
 974          * DWC_usb31 controller.
 975          */
 976         if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
 977                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
 978                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
 979                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
 980         }
 981 
 982         if (dwc->revision >= DWC3_REVISION_250A) {
 983                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
 984 
 985                 /*
 986                  * Enable hardware control of sending remote wakeup
 987                  * in HS when the device is in the L1 state.
 988                  */
 989                 if (dwc->revision >= DWC3_REVISION_290A)
 990                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
 991 
 992                 if (dwc->dis_tx_ipgap_linecheck_quirk)
 993                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
 994 
 995                 if (dwc->parkmode_disable_ss_quirk)
 996                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
 997 
 998                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
 999         }
1000 
1001         if (dwc->dr_mode == USB_DR_MODE_HOST ||
1002             dwc->dr_mode == USB_DR_MODE_OTG) {
1003                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1004 
1005                 /*
1006                  * Enable Auto retry Feature to make the controller operating in
1007                  * Host mode on seeing transaction errors(CRC errors or internal
1008                  * overrun scenerios) on IN transfers to reply to the device
1009                  * with a non-terminating retry ACK (i.e, an ACK transcation
1010                  * packet with Retry=1 & Nump != 0)
1011                  */
1012                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1013 
1014                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1015         }
1016 
1017         /*
1018          * Must config both number of packets and max burst settings to enable
1019          * RX and/or TX threshold.
1020          */
1021         if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
1022                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1023                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1024                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1025                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1026 
1027                 if (rx_thr_num && rx_maxburst) {
1028                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1029                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1030 
1031                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1032                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1033 
1034                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1035                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1036 
1037                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1038                 }
1039 
1040                 if (tx_thr_num && tx_maxburst) {
1041                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1042                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1043 
1044                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1045                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1046 
1047                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1048                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1049 
1050                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1051                 }
1052         }
1053 
1054         return 0;
1055 
1056 err4:
1057         phy_power_off(dwc->usb3_generic_phy);
1058 
1059 err3:
1060         phy_power_off(dwc->usb2_generic_phy);
1061 
1062 err2:
1063         usb_phy_set_suspend(dwc->usb2_phy, 1);
1064         usb_phy_set_suspend(dwc->usb3_phy, 1);
1065 
1066 err1:
1067         usb_phy_shutdown(dwc->usb2_phy);
1068         usb_phy_shutdown(dwc->usb3_phy);
1069         phy_exit(dwc->usb2_generic_phy);
1070         phy_exit(dwc->usb3_generic_phy);
1071 
1072 err0a:
1073         dwc3_ulpi_exit(dwc);
1074 
1075 err0:
1076         return ret;
1077 }
1078 
1079 static int dwc3_core_get_phy(struct dwc3 *dwc)
1080 {
1081         struct device           *dev = dwc->dev;
1082         struct device_node      *node = dev->of_node;
1083         int ret;
1084 
1085         if (node) {
1086                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1087                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1088         } else {
1089                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1090                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1091         }
1092 
1093         if (IS_ERR(dwc->usb2_phy)) {
1094                 ret = PTR_ERR(dwc->usb2_phy);
1095                 if (ret == -ENXIO || ret == -ENODEV) {
1096                         dwc->usb2_phy = NULL;
1097                 } else if (ret == -EPROBE_DEFER) {
1098                         return ret;
1099                 } else {
1100                         dev_err(dev, "no usb2 phy configured\n");
1101                         return ret;
1102                 }
1103         }
1104 
1105         if (IS_ERR(dwc->usb3_phy)) {
1106                 ret = PTR_ERR(dwc->usb3_phy);
1107                 if (ret == -ENXIO || ret == -ENODEV) {
1108                         dwc->usb3_phy = NULL;
1109                 } else if (ret == -EPROBE_DEFER) {
1110                         return ret;
1111                 } else {
1112                         dev_err(dev, "no usb3 phy configured\n");
1113                         return ret;
1114                 }
1115         }
1116 
1117         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1118         if (IS_ERR(dwc->usb2_generic_phy)) {
1119                 ret = PTR_ERR(dwc->usb2_generic_phy);
1120                 if (ret == -ENOSYS || ret == -ENODEV) {
1121                         dwc->usb2_generic_phy = NULL;
1122                 } else if (ret == -EPROBE_DEFER) {
1123                         return ret;
1124                 } else {
1125                         dev_err(dev, "no usb2 phy configured\n");
1126                         return ret;
1127                 }
1128         }
1129 
1130         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1131         if (IS_ERR(dwc->usb3_generic_phy)) {
1132                 ret = PTR_ERR(dwc->usb3_generic_phy);
1133                 if (ret == -ENOSYS || ret == -ENODEV) {
1134                         dwc->usb3_generic_phy = NULL;
1135                 } else if (ret == -EPROBE_DEFER) {
1136                         return ret;
1137                 } else {
1138                         dev_err(dev, "no usb3 phy configured\n");
1139                         return ret;
1140                 }
1141         }
1142 
1143         return 0;
1144 }
1145 
1146 static int dwc3_core_init_mode(struct dwc3 *dwc)
1147 {
1148         struct device *dev = dwc->dev;
1149         int ret;
1150 
1151         switch (dwc->dr_mode) {
1152         case USB_DR_MODE_PERIPHERAL:
1153                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1154 
1155                 if (dwc->usb2_phy)
1156                         otg_set_vbus(dwc->usb2_phy->otg, false);
1157                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1158                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1159 
1160                 ret = dwc3_gadget_init(dwc);
1161                 if (ret) {
1162                         if (ret != -EPROBE_DEFER)
1163                                 dev_err(dev, "failed to initialize gadget\n");
1164                         return ret;
1165                 }
1166                 break;
1167         case USB_DR_MODE_HOST:
1168                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1169 
1170                 if (dwc->usb2_phy)
1171                         otg_set_vbus(dwc->usb2_phy->otg, true);
1172                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1173                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1174 
1175                 ret = dwc3_host_init(dwc);
1176                 if (ret) {
1177                         if (ret != -EPROBE_DEFER)
1178                                 dev_err(dev, "failed to initialize host\n");
1179                         return ret;
1180                 }
1181                 break;
1182         case USB_DR_MODE_OTG:
1183                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1184                 ret = dwc3_drd_init(dwc);
1185                 if (ret) {
1186                         if (ret != -EPROBE_DEFER)
1187                                 dev_err(dev, "failed to initialize dual-role\n");
1188                         return ret;
1189                 }
1190                 break;
1191         default:
1192                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1193                 return -EINVAL;
1194         }
1195 
1196         return 0;
1197 }
1198 
1199 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1200 {
1201         switch (dwc->dr_mode) {
1202         case USB_DR_MODE_PERIPHERAL:
1203                 dwc3_gadget_exit(dwc);
1204                 break;
1205         case USB_DR_MODE_HOST:
1206                 dwc3_host_exit(dwc);
1207                 break;
1208         case USB_DR_MODE_OTG:
1209                 dwc3_drd_exit(dwc);
1210                 break;
1211         default:
1212                 /* do nothing */
1213                 break;
1214         }
1215 
1216         /* de-assert DRVVBUS for HOST and OTG mode */
1217         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1218 }
1219 
1220 static void dwc3_get_properties(struct dwc3 *dwc)
1221 {
1222         struct device           *dev = dwc->dev;
1223         u8                      lpm_nyet_threshold;
1224         u8                      tx_de_emphasis;
1225         u8                      hird_threshold;
1226         u8                      rx_thr_num_pkt_prd;
1227         u8                      rx_max_burst_prd;
1228         u8                      tx_thr_num_pkt_prd;
1229         u8                      tx_max_burst_prd;
1230 
1231         /* default to highest possible threshold */
1232         lpm_nyet_threshold = 0xf;
1233 
1234         /* default to -3.5dB de-emphasis */
1235         tx_de_emphasis = 1;
1236 
1237         /*
1238          * default to assert utmi_sleep_n and use maximum allowed HIRD
1239          * threshold value of 0b1100
1240          */
1241         hird_threshold = 12;
1242 
1243         dwc->maximum_speed = usb_get_maximum_speed(dev);
1244         dwc->dr_mode = usb_get_dr_mode(dev);
1245         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1246 
1247         dwc->sysdev_is_parent = device_property_read_bool(dev,
1248                                 "linux,sysdev_is_parent");
1249         if (dwc->sysdev_is_parent)
1250                 dwc->sysdev = dwc->dev->parent;
1251         else
1252                 dwc->sysdev = dwc->dev;
1253 
1254         dwc->has_lpm_erratum = device_property_read_bool(dev,
1255                                 "snps,has-lpm-erratum");
1256         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1257                                 &lpm_nyet_threshold);
1258         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1259                                 "snps,is-utmi-l1-suspend");
1260         device_property_read_u8(dev, "snps,hird-threshold",
1261                                 &hird_threshold);
1262         dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1263                                 "snps,dis-start-transfer-quirk");
1264         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1265                                 "snps,usb3_lpm_capable");
1266         dwc->usb2_lpm_disable = device_property_read_bool(dev,
1267                                 "snps,usb2-lpm-disable");
1268         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1269                                 &rx_thr_num_pkt_prd);
1270         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1271                                 &rx_max_burst_prd);
1272         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1273                                 &tx_thr_num_pkt_prd);
1274         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1275                                 &tx_max_burst_prd);
1276 
1277         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1278                                 "snps,disable_scramble_quirk");
1279         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1280                                 "snps,u2exit_lfps_quirk");
1281         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1282                                 "snps,u2ss_inp3_quirk");
1283         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1284                                 "snps,req_p1p2p3_quirk");
1285         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1286                                 "snps,del_p1p2p3_quirk");
1287         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1288                                 "snps,del_phy_power_chg_quirk");
1289         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1290                                 "snps,lfps_filter_quirk");
1291         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1292                                 "snps,rx_detect_poll_quirk");
1293         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1294                                 "snps,dis_u3_susphy_quirk");
1295         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1296                                 "snps,dis_u2_susphy_quirk");
1297         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1298                                 "snps,dis_enblslpm_quirk");
1299         dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1300                                 "snps,dis-u1-entry-quirk");
1301         dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1302                                 "snps,dis-u2-entry-quirk");
1303         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1304                                 "snps,dis_rxdet_inp3_quirk");
1305         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1306                                 "snps,dis-u2-freeclk-exists-quirk");
1307         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1308                                 "snps,dis-del-phy-power-chg-quirk");
1309         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1310                                 "snps,dis-tx-ipgap-linecheck-quirk");
1311         dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1312                                 "snps,parkmode-disable-ss-quirk");
1313 
1314         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1315                                 "snps,tx_de_emphasis_quirk");
1316         device_property_read_u8(dev, "snps,tx_de_emphasis",
1317                                 &tx_de_emphasis);
1318         device_property_read_string(dev, "snps,hsphy_interface",
1319                                     &dwc->hsphy_interface);
1320         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1321                                  &dwc->fladj);
1322 
1323         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1324                                 "snps,dis_metastability_quirk");
1325 
1326         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1327         dwc->tx_de_emphasis = tx_de_emphasis;
1328 
1329         dwc->hird_threshold = hird_threshold;
1330 
1331         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1332         dwc->rx_max_burst_prd = rx_max_burst_prd;
1333 
1334         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1335         dwc->tx_max_burst_prd = tx_max_burst_prd;
1336 
1337         dwc->imod_interval = 0;
1338 }
1339 
1340 /* check whether the core supports IMOD */
1341 bool dwc3_has_imod(struct dwc3 *dwc)
1342 {
1343         return ((dwc3_is_usb3(dwc) &&
1344                  dwc->revision >= DWC3_REVISION_300A) ||
1345                 (dwc3_is_usb31(dwc) &&
1346                  dwc->revision >= DWC3_USB31_REVISION_120A));
1347 }
1348 
1349 static void dwc3_check_params(struct dwc3 *dwc)
1350 {
1351         struct device *dev = dwc->dev;
1352 
1353         /* Check for proper value of imod_interval */
1354         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1355                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1356                 dwc->imod_interval = 0;
1357         }
1358 
1359         /*
1360          * Workaround for STAR 9000961433 which affects only version
1361          * 3.00a of the DWC_usb3 core. This prevents the controller
1362          * interrupt from being masked while handling events. IMOD
1363          * allows us to work around this issue. Enable it for the
1364          * affected version.
1365          */
1366         if (!dwc->imod_interval &&
1367             (dwc->revision == DWC3_REVISION_300A))
1368                 dwc->imod_interval = 1;
1369 
1370         /* Check the maximum_speed parameter */
1371         switch (dwc->maximum_speed) {
1372         case USB_SPEED_LOW:
1373         case USB_SPEED_FULL:
1374         case USB_SPEED_HIGH:
1375         case USB_SPEED_SUPER:
1376         case USB_SPEED_SUPER_PLUS:
1377                 break;
1378         default:
1379                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1380                         dwc->maximum_speed);
1381                 /* fall through */
1382         case USB_SPEED_UNKNOWN:
1383                 /* default to superspeed */
1384                 dwc->maximum_speed = USB_SPEED_SUPER;
1385 
1386                 /*
1387                  * default to superspeed plus if we are capable.
1388                  */
1389                 if (dwc3_is_usb31(dwc) &&
1390                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1391                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1392                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1393 
1394                 break;
1395         }
1396 }
1397 
1398 static int dwc3_probe(struct platform_device *pdev)
1399 {
1400         struct device           *dev = &pdev->dev;
1401         struct resource         *res, dwc_res;
1402         struct dwc3             *dwc;
1403 
1404         int                     ret;
1405 
1406         void __iomem            *regs;
1407 
1408         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1409         if (!dwc)
1410                 return -ENOMEM;
1411 
1412         dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
1413                                  GFP_KERNEL);
1414         if (!dwc->clks)
1415                 return -ENOMEM;
1416 
1417         dwc->dev = dev;
1418 
1419         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1420         if (!res) {
1421                 dev_err(dev, "missing memory resource\n");
1422                 return -ENODEV;
1423         }
1424 
1425         dwc->xhci_resources[0].start = res->start;
1426         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1427                                         DWC3_XHCI_REGS_END;
1428         dwc->xhci_resources[0].flags = res->flags;
1429         dwc->xhci_resources[0].name = res->name;
1430 
1431         /*
1432          * Request memory region but exclude xHCI regs,
1433          * since it will be requested by the xhci-plat driver.
1434          */
1435         dwc_res = *res;
1436         dwc_res.start += DWC3_GLOBALS_REGS_START;
1437 
1438         regs = devm_ioremap_resource(dev, &dwc_res);
1439         if (IS_ERR(regs))
1440                 return PTR_ERR(regs);
1441 
1442         dwc->regs       = regs;
1443         dwc->regs_size  = resource_size(&dwc_res);
1444 
1445         dwc3_get_properties(dwc);
1446 
1447         dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
1448         if (IS_ERR(dwc->reset))
1449                 return PTR_ERR(dwc->reset);
1450 
1451         if (dev->of_node) {
1452                 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
1453 
1454                 ret = devm_clk_bulk_get(dev, dwc->num_clks, dwc->clks);
1455                 if (ret == -EPROBE_DEFER)
1456                         return ret;
1457                 /*
1458                  * Clocks are optional, but new DT platforms should support all
1459                  * clocks as required by the DT-binding.
1460                  */
1461                 if (ret)
1462                         dwc->num_clks = 0;
1463         }
1464 
1465         ret = reset_control_deassert(dwc->reset);
1466         if (ret)
1467                 return ret;
1468 
1469         ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1470         if (ret)
1471                 goto assert_reset;
1472 
1473         if (!dwc3_core_is_valid(dwc)) {
1474                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1475                 ret = -ENODEV;
1476                 goto disable_clks;
1477         }
1478 
1479         platform_set_drvdata(pdev, dwc);
1480         dwc3_cache_hwparams(dwc);
1481 
1482         spin_lock_init(&dwc->lock);
1483 
1484         pm_runtime_set_active(dev);
1485         pm_runtime_use_autosuspend(dev);
1486         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1487         pm_runtime_enable(dev);
1488         ret = pm_runtime_get_sync(dev);
1489         if (ret < 0)
1490                 goto err1;
1491 
1492         pm_runtime_forbid(dev);
1493 
1494         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1495         if (ret) {
1496                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1497                 ret = -ENOMEM;
1498                 goto err2;
1499         }
1500 
1501         ret = dwc3_get_dr_mode(dwc);
1502         if (ret)
1503                 goto err3;
1504 
1505         ret = dwc3_alloc_scratch_buffers(dwc);
1506         if (ret)
1507                 goto err3;
1508 
1509         ret = dwc3_core_init(dwc);
1510         if (ret) {
1511                 if (ret != -EPROBE_DEFER)
1512                         dev_err(dev, "failed to initialize core: %d\n", ret);
1513                 goto err4;
1514         }
1515 
1516         dwc3_check_params(dwc);
1517 
1518         ret = dwc3_core_init_mode(dwc);
1519         if (ret)
1520                 goto err5;
1521 
1522         dwc3_debugfs_init(dwc);
1523         pm_runtime_put(dev);
1524 
1525         return 0;
1526 
1527 err5:
1528         dwc3_event_buffers_cleanup(dwc);
1529         dwc3_ulpi_exit(dwc);
1530 
1531 err4:
1532         dwc3_free_scratch_buffers(dwc);
1533 
1534 err3:
1535         dwc3_free_event_buffers(dwc);
1536 
1537 err2:
1538         pm_runtime_allow(&pdev->dev);
1539 
1540 err1:
1541         pm_runtime_put_sync(&pdev->dev);
1542         pm_runtime_disable(&pdev->dev);
1543 
1544 disable_clks:
1545         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1546 assert_reset:
1547         reset_control_assert(dwc->reset);
1548 
1549         return ret;
1550 }
1551 
1552 static int dwc3_remove(struct platform_device *pdev)
1553 {
1554         struct dwc3     *dwc = platform_get_drvdata(pdev);
1555 
1556         pm_runtime_get_sync(&pdev->dev);
1557 
1558         dwc3_debugfs_exit(dwc);
1559         dwc3_core_exit_mode(dwc);
1560 
1561         dwc3_core_exit(dwc);
1562         dwc3_ulpi_exit(dwc);
1563 
1564         pm_runtime_put_sync(&pdev->dev);
1565         pm_runtime_allow(&pdev->dev);
1566         pm_runtime_disable(&pdev->dev);
1567 
1568         dwc3_free_event_buffers(dwc);
1569         dwc3_free_scratch_buffers(dwc);
1570 
1571         return 0;
1572 }
1573 
1574 #ifdef CONFIG_PM
1575 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1576 {
1577         int ret;
1578 
1579         ret = reset_control_deassert(dwc->reset);
1580         if (ret)
1581                 return ret;
1582 
1583         ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1584         if (ret)
1585                 goto assert_reset;
1586 
1587         ret = dwc3_core_init(dwc);
1588         if (ret)
1589                 goto disable_clks;
1590 
1591         return 0;
1592 
1593 disable_clks:
1594         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1595 assert_reset:
1596         reset_control_assert(dwc->reset);
1597 
1598         return ret;
1599 }
1600 
1601 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1602 {
1603         unsigned long   flags;
1604         u32 reg;
1605 
1606         switch (dwc->current_dr_role) {
1607         case DWC3_GCTL_PRTCAP_DEVICE:
1608                 spin_lock_irqsave(&dwc->lock, flags);
1609                 dwc3_gadget_suspend(dwc);
1610                 spin_unlock_irqrestore(&dwc->lock, flags);
1611                 synchronize_irq(dwc->irq_gadget);
1612                 dwc3_core_exit(dwc);
1613                 break;
1614         case DWC3_GCTL_PRTCAP_HOST:
1615                 if (!PMSG_IS_AUTO(msg)) {
1616                         dwc3_core_exit(dwc);
1617                         break;
1618                 }
1619 
1620                 /* Let controller to suspend HSPHY before PHY driver suspends */
1621                 if (dwc->dis_u2_susphy_quirk ||
1622                     dwc->dis_enblslpm_quirk) {
1623                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1624                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1625                                 DWC3_GUSB2PHYCFG_SUSPHY;
1626                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1627 
1628                         /* Give some time for USB2 PHY to suspend */
1629                         usleep_range(5000, 6000);
1630                 }
1631 
1632                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1633                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1634                 break;
1635         case DWC3_GCTL_PRTCAP_OTG:
1636                 /* do nothing during runtime_suspend */
1637                 if (PMSG_IS_AUTO(msg))
1638                         break;
1639 
1640                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1641                         spin_lock_irqsave(&dwc->lock, flags);
1642                         dwc3_gadget_suspend(dwc);
1643                         spin_unlock_irqrestore(&dwc->lock, flags);
1644                         synchronize_irq(dwc->irq_gadget);
1645                 }
1646 
1647                 dwc3_otg_exit(dwc);
1648                 dwc3_core_exit(dwc);
1649                 break;
1650         default:
1651                 /* do nothing */
1652                 break;
1653         }
1654 
1655         return 0;
1656 }
1657 
1658 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1659 {
1660         unsigned long   flags;
1661         int             ret;
1662         u32             reg;
1663 
1664         switch (dwc->current_dr_role) {
1665         case DWC3_GCTL_PRTCAP_DEVICE:
1666                 ret = dwc3_core_init_for_resume(dwc);
1667                 if (ret)
1668                         return ret;
1669 
1670                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1671                 spin_lock_irqsave(&dwc->lock, flags);
1672                 dwc3_gadget_resume(dwc);
1673                 spin_unlock_irqrestore(&dwc->lock, flags);
1674                 break;
1675         case DWC3_GCTL_PRTCAP_HOST:
1676                 if (!PMSG_IS_AUTO(msg)) {
1677                         ret = dwc3_core_init_for_resume(dwc);
1678                         if (ret)
1679                                 return ret;
1680                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1681                         break;
1682                 }
1683                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1684                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1685                 if (dwc->dis_u2_susphy_quirk)
1686                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1687 
1688                 if (dwc->dis_enblslpm_quirk)
1689                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1690 
1691                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1692 
1693                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1694                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1695                 break;
1696         case DWC3_GCTL_PRTCAP_OTG:
1697                 /* nothing to do on runtime_resume */
1698                 if (PMSG_IS_AUTO(msg))
1699                         break;
1700 
1701                 ret = dwc3_core_init(dwc);
1702                 if (ret)
1703                         return ret;
1704 
1705                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1706 
1707                 dwc3_otg_init(dwc);
1708                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1709                         dwc3_otg_host_init(dwc);
1710                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1711                         spin_lock_irqsave(&dwc->lock, flags);
1712                         dwc3_gadget_resume(dwc);
1713                         spin_unlock_irqrestore(&dwc->lock, flags);
1714                 }
1715 
1716                 break;
1717         default:
1718                 /* do nothing */
1719                 break;
1720         }
1721 
1722         return 0;
1723 }
1724 
1725 static int dwc3_runtime_checks(struct dwc3 *dwc)
1726 {
1727         switch (dwc->current_dr_role) {
1728         case DWC3_GCTL_PRTCAP_DEVICE:
1729                 if (dwc->connected)
1730                         return -EBUSY;
1731                 break;
1732         case DWC3_GCTL_PRTCAP_HOST:
1733         default:
1734                 /* do nothing */
1735                 break;
1736         }
1737 
1738         return 0;
1739 }
1740 
1741 static int dwc3_runtime_suspend(struct device *dev)
1742 {
1743         struct dwc3     *dwc = dev_get_drvdata(dev);
1744         int             ret;
1745 
1746         if (dwc3_runtime_checks(dwc))
1747                 return -EBUSY;
1748 
1749         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1750         if (ret)
1751                 return ret;
1752 
1753         device_init_wakeup(dev, true);
1754 
1755         return 0;
1756 }
1757 
1758 static int dwc3_runtime_resume(struct device *dev)
1759 {
1760         struct dwc3     *dwc = dev_get_drvdata(dev);
1761         int             ret;
1762 
1763         device_init_wakeup(dev, false);
1764 
1765         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1766         if (ret)
1767                 return ret;
1768 
1769         switch (dwc->current_dr_role) {
1770         case DWC3_GCTL_PRTCAP_DEVICE:
1771                 dwc3_gadget_process_pending_events(dwc);
1772                 break;
1773         case DWC3_GCTL_PRTCAP_HOST:
1774         default:
1775                 /* do nothing */
1776                 break;
1777         }
1778 
1779         pm_runtime_mark_last_busy(dev);
1780 
1781         return 0;
1782 }
1783 
1784 static int dwc3_runtime_idle(struct device *dev)
1785 {
1786         struct dwc3     *dwc = dev_get_drvdata(dev);
1787 
1788         switch (dwc->current_dr_role) {
1789         case DWC3_GCTL_PRTCAP_DEVICE:
1790                 if (dwc3_runtime_checks(dwc))
1791                         return -EBUSY;
1792                 break;
1793         case DWC3_GCTL_PRTCAP_HOST:
1794         default:
1795                 /* do nothing */
1796                 break;
1797         }
1798 
1799         pm_runtime_mark_last_busy(dev);
1800         pm_runtime_autosuspend(dev);
1801 
1802         return 0;
1803 }
1804 #endif /* CONFIG_PM */
1805 
1806 #ifdef CONFIG_PM_SLEEP
1807 static int dwc3_suspend(struct device *dev)
1808 {
1809         struct dwc3     *dwc = dev_get_drvdata(dev);
1810         int             ret;
1811 
1812         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1813         if (ret)
1814                 return ret;
1815 
1816         pinctrl_pm_select_sleep_state(dev);
1817 
1818         return 0;
1819 }
1820 
1821 static int dwc3_resume(struct device *dev)
1822 {
1823         struct dwc3     *dwc = dev_get_drvdata(dev);
1824         int             ret;
1825 
1826         pinctrl_pm_select_default_state(dev);
1827 
1828         ret = dwc3_resume_common(dwc, PMSG_RESUME);
1829         if (ret)
1830                 return ret;
1831 
1832         pm_runtime_disable(dev);
1833         pm_runtime_set_active(dev);
1834         pm_runtime_enable(dev);
1835 
1836         return 0;
1837 }
1838 #endif /* CONFIG_PM_SLEEP */
1839 
1840 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1841         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1842         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1843                         dwc3_runtime_idle)
1844 };
1845 
1846 #ifdef CONFIG_OF
1847 static const struct of_device_id of_dwc3_match[] = {
1848         {
1849                 .compatible = "snps,dwc3"
1850         },
1851         {
1852                 .compatible = "synopsys,dwc3"
1853         },
1854         { },
1855 };
1856 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1857 #endif
1858 
1859 #ifdef CONFIG_ACPI
1860 
1861 #define ACPI_ID_INTEL_BSW       "808622B7"
1862 
1863 static const struct acpi_device_id dwc3_acpi_match[] = {
1864         { ACPI_ID_INTEL_BSW, 0 },
1865         { },
1866 };
1867 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1868 #endif
1869 
1870 static struct platform_driver dwc3_driver = {
1871         .probe          = dwc3_probe,
1872         .remove         = dwc3_remove,
1873         .driver         = {
1874                 .name   = "dwc3",
1875                 .of_match_table = of_match_ptr(of_dwc3_match),
1876                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1877                 .pm     = &dwc3_dev_pm_ops,
1878         },
1879 };
1880 
1881 module_platform_driver(dwc3_driver);
1882 
1883 MODULE_ALIAS("platform:dwc3");
1884 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1885 MODULE_LICENSE("GPL v2");
1886 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/usb/dwc3/core.c

DEFINITIONS
