This source file includes following definitions.
- to_cdns_i3c_master
- cdns_i3c_master_wr_to_tx_fifo
- cdns_i3c_master_rd_from_rx_fifo
- cdns_i3c_master_supports_ccc_cmd
- cdns_i3c_master_disable
- cdns_i3c_master_enable
- cdns_i3c_master_alloc_xfer
- cdns_i3c_master_free_xfer
- cdns_i3c_master_start_xfer_locked
- cdns_i3c_master_end_xfer_locked
- cdns_i3c_master_queue_xfer
- cdns_i3c_master_unqueue_xfer
- cdns_i3c_cmd_get_err
- cdns_i3c_master_send_ccc_cmd
- cdns_i3c_master_priv_xfers
- cdns_i3c_master_i2c_xfers
- prepare_rr0_dev_address
- cdns_i3c_master_upd_i3c_addr
- cdns_i3c_master_get_rr_slot
- cdns_i3c_master_reattach_i3c_dev
- cdns_i3c_master_attach_i3c_dev
- cdns_i3c_master_detach_i3c_dev
- cdns_i3c_master_attach_i2c_dev
- cdns_i3c_master_detach_i2c_dev
- cdns_i3c_master_bus_cleanup
- cdns_i3c_master_dev_rr_to_info
- cdns_i3c_master_upd_i3c_scl_lim
- cdns_i3c_master_do_daa
- cdns_i3c_master_bus_init
- cdns_i3c_master_handle_ibi
- cnds_i3c_master_demux_ibis
- cdns_i3c_master_interrupt
- cdns_i3c_master_disable_ibi
- cdns_i3c_master_enable_ibi
- cdns_i3c_master_request_ibi
- cdns_i3c_master_free_ibi
- cdns_i3c_master_recycle_ibi_slot
- cdns_i3c_master_hj
- cdns_i3c_master_probe
- cdns_i3c_master_remove
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7
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/err.h>
11 #include <linux/errno.h>
12 #include <linux/i3c/master.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/iopoll.h>
16 #include <linux/ioport.h>
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
24 #include <linux/workqueue.h>
25
26 #define DEV_ID 0x0
27 #define DEV_ID_I3C_MASTER 0x5034
28
29 #define CONF_STATUS0 0x4
30 #define CONF_STATUS0_CMDR_DEPTH(x) (4 << (((x) & GENMASK(31, 29)) >> 29))
31 #define CONF_STATUS0_ECC_CHK BIT(28)
32 #define CONF_STATUS0_INTEG_CHK BIT(27)
33 #define CONF_STATUS0_CSR_DAP_CHK BIT(26)
34 #define CONF_STATUS0_TRANS_TOUT_CHK BIT(25)
35 #define CONF_STATUS0_PROT_FAULTS_CHK BIT(24)
36 #define CONF_STATUS0_GPO_NUM(x) (((x) & GENMASK(23, 16)) >> 16)
37 #define CONF_STATUS0_GPI_NUM(x) (((x) & GENMASK(15, 8)) >> 8)
38 #define CONF_STATUS0_IBIR_DEPTH(x) (4 << (((x) & GENMASK(7, 6)) >> 7))
39 #define CONF_STATUS0_SUPPORTS_DDR BIT(5)
40 #define CONF_STATUS0_SEC_MASTER BIT(4)
41 #define CONF_STATUS0_DEVS_NUM(x) ((x) & GENMASK(3, 0))
42
43 #define CONF_STATUS1 0x8
44 #define CONF_STATUS1_IBI_HW_RES(x) ((((x) & GENMASK(31, 28)) >> 28) + 1)
45 #define CONF_STATUS1_CMD_DEPTH(x) (4 << (((x) & GENMASK(27, 26)) >> 26))
46 #define CONF_STATUS1_SLVDDR_RX_DEPTH(x) (8 << (((x) & GENMASK(25, 21)) >> 21))
47 #define CONF_STATUS1_SLVDDR_TX_DEPTH(x) (8 << (((x) & GENMASK(20, 16)) >> 16))
48 #define CONF_STATUS1_IBI_DEPTH(x) (2 << (((x) & GENMASK(12, 10)) >> 10))
49 #define CONF_STATUS1_RX_DEPTH(x) (8 << (((x) & GENMASK(9, 5)) >> 5))
50 #define CONF_STATUS1_TX_DEPTH(x) (8 << ((x) & GENMASK(4, 0)))
51
52 #define REV_ID 0xc
53 #define REV_ID_VID(id) (((id) & GENMASK(31, 20)) >> 20)
54 #define REV_ID_PID(id) (((id) & GENMASK(19, 8)) >> 8)
55 #define REV_ID_REV_MAJOR(id) (((id) & GENMASK(7, 4)) >> 4)
56 #define REV_ID_REV_MINOR(id) ((id) & GENMASK(3, 0))
57
58 #define CTRL 0x10
59 #define CTRL_DEV_EN BIT(31)
60 #define CTRL_HALT_EN BIT(30)
61 #define CTRL_MCS BIT(29)
62 #define CTRL_MCS_EN BIT(28)
63 #define CTRL_HJ_DISEC BIT(8)
64 #define CTRL_MST_ACK BIT(7)
65 #define CTRL_HJ_ACK BIT(6)
66 #define CTRL_HJ_INIT BIT(5)
67 #define CTRL_MST_INIT BIT(4)
68 #define CTRL_AHDR_OPT BIT(3)
69 #define CTRL_PURE_BUS_MODE 0
70 #define CTRL_MIXED_FAST_BUS_MODE 2
71 #define CTRL_MIXED_SLOW_BUS_MODE 3
72 #define CTRL_BUS_MODE_MASK GENMASK(1, 0)
73
74 #define PRESCL_CTRL0 0x14
75 #define PRESCL_CTRL0_I2C(x) ((x) << 16)
76 #define PRESCL_CTRL0_I3C(x) (x)
77 #define PRESCL_CTRL0_MAX GENMASK(9, 0)
78
79 #define PRESCL_CTRL1 0x18
80 #define PRESCL_CTRL1_PP_LOW_MASK GENMASK(15, 8)
81 #define PRESCL_CTRL1_PP_LOW(x) ((x) << 8)
82 #define PRESCL_CTRL1_OD_LOW_MASK GENMASK(7, 0)
83 #define PRESCL_CTRL1_OD_LOW(x) (x)
84
85 #define MST_IER 0x20
86 #define MST_IDR 0x24
87 #define MST_IMR 0x28
88 #define MST_ICR 0x2c
89 #define MST_ISR 0x30
90 #define MST_INT_HALTED BIT(18)
91 #define MST_INT_MR_DONE BIT(17)
92 #define MST_INT_IMM_COMP BIT(16)
93 #define MST_INT_TX_THR BIT(15)
94 #define MST_INT_TX_OVF BIT(14)
95 #define MST_INT_IBID_THR BIT(12)
96 #define MST_INT_IBID_UNF BIT(11)
97 #define MST_INT_IBIR_THR BIT(10)
98 #define MST_INT_IBIR_UNF BIT(9)
99 #define MST_INT_IBIR_OVF BIT(8)
100 #define MST_INT_RX_THR BIT(7)
101 #define MST_INT_RX_UNF BIT(6)
102 #define MST_INT_CMDD_EMP BIT(5)
103 #define MST_INT_CMDD_THR BIT(4)
104 #define MST_INT_CMDD_OVF BIT(3)
105 #define MST_INT_CMDR_THR BIT(2)
106 #define MST_INT_CMDR_UNF BIT(1)
107 #define MST_INT_CMDR_OVF BIT(0)
108
109 #define MST_STATUS0 0x34
110 #define MST_STATUS0_IDLE BIT(18)
111 #define MST_STATUS0_HALTED BIT(17)
112 #define MST_STATUS0_MASTER_MODE BIT(16)
113 #define MST_STATUS0_TX_FULL BIT(13)
114 #define MST_STATUS0_IBID_FULL BIT(12)
115 #define MST_STATUS0_IBIR_FULL BIT(11)
116 #define MST_STATUS0_RX_FULL BIT(10)
117 #define MST_STATUS0_CMDD_FULL BIT(9)
118 #define MST_STATUS0_CMDR_FULL BIT(8)
119 #define MST_STATUS0_TX_EMP BIT(5)
120 #define MST_STATUS0_IBID_EMP BIT(4)
121 #define MST_STATUS0_IBIR_EMP BIT(3)
122 #define MST_STATUS0_RX_EMP BIT(2)
123 #define MST_STATUS0_CMDD_EMP BIT(1)
124 #define MST_STATUS0_CMDR_EMP BIT(0)
125
126 #define CMDR 0x38
127 #define CMDR_NO_ERROR 0
128 #define CMDR_DDR_PREAMBLE_ERROR 1
129 #define CMDR_DDR_PARITY_ERROR 2
130 #define CMDR_DDR_RX_FIFO_OVF 3
131 #define CMDR_DDR_TX_FIFO_UNF 4
132 #define CMDR_M0_ERROR 5
133 #define CMDR_M1_ERROR 6
134 #define CMDR_M2_ERROR 7
135 #define CMDR_MST_ABORT 8
136 #define CMDR_NACK_RESP 9
137 #define CMDR_INVALID_DA 10
138 #define CMDR_DDR_DROPPED 11
139 #define CMDR_ERROR(x) (((x) & GENMASK(27, 24)) >> 24)
140 #define CMDR_XFER_BYTES(x) (((x) & GENMASK(19, 8)) >> 8)
141 #define CMDR_CMDID_HJACK_DISEC 0xfe
142 #define CMDR_CMDID_HJACK_ENTDAA 0xff
143 #define CMDR_CMDID(x) ((x) & GENMASK(7, 0))
144
145 #define IBIR 0x3c
146 #define IBIR_ACKED BIT(12)
147 #define IBIR_SLVID(x) (((x) & GENMASK(11, 8)) >> 8)
148 #define IBIR_ERROR BIT(7)
149 #define IBIR_XFER_BYTES(x) (((x) & GENMASK(6, 2)) >> 2)
150 #define IBIR_TYPE_IBI 0
151 #define IBIR_TYPE_HJ 1
152 #define IBIR_TYPE_MR 2
153 #define IBIR_TYPE(x) ((x) & GENMASK(1, 0))
154
155 #define SLV_IER 0x40
156 #define SLV_IDR 0x44
157 #define SLV_IMR 0x48
158 #define SLV_ICR 0x4c
159 #define SLV_ISR 0x50
160 #define SLV_INT_TM BIT(20)
161 #define SLV_INT_ERROR BIT(19)
162 #define SLV_INT_EVENT_UP BIT(18)
163 #define SLV_INT_HJ_DONE BIT(17)
164 #define SLV_INT_MR_DONE BIT(16)
165 #define SLV_INT_DA_UPD BIT(15)
166 #define SLV_INT_SDR_FAIL BIT(14)
167 #define SLV_INT_DDR_FAIL BIT(13)
168 #define SLV_INT_M_RD_ABORT BIT(12)
169 #define SLV_INT_DDR_RX_THR BIT(11)
170 #define SLV_INT_DDR_TX_THR BIT(10)
171 #define SLV_INT_SDR_RX_THR BIT(9)
172 #define SLV_INT_SDR_TX_THR BIT(8)
173 #define SLV_INT_DDR_RX_UNF BIT(7)
174 #define SLV_INT_DDR_TX_OVF BIT(6)
175 #define SLV_INT_SDR_RX_UNF BIT(5)
176 #define SLV_INT_SDR_TX_OVF BIT(4)
177 #define SLV_INT_DDR_RD_COMP BIT(3)
178 #define SLV_INT_DDR_WR_COMP BIT(2)
179 #define SLV_INT_SDR_RD_COMP BIT(1)
180 #define SLV_INT_SDR_WR_COMP BIT(0)
181
182 #define SLV_STATUS0 0x54
183 #define SLV_STATUS0_REG_ADDR(s) (((s) & GENMASK(23, 16)) >> 16)
184 #define SLV_STATUS0_XFRD_BYTES(s) ((s) & GENMASK(15, 0))
185
186 #define SLV_STATUS1 0x58
187 #define SLV_STATUS1_AS(s) (((s) & GENMASK(21, 20)) >> 20)
188 #define SLV_STATUS1_VEN_TM BIT(19)
189 #define SLV_STATUS1_HJ_DIS BIT(18)
190 #define SLV_STATUS1_MR_DIS BIT(17)
191 #define SLV_STATUS1_PROT_ERR BIT(16)
192 #define SLV_STATUS1_DA(x) (((s) & GENMASK(15, 9)) >> 9)
193 #define SLV_STATUS1_HAS_DA BIT(8)
194 #define SLV_STATUS1_DDR_RX_FULL BIT(7)
195 #define SLV_STATUS1_DDR_TX_FULL BIT(6)
196 #define SLV_STATUS1_DDR_RX_EMPTY BIT(5)
197 #define SLV_STATUS1_DDR_TX_EMPTY BIT(4)
198 #define SLV_STATUS1_SDR_RX_FULL BIT(3)
199 #define SLV_STATUS1_SDR_TX_FULL BIT(2)
200 #define SLV_STATUS1_SDR_RX_EMPTY BIT(1)
201 #define SLV_STATUS1_SDR_TX_EMPTY BIT(0)
202
203 #define CMD0_FIFO 0x60
204 #define CMD0_FIFO_IS_DDR BIT(31)
205 #define CMD0_FIFO_IS_CCC BIT(30)
206 #define CMD0_FIFO_BCH BIT(29)
207 #define XMIT_BURST_STATIC_SUBADDR 0
208 #define XMIT_SINGLE_INC_SUBADDR 1
209 #define XMIT_SINGLE_STATIC_SUBADDR 2
210 #define XMIT_BURST_WITHOUT_SUBADDR 3
211 #define CMD0_FIFO_PRIV_XMIT_MODE(m) ((m) << 27)
212 #define CMD0_FIFO_SBCA BIT(26)
213 #define CMD0_FIFO_RSBC BIT(25)
214 #define CMD0_FIFO_IS_10B BIT(24)
215 #define CMD0_FIFO_PL_LEN(l) ((l) << 12)
216 #define CMD0_FIFO_PL_LEN_MAX 4095
217 #define CMD0_FIFO_DEV_ADDR(a) ((a) << 1)
218 #define CMD0_FIFO_RNW BIT(0)
219
220 #define CMD1_FIFO 0x64
221 #define CMD1_FIFO_CMDID(id) ((id) << 24)
222 #define CMD1_FIFO_CSRADDR(a) (a)
223 #define CMD1_FIFO_CCC(id) (id)
224
225 #define TX_FIFO 0x68
226
227 #define IMD_CMD0 0x70
228 #define IMD_CMD0_PL_LEN(l) ((l) << 12)
229 #define IMD_CMD0_DEV_ADDR(a) ((a) << 1)
230 #define IMD_CMD0_RNW BIT(0)
231
232 #define IMD_CMD1 0x74
233 #define IMD_CMD1_CCC(id) (id)
234
235 #define IMD_DATA 0x78
236 #define RX_FIFO 0x80
237 #define IBI_DATA_FIFO 0x84
238 #define SLV_DDR_TX_FIFO 0x88
239 #define SLV_DDR_RX_FIFO 0x8c
240
241 #define CMD_IBI_THR_CTRL 0x90
242 #define IBIR_THR(t) ((t) << 24)
243 #define CMDR_THR(t) ((t) << 16)
244 #define IBI_THR(t) ((t) << 8)
245 #define CMD_THR(t) (t)
246
247 #define TX_RX_THR_CTRL 0x94
248 #define RX_THR(t) ((t) << 16)
249 #define TX_THR(t) (t)
250
251 #define SLV_DDR_TX_RX_THR_CTRL 0x98
252 #define SLV_DDR_RX_THR(t) ((t) << 16)
253 #define SLV_DDR_TX_THR(t) (t)
254
255 #define FLUSH_CTRL 0x9c
256 #define FLUSH_IBI_RESP BIT(23)
257 #define FLUSH_CMD_RESP BIT(22)
258 #define FLUSH_SLV_DDR_RX_FIFO BIT(22)
259 #define FLUSH_SLV_DDR_TX_FIFO BIT(21)
260 #define FLUSH_IMM_FIFO BIT(20)
261 #define FLUSH_IBI_FIFO BIT(19)
262 #define FLUSH_RX_FIFO BIT(18)
263 #define FLUSH_TX_FIFO BIT(17)
264 #define FLUSH_CMD_FIFO BIT(16)
265
266 #define TTO_PRESCL_CTRL0 0xb0
267 #define TTO_PRESCL_CTRL0_DIVB(x) ((x) << 16)
268 #define TTO_PRESCL_CTRL0_DIVA(x) (x)
269
270 #define TTO_PRESCL_CTRL1 0xb4
271 #define TTO_PRESCL_CTRL1_DIVB(x) ((x) << 16)
272 #define TTO_PRESCL_CTRL1_DIVA(x) (x)
273
274 #define DEVS_CTRL 0xb8
275 #define DEVS_CTRL_DEV_CLR_SHIFT 16
276 #define DEVS_CTRL_DEV_CLR_ALL GENMASK(31, 16)
277 #define DEVS_CTRL_DEV_CLR(dev) BIT(16 + (dev))
278 #define DEVS_CTRL_DEV_ACTIVE(dev) BIT(dev)
279 #define DEVS_CTRL_DEVS_ACTIVE_MASK GENMASK(15, 0)
280 #define MAX_DEVS 16
281
282 #define DEV_ID_RR0(d) (0xc0 + ((d) * 0x10))
283 #define DEV_ID_RR0_LVR_EXT_ADDR BIT(11)
284 #define DEV_ID_RR0_HDR_CAP BIT(10)
285 #define DEV_ID_RR0_IS_I3C BIT(9)
286 #define DEV_ID_RR0_DEV_ADDR_MASK (GENMASK(6, 0) | GENMASK(15, 13))
287 #define DEV_ID_RR0_SET_DEV_ADDR(a) (((a) & GENMASK(6, 0)) | \
288 (((a) & GENMASK(9, 7)) << 6))
289 #define DEV_ID_RR0_GET_DEV_ADDR(x) ((((x) >> 1) & GENMASK(6, 0)) | \
290 (((x) >> 6) & GENMASK(9, 7)))
291
292 #define DEV_ID_RR1(d) (0xc4 + ((d) * 0x10))
293 #define DEV_ID_RR1_PID_MSB(pid) (pid)
294
295 #define DEV_ID_RR2(d) (0xc8 + ((d) * 0x10))
296 #define DEV_ID_RR2_PID_LSB(pid) ((pid) << 16)
297 #define DEV_ID_RR2_BCR(bcr) ((bcr) << 8)
298 #define DEV_ID_RR2_DCR(dcr) (dcr)
299 #define DEV_ID_RR2_LVR(lvr) (lvr)
300
301 #define SIR_MAP(x) (0x180 + ((x) * 4))
302 #define SIR_MAP_DEV_REG(d) SIR_MAP((d) / 2)
303 #define SIR_MAP_DEV_SHIFT(d, fs) ((fs) + (((d) % 2) ? 16 : 0))
304 #define SIR_MAP_DEV_CONF_MASK(d) (GENMASK(15, 0) << (((d) % 2) ? 16 : 0))
305 #define SIR_MAP_DEV_CONF(d, c) ((c) << (((d) % 2) ? 16 : 0))
306 #define DEV_ROLE_SLAVE 0
307 #define DEV_ROLE_MASTER 1
308 #define SIR_MAP_DEV_ROLE(role) ((role) << 14)
309 #define SIR_MAP_DEV_SLOW BIT(13)
310 #define SIR_MAP_DEV_PL(l) ((l) << 8)
311 #define SIR_MAP_PL_MAX GENMASK(4, 0)
312 #define SIR_MAP_DEV_DA(a) ((a) << 1)
313 #define SIR_MAP_DEV_ACK BIT(0)
314
315 #define GPIR_WORD(x) (0x200 + ((x) * 4))
316 #define GPI_REG(val, id) \
317 (((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))
318
319 #define GPOR_WORD(x) (0x220 + ((x) * 4))
320 #define GPO_REG(val, id) \
321 (((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))
322
323 #define ASF_INT_STATUS 0x300
324 #define ASF_INT_RAW_STATUS 0x304
325 #define ASF_INT_MASK 0x308
326 #define ASF_INT_TEST 0x30c
327 #define ASF_INT_FATAL_SELECT 0x310
328 #define ASF_INTEGRITY_ERR BIT(6)
329 #define ASF_PROTOCOL_ERR BIT(5)
330 #define ASF_TRANS_TIMEOUT_ERR BIT(4)
331 #define ASF_CSR_ERR BIT(3)
332 #define ASF_DAP_ERR BIT(2)
333 #define ASF_SRAM_UNCORR_ERR BIT(1)
334 #define ASF_SRAM_CORR_ERR BIT(0)
335
336 #define ASF_SRAM_CORR_FAULT_STATUS 0x320
337 #define ASF_SRAM_UNCORR_FAULT_STATUS 0x324
338 #define ASF_SRAM_CORR_FAULT_INSTANCE(x) ((x) >> 24)
339 #define ASF_SRAM_CORR_FAULT_ADDR(x) ((x) & GENMASK(23, 0))
340
341 #define ASF_SRAM_FAULT_STATS 0x328
342 #define ASF_SRAM_FAULT_UNCORR_STATS(x) ((x) >> 16)
343 #define ASF_SRAM_FAULT_CORR_STATS(x) ((x) & GENMASK(15, 0))
344
345 #define ASF_TRANS_TOUT_CTRL 0x330
346 #define ASF_TRANS_TOUT_EN BIT(31)
347 #define ASF_TRANS_TOUT_VAL(x) (x)
348
349 #define ASF_TRANS_TOUT_FAULT_MASK 0x334
350 #define ASF_TRANS_TOUT_FAULT_STATUS 0x338
351 #define ASF_TRANS_TOUT_FAULT_APB BIT(3)
352 #define ASF_TRANS_TOUT_FAULT_SCL_LOW BIT(2)
353 #define ASF_TRANS_TOUT_FAULT_SCL_HIGH BIT(1)
354 #define ASF_TRANS_TOUT_FAULT_FSCL_HIGH BIT(0)
355
356 #define ASF_PROTO_FAULT_MASK 0x340
357 #define ASF_PROTO_FAULT_STATUS 0x344
358 #define ASF_PROTO_FAULT_SLVSDR_RD_ABORT BIT(31)
359 #define ASF_PROTO_FAULT_SLVDDR_FAIL BIT(30)
360 #define ASF_PROTO_FAULT_S(x) BIT(16 + (x))
361 #define ASF_PROTO_FAULT_MSTSDR_RD_ABORT BIT(15)
362 #define ASF_PROTO_FAULT_MSTDDR_FAIL BIT(14)
363 #define ASF_PROTO_FAULT_M(x) BIT(x)
364
365 struct cdns_i3c_master_caps {
366 u32 cmdfifodepth;
367 u32 cmdrfifodepth;
368 u32 txfifodepth;
369 u32 rxfifodepth;
370 u32 ibirfifodepth;
371 };
372
373 struct cdns_i3c_cmd {
374 u32 cmd0;
375 u32 cmd1;
376 u32 tx_len;
377 const void *tx_buf;
378 u32 rx_len;
379 void *rx_buf;
380 u32 error;
381 };
382
383 struct cdns_i3c_xfer {
384 struct list_head node;
385 struct completion comp;
386 int ret;
387 unsigned int ncmds;
388 struct cdns_i3c_cmd cmds[0];
389 };
390
391 struct cdns_i3c_master {
392 struct work_struct hj_work;
393 struct i3c_master_controller base;
394 u32 free_rr_slots;
395 unsigned int maxdevs;
396 struct {
397 unsigned int num_slots;
398 struct i3c_dev_desc **slots;
399 spinlock_t lock;
400 } ibi;
401 struct {
402 struct list_head list;
403 struct cdns_i3c_xfer *cur;
404 spinlock_t lock;
405 } xferqueue;
406 void __iomem *regs;
407 struct clk *sysclk;
408 struct clk *pclk;
409 struct cdns_i3c_master_caps caps;
410 unsigned long i3c_scl_lim;
411 };
412
413 static inline struct cdns_i3c_master *
414 to_cdns_i3c_master(struct i3c_master_controller *master)
415 {
416 return container_of(master, struct cdns_i3c_master, base);
417 }
418
419 static void cdns_i3c_master_wr_to_tx_fifo(struct cdns_i3c_master *master,
420 const u8 *bytes, int nbytes)
421 {
422 writesl(master->regs + TX_FIFO, bytes, nbytes / 4);
423 if (nbytes & 3) {
424 u32 tmp = 0;
425
426 memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3);
427 writesl(master->regs + TX_FIFO, &tmp, 1);
428 }
429 }
430
431 static void cdns_i3c_master_rd_from_rx_fifo(struct cdns_i3c_master *master,
432 u8 *bytes, int nbytes)
433 {
434 readsl(master->regs + RX_FIFO, bytes, nbytes / 4);
435 if (nbytes & 3) {
436 u32 tmp;
437
438 readsl(master->regs + RX_FIFO, &tmp, 1);
439 memcpy(bytes + (nbytes & ~3), &tmp, nbytes & 3);
440 }
441 }
442
443 static bool cdns_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
444 const struct i3c_ccc_cmd *cmd)
445 {
446 if (cmd->ndests > 1)
447 return false;
448
449 switch (cmd->id) {
450 case I3C_CCC_ENEC(true):
451 case I3C_CCC_ENEC(false):
452 case I3C_CCC_DISEC(true):
453 case I3C_CCC_DISEC(false):
454 case I3C_CCC_ENTAS(0, true):
455 case I3C_CCC_ENTAS(0, false):
456 case I3C_CCC_RSTDAA(true):
457 case I3C_CCC_RSTDAA(false):
458 case I3C_CCC_ENTDAA:
459 case I3C_CCC_SETMWL(true):
460 case I3C_CCC_SETMWL(false):
461 case I3C_CCC_SETMRL(true):
462 case I3C_CCC_SETMRL(false):
463 case I3C_CCC_DEFSLVS:
464 case I3C_CCC_ENTHDR(0):
465 case I3C_CCC_SETDASA:
466 case I3C_CCC_SETNEWDA:
467 case I3C_CCC_GETMWL:
468 case I3C_CCC_GETMRL:
469 case I3C_CCC_GETPID:
470 case I3C_CCC_GETBCR:
471 case I3C_CCC_GETDCR:
472 case I3C_CCC_GETSTATUS:
473 case I3C_CCC_GETACCMST:
474 case I3C_CCC_GETMXDS:
475 case I3C_CCC_GETHDRCAP:
476 return true;
477 default:
478 break;
479 }
480
481 return false;
482 }
483
484 static int cdns_i3c_master_disable(struct cdns_i3c_master *master)
485 {
486 u32 status;
487
488 writel(readl(master->regs + CTRL) & ~CTRL_DEV_EN, master->regs + CTRL);
489
490 return readl_poll_timeout(master->regs + MST_STATUS0, status,
491 status & MST_STATUS0_IDLE, 10, 1000000);
492 }
493
494 static void cdns_i3c_master_enable(struct cdns_i3c_master *master)
495 {
496 writel(readl(master->regs + CTRL) | CTRL_DEV_EN, master->regs + CTRL);
497 }
498
499 static struct cdns_i3c_xfer *
500 cdns_i3c_master_alloc_xfer(struct cdns_i3c_master *master, unsigned int ncmds)
501 {
502 struct cdns_i3c_xfer *xfer;
503
504 xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL);
505 if (!xfer)
506 return NULL;
507
508 INIT_LIST_HEAD(&xfer->node);
509 xfer->ncmds = ncmds;
510 xfer->ret = -ETIMEDOUT;
511
512 return xfer;
513 }
514
515 static void cdns_i3c_master_free_xfer(struct cdns_i3c_xfer *xfer)
516 {
517 kfree(xfer);
518 }
519
520 static void cdns_i3c_master_start_xfer_locked(struct cdns_i3c_master *master)
521 {
522 struct cdns_i3c_xfer *xfer = master->xferqueue.cur;
523 unsigned int i;
524
525 if (!xfer)
526 return;
527
528 writel(MST_INT_CMDD_EMP, master->regs + MST_ICR);
529 for (i = 0; i < xfer->ncmds; i++) {
530 struct cdns_i3c_cmd *cmd = &xfer->cmds[i];
531
532 cdns_i3c_master_wr_to_tx_fifo(master, cmd->tx_buf,
533 cmd->tx_len);
534 }
535
536 for (i = 0; i < xfer->ncmds; i++) {
537 struct cdns_i3c_cmd *cmd = &xfer->cmds[i];
538
539 writel(cmd->cmd1 | CMD1_FIFO_CMDID(i),
540 master->regs + CMD1_FIFO);
541 writel(cmd->cmd0, master->regs + CMD0_FIFO);
542 }
543
544 writel(readl(master->regs + CTRL) | CTRL_MCS,
545 master->regs + CTRL);
546 writel(MST_INT_CMDD_EMP, master->regs + MST_IER);
547 }
548
549 static void cdns_i3c_master_end_xfer_locked(struct cdns_i3c_master *master,
550 u32 isr)
551 {
552 struct cdns_i3c_xfer *xfer = master->xferqueue.cur;
553 int i, ret = 0;
554 u32 status0;
555
556 if (!xfer)
557 return;
558
559 if (!(isr & MST_INT_CMDD_EMP))
560 return;
561
562 writel(MST_INT_CMDD_EMP, master->regs + MST_IDR);
563
564 for (status0 = readl(master->regs + MST_STATUS0);
565 !(status0 & MST_STATUS0_CMDR_EMP);
566 status0 = readl(master->regs + MST_STATUS0)) {
567 struct cdns_i3c_cmd *cmd;
568 u32 cmdr, rx_len, id;
569
570 cmdr = readl(master->regs + CMDR);
571 id = CMDR_CMDID(cmdr);
572 if (id == CMDR_CMDID_HJACK_DISEC ||
573 id == CMDR_CMDID_HJACK_ENTDAA ||
574 WARN_ON(id >= xfer->ncmds))
575 continue;
576
577 cmd = &xfer->cmds[CMDR_CMDID(cmdr)];
578 rx_len = min_t(u32, CMDR_XFER_BYTES(cmdr), cmd->rx_len);
579 cdns_i3c_master_rd_from_rx_fifo(master, cmd->rx_buf, rx_len);
580 cmd->error = CMDR_ERROR(cmdr);
581 }
582
583 for (i = 0; i < xfer->ncmds; i++) {
584 switch (xfer->cmds[i].error) {
585 case CMDR_NO_ERROR:
586 break;
587
588 case CMDR_DDR_PREAMBLE_ERROR:
589 case CMDR_DDR_PARITY_ERROR:
590 case CMDR_M0_ERROR:
591 case CMDR_M1_ERROR:
592 case CMDR_M2_ERROR:
593 case CMDR_MST_ABORT:
594 case CMDR_NACK_RESP:
595 case CMDR_DDR_DROPPED:
596 ret = -EIO;
597 break;
598
599 case CMDR_DDR_RX_FIFO_OVF:
600 case CMDR_DDR_TX_FIFO_UNF:
601 ret = -ENOSPC;
602 break;
603
604 case CMDR_INVALID_DA:
605 default:
606 ret = -EINVAL;
607 break;
608 }
609 }
610
611 xfer->ret = ret;
612 complete(&xfer->comp);
613
614 xfer = list_first_entry_or_null(&master->xferqueue.list,
615 struct cdns_i3c_xfer, node);
616 if (xfer)
617 list_del_init(&xfer->node);
618
619 master->xferqueue.cur = xfer;
620 cdns_i3c_master_start_xfer_locked(master);
621 }
622
623 static void cdns_i3c_master_queue_xfer(struct cdns_i3c_master *master,
624 struct cdns_i3c_xfer *xfer)
625 {
626 unsigned long flags;
627
628 init_completion(&xfer->comp);
629 spin_lock_irqsave(&master->xferqueue.lock, flags);
630 if (master->xferqueue.cur) {
631 list_add_tail(&xfer->node, &master->xferqueue.list);
632 } else {
633 master->xferqueue.cur = xfer;
634 cdns_i3c_master_start_xfer_locked(master);
635 }
636 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
637 }
638
639 static void cdns_i3c_master_unqueue_xfer(struct cdns_i3c_master *master,
640 struct cdns_i3c_xfer *xfer)
641 {
642 unsigned long flags;
643
644 spin_lock_irqsave(&master->xferqueue.lock, flags);
645 if (master->xferqueue.cur == xfer) {
646 u32 status;
647
648 writel(readl(master->regs + CTRL) & ~CTRL_DEV_EN,
649 master->regs + CTRL);
650 readl_poll_timeout_atomic(master->regs + MST_STATUS0, status,
651 status & MST_STATUS0_IDLE, 10,
652 1000000);
653 master->xferqueue.cur = NULL;
654 writel(FLUSH_RX_FIFO | FLUSH_TX_FIFO | FLUSH_CMD_FIFO |
655 FLUSH_CMD_RESP,
656 master->regs + FLUSH_CTRL);
657 writel(MST_INT_CMDD_EMP, master->regs + MST_IDR);
658 writel(readl(master->regs + CTRL) | CTRL_DEV_EN,
659 master->regs + CTRL);
660 } else {
661 list_del_init(&xfer->node);
662 }
663 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
664 }
665
666 static enum i3c_error_code cdns_i3c_cmd_get_err(struct cdns_i3c_cmd *cmd)
667 {
668 switch (cmd->error) {
669 case CMDR_M0_ERROR:
670 return I3C_ERROR_M0;
671
672 case CMDR_M1_ERROR:
673 return I3C_ERROR_M1;
674
675 case CMDR_M2_ERROR:
676 case CMDR_NACK_RESP:
677 return I3C_ERROR_M2;
678
679 default:
680 break;
681 }
682
683 return I3C_ERROR_UNKNOWN;
684 }
685
686 static int cdns_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
687 struct i3c_ccc_cmd *cmd)
688 {
689 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
690 struct cdns_i3c_xfer *xfer;
691 struct cdns_i3c_cmd *ccmd;
692 int ret;
693
694 xfer = cdns_i3c_master_alloc_xfer(master, 1);
695 if (!xfer)
696 return -ENOMEM;
697
698 ccmd = xfer->cmds;
699 ccmd->cmd1 = CMD1_FIFO_CCC(cmd->id);
700 ccmd->cmd0 = CMD0_FIFO_IS_CCC |
701 CMD0_FIFO_PL_LEN(cmd->dests[0].payload.len);
702
703 if (cmd->id & I3C_CCC_DIRECT)
704 ccmd->cmd0 |= CMD0_FIFO_DEV_ADDR(cmd->dests[0].addr);
705
706 if (cmd->rnw) {
707 ccmd->cmd0 |= CMD0_FIFO_RNW;
708 ccmd->rx_buf = cmd->dests[0].payload.data;
709 ccmd->rx_len = cmd->dests[0].payload.len;
710 } else {
711 ccmd->tx_buf = cmd->dests[0].payload.data;
712 ccmd->tx_len = cmd->dests[0].payload.len;
713 }
714
715 cdns_i3c_master_queue_xfer(master, xfer);
716 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
717 cdns_i3c_master_unqueue_xfer(master, xfer);
718
719 ret = xfer->ret;
720 cmd->err = cdns_i3c_cmd_get_err(&xfer->cmds[0]);
721 cdns_i3c_master_free_xfer(xfer);
722
723 return ret;
724 }
725
726 static int cdns_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
727 struct i3c_priv_xfer *xfers,
728 int nxfers)
729 {
730 struct i3c_master_controller *m = i3c_dev_get_master(dev);
731 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
732 int txslots = 0, rxslots = 0, i, ret;
733 struct cdns_i3c_xfer *cdns_xfer;
734
735 for (i = 0; i < nxfers; i++) {
736 if (xfers[i].len > CMD0_FIFO_PL_LEN_MAX)
737 return -ENOTSUPP;
738 }
739
740 if (!nxfers)
741 return 0;
742
743 if (nxfers > master->caps.cmdfifodepth ||
744 nxfers > master->caps.cmdrfifodepth)
745 return -ENOTSUPP;
746
747
748
749
750
751 for (i = 0; i < nxfers; i++) {
752 if (xfers[i].rnw)
753 rxslots += DIV_ROUND_UP(xfers[i].len, 4);
754 else
755 txslots += DIV_ROUND_UP(xfers[i].len, 4);
756 }
757
758 if (rxslots > master->caps.rxfifodepth ||
759 txslots > master->caps.txfifodepth)
760 return -ENOTSUPP;
761
762 cdns_xfer = cdns_i3c_master_alloc_xfer(master, nxfers);
763 if (!cdns_xfer)
764 return -ENOMEM;
765
766 for (i = 0; i < nxfers; i++) {
767 struct cdns_i3c_cmd *ccmd = &cdns_xfer->cmds[i];
768 u32 pl_len = xfers[i].len;
769
770 ccmd->cmd0 = CMD0_FIFO_DEV_ADDR(dev->info.dyn_addr) |
771 CMD0_FIFO_PRIV_XMIT_MODE(XMIT_BURST_WITHOUT_SUBADDR);
772
773 if (xfers[i].rnw) {
774 ccmd->cmd0 |= CMD0_FIFO_RNW;
775 ccmd->rx_buf = xfers[i].data.in;
776 ccmd->rx_len = xfers[i].len;
777 pl_len++;
778 } else {
779 ccmd->tx_buf = xfers[i].data.out;
780 ccmd->tx_len = xfers[i].len;
781 }
782
783 ccmd->cmd0 |= CMD0_FIFO_PL_LEN(pl_len);
784
785 if (i < nxfers - 1)
786 ccmd->cmd0 |= CMD0_FIFO_RSBC;
787
788 if (!i)
789 ccmd->cmd0 |= CMD0_FIFO_BCH;
790 }
791
792 cdns_i3c_master_queue_xfer(master, cdns_xfer);
793 if (!wait_for_completion_timeout(&cdns_xfer->comp,
794 msecs_to_jiffies(1000)))
795 cdns_i3c_master_unqueue_xfer(master, cdns_xfer);
796
797 ret = cdns_xfer->ret;
798
799 for (i = 0; i < nxfers; i++)
800 xfers[i].err = cdns_i3c_cmd_get_err(&cdns_xfer->cmds[i]);
801
802 cdns_i3c_master_free_xfer(cdns_xfer);
803
804 return ret;
805 }
806
807 static int cdns_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
808 const struct i2c_msg *xfers, int nxfers)
809 {
810 struct i3c_master_controller *m = i2c_dev_get_master(dev);
811 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
812 unsigned int nrxwords = 0, ntxwords = 0;
813 struct cdns_i3c_xfer *xfer;
814 int i, ret = 0;
815
816 if (nxfers > master->caps.cmdfifodepth)
817 return -ENOTSUPP;
818
819 for (i = 0; i < nxfers; i++) {
820 if (xfers[i].len > CMD0_FIFO_PL_LEN_MAX)
821 return -ENOTSUPP;
822
823 if (xfers[i].flags & I2C_M_RD)
824 nrxwords += DIV_ROUND_UP(xfers[i].len, 4);
825 else
826 ntxwords += DIV_ROUND_UP(xfers[i].len, 4);
827 }
828
829 if (ntxwords > master->caps.txfifodepth ||
830 nrxwords > master->caps.rxfifodepth)
831 return -ENOTSUPP;
832
833 xfer = cdns_i3c_master_alloc_xfer(master, nxfers);
834 if (!xfer)
835 return -ENOMEM;
836
837 for (i = 0; i < nxfers; i++) {
838 struct cdns_i3c_cmd *ccmd = &xfer->cmds[i];
839
840 ccmd->cmd0 = CMD0_FIFO_DEV_ADDR(xfers[i].addr) |
841 CMD0_FIFO_PL_LEN(xfers[i].len) |
842 CMD0_FIFO_PRIV_XMIT_MODE(XMIT_BURST_WITHOUT_SUBADDR);
843
844 if (xfers[i].flags & I2C_M_TEN)
845 ccmd->cmd0 |= CMD0_FIFO_IS_10B;
846
847 if (xfers[i].flags & I2C_M_RD) {
848 ccmd->cmd0 |= CMD0_FIFO_RNW;
849 ccmd->rx_buf = xfers[i].buf;
850 ccmd->rx_len = xfers[i].len;
851 } else {
852 ccmd->tx_buf = xfers[i].buf;
853 ccmd->tx_len = xfers[i].len;
854 }
855 }
856
857 cdns_i3c_master_queue_xfer(master, xfer);
858 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
859 cdns_i3c_master_unqueue_xfer(master, xfer);
860
861 ret = xfer->ret;
862 cdns_i3c_master_free_xfer(xfer);
863
864 return ret;
865 }
866
867 struct cdns_i3c_i2c_dev_data {
868 u16 id;
869 s16 ibi;
870 struct i3c_generic_ibi_pool *ibi_pool;
871 };
872
873 static u32 prepare_rr0_dev_address(u32 addr)
874 {
875 u32 ret = (addr << 1) & 0xff;
876
877
878 ret |= (addr & GENMASK(6, 0)) << 1;
879
880
881 ret |= (addr & GENMASK(9, 7)) << 6;
882
883
884 if (!(hweight8(addr & 0x7f) & 1))
885 ret |= 1;
886
887 return ret;
888 }
889
890 static void cdns_i3c_master_upd_i3c_addr(struct i3c_dev_desc *dev)
891 {
892 struct i3c_master_controller *m = i3c_dev_get_master(dev);
893 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
894 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
895 u32 rr;
896
897 rr = prepare_rr0_dev_address(dev->info.dyn_addr ?
898 dev->info.dyn_addr :
899 dev->info.static_addr);
900 writel(DEV_ID_RR0_IS_I3C | rr, master->regs + DEV_ID_RR0(data->id));
901 }
902
903 static int cdns_i3c_master_get_rr_slot(struct cdns_i3c_master *master,
904 u8 dyn_addr)
905 {
906 unsigned long activedevs;
907 u32 rr;
908 int i;
909
910 if (!dyn_addr) {
911 if (!master->free_rr_slots)
912 return -ENOSPC;
913
914 return ffs(master->free_rr_slots) - 1;
915 }
916
917 activedevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
918 activedevs &= ~BIT(0);
919
920 for_each_set_bit(i, &activedevs, master->maxdevs + 1) {
921 rr = readl(master->regs + DEV_ID_RR0(i));
922 if (!(rr & DEV_ID_RR0_IS_I3C) ||
923 DEV_ID_RR0_GET_DEV_ADDR(rr) != dyn_addr)
924 continue;
925
926 return i;
927 }
928
929 return -EINVAL;
930 }
931
932 static int cdns_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
933 u8 old_dyn_addr)
934 {
935 cdns_i3c_master_upd_i3c_addr(dev);
936
937 return 0;
938 }
939
940 static int cdns_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
941 {
942 struct i3c_master_controller *m = i3c_dev_get_master(dev);
943 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
944 struct cdns_i3c_i2c_dev_data *data;
945 int slot;
946
947 data = kzalloc(sizeof(*data), GFP_KERNEL);
948 if (!data)
949 return -ENOMEM;
950
951 slot = cdns_i3c_master_get_rr_slot(master, dev->info.dyn_addr);
952 if (slot < 0) {
953 kfree(data);
954 return slot;
955 }
956
957 data->ibi = -1;
958 data->id = slot;
959 i3c_dev_set_master_data(dev, data);
960 master->free_rr_slots &= ~BIT(slot);
961
962 if (!dev->info.dyn_addr) {
963 cdns_i3c_master_upd_i3c_addr(dev);
964 writel(readl(master->regs + DEVS_CTRL) |
965 DEVS_CTRL_DEV_ACTIVE(data->id),
966 master->regs + DEVS_CTRL);
967 }
968
969 return 0;
970 }
971
972 static void cdns_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
973 {
974 struct i3c_master_controller *m = i3c_dev_get_master(dev);
975 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
976 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
977
978 writel(readl(master->regs + DEVS_CTRL) |
979 DEVS_CTRL_DEV_CLR(data->id),
980 master->regs + DEVS_CTRL);
981
982 i3c_dev_set_master_data(dev, NULL);
983 master->free_rr_slots |= BIT(data->id);
984 kfree(data);
985 }
986
987 static int cdns_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
988 {
989 struct i3c_master_controller *m = i2c_dev_get_master(dev);
990 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
991 struct cdns_i3c_i2c_dev_data *data;
992 int slot;
993
994 slot = cdns_i3c_master_get_rr_slot(master, 0);
995 if (slot < 0)
996 return slot;
997
998 data = kzalloc(sizeof(*data), GFP_KERNEL);
999 if (!data)
1000 return -ENOMEM;
1001
1002 data->id = slot;
1003 master->free_rr_slots &= ~BIT(slot);
1004 i2c_dev_set_master_data(dev, data);
1005
1006 writel(prepare_rr0_dev_address(dev->addr),
1007 master->regs + DEV_ID_RR0(data->id));
1008 writel(dev->lvr, master->regs + DEV_ID_RR2(data->id));
1009 writel(readl(master->regs + DEVS_CTRL) |
1010 DEVS_CTRL_DEV_ACTIVE(data->id),
1011 master->regs + DEVS_CTRL);
1012
1013 return 0;
1014 }
1015
1016 static void cdns_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
1017 {
1018 struct i3c_master_controller *m = i2c_dev_get_master(dev);
1019 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1020 struct cdns_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
1021
1022 writel(readl(master->regs + DEVS_CTRL) |
1023 DEVS_CTRL_DEV_CLR(data->id),
1024 master->regs + DEVS_CTRL);
1025 master->free_rr_slots |= BIT(data->id);
1026
1027 i2c_dev_set_master_data(dev, NULL);
1028 kfree(data);
1029 }
1030
1031 static void cdns_i3c_master_bus_cleanup(struct i3c_master_controller *m)
1032 {
1033 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1034
1035 cdns_i3c_master_disable(master);
1036 }
1037
1038 static void cdns_i3c_master_dev_rr_to_info(struct cdns_i3c_master *master,
1039 unsigned int slot,
1040 struct i3c_device_info *info)
1041 {
1042 u32 rr;
1043
1044 memset(info, 0, sizeof(*info));
1045 rr = readl(master->regs + DEV_ID_RR0(slot));
1046 info->dyn_addr = DEV_ID_RR0_GET_DEV_ADDR(rr);
1047 rr = readl(master->regs + DEV_ID_RR2(slot));
1048 info->dcr = rr;
1049 info->bcr = rr >> 8;
1050 info->pid = rr >> 16;
1051 info->pid |= (u64)readl(master->regs + DEV_ID_RR1(slot)) << 16;
1052 }
1053
1054 static void cdns_i3c_master_upd_i3c_scl_lim(struct cdns_i3c_master *master)
1055 {
1056 struct i3c_master_controller *m = &master->base;
1057 unsigned long i3c_lim_period, pres_step, ncycles;
1058 struct i3c_bus *bus = i3c_master_get_bus(m);
1059 unsigned long new_i3c_scl_lim = 0;
1060 struct i3c_dev_desc *dev;
1061 u32 prescl1, ctrl;
1062
1063 i3c_bus_for_each_i3cdev(bus, dev) {
1064 unsigned long max_fscl;
1065
1066 max_fscl = max(I3C_CCC_MAX_SDR_FSCL(dev->info.max_read_ds),
1067 I3C_CCC_MAX_SDR_FSCL(dev->info.max_write_ds));
1068 switch (max_fscl) {
1069 case I3C_SDR1_FSCL_8MHZ:
1070 max_fscl = 8000000;
1071 break;
1072 case I3C_SDR2_FSCL_6MHZ:
1073 max_fscl = 6000000;
1074 break;
1075 case I3C_SDR3_FSCL_4MHZ:
1076 max_fscl = 4000000;
1077 break;
1078 case I3C_SDR4_FSCL_2MHZ:
1079 max_fscl = 2000000;
1080 break;
1081 case I3C_SDR0_FSCL_MAX:
1082 default:
1083 max_fscl = 0;
1084 break;
1085 }
1086
1087 if (max_fscl &&
1088 (new_i3c_scl_lim > max_fscl || !new_i3c_scl_lim))
1089 new_i3c_scl_lim = max_fscl;
1090 }
1091
1092
1093 if (new_i3c_scl_lim == master->i3c_scl_lim)
1094 return;
1095 master->i3c_scl_lim = new_i3c_scl_lim;
1096 if (!new_i3c_scl_lim)
1097 return;
1098 pres_step = 1000000000UL / (bus->scl_rate.i3c * 4);
1099
1100
1101 prescl1 = readl(master->regs + PRESCL_CTRL1) &
1102 ~PRESCL_CTRL1_PP_LOW_MASK;
1103 ctrl = readl(master->regs + CTRL);
1104
1105 i3c_lim_period = DIV_ROUND_UP(1000000000, master->i3c_scl_lim);
1106 ncycles = DIV_ROUND_UP(i3c_lim_period, pres_step);
1107 if (ncycles < 4)
1108 ncycles = 0;
1109 else
1110 ncycles -= 4;
1111
1112 prescl1 |= PRESCL_CTRL1_PP_LOW(ncycles);
1113
1114
1115 if (ctrl & CTRL_DEV_EN)
1116 cdns_i3c_master_disable(master);
1117
1118 writel(prescl1, master->regs + PRESCL_CTRL1);
1119
1120 if (ctrl & CTRL_DEV_EN)
1121 cdns_i3c_master_enable(master);
1122 }
1123
1124 static int cdns_i3c_master_do_daa(struct i3c_master_controller *m)
1125 {
1126 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1127 unsigned long olddevs, newdevs;
1128 int ret, slot;
1129 u8 addrs[MAX_DEVS] = { };
1130 u8 last_addr = 0;
1131
1132 olddevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
1133 olddevs |= BIT(0);
1134
1135
1136 for_each_clear_bit(slot, &olddevs, master->maxdevs + 1) {
1137 ret = i3c_master_get_free_addr(m, last_addr + 1);
1138 if (ret < 0)
1139 return -ENOSPC;
1140
1141 last_addr = ret;
1142 addrs[slot] = last_addr;
1143 writel(prepare_rr0_dev_address(last_addr) | DEV_ID_RR0_IS_I3C,
1144 master->regs + DEV_ID_RR0(slot));
1145 writel(0, master->regs + DEV_ID_RR1(slot));
1146 writel(0, master->regs + DEV_ID_RR2(slot));
1147 }
1148
1149 ret = i3c_master_entdaa_locked(&master->base);
1150 if (ret && ret != I3C_ERROR_M2)
1151 return ret;
1152
1153 newdevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
1154 newdevs &= ~olddevs;
1155
1156
1157
1158
1159
1160 for_each_set_bit(slot, &newdevs, master->maxdevs + 1)
1161 i3c_master_add_i3c_dev_locked(m, addrs[slot]);
1162
1163
1164
1165
1166
1167
1168
1169 writel(readl(master->regs + DEVS_CTRL) |
1170 master->free_rr_slots << DEVS_CTRL_DEV_CLR_SHIFT,
1171 master->regs + DEVS_CTRL);
1172
1173 i3c_master_defslvs_locked(&master->base);
1174
1175 cdns_i3c_master_upd_i3c_scl_lim(master);
1176
1177
1178 i3c_master_enec_locked(m, I3C_BROADCAST_ADDR,
1179 I3C_CCC_EVENT_HJ | I3C_CCC_EVENT_MR);
1180
1181 return 0;
1182 }
1183
1184 static int cdns_i3c_master_bus_init(struct i3c_master_controller *m)
1185 {
1186 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1187 unsigned long pres_step, sysclk_rate, max_i2cfreq;
1188 struct i3c_bus *bus = i3c_master_get_bus(m);
1189 u32 ctrl, prescl0, prescl1, pres, low;
1190 struct i3c_device_info info = { };
1191 int ret, ncycles;
1192
1193 switch (bus->mode) {
1194 case I3C_BUS_MODE_PURE:
1195 ctrl = CTRL_PURE_BUS_MODE;
1196 break;
1197
1198 case I3C_BUS_MODE_MIXED_FAST:
1199 ctrl = CTRL_MIXED_FAST_BUS_MODE;
1200 break;
1201
1202 case I3C_BUS_MODE_MIXED_SLOW:
1203 ctrl = CTRL_MIXED_SLOW_BUS_MODE;
1204 break;
1205
1206 default:
1207 return -EINVAL;
1208 }
1209
1210 sysclk_rate = clk_get_rate(master->sysclk);
1211 if (!sysclk_rate)
1212 return -EINVAL;
1213
1214 pres = DIV_ROUND_UP(sysclk_rate, (bus->scl_rate.i3c * 4)) - 1;
1215 if (pres > PRESCL_CTRL0_MAX)
1216 return -ERANGE;
1217
1218 bus->scl_rate.i3c = sysclk_rate / ((pres + 1) * 4);
1219
1220 prescl0 = PRESCL_CTRL0_I3C(pres);
1221
1222 low = ((I3C_BUS_TLOW_OD_MIN_NS * sysclk_rate) / (pres + 1)) - 2;
1223 prescl1 = PRESCL_CTRL1_OD_LOW(low);
1224
1225 max_i2cfreq = bus->scl_rate.i2c;
1226
1227 pres = (sysclk_rate / (max_i2cfreq * 5)) - 1;
1228 if (pres > PRESCL_CTRL0_MAX)
1229 return -ERANGE;
1230
1231 bus->scl_rate.i2c = sysclk_rate / ((pres + 1) * 5);
1232
1233 prescl0 |= PRESCL_CTRL0_I2C(pres);
1234 writel(prescl0, master->regs + PRESCL_CTRL0);
1235
1236
1237 pres_step = 1000000000 / (bus->scl_rate.i3c * 4);
1238 ncycles = DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, pres_step) - 2;
1239 if (ncycles < 0)
1240 ncycles = 0;
1241 prescl1 = PRESCL_CTRL1_OD_LOW(ncycles);
1242 writel(prescl1, master->regs + PRESCL_CTRL1);
1243
1244
1245 ret = i3c_master_get_free_addr(m, 0);
1246 if (ret < 0)
1247 return ret;
1248
1249 writel(prepare_rr0_dev_address(ret) | DEV_ID_RR0_IS_I3C,
1250 master->regs + DEV_ID_RR0(0));
1251
1252 cdns_i3c_master_dev_rr_to_info(master, 0, &info);
1253 if (info.bcr & I3C_BCR_HDR_CAP)
1254 info.hdr_cap = I3C_CCC_HDR_MODE(I3C_HDR_DDR);
1255
1256 ret = i3c_master_set_info(&master->base, &info);
1257 if (ret)
1258 return ret;
1259
1260
1261
1262
1263
1264
1265
1266 ctrl |= CTRL_HJ_ACK | CTRL_HJ_DISEC | CTRL_HALT_EN | CTRL_MCS_EN;
1267 writel(ctrl, master->regs + CTRL);
1268
1269 cdns_i3c_master_enable(master);
1270
1271 return 0;
1272 }
1273
1274 static void cdns_i3c_master_handle_ibi(struct cdns_i3c_master *master,
1275 u32 ibir)
1276 {
1277 struct cdns_i3c_i2c_dev_data *data;
1278 bool data_consumed = false;
1279 struct i3c_ibi_slot *slot;
1280 u32 id = IBIR_SLVID(ibir);
1281 struct i3c_dev_desc *dev;
1282 size_t nbytes;
1283 u8 *buf;
1284
1285
1286
1287
1288
1289 if (id >= master->ibi.num_slots || (ibir & IBIR_ERROR))
1290 goto out;
1291
1292 dev = master->ibi.slots[id];
1293 spin_lock(&master->ibi.lock);
1294
1295 data = i3c_dev_get_master_data(dev);
1296 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
1297 if (!slot)
1298 goto out_unlock;
1299
1300 buf = slot->data;
1301
1302 nbytes = IBIR_XFER_BYTES(ibir);
1303 readsl(master->regs + IBI_DATA_FIFO, buf, nbytes / 4);
1304 if (nbytes % 3) {
1305 u32 tmp = __raw_readl(master->regs + IBI_DATA_FIFO);
1306
1307 memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3);
1308 }
1309
1310 slot->len = min_t(unsigned int, IBIR_XFER_BYTES(ibir),
1311 dev->ibi->max_payload_len);
1312 i3c_master_queue_ibi(dev, slot);
1313 data_consumed = true;
1314
1315 out_unlock:
1316 spin_unlock(&master->ibi.lock);
1317
1318 out:
1319
1320 if (!data_consumed) {
1321 int i;
1322
1323 for (i = 0; i < IBIR_XFER_BYTES(ibir); i += 4)
1324 readl(master->regs + IBI_DATA_FIFO);
1325 }
1326 }
1327
1328 static void cnds_i3c_master_demux_ibis(struct cdns_i3c_master *master)
1329 {
1330 u32 status0;
1331
1332 writel(MST_INT_IBIR_THR, master->regs + MST_ICR);
1333
1334 for (status0 = readl(master->regs + MST_STATUS0);
1335 !(status0 & MST_STATUS0_IBIR_EMP);
1336 status0 = readl(master->regs + MST_STATUS0)) {
1337 u32 ibir = readl(master->regs + IBIR);
1338
1339 switch (IBIR_TYPE(ibir)) {
1340 case IBIR_TYPE_IBI:
1341 cdns_i3c_master_handle_ibi(master, ibir);
1342 break;
1343
1344 case IBIR_TYPE_HJ:
1345 WARN_ON(IBIR_XFER_BYTES(ibir) || (ibir & IBIR_ERROR));
1346 queue_work(master->base.wq, &master->hj_work);
1347 break;
1348
1349 case IBIR_TYPE_MR:
1350 WARN_ON(IBIR_XFER_BYTES(ibir) || (ibir & IBIR_ERROR));
1351 default:
1352 break;
1353 }
1354 }
1355 }
1356
1357 static irqreturn_t cdns_i3c_master_interrupt(int irq, void *data)
1358 {
1359 struct cdns_i3c_master *master = data;
1360 u32 status;
1361
1362 status = readl(master->regs + MST_ISR);
1363 if (!(status & readl(master->regs + MST_IMR)))
1364 return IRQ_NONE;
1365
1366 spin_lock(&master->xferqueue.lock);
1367 cdns_i3c_master_end_xfer_locked(master, status);
1368 spin_unlock(&master->xferqueue.lock);
1369
1370 if (status & MST_INT_IBIR_THR)
1371 cnds_i3c_master_demux_ibis(master);
1372
1373 return IRQ_HANDLED;
1374 }
1375
1376 static int cdns_i3c_master_disable_ibi(struct i3c_dev_desc *dev)
1377 {
1378 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1379 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1380 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1381 unsigned long flags;
1382 u32 sirmap;
1383 int ret;
1384
1385 ret = i3c_master_disec_locked(m, dev->info.dyn_addr,
1386 I3C_CCC_EVENT_SIR);
1387 if (ret)
1388 return ret;
1389
1390 spin_lock_irqsave(&master->ibi.lock, flags);
1391 sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
1392 sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
1393 sirmap |= SIR_MAP_DEV_CONF(data->ibi,
1394 SIR_MAP_DEV_DA(I3C_BROADCAST_ADDR));
1395 writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
1396 spin_unlock_irqrestore(&master->ibi.lock, flags);
1397
1398 return ret;
1399 }
1400
1401 static int cdns_i3c_master_enable_ibi(struct i3c_dev_desc *dev)
1402 {
1403 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1404 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1405 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1406 unsigned long flags;
1407 u32 sircfg, sirmap;
1408 int ret;
1409
1410 spin_lock_irqsave(&master->ibi.lock, flags);
1411 sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
1412 sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
1413 sircfg = SIR_MAP_DEV_ROLE(dev->info.bcr >> 6) |
1414 SIR_MAP_DEV_DA(dev->info.dyn_addr) |
1415 SIR_MAP_DEV_PL(dev->info.max_ibi_len) |
1416 SIR_MAP_DEV_ACK;
1417
1418 if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM)
1419 sircfg |= SIR_MAP_DEV_SLOW;
1420
1421 sirmap |= SIR_MAP_DEV_CONF(data->ibi, sircfg);
1422 writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
1423 spin_unlock_irqrestore(&master->ibi.lock, flags);
1424
1425 ret = i3c_master_enec_locked(m, dev->info.dyn_addr,
1426 I3C_CCC_EVENT_SIR);
1427 if (ret) {
1428 spin_lock_irqsave(&master->ibi.lock, flags);
1429 sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
1430 sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
1431 sirmap |= SIR_MAP_DEV_CONF(data->ibi,
1432 SIR_MAP_DEV_DA(I3C_BROADCAST_ADDR));
1433 writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
1434 spin_unlock_irqrestore(&master->ibi.lock, flags);
1435 }
1436
1437 return ret;
1438 }
1439
1440 static int cdns_i3c_master_request_ibi(struct i3c_dev_desc *dev,
1441 const struct i3c_ibi_setup *req)
1442 {
1443 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1444 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1445 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1446 unsigned long flags;
1447 unsigned int i;
1448
1449 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req);
1450 if (IS_ERR(data->ibi_pool))
1451 return PTR_ERR(data->ibi_pool);
1452
1453 spin_lock_irqsave(&master->ibi.lock, flags);
1454 for (i = 0; i < master->ibi.num_slots; i++) {
1455 if (!master->ibi.slots[i]) {
1456 data->ibi = i;
1457 master->ibi.slots[i] = dev;
1458 break;
1459 }
1460 }
1461 spin_unlock_irqrestore(&master->ibi.lock, flags);
1462
1463 if (i < master->ibi.num_slots)
1464 return 0;
1465
1466 i3c_generic_ibi_free_pool(data->ibi_pool);
1467 data->ibi_pool = NULL;
1468
1469 return -ENOSPC;
1470 }
1471
1472 static void cdns_i3c_master_free_ibi(struct i3c_dev_desc *dev)
1473 {
1474 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1475 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1476 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1477 unsigned long flags;
1478
1479 spin_lock_irqsave(&master->ibi.lock, flags);
1480 master->ibi.slots[data->ibi] = NULL;
1481 data->ibi = -1;
1482 spin_unlock_irqrestore(&master->ibi.lock, flags);
1483
1484 i3c_generic_ibi_free_pool(data->ibi_pool);
1485 }
1486
1487 static void cdns_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev,
1488 struct i3c_ibi_slot *slot)
1489 {
1490 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1491
1492 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
1493 }
1494
1495 static const struct i3c_master_controller_ops cdns_i3c_master_ops = {
1496 .bus_init = cdns_i3c_master_bus_init,
1497 .bus_cleanup = cdns_i3c_master_bus_cleanup,
1498 .do_daa = cdns_i3c_master_do_daa,
1499 .attach_i3c_dev = cdns_i3c_master_attach_i3c_dev,
1500 .reattach_i3c_dev = cdns_i3c_master_reattach_i3c_dev,
1501 .detach_i3c_dev = cdns_i3c_master_detach_i3c_dev,
1502 .attach_i2c_dev = cdns_i3c_master_attach_i2c_dev,
1503 .detach_i2c_dev = cdns_i3c_master_detach_i2c_dev,
1504 .supports_ccc_cmd = cdns_i3c_master_supports_ccc_cmd,
1505 .send_ccc_cmd = cdns_i3c_master_send_ccc_cmd,
1506 .priv_xfers = cdns_i3c_master_priv_xfers,
1507 .i2c_xfers = cdns_i3c_master_i2c_xfers,
1508 .enable_ibi = cdns_i3c_master_enable_ibi,
1509 .disable_ibi = cdns_i3c_master_disable_ibi,
1510 .request_ibi = cdns_i3c_master_request_ibi,
1511 .free_ibi = cdns_i3c_master_free_ibi,
1512 .recycle_ibi_slot = cdns_i3c_master_recycle_ibi_slot,
1513 };
1514
1515 static void cdns_i3c_master_hj(struct work_struct *work)
1516 {
1517 struct cdns_i3c_master *master = container_of(work,
1518 struct cdns_i3c_master,
1519 hj_work);
1520
1521 i3c_master_do_daa(&master->base);
1522 }
1523
1524 static int cdns_i3c_master_probe(struct platform_device *pdev)
1525 {
1526 struct cdns_i3c_master *master;
1527 struct resource *res;
1528 int ret, irq;
1529 u32 val;
1530
1531 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1532 if (!master)
1533 return -ENOMEM;
1534
1535 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1536 master->regs = devm_ioremap_resource(&pdev->dev, res);
1537 if (IS_ERR(master->regs))
1538 return PTR_ERR(master->regs);
1539
1540 master->pclk = devm_clk_get(&pdev->dev, "pclk");
1541 if (IS_ERR(master->pclk))
1542 return PTR_ERR(master->pclk);
1543
1544 master->sysclk = devm_clk_get(&pdev->dev, "sysclk");
1545 if (IS_ERR(master->sysclk))
1546 return PTR_ERR(master->sysclk);
1547
1548 irq = platform_get_irq(pdev, 0);
1549 if (irq < 0)
1550 return irq;
1551
1552 ret = clk_prepare_enable(master->pclk);
1553 if (ret)
1554 return ret;
1555
1556 ret = clk_prepare_enable(master->sysclk);
1557 if (ret)
1558 goto err_disable_pclk;
1559
1560 if (readl(master->regs + DEV_ID) != DEV_ID_I3C_MASTER) {
1561 ret = -EINVAL;
1562 goto err_disable_sysclk;
1563 }
1564
1565 spin_lock_init(&master->xferqueue.lock);
1566 INIT_LIST_HEAD(&master->xferqueue.list);
1567
1568 INIT_WORK(&master->hj_work, cdns_i3c_master_hj);
1569 writel(0xffffffff, master->regs + MST_IDR);
1570 writel(0xffffffff, master->regs + SLV_IDR);
1571 ret = devm_request_irq(&pdev->dev, irq, cdns_i3c_master_interrupt, 0,
1572 dev_name(&pdev->dev), master);
1573 if (ret)
1574 goto err_disable_sysclk;
1575
1576 platform_set_drvdata(pdev, master);
1577
1578 val = readl(master->regs + CONF_STATUS0);
1579
1580
1581 master->maxdevs = CONF_STATUS0_DEVS_NUM(val);
1582 master->free_rr_slots = GENMASK(master->maxdevs, 1);
1583
1584 val = readl(master->regs + CONF_STATUS1);
1585 master->caps.cmdfifodepth = CONF_STATUS1_CMD_DEPTH(val);
1586 master->caps.rxfifodepth = CONF_STATUS1_RX_DEPTH(val);
1587 master->caps.txfifodepth = CONF_STATUS1_TX_DEPTH(val);
1588 master->caps.ibirfifodepth = CONF_STATUS0_IBIR_DEPTH(val);
1589 master->caps.cmdrfifodepth = CONF_STATUS0_CMDR_DEPTH(val);
1590
1591 spin_lock_init(&master->ibi.lock);
1592 master->ibi.num_slots = CONF_STATUS1_IBI_HW_RES(val);
1593 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots,
1594 sizeof(*master->ibi.slots),
1595 GFP_KERNEL);
1596 if (!master->ibi.slots)
1597 goto err_disable_sysclk;
1598
1599 writel(IBIR_THR(1), master->regs + CMD_IBI_THR_CTRL);
1600 writel(MST_INT_IBIR_THR, master->regs + MST_IER);
1601 writel(DEVS_CTRL_DEV_CLR_ALL, master->regs + DEVS_CTRL);
1602
1603 ret = i3c_master_register(&master->base, &pdev->dev,
1604 &cdns_i3c_master_ops, false);
1605 if (ret)
1606 goto err_disable_sysclk;
1607
1608 return 0;
1609
1610 err_disable_sysclk:
1611 clk_disable_unprepare(master->sysclk);
1612
1613 err_disable_pclk:
1614 clk_disable_unprepare(master->pclk);
1615
1616 return ret;
1617 }
1618
1619 static int cdns_i3c_master_remove(struct platform_device *pdev)
1620 {
1621 struct cdns_i3c_master *master = platform_get_drvdata(pdev);
1622 int ret;
1623
1624 ret = i3c_master_unregister(&master->base);
1625 if (ret)
1626 return ret;
1627
1628 clk_disable_unprepare(master->sysclk);
1629 clk_disable_unprepare(master->pclk);
1630
1631 return 0;
1632 }
1633
1634 static const struct of_device_id cdns_i3c_master_of_ids[] = {
1635 { .compatible = "cdns,i3c-master" },
1636 { },
1637 };
1638
1639 static struct platform_driver cdns_i3c_master = {
1640 .probe = cdns_i3c_master_probe,
1641 .remove = cdns_i3c_master_remove,
1642 .driver = {
1643 .name = "cdns-i3c-master",
1644 .of_match_table = cdns_i3c_master_of_ids,
1645 },
1646 };
1647 module_platform_driver(cdns_i3c_master);
1648
1649 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>");
1650 MODULE_DESCRIPTION("Cadence I3C master driver");
1651 MODULE_LICENSE("GPL v2");
1652 MODULE_ALIAS("platform:cdns-i3c-master");