This source file includes following definitions.
- to_davinci_clockevent
- davinci_clockevent_read
- davinci_clockevent_write
- davinci_tim12_shutdown
- davinci_tim12_set_oneshot
- davinci_clockevent_shutdown
- davinci_clockevent_set_oneshot
- davinci_clockevent_set_next_event_std
- davinci_clockevent_set_next_event_cmp
- davinci_timer_irq_timer
- davinci_timer_read_sched_clock
- davinci_clocksource_read
- davinci_clocksource_init_tim34
- davinci_clocksource_init_tim12
- davinci_timer_init
- davinci_timer_register
- of_davinci_timer_register
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10 #include <linux/clk.h>
11 #include <linux/clockchips.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/sched_clock.h>
17
18 #include <clocksource/timer-davinci.h>
19
20 #undef pr_fmt
21 #define pr_fmt(fmt) "%s: " fmt "\n", __func__
22
23 #define DAVINCI_TIMER_REG_TIM12 0x10
24 #define DAVINCI_TIMER_REG_TIM34 0x14
25 #define DAVINCI_TIMER_REG_PRD12 0x18
26 #define DAVINCI_TIMER_REG_PRD34 0x1c
27 #define DAVINCI_TIMER_REG_TCR 0x20
28 #define DAVINCI_TIMER_REG_TGCR 0x24
29
30 #define DAVINCI_TIMER_TIMMODE_MASK GENMASK(3, 2)
31 #define DAVINCI_TIMER_RESET_MASK GENMASK(1, 0)
32 #define DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED BIT(2)
33 #define DAVINCI_TIMER_UNRESET GENMASK(1, 0)
34
35 #define DAVINCI_TIMER_ENAMODE_MASK GENMASK(1, 0)
36 #define DAVINCI_TIMER_ENAMODE_DISABLED 0x00
37 #define DAVINCI_TIMER_ENAMODE_ONESHOT BIT(0)
38 #define DAVINCI_TIMER_ENAMODE_PERIODIC BIT(1)
39
40 #define DAVINCI_TIMER_ENAMODE_SHIFT_TIM12 6
41 #define DAVINCI_TIMER_ENAMODE_SHIFT_TIM34 22
42
43 #define DAVINCI_TIMER_MIN_DELTA 0x01
44 #define DAVINCI_TIMER_MAX_DELTA 0xfffffffe
45
46 #define DAVINCI_TIMER_CLKSRC_BITS 32
47
48 #define DAVINCI_TIMER_TGCR_DEFAULT \
49 (DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED | DAVINCI_TIMER_UNRESET)
50
51 struct davinci_clockevent {
52 struct clock_event_device dev;
53 void __iomem *base;
54 unsigned int cmp_off;
55 };
56
57
58
59
60
61 static struct {
62 struct clocksource dev;
63 void __iomem *base;
64 unsigned int tim_off;
65 } davinci_clocksource;
66
67 static struct davinci_clockevent *
68 to_davinci_clockevent(struct clock_event_device *clockevent)
69 {
70 return container_of(clockevent, struct davinci_clockevent, dev);
71 }
72
73 static unsigned int
74 davinci_clockevent_read(struct davinci_clockevent *clockevent,
75 unsigned int reg)
76 {
77 return readl_relaxed(clockevent->base + reg);
78 }
79
80 static void davinci_clockevent_write(struct davinci_clockevent *clockevent,
81 unsigned int reg, unsigned int val)
82 {
83 writel_relaxed(val, clockevent->base + reg);
84 }
85
86 static void davinci_tim12_shutdown(void __iomem *base)
87 {
88 unsigned int tcr;
89
90 tcr = DAVINCI_TIMER_ENAMODE_DISABLED <<
91 DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
92
93
94
95
96
97 tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC <<
98 DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
99
100 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
101 }
102
103 static void davinci_tim12_set_oneshot(void __iomem *base)
104 {
105 unsigned int tcr;
106
107 tcr = DAVINCI_TIMER_ENAMODE_ONESHOT <<
108 DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
109
110 tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC <<
111 DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
112
113 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
114 }
115
116 static int davinci_clockevent_shutdown(struct clock_event_device *dev)
117 {
118 struct davinci_clockevent *clockevent;
119
120 clockevent = to_davinci_clockevent(dev);
121
122 davinci_tim12_shutdown(clockevent->base);
123
124 return 0;
125 }
126
127 static int davinci_clockevent_set_oneshot(struct clock_event_device *dev)
128 {
129 struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
130
131 davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_TIM12, 0x0);
132
133 davinci_tim12_set_oneshot(clockevent->base);
134
135 return 0;
136 }
137
138 static int
139 davinci_clockevent_set_next_event_std(unsigned long cycles,
140 struct clock_event_device *dev)
141 {
142 struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
143
144 davinci_clockevent_shutdown(dev);
145
146 davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_TIM12, 0x0);
147 davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_PRD12, cycles);
148
149 davinci_clockevent_set_oneshot(dev);
150
151 return 0;
152 }
153
154 static int
155 davinci_clockevent_set_next_event_cmp(unsigned long cycles,
156 struct clock_event_device *dev)
157 {
158 struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
159 unsigned int curr_time;
160
161 curr_time = davinci_clockevent_read(clockevent,
162 DAVINCI_TIMER_REG_TIM12);
163 davinci_clockevent_write(clockevent,
164 clockevent->cmp_off, curr_time + cycles);
165
166 return 0;
167 }
168
169 static irqreturn_t davinci_timer_irq_timer(int irq, void *data)
170 {
171 struct davinci_clockevent *clockevent = data;
172
173 if (!clockevent_state_oneshot(&clockevent->dev))
174 davinci_tim12_shutdown(clockevent->base);
175
176 clockevent->dev.event_handler(&clockevent->dev);
177
178 return IRQ_HANDLED;
179 }
180
181 static u64 notrace davinci_timer_read_sched_clock(void)
182 {
183 return readl_relaxed(davinci_clocksource.base +
184 davinci_clocksource.tim_off);
185 }
186
187 static u64 davinci_clocksource_read(struct clocksource *dev)
188 {
189 return davinci_timer_read_sched_clock();
190 }
191
192
193
194
195
196
197 static void davinci_clocksource_init_tim34(void __iomem *base)
198 {
199 int tcr;
200
201 tcr = DAVINCI_TIMER_ENAMODE_PERIODIC <<
202 DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
203 tcr |= DAVINCI_TIMER_ENAMODE_ONESHOT <<
204 DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
205
206 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34);
207 writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD34);
208 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
209 }
210
211
212
213
214
215
216 static void davinci_clocksource_init_tim12(void __iomem *base)
217 {
218 unsigned int tcr;
219
220 tcr = DAVINCI_TIMER_ENAMODE_PERIODIC <<
221 DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
222
223 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12);
224 writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD12);
225 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
226 }
227
228 static void davinci_timer_init(void __iomem *base)
229 {
230
231 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TCR);
232
233
234
235
236 writel_relaxed(DAVINCI_TIMER_TGCR_DEFAULT,
237 base + DAVINCI_TIMER_REG_TGCR);
238
239 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12);
240 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34);
241 }
242
243 int __init davinci_timer_register(struct clk *clk,
244 const struct davinci_timer_cfg *timer_cfg)
245 {
246 struct davinci_clockevent *clockevent;
247 unsigned int tick_rate;
248 void __iomem *base;
249 int rv;
250
251 rv = clk_prepare_enable(clk);
252 if (rv) {
253 pr_err("Unable to prepare and enable the timer clock");
254 return rv;
255 }
256
257 if (!request_mem_region(timer_cfg->reg.start,
258 resource_size(&timer_cfg->reg),
259 "davinci-timer")) {
260 pr_err("Unable to request memory region");
261 return -EBUSY;
262 }
263
264 base = ioremap(timer_cfg->reg.start, resource_size(&timer_cfg->reg));
265 if (!base) {
266 pr_err("Unable to map the register range");
267 return -ENOMEM;
268 }
269
270 davinci_timer_init(base);
271 tick_rate = clk_get_rate(clk);
272
273 clockevent = kzalloc(sizeof(*clockevent), GFP_KERNEL | __GFP_NOFAIL);
274 if (!clockevent) {
275 pr_err("Error allocating memory for clockevent data");
276 return -ENOMEM;
277 }
278
279 clockevent->dev.name = "tim12";
280 clockevent->dev.features = CLOCK_EVT_FEAT_ONESHOT;
281 clockevent->dev.cpumask = cpumask_of(0);
282 clockevent->base = base;
283
284 if (timer_cfg->cmp_off) {
285 clockevent->cmp_off = timer_cfg->cmp_off;
286 clockevent->dev.set_next_event =
287 davinci_clockevent_set_next_event_cmp;
288 } else {
289 clockevent->dev.set_next_event =
290 davinci_clockevent_set_next_event_std;
291 clockevent->dev.set_state_oneshot =
292 davinci_clockevent_set_oneshot;
293 clockevent->dev.set_state_shutdown =
294 davinci_clockevent_shutdown;
295 }
296
297 rv = request_irq(timer_cfg->irq[DAVINCI_TIMER_CLOCKEVENT_IRQ].start,
298 davinci_timer_irq_timer, IRQF_TIMER,
299 "clockevent/tim12", clockevent);
300 if (rv) {
301 pr_err("Unable to request the clockevent interrupt");
302 return rv;
303 }
304
305 davinci_clocksource.dev.rating = 300;
306 davinci_clocksource.dev.read = davinci_clocksource_read;
307 davinci_clocksource.dev.mask =
308 CLOCKSOURCE_MASK(DAVINCI_TIMER_CLKSRC_BITS);
309 davinci_clocksource.dev.flags = CLOCK_SOURCE_IS_CONTINUOUS;
310 davinci_clocksource.base = base;
311
312 if (timer_cfg->cmp_off) {
313 davinci_clocksource.dev.name = "tim12";
314 davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM12;
315 davinci_clocksource_init_tim12(base);
316 } else {
317 davinci_clocksource.dev.name = "tim34";
318 davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM34;
319 davinci_clocksource_init_tim34(base);
320 }
321
322 clockevents_config_and_register(&clockevent->dev, tick_rate,
323 DAVINCI_TIMER_MIN_DELTA,
324 DAVINCI_TIMER_MAX_DELTA);
325
326 rv = clocksource_register_hz(&davinci_clocksource.dev, tick_rate);
327 if (rv) {
328 pr_err("Unable to register clocksource");
329 return rv;
330 }
331
332 sched_clock_register(davinci_timer_read_sched_clock,
333 DAVINCI_TIMER_CLKSRC_BITS, tick_rate);
334
335 return 0;
336 }
337
338 static int __init of_davinci_timer_register(struct device_node *np)
339 {
340 struct davinci_timer_cfg timer_cfg = { };
341 struct clk *clk;
342 int rv;
343
344 rv = of_address_to_resource(np, 0, &timer_cfg.reg);
345 if (rv) {
346 pr_err("Unable to get the register range for timer");
347 return rv;
348 }
349
350 rv = of_irq_to_resource_table(np, timer_cfg.irq,
351 DAVINCI_TIMER_NUM_IRQS);
352 if (rv != DAVINCI_TIMER_NUM_IRQS) {
353 pr_err("Unable to get the interrupts for timer");
354 return rv;
355 }
356
357 clk = of_clk_get(np, 0);
358 if (IS_ERR(clk)) {
359 pr_err("Unable to get the timer clock");
360 return PTR_ERR(clk);
361 }
362
363 rv = davinci_timer_register(clk, &timer_cfg);
364 if (rv)
365 clk_put(clk);
366
367 return rv;
368 }
369 TIMER_OF_DECLARE(davinci_timer, "ti,da830-timer", of_davinci_timer_register);