1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA v0 core
5 *
6 * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
7 */
8
9 #ifndef _DW_EDMA_V0_REGS_H
10 #define _DW_EDMA_V0_REGS_H
11
12 #include <linux/dmaengine.h>
13
14 #define EDMA_V0_MAX_NR_CH 8
15 #define EDMA_V0_VIEWPORT_MASK GENMASK(2, 0)
16 #define EDMA_V0_DONE_INT_MASK GENMASK(7, 0)
17 #define EDMA_V0_ABORT_INT_MASK GENMASK(23, 16)
18 #define EDMA_V0_WRITE_CH_COUNT_MASK GENMASK(3, 0)
19 #define EDMA_V0_READ_CH_COUNT_MASK GENMASK(19, 16)
20 #define EDMA_V0_CH_STATUS_MASK GENMASK(6, 5)
21 #define EDMA_V0_DOORBELL_CH_MASK GENMASK(2, 0)
22 #define EDMA_V0_LINKED_LIST_ERR_MASK GENMASK(7, 0)
23
24 #define EDMA_V0_CH_ODD_MSI_DATA_MASK GENMASK(31, 16)
25 #define EDMA_V0_CH_EVEN_MSI_DATA_MASK GENMASK(15, 0)
26
27 struct dw_edma_v0_ch_regs {
28 u32 ch_control1; /* 0x000 */
29 u32 ch_control2; /* 0x004 */
30 u32 transfer_size; /* 0x008 */
31 u32 sar_low; /* 0x00c */
32 u32 sar_high; /* 0x010 */
33 u32 dar_low; /* 0x014 */
34 u32 dar_high; /* 0x018 */
35 u32 llp_low; /* 0x01c */
36 u32 llp_high; /* 0x020 */
37 };
38
39 struct dw_edma_v0_ch {
40 struct dw_edma_v0_ch_regs wr; /* 0x200 */
41 u32 padding_1[55]; /* [0x224..0x2fc] */
42 struct dw_edma_v0_ch_regs rd; /* 0x300 */
43 u32 padding_2[55]; /* [0x224..0x2fc] */
44 };
45
46 struct dw_edma_v0_unroll {
47 u32 padding_1; /* 0x0f8 */
48 u32 wr_engine_chgroup; /* 0x100 */
49 u32 rd_engine_chgroup; /* 0x104 */
50 u32 wr_engine_hshake_cnt_low; /* 0x108 */
51 u32 wr_engine_hshake_cnt_high; /* 0x10c */
52 u32 padding_2[2]; /* [0x110..0x114] */
53 u32 rd_engine_hshake_cnt_low; /* 0x118 */
54 u32 rd_engine_hshake_cnt_high; /* 0x11c */
55 u32 padding_3[2]; /* [0x120..0x124] */
56 u32 wr_ch0_pwr_en; /* 0x128 */
57 u32 wr_ch1_pwr_en; /* 0x12c */
58 u32 wr_ch2_pwr_en; /* 0x130 */
59 u32 wr_ch3_pwr_en; /* 0x134 */
60 u32 wr_ch4_pwr_en; /* 0x138 */
61 u32 wr_ch5_pwr_en; /* 0x13c */
62 u32 wr_ch6_pwr_en; /* 0x140 */
63 u32 wr_ch7_pwr_en; /* 0x144 */
64 u32 padding_4[8]; /* [0x148..0x164] */
65 u32 rd_ch0_pwr_en; /* 0x168 */
66 u32 rd_ch1_pwr_en; /* 0x16c */
67 u32 rd_ch2_pwr_en; /* 0x170 */
68 u32 rd_ch3_pwr_en; /* 0x174 */
69 u32 rd_ch4_pwr_en; /* 0x178 */
70 u32 rd_ch5_pwr_en; /* 0x18c */
71 u32 rd_ch6_pwr_en; /* 0x180 */
72 u32 rd_ch7_pwr_en; /* 0x184 */
73 u32 padding_5[30]; /* [0x188..0x1fc] */
74 struct dw_edma_v0_ch ch[EDMA_V0_MAX_NR_CH]; /* [0x200..0x1120] */
75 };
76
77 struct dw_edma_v0_legacy {
78 u32 viewport_sel; /* 0x0f8 */
79 struct dw_edma_v0_ch_regs ch; /* [0x100..0x120] */
80 };
81
82 struct dw_edma_v0_regs {
83 /* eDMA global registers */
84 u32 ctrl_data_arb_prior; /* 0x000 */
85 u32 padding_1; /* 0x004 */
86 u32 ctrl; /* 0x008 */
87 u32 wr_engine_en; /* 0x00c */
88 u32 wr_doorbell; /* 0x010 */
89 u32 padding_2; /* 0x014 */
90 u32 wr_ch_arb_weight_low; /* 0x018 */
91 u32 wr_ch_arb_weight_high; /* 0x01c */
92 u32 padding_3[3]; /* [0x020..0x028] */
93 u32 rd_engine_en; /* 0x02c */
94 u32 rd_doorbell; /* 0x030 */
95 u32 padding_4; /* 0x034 */
96 u32 rd_ch_arb_weight_low; /* 0x038 */
97 u32 rd_ch_arb_weight_high; /* 0x03c */
98 u32 padding_5[3]; /* [0x040..0x048] */
99 /* eDMA interrupts registers */
100 u32 wr_int_status; /* 0x04c */
101 u32 padding_6; /* 0x050 */
102 u32 wr_int_mask; /* 0x054 */
103 u32 wr_int_clear; /* 0x058 */
104 u32 wr_err_status; /* 0x05c */
105 u32 wr_done_imwr_low; /* 0x060 */
106 u32 wr_done_imwr_high; /* 0x064 */
107 u32 wr_abort_imwr_low; /* 0x068 */
108 u32 wr_abort_imwr_high; /* 0x06c */
109 u32 wr_ch01_imwr_data; /* 0x070 */
110 u32 wr_ch23_imwr_data; /* 0x074 */
111 u32 wr_ch45_imwr_data; /* 0x078 */
112 u32 wr_ch67_imwr_data; /* 0x07c */
113 u32 padding_7[4]; /* [0x080..0x08c] */
114 u32 wr_linked_list_err_en; /* 0x090 */
115 u32 padding_8[3]; /* [0x094..0x09c] */
116 u32 rd_int_status; /* 0x0a0 */
117 u32 padding_9; /* 0x0a4 */
118 u32 rd_int_mask; /* 0x0a8 */
119 u32 rd_int_clear; /* 0x0ac */
120 u32 padding_10; /* 0x0b0 */
121 u32 rd_err_status_low; /* 0x0b4 */
122 u32 rd_err_status_high; /* 0x0b8 */
123 u32 padding_11[2]; /* [0x0bc..0x0c0] */
124 u32 rd_linked_list_err_en; /* 0x0c4 */
125 u32 padding_12; /* 0x0c8 */
126 u32 rd_done_imwr_low; /* 0x0cc */
127 u32 rd_done_imwr_high; /* 0x0d0 */
128 u32 rd_abort_imwr_low; /* 0x0d4 */
129 u32 rd_abort_imwr_high; /* 0x0d8 */
130 u32 rd_ch01_imwr_data; /* 0x0dc */
131 u32 rd_ch23_imwr_data; /* 0x0e0 */
132 u32 rd_ch45_imwr_data; /* 0x0e4 */
133 u32 rd_ch67_imwr_data; /* 0x0e8 */
134 u32 padding_13[4]; /* [0x0ec..0x0f8] */
135 /* eDMA channel context grouping */
136 union dw_edma_v0_type {
137 struct dw_edma_v0_legacy legacy; /* [0x0f8..0x120] */
138 struct dw_edma_v0_unroll unroll; /* [0x0f8..0x1120] */
139 } type;
140 };
141
142 struct dw_edma_v0_lli {
143 u32 control;
144 u32 transfer_size;
145 u32 sar_low;
146 u32 sar_high;
147 u32 dar_low;
148 u32 dar_high;
149 };
150
151 struct dw_edma_v0_llp {
152 u32 control;
153 u32 reserved;
154 u32 llp_low;
155 u32 llp_high;
156 };
157
158 #endif /* _DW_EDMA_V0_REGS_H */