This source file includes following definitions.
- to_jz4780_dma_chan
- to_jz4780_dma_desc
- jz4780_dma_chan_parent
- jz4780_dma_chn_readl
- jz4780_dma_chn_writel
- jz4780_dma_ctrl_readl
- jz4780_dma_ctrl_writel
- jz4780_dma_chan_enable
- jz4780_dma_chan_disable
- jz4780_dma_desc_alloc
- jz4780_dma_desc_free
- jz4780_dma_transfer_size
- jz4780_dma_setup_hwdesc
- jz4780_dma_prep_slave_sg
- jz4780_dma_prep_dma_cyclic
- jz4780_dma_prep_dma_memcpy
- jz4780_dma_begin
- jz4780_dma_issue_pending
- jz4780_dma_terminate_all
- jz4780_dma_synchronize
- jz4780_dma_config
- jz4780_dma_desc_residue
- jz4780_dma_tx_status
- jz4780_dma_chan_irq
- jz4780_dma_irq_handler
- jz4780_dma_alloc_chan_resources
- jz4780_dma_free_chan_resources
- jz4780_dma_filter_fn
- jz4780_of_dma_xlate
- jz4780_dma_probe
- jz4780_dma_remove
- jz4780_dma_init
- jz4780_dma_exit
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8
9 #include <linux/clk.h>
10 #include <linux/dmapool.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_device.h>
16 #include <linux/of_dma.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19
20 #include "dmaengine.h"
21 #include "virt-dma.h"
22
23
24 #define JZ_DMA_REG_DMAC 0x00
25 #define JZ_DMA_REG_DIRQP 0x04
26 #define JZ_DMA_REG_DDR 0x08
27 #define JZ_DMA_REG_DDRS 0x0c
28 #define JZ_DMA_REG_DCKE 0x10
29 #define JZ_DMA_REG_DCKES 0x14
30 #define JZ_DMA_REG_DCKEC 0x18
31 #define JZ_DMA_REG_DMACP 0x1c
32 #define JZ_DMA_REG_DSIRQP 0x20
33 #define JZ_DMA_REG_DSIRQM 0x24
34 #define JZ_DMA_REG_DCIRQP 0x28
35 #define JZ_DMA_REG_DCIRQM 0x2c
36
37
38 #define JZ_DMA_REG_CHAN(n) (n * 0x20)
39 #define JZ_DMA_REG_DSA 0x00
40 #define JZ_DMA_REG_DTA 0x04
41 #define JZ_DMA_REG_DTC 0x08
42 #define JZ_DMA_REG_DRT 0x0c
43 #define JZ_DMA_REG_DCS 0x10
44 #define JZ_DMA_REG_DCM 0x14
45 #define JZ_DMA_REG_DDA 0x18
46 #define JZ_DMA_REG_DSD 0x1c
47
48 #define JZ_DMA_DMAC_DMAE BIT(0)
49 #define JZ_DMA_DMAC_AR BIT(2)
50 #define JZ_DMA_DMAC_HLT BIT(3)
51 #define JZ_DMA_DMAC_FAIC BIT(27)
52 #define JZ_DMA_DMAC_FMSC BIT(31)
53
54 #define JZ_DMA_DRT_AUTO 0x8
55
56 #define JZ_DMA_DCS_CTE BIT(0)
57 #define JZ_DMA_DCS_HLT BIT(2)
58 #define JZ_DMA_DCS_TT BIT(3)
59 #define JZ_DMA_DCS_AR BIT(4)
60 #define JZ_DMA_DCS_DES8 BIT(30)
61
62 #define JZ_DMA_DCM_LINK BIT(0)
63 #define JZ_DMA_DCM_TIE BIT(1)
64 #define JZ_DMA_DCM_STDE BIT(2)
65 #define JZ_DMA_DCM_TSZ_SHIFT 8
66 #define JZ_DMA_DCM_TSZ_MASK (0x7 << JZ_DMA_DCM_TSZ_SHIFT)
67 #define JZ_DMA_DCM_DP_SHIFT 12
68 #define JZ_DMA_DCM_SP_SHIFT 14
69 #define JZ_DMA_DCM_DAI BIT(22)
70 #define JZ_DMA_DCM_SAI BIT(23)
71
72 #define JZ_DMA_SIZE_4_BYTE 0x0
73 #define JZ_DMA_SIZE_1_BYTE 0x1
74 #define JZ_DMA_SIZE_2_BYTE 0x2
75 #define JZ_DMA_SIZE_16_BYTE 0x3
76 #define JZ_DMA_SIZE_32_BYTE 0x4
77 #define JZ_DMA_SIZE_64_BYTE 0x5
78 #define JZ_DMA_SIZE_128_BYTE 0x6
79
80 #define JZ_DMA_WIDTH_32_BIT 0x0
81 #define JZ_DMA_WIDTH_8_BIT 0x1
82 #define JZ_DMA_WIDTH_16_BIT 0x2
83
84 #define JZ_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
85 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
86 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
87
88 #define JZ4780_DMA_CTRL_OFFSET 0x1000
89
90
91 #define JZ_SOC_DATA_ALLOW_LEGACY_DT BIT(0)
92 #define JZ_SOC_DATA_PROGRAMMABLE_DMA BIT(1)
93 #define JZ_SOC_DATA_PER_CHAN_PM BIT(2)
94 #define JZ_SOC_DATA_NO_DCKES_DCKEC BIT(3)
95 #define JZ_SOC_DATA_BREAK_LINKS BIT(4)
96
97
98
99
100
101
102
103
104
105
106 struct jz4780_dma_hwdesc {
107 uint32_t dcm;
108 uint32_t dsa;
109 uint32_t dta;
110 uint32_t dtc;
111 };
112
113
114 #define JZ_DMA_DESC_BLOCK_SIZE PAGE_SIZE
115 #define JZ_DMA_MAX_DESC \
116 (JZ_DMA_DESC_BLOCK_SIZE / sizeof(struct jz4780_dma_hwdesc))
117
118 struct jz4780_dma_desc {
119 struct virt_dma_desc vdesc;
120
121 struct jz4780_dma_hwdesc *desc;
122 dma_addr_t desc_phys;
123 unsigned int count;
124 enum dma_transaction_type type;
125 uint32_t status;
126 };
127
128 struct jz4780_dma_chan {
129 struct virt_dma_chan vchan;
130 unsigned int id;
131 struct dma_pool *desc_pool;
132
133 uint32_t transfer_type;
134 uint32_t transfer_shift;
135 struct dma_slave_config config;
136
137 struct jz4780_dma_desc *desc;
138 unsigned int curr_hwdesc;
139 };
140
141 struct jz4780_dma_soc_data {
142 unsigned int nb_channels;
143 unsigned int transfer_ord_max;
144 unsigned long flags;
145 };
146
147 struct jz4780_dma_dev {
148 struct dma_device dma_device;
149 void __iomem *chn_base;
150 void __iomem *ctrl_base;
151 struct clk *clk;
152 unsigned int irq;
153 const struct jz4780_dma_soc_data *soc_data;
154
155 uint32_t chan_reserved;
156 struct jz4780_dma_chan chan[];
157 };
158
159 struct jz4780_dma_filter_data {
160 uint32_t transfer_type;
161 int channel;
162 };
163
164 static inline struct jz4780_dma_chan *to_jz4780_dma_chan(struct dma_chan *chan)
165 {
166 return container_of(chan, struct jz4780_dma_chan, vchan.chan);
167 }
168
169 static inline struct jz4780_dma_desc *to_jz4780_dma_desc(
170 struct virt_dma_desc *vdesc)
171 {
172 return container_of(vdesc, struct jz4780_dma_desc, vdesc);
173 }
174
175 static inline struct jz4780_dma_dev *jz4780_dma_chan_parent(
176 struct jz4780_dma_chan *jzchan)
177 {
178 return container_of(jzchan->vchan.chan.device, struct jz4780_dma_dev,
179 dma_device);
180 }
181
182 static inline uint32_t jz4780_dma_chn_readl(struct jz4780_dma_dev *jzdma,
183 unsigned int chn, unsigned int reg)
184 {
185 return readl(jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));
186 }
187
188 static inline void jz4780_dma_chn_writel(struct jz4780_dma_dev *jzdma,
189 unsigned int chn, unsigned int reg, uint32_t val)
190 {
191 writel(val, jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));
192 }
193
194 static inline uint32_t jz4780_dma_ctrl_readl(struct jz4780_dma_dev *jzdma,
195 unsigned int reg)
196 {
197 return readl(jzdma->ctrl_base + reg);
198 }
199
200 static inline void jz4780_dma_ctrl_writel(struct jz4780_dma_dev *jzdma,
201 unsigned int reg, uint32_t val)
202 {
203 writel(val, jzdma->ctrl_base + reg);
204 }
205
206 static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma,
207 unsigned int chn)
208 {
209 if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) {
210 unsigned int reg;
211
212 if (jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC)
213 reg = JZ_DMA_REG_DCKE;
214 else
215 reg = JZ_DMA_REG_DCKES;
216
217 jz4780_dma_ctrl_writel(jzdma, reg, BIT(chn));
218 }
219 }
220
221 static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev *jzdma,
222 unsigned int chn)
223 {
224 if ((jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) &&
225 !(jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC))
226 jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKEC, BIT(chn));
227 }
228
229 static struct jz4780_dma_desc *jz4780_dma_desc_alloc(
230 struct jz4780_dma_chan *jzchan, unsigned int count,
231 enum dma_transaction_type type)
232 {
233 struct jz4780_dma_desc *desc;
234
235 if (count > JZ_DMA_MAX_DESC)
236 return NULL;
237
238 desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
239 if (!desc)
240 return NULL;
241
242 desc->desc = dma_pool_alloc(jzchan->desc_pool, GFP_NOWAIT,
243 &desc->desc_phys);
244 if (!desc->desc) {
245 kfree(desc);
246 return NULL;
247 }
248
249 desc->count = count;
250 desc->type = type;
251 return desc;
252 }
253
254 static void jz4780_dma_desc_free(struct virt_dma_desc *vdesc)
255 {
256 struct jz4780_dma_desc *desc = to_jz4780_dma_desc(vdesc);
257 struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(vdesc->tx.chan);
258
259 dma_pool_free(jzchan->desc_pool, desc->desc, desc->desc_phys);
260 kfree(desc);
261 }
262
263 static uint32_t jz4780_dma_transfer_size(struct jz4780_dma_chan *jzchan,
264 unsigned long val, uint32_t *shift)
265 {
266 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
267 int ord = ffs(val) - 1;
268
269
270
271
272
273
274
275
276 if (ord == 3)
277 ord = 2;
278 else if (ord > jzdma->soc_data->transfer_ord_max)
279 ord = jzdma->soc_data->transfer_ord_max;
280
281 *shift = ord;
282
283 switch (ord) {
284 case 0:
285 return JZ_DMA_SIZE_1_BYTE;
286 case 1:
287 return JZ_DMA_SIZE_2_BYTE;
288 case 2:
289 return JZ_DMA_SIZE_4_BYTE;
290 case 4:
291 return JZ_DMA_SIZE_16_BYTE;
292 case 5:
293 return JZ_DMA_SIZE_32_BYTE;
294 case 6:
295 return JZ_DMA_SIZE_64_BYTE;
296 default:
297 return JZ_DMA_SIZE_128_BYTE;
298 }
299 }
300
301 static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan,
302 struct jz4780_dma_hwdesc *desc, dma_addr_t addr, size_t len,
303 enum dma_transfer_direction direction)
304 {
305 struct dma_slave_config *config = &jzchan->config;
306 uint32_t width, maxburst, tsz;
307
308 if (direction == DMA_MEM_TO_DEV) {
309 desc->dcm = JZ_DMA_DCM_SAI;
310 desc->dsa = addr;
311 desc->dta = config->dst_addr;
312
313 width = config->dst_addr_width;
314 maxburst = config->dst_maxburst;
315 } else {
316 desc->dcm = JZ_DMA_DCM_DAI;
317 desc->dsa = config->src_addr;
318 desc->dta = addr;
319
320 width = config->src_addr_width;
321 maxburst = config->src_maxburst;
322 }
323
324
325
326
327
328
329
330
331 tsz = jz4780_dma_transfer_size(jzchan, addr | len | (width * maxburst),
332 &jzchan->transfer_shift);
333
334 switch (width) {
335 case DMA_SLAVE_BUSWIDTH_1_BYTE:
336 case DMA_SLAVE_BUSWIDTH_2_BYTES:
337 break;
338 case DMA_SLAVE_BUSWIDTH_4_BYTES:
339 width = JZ_DMA_WIDTH_32_BIT;
340 break;
341 default:
342 return -EINVAL;
343 }
344
345 desc->dcm |= tsz << JZ_DMA_DCM_TSZ_SHIFT;
346 desc->dcm |= width << JZ_DMA_DCM_SP_SHIFT;
347 desc->dcm |= width << JZ_DMA_DCM_DP_SHIFT;
348
349 desc->dtc = len >> jzchan->transfer_shift;
350 return 0;
351 }
352
353 static struct dma_async_tx_descriptor *jz4780_dma_prep_slave_sg(
354 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
355 enum dma_transfer_direction direction, unsigned long flags,
356 void *context)
357 {
358 struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
359 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
360 struct jz4780_dma_desc *desc;
361 unsigned int i;
362 int err;
363
364 desc = jz4780_dma_desc_alloc(jzchan, sg_len, DMA_SLAVE);
365 if (!desc)
366 return NULL;
367
368 for (i = 0; i < sg_len; i++) {
369 err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i],
370 sg_dma_address(&sgl[i]),
371 sg_dma_len(&sgl[i]),
372 direction);
373 if (err < 0) {
374 jz4780_dma_desc_free(&jzchan->desc->vdesc);
375 return NULL;
376 }
377
378 desc->desc[i].dcm |= JZ_DMA_DCM_TIE;
379
380 if (i != (sg_len - 1) &&
381 !(jzdma->soc_data->flags & JZ_SOC_DATA_BREAK_LINKS)) {
382
383 desc->desc[i].dcm |= JZ_DMA_DCM_LINK;
384
385
386
387
388
389
390 desc->desc[i].dtc |=
391 (((i + 1) * sizeof(*desc->desc)) >> 4) << 24;
392 }
393 }
394
395 return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
396 }
397
398 static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_cyclic(
399 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
400 size_t period_len, enum dma_transfer_direction direction,
401 unsigned long flags)
402 {
403 struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
404 struct jz4780_dma_desc *desc;
405 unsigned int periods, i;
406 int err;
407
408 if (buf_len % period_len)
409 return NULL;
410
411 periods = buf_len / period_len;
412
413 desc = jz4780_dma_desc_alloc(jzchan, periods, DMA_CYCLIC);
414 if (!desc)
415 return NULL;
416
417 for (i = 0; i < periods; i++) {
418 err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i], buf_addr,
419 period_len, direction);
420 if (err < 0) {
421 jz4780_dma_desc_free(&jzchan->desc->vdesc);
422 return NULL;
423 }
424
425 buf_addr += period_len;
426
427
428
429
430
431
432
433 desc->desc[i].dcm |= JZ_DMA_DCM_TIE | JZ_DMA_DCM_LINK;
434
435
436
437
438
439
440
441 if (i != (periods - 1)) {
442 desc->desc[i].dtc |=
443 (((i + 1) * sizeof(*desc->desc)) >> 4) << 24;
444 }
445 }
446
447 return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
448 }
449
450 static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy(
451 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
452 size_t len, unsigned long flags)
453 {
454 struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
455 struct jz4780_dma_desc *desc;
456 uint32_t tsz;
457
458 desc = jz4780_dma_desc_alloc(jzchan, 1, DMA_MEMCPY);
459 if (!desc)
460 return NULL;
461
462 tsz = jz4780_dma_transfer_size(jzchan, dest | src | len,
463 &jzchan->transfer_shift);
464
465 jzchan->transfer_type = JZ_DMA_DRT_AUTO;
466
467 desc->desc[0].dsa = src;
468 desc->desc[0].dta = dest;
469 desc->desc[0].dcm = JZ_DMA_DCM_TIE | JZ_DMA_DCM_SAI | JZ_DMA_DCM_DAI |
470 tsz << JZ_DMA_DCM_TSZ_SHIFT |
471 JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_SP_SHIFT |
472 JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_DP_SHIFT;
473 desc->desc[0].dtc = len >> jzchan->transfer_shift;
474
475 return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
476 }
477
478 static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan)
479 {
480 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
481 struct virt_dma_desc *vdesc;
482 unsigned int i;
483 dma_addr_t desc_phys;
484
485 if (!jzchan->desc) {
486 vdesc = vchan_next_desc(&jzchan->vchan);
487 if (!vdesc)
488 return;
489
490 list_del(&vdesc->node);
491
492 jzchan->desc = to_jz4780_dma_desc(vdesc);
493 jzchan->curr_hwdesc = 0;
494
495 if (jzchan->desc->type == DMA_CYCLIC && vdesc->tx.callback) {
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510 for (i = 0; i < jzchan->desc->count; i++)
511 jzchan->desc->desc[i].dcm &= ~JZ_DMA_DCM_LINK;
512 }
513 } else {
514
515
516
517
518
519 jzchan->curr_hwdesc =
520 (jzchan->curr_hwdesc + 1) % jzchan->desc->count;
521 }
522
523
524 jz4780_dma_chan_enable(jzdma, jzchan->id);
525
526
527 jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
528
529
530 jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DRT,
531 jzchan->transfer_type);
532
533
534
535
536
537
538
539 jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DTC,
540 jzchan->desc->desc[jzchan->curr_hwdesc].dtc);
541
542
543 desc_phys = jzchan->desc->desc_phys +
544 (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc));
545 jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DDA, desc_phys);
546 jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id));
547
548
549 jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS,
550 JZ_DMA_DCS_CTE);
551 }
552
553 static void jz4780_dma_issue_pending(struct dma_chan *chan)
554 {
555 struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
556 unsigned long flags;
557
558 spin_lock_irqsave(&jzchan->vchan.lock, flags);
559
560 if (vchan_issue_pending(&jzchan->vchan) && !jzchan->desc)
561 jz4780_dma_begin(jzchan);
562
563 spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
564 }
565
566 static int jz4780_dma_terminate_all(struct dma_chan *chan)
567 {
568 struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
569 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
570 unsigned long flags;
571 LIST_HEAD(head);
572
573 spin_lock_irqsave(&jzchan->vchan.lock, flags);
574
575
576 jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
577 if (jzchan->desc) {
578 vchan_terminate_vdesc(&jzchan->desc->vdesc);
579 jzchan->desc = NULL;
580 }
581
582 jz4780_dma_chan_disable(jzdma, jzchan->id);
583
584 vchan_get_all_descriptors(&jzchan->vchan, &head);
585
586 spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
587
588 vchan_dma_desc_free_list(&jzchan->vchan, &head);
589 return 0;
590 }
591
592 static void jz4780_dma_synchronize(struct dma_chan *chan)
593 {
594 struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
595 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
596
597 vchan_synchronize(&jzchan->vchan);
598 jz4780_dma_chan_disable(jzdma, jzchan->id);
599 }
600
601 static int jz4780_dma_config(struct dma_chan *chan,
602 struct dma_slave_config *config)
603 {
604 struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
605
606 if ((config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
607 || (config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES))
608 return -EINVAL;
609
610
611 memcpy(&jzchan->config, config, sizeof(jzchan->config));
612
613 return 0;
614 }
615
616 static size_t jz4780_dma_desc_residue(struct jz4780_dma_chan *jzchan,
617 struct jz4780_dma_desc *desc, unsigned int next_sg)
618 {
619 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
620 unsigned int count = 0;
621 unsigned int i;
622
623 for (i = next_sg; i < desc->count; i++)
624 count += desc->desc[i].dtc & GENMASK(23, 0);
625
626 if (next_sg != 0)
627 count += jz4780_dma_chn_readl(jzdma, jzchan->id,
628 JZ_DMA_REG_DTC);
629
630 return count << jzchan->transfer_shift;
631 }
632
633 static enum dma_status jz4780_dma_tx_status(struct dma_chan *chan,
634 dma_cookie_t cookie, struct dma_tx_state *txstate)
635 {
636 struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
637 struct virt_dma_desc *vdesc;
638 enum dma_status status;
639 unsigned long flags;
640 unsigned long residue = 0;
641
642 status = dma_cookie_status(chan, cookie, txstate);
643 if ((status == DMA_COMPLETE) || (txstate == NULL))
644 return status;
645
646 spin_lock_irqsave(&jzchan->vchan.lock, flags);
647
648 vdesc = vchan_find_desc(&jzchan->vchan, cookie);
649 if (vdesc) {
650
651 residue = jz4780_dma_desc_residue(jzchan,
652 to_jz4780_dma_desc(vdesc), 0);
653 } else if (cookie == jzchan->desc->vdesc.tx.cookie) {
654 residue = jz4780_dma_desc_residue(jzchan, jzchan->desc,
655 jzchan->curr_hwdesc + 1);
656 }
657 dma_set_residue(txstate, residue);
658
659 if (vdesc && jzchan->desc && vdesc == &jzchan->desc->vdesc
660 && jzchan->desc->status & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT))
661 status = DMA_ERROR;
662
663 spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
664 return status;
665 }
666
667 static bool jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma,
668 struct jz4780_dma_chan *jzchan)
669 {
670 const unsigned int soc_flags = jzdma->soc_data->flags;
671 struct jz4780_dma_desc *desc = jzchan->desc;
672 uint32_t dcs;
673 bool ack = true;
674
675 spin_lock(&jzchan->vchan.lock);
676
677 dcs = jz4780_dma_chn_readl(jzdma, jzchan->id, JZ_DMA_REG_DCS);
678 jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
679
680 if (dcs & JZ_DMA_DCS_AR) {
681 dev_warn(&jzchan->vchan.chan.dev->device,
682 "address error (DCS=0x%x)\n", dcs);
683 }
684
685 if (dcs & JZ_DMA_DCS_HLT) {
686 dev_warn(&jzchan->vchan.chan.dev->device,
687 "channel halt (DCS=0x%x)\n", dcs);
688 }
689
690 if (jzchan->desc) {
691 jzchan->desc->status = dcs;
692
693 if ((dcs & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) == 0) {
694 if (jzchan->desc->type == DMA_CYCLIC) {
695 vchan_cyclic_callback(&jzchan->desc->vdesc);
696
697 jz4780_dma_begin(jzchan);
698 } else if (dcs & JZ_DMA_DCS_TT) {
699 if (!(soc_flags & JZ_SOC_DATA_BREAK_LINKS) ||
700 (jzchan->curr_hwdesc + 1 == desc->count)) {
701 vchan_cookie_complete(&desc->vdesc);
702 jzchan->desc = NULL;
703 }
704
705 jz4780_dma_begin(jzchan);
706 } else {
707
708 ack = false;
709 jz4780_dma_chn_writel(jzdma, jzchan->id,
710 JZ_DMA_REG_DCS,
711 JZ_DMA_DCS_CTE);
712 }
713 }
714 } else {
715 dev_err(&jzchan->vchan.chan.dev->device,
716 "channel IRQ with no active transfer\n");
717 }
718
719 spin_unlock(&jzchan->vchan.lock);
720
721 return ack;
722 }
723
724 static irqreturn_t jz4780_dma_irq_handler(int irq, void *data)
725 {
726 struct jz4780_dma_dev *jzdma = data;
727 unsigned int nb_channels = jzdma->soc_data->nb_channels;
728 unsigned long pending;
729 uint32_t dmac;
730 int i;
731
732 pending = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DIRQP);
733
734 for_each_set_bit(i, &pending, nb_channels) {
735 if (jz4780_dma_chan_irq(jzdma, &jzdma->chan[i]))
736 pending &= ~BIT(i);
737 }
738
739
740 dmac = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DMAC);
741 dmac &= ~(JZ_DMA_DMAC_HLT | JZ_DMA_DMAC_AR);
742 jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, dmac);
743
744
745 jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DIRQP, pending);
746
747 return IRQ_HANDLED;
748 }
749
750 static int jz4780_dma_alloc_chan_resources(struct dma_chan *chan)
751 {
752 struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
753
754 jzchan->desc_pool = dma_pool_create(dev_name(&chan->dev->device),
755 chan->device->dev,
756 JZ_DMA_DESC_BLOCK_SIZE,
757 PAGE_SIZE, 0);
758 if (!jzchan->desc_pool) {
759 dev_err(&chan->dev->device,
760 "failed to allocate descriptor pool\n");
761 return -ENOMEM;
762 }
763
764 return 0;
765 }
766
767 static void jz4780_dma_free_chan_resources(struct dma_chan *chan)
768 {
769 struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
770
771 vchan_free_chan_resources(&jzchan->vchan);
772 dma_pool_destroy(jzchan->desc_pool);
773 jzchan->desc_pool = NULL;
774 }
775
776 static bool jz4780_dma_filter_fn(struct dma_chan *chan, void *param)
777 {
778 struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
779 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
780 struct jz4780_dma_filter_data *data = param;
781
782
783 if (data->channel > -1) {
784 if (data->channel != jzchan->id)
785 return false;
786 } else if (jzdma->chan_reserved & BIT(jzchan->id)) {
787 return false;
788 }
789
790 jzchan->transfer_type = data->transfer_type;
791
792 return true;
793 }
794
795 static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec,
796 struct of_dma *ofdma)
797 {
798 struct jz4780_dma_dev *jzdma = ofdma->of_dma_data;
799 dma_cap_mask_t mask = jzdma->dma_device.cap_mask;
800 struct jz4780_dma_filter_data data;
801
802 if (dma_spec->args_count != 2)
803 return NULL;
804
805 data.transfer_type = dma_spec->args[0];
806 data.channel = dma_spec->args[1];
807
808 if (data.channel > -1) {
809 if (data.channel >= jzdma->soc_data->nb_channels) {
810 dev_err(jzdma->dma_device.dev,
811 "device requested non-existent channel %u\n",
812 data.channel);
813 return NULL;
814 }
815
816
817 if (!(jzdma->chan_reserved & BIT(data.channel))) {
818 dev_err(jzdma->dma_device.dev,
819 "device requested unreserved channel %u\n",
820 data.channel);
821 return NULL;
822 }
823
824 jzdma->chan[data.channel].transfer_type = data.transfer_type;
825
826 return dma_get_slave_channel(
827 &jzdma->chan[data.channel].vchan.chan);
828 } else {
829 return __dma_request_channel(&mask, jz4780_dma_filter_fn, &data,
830 ofdma->of_node);
831 }
832 }
833
834 static int jz4780_dma_probe(struct platform_device *pdev)
835 {
836 struct device *dev = &pdev->dev;
837 const struct jz4780_dma_soc_data *soc_data;
838 struct jz4780_dma_dev *jzdma;
839 struct jz4780_dma_chan *jzchan;
840 struct dma_device *dd;
841 struct resource *res;
842 int i, ret;
843
844 if (!dev->of_node) {
845 dev_err(dev, "This driver must be probed from devicetree\n");
846 return -EINVAL;
847 }
848
849 soc_data = device_get_match_data(dev);
850 if (!soc_data)
851 return -EINVAL;
852
853 jzdma = devm_kzalloc(dev, struct_size(jzdma, chan,
854 soc_data->nb_channels), GFP_KERNEL);
855 if (!jzdma)
856 return -ENOMEM;
857
858 jzdma->soc_data = soc_data;
859 platform_set_drvdata(pdev, jzdma);
860
861 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
862 if (!res) {
863 dev_err(dev, "failed to get I/O memory\n");
864 return -EINVAL;
865 }
866
867 jzdma->chn_base = devm_ioremap_resource(dev, res);
868 if (IS_ERR(jzdma->chn_base))
869 return PTR_ERR(jzdma->chn_base);
870
871 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
872 if (res) {
873 jzdma->ctrl_base = devm_ioremap_resource(dev, res);
874 if (IS_ERR(jzdma->ctrl_base))
875 return PTR_ERR(jzdma->ctrl_base);
876 } else if (soc_data->flags & JZ_SOC_DATA_ALLOW_LEGACY_DT) {
877
878
879
880
881
882 jzdma->ctrl_base = jzdma->chn_base + JZ4780_DMA_CTRL_OFFSET;
883 } else {
884 dev_err(dev, "failed to get I/O memory\n");
885 return -EINVAL;
886 }
887
888 ret = platform_get_irq(pdev, 0);
889 if (ret < 0)
890 return ret;
891
892 jzdma->irq = ret;
893
894 ret = request_irq(jzdma->irq, jz4780_dma_irq_handler, 0, dev_name(dev),
895 jzdma);
896 if (ret) {
897 dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq);
898 return ret;
899 }
900
901 jzdma->clk = devm_clk_get(dev, NULL);
902 if (IS_ERR(jzdma->clk)) {
903 dev_err(dev, "failed to get clock\n");
904 ret = PTR_ERR(jzdma->clk);
905 goto err_free_irq;
906 }
907
908 clk_prepare_enable(jzdma->clk);
909
910
911 of_property_read_u32_index(dev->of_node, "ingenic,reserved-channels",
912 0, &jzdma->chan_reserved);
913
914 dd = &jzdma->dma_device;
915
916 dma_cap_set(DMA_MEMCPY, dd->cap_mask);
917 dma_cap_set(DMA_SLAVE, dd->cap_mask);
918 dma_cap_set(DMA_CYCLIC, dd->cap_mask);
919
920 dd->dev = dev;
921 dd->copy_align = DMAENGINE_ALIGN_4_BYTES;
922 dd->device_alloc_chan_resources = jz4780_dma_alloc_chan_resources;
923 dd->device_free_chan_resources = jz4780_dma_free_chan_resources;
924 dd->device_prep_slave_sg = jz4780_dma_prep_slave_sg;
925 dd->device_prep_dma_cyclic = jz4780_dma_prep_dma_cyclic;
926 dd->device_prep_dma_memcpy = jz4780_dma_prep_dma_memcpy;
927 dd->device_config = jz4780_dma_config;
928 dd->device_terminate_all = jz4780_dma_terminate_all;
929 dd->device_synchronize = jz4780_dma_synchronize;
930 dd->device_tx_status = jz4780_dma_tx_status;
931 dd->device_issue_pending = jz4780_dma_issue_pending;
932 dd->src_addr_widths = JZ_DMA_BUSWIDTHS;
933 dd->dst_addr_widths = JZ_DMA_BUSWIDTHS;
934 dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
935 dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
936
937
938
939
940
941
942 jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, JZ_DMA_DMAC_DMAE |
943 JZ_DMA_DMAC_FAIC | JZ_DMA_DMAC_FMSC);
944
945 if (soc_data->flags & JZ_SOC_DATA_PROGRAMMABLE_DMA)
946 jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMACP, 0);
947
948 INIT_LIST_HEAD(&dd->channels);
949
950 for (i = 0; i < soc_data->nb_channels; i++) {
951 jzchan = &jzdma->chan[i];
952 jzchan->id = i;
953
954 vchan_init(&jzchan->vchan, dd);
955 jzchan->vchan.desc_free = jz4780_dma_desc_free;
956 }
957
958 ret = dmaenginem_async_device_register(dd);
959 if (ret) {
960 dev_err(dev, "failed to register device\n");
961 goto err_disable_clk;
962 }
963
964
965 ret = of_dma_controller_register(dev->of_node, jz4780_of_dma_xlate,
966 jzdma);
967 if (ret) {
968 dev_err(dev, "failed to register OF DMA controller\n");
969 goto err_disable_clk;
970 }
971
972 dev_info(dev, "JZ4780 DMA controller initialised\n");
973 return 0;
974
975 err_disable_clk:
976 clk_disable_unprepare(jzdma->clk);
977
978 err_free_irq:
979 free_irq(jzdma->irq, jzdma);
980 return ret;
981 }
982
983 static int jz4780_dma_remove(struct platform_device *pdev)
984 {
985 struct jz4780_dma_dev *jzdma = platform_get_drvdata(pdev);
986 int i;
987
988 of_dma_controller_free(pdev->dev.of_node);
989
990 free_irq(jzdma->irq, jzdma);
991
992 for (i = 0; i < jzdma->soc_data->nb_channels; i++)
993 tasklet_kill(&jzdma->chan[i].vchan.task);
994
995 return 0;
996 }
997
998 static const struct jz4780_dma_soc_data jz4740_dma_soc_data = {
999 .nb_channels = 6,
1000 .transfer_ord_max = 5,
1001 .flags = JZ_SOC_DATA_BREAK_LINKS,
1002 };
1003
1004 static const struct jz4780_dma_soc_data jz4725b_dma_soc_data = {
1005 .nb_channels = 6,
1006 .transfer_ord_max = 5,
1007 .flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC |
1008 JZ_SOC_DATA_BREAK_LINKS,
1009 };
1010
1011 static const struct jz4780_dma_soc_data jz4770_dma_soc_data = {
1012 .nb_channels = 6,
1013 .transfer_ord_max = 6,
1014 .flags = JZ_SOC_DATA_PER_CHAN_PM,
1015 };
1016
1017 static const struct jz4780_dma_soc_data jz4780_dma_soc_data = {
1018 .nb_channels = 32,
1019 .transfer_ord_max = 7,
1020 .flags = JZ_SOC_DATA_ALLOW_LEGACY_DT | JZ_SOC_DATA_PROGRAMMABLE_DMA,
1021 };
1022
1023 static const struct of_device_id jz4780_dma_dt_match[] = {
1024 { .compatible = "ingenic,jz4740-dma", .data = &jz4740_dma_soc_data },
1025 { .compatible = "ingenic,jz4725b-dma", .data = &jz4725b_dma_soc_data },
1026 { .compatible = "ingenic,jz4770-dma", .data = &jz4770_dma_soc_data },
1027 { .compatible = "ingenic,jz4780-dma", .data = &jz4780_dma_soc_data },
1028 {},
1029 };
1030 MODULE_DEVICE_TABLE(of, jz4780_dma_dt_match);
1031
1032 static struct platform_driver jz4780_dma_driver = {
1033 .probe = jz4780_dma_probe,
1034 .remove = jz4780_dma_remove,
1035 .driver = {
1036 .name = "jz4780-dma",
1037 .of_match_table = of_match_ptr(jz4780_dma_dt_match),
1038 },
1039 };
1040
1041 static int __init jz4780_dma_init(void)
1042 {
1043 return platform_driver_register(&jz4780_dma_driver);
1044 }
1045 subsys_initcall(jz4780_dma_init);
1046
1047 static void __exit jz4780_dma_exit(void)
1048 {
1049 platform_driver_unregister(&jz4780_dma_driver);
1050 }
1051 module_exit(jz4780_dma_exit);
1052
1053 MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
1054 MODULE_DESCRIPTION("Ingenic JZ4780 DMA controller driver");
1055 MODULE_LICENSE("GPL");