root/drivers/dma/ioat/registers.h

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INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
   4  */
   5 #ifndef _IOAT_REGISTERS_H_
   6 #define _IOAT_REGISTERS_H_
   7 
   8 #define IOAT_PCI_DMACTRL_OFFSET                 0x48
   9 #define IOAT_PCI_DMACTRL_DMA_EN                 0x00000001
  10 #define IOAT_PCI_DMACTRL_MSI_EN                 0x00000002
  11 
  12 #define IOAT_PCI_DEVICE_ID_OFFSET               0x02
  13 #define IOAT_PCI_DMAUNCERRSTS_OFFSET            0x148
  14 #define IOAT_PCI_CHANERR_INT_OFFSET             0x180
  15 #define IOAT_PCI_CHANERRMASK_INT_OFFSET         0x184
  16 
  17 /* PCIe config registers */
  18 
  19 /* EXPCAPID + N */
  20 #define IOAT_DEVCTRL_OFFSET                     0x8
  21 /* relaxed ordering enable */
  22 #define IOAT_DEVCTRL_ROE                        0x10
  23 
  24 /* MMIO Device Registers */
  25 #define IOAT_CHANCNT_OFFSET                     0x00    /*  8-bit */
  26 
  27 #define IOAT_XFERCAP_OFFSET                     0x01    /*  8-bit */
  28 #define IOAT_XFERCAP_4KB                        12
  29 #define IOAT_XFERCAP_8KB                        13
  30 #define IOAT_XFERCAP_16KB                       14
  31 #define IOAT_XFERCAP_32KB                       15
  32 #define IOAT_XFERCAP_32GB                       0
  33 
  34 #define IOAT_GENCTRL_OFFSET                     0x02    /*  8-bit */
  35 #define IOAT_GENCTRL_DEBUG_EN                   0x01
  36 
  37 #define IOAT_INTRCTRL_OFFSET                    0x03    /*  8-bit */
  38 #define IOAT_INTRCTRL_MASTER_INT_EN             0x01    /* Master Interrupt Enable */
  39 #define IOAT_INTRCTRL_INT_STATUS                0x02    /* ATTNSTATUS -or- Channel Int */
  40 #define IOAT_INTRCTRL_INT                       0x04    /* INT_STATUS -and- MASTER_INT_EN */
  41 #define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL       0x08    /* Enable all MSI-X vectors */
  42 
  43 #define IOAT_ATTNSTATUS_OFFSET                  0x04    /* Each bit is a channel */
  44 
  45 #define IOAT_VER_OFFSET                         0x08    /*  8-bit */
  46 #define IOAT_VER_MAJOR_MASK                     0xF0
  47 #define IOAT_VER_MINOR_MASK                     0x0F
  48 #define GET_IOAT_VER_MAJOR(x)                   (((x) & IOAT_VER_MAJOR_MASK) >> 4)
  49 #define GET_IOAT_VER_MINOR(x)                   ((x) & IOAT_VER_MINOR_MASK)
  50 
  51 #define IOAT_PERPORTOFFSET_OFFSET               0x0A    /* 16-bit */
  52 
  53 #define IOAT_INTRDELAY_OFFSET                   0x0C    /* 16-bit */
  54 #define IOAT_INTRDELAY_MASK                     0x3FFF  /* Interrupt Delay Time */
  55 #define IOAT_INTRDELAY_COALESE_SUPPORT          0x8000  /* Interrupt Coalescing Supported */
  56 
  57 #define IOAT_DEVICE_STATUS_OFFSET               0x0E    /* 16-bit */
  58 #define IOAT_DEVICE_STATUS_DEGRADED_MODE        0x0001
  59 #define IOAT_DEVICE_MMIO_RESTRICTED             0x0002
  60 #define IOAT_DEVICE_MEMORY_BYPASS               0x0004
  61 #define IOAT_DEVICE_ADDRESS_REMAPPING           0x0008
  62 
  63 #define IOAT_DMA_CAP_OFFSET                     0x10    /* 32-bit */
  64 #define IOAT_CAP_PAGE_BREAK                     0x00000001
  65 #define IOAT_CAP_CRC                            0x00000002
  66 #define IOAT_CAP_SKIP_MARKER                    0x00000004
  67 #define IOAT_CAP_DCA                            0x00000010
  68 #define IOAT_CAP_CRC_MOVE                       0x00000020
  69 #define IOAT_CAP_FILL_BLOCK                     0x00000040
  70 #define IOAT_CAP_APIC                           0x00000080
  71 #define IOAT_CAP_XOR                            0x00000100
  72 #define IOAT_CAP_PQ                             0x00000200
  73 #define IOAT_CAP_DWBES                          0x00002000
  74 #define IOAT_CAP_RAID16SS                       0x00020000
  75 #define IOAT_CAP_DPS                            0x00800000
  76 
  77 #define IOAT_PREFETCH_LIMIT_OFFSET              0x4C    /* CHWPREFLMT */
  78 
  79 #define IOAT_CHANNEL_MMIO_SIZE                  0x80    /* Each Channel MMIO space is this size */
  80 
  81 /* DMA Channel Registers */
  82 #define IOAT_CHANCTRL_OFFSET                    0x00    /* 16-bit Channel Control Register */
  83 #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK     0xF000
  84 #define IOAT3_CHANCTRL_COMPL_DCA_EN             0x0200
  85 #define IOAT_CHANCTRL_CHANNEL_IN_USE            0x0100
  86 #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL     0x0020
  87 #define IOAT_CHANCTRL_ERR_INT_EN                0x0010
  88 #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN          0x0008
  89 #define IOAT_CHANCTRL_ERR_COMPLETION_EN         0x0004
  90 #define IOAT_CHANCTRL_INT_REARM                 0x0001
  91 #define IOAT_CHANCTRL_RUN                       (IOAT_CHANCTRL_INT_REARM |\
  92                                                  IOAT_CHANCTRL_ERR_INT_EN |\
  93                                                  IOAT_CHANCTRL_ERR_COMPLETION_EN |\
  94                                                  IOAT_CHANCTRL_ANY_ERR_ABORT_EN)
  95 
  96 #define IOAT_DMA_COMP_OFFSET                    0x02    /* 16-bit DMA channel compatibility */
  97 #define IOAT_DMA_COMP_V1                        0x0001  /* Compatibility with DMA version 1 */
  98 #define IOAT_DMA_COMP_V2                        0x0002  /* Compatibility with DMA version 2 */
  99 
 100 #define IOAT_CHANSTS_OFFSET             0x08    /* 64-bit Channel Status Register */
 101 #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR  (~0x3fULL)
 102 #define IOAT_CHANSTS_SOFT_ERR                   0x10ULL
 103 #define IOAT_CHANSTS_UNAFFILIATED_ERR           0x8ULL
 104 #define IOAT_CHANSTS_STATUS     0x7ULL
 105 #define IOAT_CHANSTS_ACTIVE     0x0
 106 #define IOAT_CHANSTS_DONE       0x1
 107 #define IOAT_CHANSTS_SUSPENDED  0x2
 108 #define IOAT_CHANSTS_HALTED     0x3
 109 
 110 
 111 
 112 #define IOAT_CHAN_DMACOUNT_OFFSET       0x06    /* 16-bit DMA Count register */
 113 
 114 #define IOAT_DCACTRL_OFFSET         0x30   /* 32 bit Direct Cache Access Control Register */
 115 #define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000
 116 #define IOAT_DCACTRL_TARGET_CPU_MASK   0xFFFF /* APIC ID */
 117 
 118 /* CB DCA Memory Space Registers */
 119 #define IOAT_DCAOFFSET_OFFSET       0x14
 120 /* CB_BAR + IOAT_DCAOFFSET value */
 121 #define IOAT_DCA_VER_OFFSET         0x00
 122 #define IOAT_DCA_VER_MAJOR_MASK     0xF0
 123 #define IOAT_DCA_VER_MINOR_MASK     0x0F
 124 
 125 #define IOAT_DCA_COMP_OFFSET        0x02
 126 #define IOAT_DCA_COMP_V1            0x1
 127 
 128 #define IOAT_FSB_CAPABILITY_OFFSET  0x04
 129 #define IOAT_FSB_CAPABILITY_PREFETCH    0x1
 130 
 131 #define IOAT_PCI_CAPABILITY_OFFSET  0x06
 132 #define IOAT_PCI_CAPABILITY_MEMWR   0x1
 133 
 134 #define IOAT_FSB_CAP_ENABLE_OFFSET  0x08
 135 #define IOAT_FSB_CAP_ENABLE_PREFETCH    0x1
 136 
 137 #define IOAT_PCI_CAP_ENABLE_OFFSET  0x0A
 138 #define IOAT_PCI_CAP_ENABLE_MEMWR   0x1
 139 
 140 #define IOAT_APICID_TAG_MAP_OFFSET  0x0C
 141 #define IOAT_APICID_TAG_MAP_TAG0    0x0000000F
 142 #define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0
 143 #define IOAT_APICID_TAG_MAP_TAG1    0x000000F0
 144 #define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4
 145 #define IOAT_APICID_TAG_MAP_TAG2    0x00000F00
 146 #define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8
 147 #define IOAT_APICID_TAG_MAP_TAG3    0x0000F000
 148 #define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12
 149 #define IOAT_APICID_TAG_MAP_TAG4    0x000F0000
 150 #define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16
 151 #define IOAT_APICID_TAG_CB2_VALID   0x8080808080
 152 
 153 #define IOAT_DCA_GREQID_OFFSET      0x10
 154 #define IOAT_DCA_GREQID_SIZE        0x04
 155 #define IOAT_DCA_GREQID_MASK        0xFFFF
 156 #define IOAT_DCA_GREQID_IGNOREFUN   0x10000000
 157 #define IOAT_DCA_GREQID_VALID       0x20000000
 158 #define IOAT_DCA_GREQID_LASTID      0x80000000
 159 
 160 #define IOAT3_CSI_CAPABILITY_OFFSET 0x08
 161 #define IOAT3_CSI_CAPABILITY_PREFETCH    0x1
 162 
 163 #define IOAT3_PCI_CAPABILITY_OFFSET 0x0A
 164 #define IOAT3_PCI_CAPABILITY_MEMWR  0x1
 165 
 166 #define IOAT3_CSI_CONTROL_OFFSET    0x0C
 167 #define IOAT3_CSI_CONTROL_PREFETCH  0x1
 168 
 169 #define IOAT3_PCI_CONTROL_OFFSET    0x0E
 170 #define IOAT3_PCI_CONTROL_MEMWR     0x1
 171 
 172 #define IOAT3_APICID_TAG_MAP_OFFSET 0x10
 173 #define IOAT3_APICID_TAG_MAP_OFFSET_LOW  0x10
 174 #define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14
 175 
 176 #define IOAT3_DCA_GREQID_OFFSET     0x02
 177 
 178 #define IOAT1_CHAINADDR_OFFSET          0x0C    /* 64-bit Descriptor Chain Address Register */
 179 #define IOAT2_CHAINADDR_OFFSET          0x10    /* 64-bit Descriptor Chain Address Register */
 180 #define IOAT_CHAINADDR_OFFSET(ver)              ((ver) < IOAT_VER_2_0 \
 181                                                 ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET)
 182 #define IOAT1_CHAINADDR_OFFSET_LOW      0x0C
 183 #define IOAT2_CHAINADDR_OFFSET_LOW      0x10
 184 #define IOAT_CHAINADDR_OFFSET_LOW(ver)          ((ver) < IOAT_VER_2_0 \
 185                                                 ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW)
 186 #define IOAT1_CHAINADDR_OFFSET_HIGH     0x10
 187 #define IOAT2_CHAINADDR_OFFSET_HIGH     0x14
 188 #define IOAT_CHAINADDR_OFFSET_HIGH(ver)         ((ver) < IOAT_VER_2_0 \
 189                                                 ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH)
 190 
 191 #define IOAT1_CHANCMD_OFFSET            0x14    /*  8-bit DMA Channel Command Register */
 192 #define IOAT2_CHANCMD_OFFSET            0x04    /*  8-bit DMA Channel Command Register */
 193 #define IOAT_CHANCMD_OFFSET(ver)                ((ver) < IOAT_VER_2_0 \
 194                                                 ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET)
 195 #define IOAT_CHANCMD_RESET                      0x20
 196 #define IOAT_CHANCMD_RESUME                     0x10
 197 #define IOAT_CHANCMD_ABORT                      0x08
 198 #define IOAT_CHANCMD_SUSPEND                    0x04
 199 #define IOAT_CHANCMD_APPEND                     0x02
 200 #define IOAT_CHANCMD_START                      0x01
 201 
 202 #define IOAT_CHANCMP_OFFSET                     0x18    /* 64-bit Channel Completion Address Register */
 203 #define IOAT_CHANCMP_OFFSET_LOW                 0x18
 204 #define IOAT_CHANCMP_OFFSET_HIGH                0x1C
 205 
 206 #define IOAT_CDAR_OFFSET                        0x20    /* 64-bit Current Descriptor Address Register */
 207 #define IOAT_CDAR_OFFSET_LOW                    0x20
 208 #define IOAT_CDAR_OFFSET_HIGH                   0x24
 209 
 210 #define IOAT_CHANERR_OFFSET                     0x28    /* 32-bit Channel Error Register */
 211 #define IOAT_CHANERR_SRC_ADDR_ERR       0x0001
 212 #define IOAT_CHANERR_DEST_ADDR_ERR      0x0002
 213 #define IOAT_CHANERR_NEXT_ADDR_ERR      0x0004
 214 #define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR        0x0008
 215 #define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR       0x0010
 216 #define IOAT_CHANERR_CHANCMD_ERR                0x0020
 217 #define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR   0x0040
 218 #define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR       0x0080
 219 #define IOAT_CHANERR_READ_DATA_ERR              0x0100
 220 #define IOAT_CHANERR_WRITE_DATA_ERR             0x0200
 221 #define IOAT_CHANERR_CONTROL_ERR        0x0400
 222 #define IOAT_CHANERR_LENGTH_ERR 0x0800
 223 #define IOAT_CHANERR_COMPLETION_ADDR_ERR        0x1000
 224 #define IOAT_CHANERR_INT_CONFIGURATION_ERR      0x2000
 225 #define IOAT_CHANERR_SOFT_ERR                   0x4000
 226 #define IOAT_CHANERR_UNAFFILIATED_ERR           0x8000
 227 #define IOAT_CHANERR_XOR_P_OR_CRC_ERR           0x10000
 228 #define IOAT_CHANERR_XOR_Q_ERR                  0x20000
 229 #define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR       0x40000
 230 
 231 #define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR)
 232 #define IOAT_CHANERR_RECOVER_MASK (IOAT_CHANERR_READ_DATA_ERR | \
 233                                    IOAT_CHANERR_WRITE_DATA_ERR)
 234 
 235 #define IOAT_CHANERR_MASK_OFFSET                0x2C    /* 32-bit Channel Error Register */
 236 
 237 #define IOAT_CHAN_DRSCTL_OFFSET                 0xB6
 238 #define IOAT_CHAN_DRSZ_4KB                      0x0000
 239 #define IOAT_CHAN_DRSZ_8KB                      0x0001
 240 #define IOAT_CHAN_DRSZ_2MB                      0x0009
 241 #define IOAT_CHAN_DRS_EN                        0x0100
 242 #define IOAT_CHAN_DRS_AUTOWRAP                  0x0200
 243 
 244 #define IOAT_CHAN_LTR_SWSEL_OFFSET              0xBC
 245 #define IOAT_CHAN_LTR_SWSEL_ACTIVE              0x0
 246 #define IOAT_CHAN_LTR_SWSEL_IDLE                0x1
 247 
 248 #define IOAT_CHAN_LTR_ACTIVE_OFFSET             0xC0
 249 #define IOAT_CHAN_LTR_ACTIVE_SNVAL              0x0000  /* 0 us */
 250 #define IOAT_CHAN_LTR_ACTIVE_SNLATSCALE         0x0800  /* 1us scale */
 251 #define IOAT_CHAN_LTR_ACTIVE_SNREQMNT           0x8000  /* snoop req enable */
 252 
 253 #define IOAT_CHAN_LTR_IDLE_OFFSET               0xC4
 254 #define IOAT_CHAN_LTR_IDLE_SNVAL                0x0258  /* 600 us */
 255 #define IOAT_CHAN_LTR_IDLE_SNLATSCALE           0x0800  /* 1us scale */
 256 #define IOAT_CHAN_LTR_IDLE_SNREQMNT             0x8000  /* snoop req enable */
 257 
 258 #endif /* _IOAT_REGISTERS_H_ */
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