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2
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4
5 #ifndef _IOAT_HW_H_
6 #define _IOAT_HW_H_
7
8
9 #define IOAT_MMIO_BAR 0
10
11
12 #define PCI_DEVICE_ID_INTEL_IOAT_IVB0 0x0e20
13 #define PCI_DEVICE_ID_INTEL_IOAT_IVB1 0x0e21
14 #define PCI_DEVICE_ID_INTEL_IOAT_IVB2 0x0e22
15 #define PCI_DEVICE_ID_INTEL_IOAT_IVB3 0x0e23
16 #define PCI_DEVICE_ID_INTEL_IOAT_IVB4 0x0e24
17 #define PCI_DEVICE_ID_INTEL_IOAT_IVB5 0x0e25
18 #define PCI_DEVICE_ID_INTEL_IOAT_IVB6 0x0e26
19 #define PCI_DEVICE_ID_INTEL_IOAT_IVB7 0x0e27
20 #define PCI_DEVICE_ID_INTEL_IOAT_IVB8 0x0e2e
21 #define PCI_DEVICE_ID_INTEL_IOAT_IVB9 0x0e2f
22
23 #define PCI_DEVICE_ID_INTEL_IOAT_HSW0 0x2f20
24 #define PCI_DEVICE_ID_INTEL_IOAT_HSW1 0x2f21
25 #define PCI_DEVICE_ID_INTEL_IOAT_HSW2 0x2f22
26 #define PCI_DEVICE_ID_INTEL_IOAT_HSW3 0x2f23
27 #define PCI_DEVICE_ID_INTEL_IOAT_HSW4 0x2f24
28 #define PCI_DEVICE_ID_INTEL_IOAT_HSW5 0x2f25
29 #define PCI_DEVICE_ID_INTEL_IOAT_HSW6 0x2f26
30 #define PCI_DEVICE_ID_INTEL_IOAT_HSW7 0x2f27
31 #define PCI_DEVICE_ID_INTEL_IOAT_HSW8 0x2f2e
32 #define PCI_DEVICE_ID_INTEL_IOAT_HSW9 0x2f2f
33
34 #define PCI_DEVICE_ID_INTEL_IOAT_BWD0 0x0C50
35 #define PCI_DEVICE_ID_INTEL_IOAT_BWD1 0x0C51
36 #define PCI_DEVICE_ID_INTEL_IOAT_BWD2 0x0C52
37 #define PCI_DEVICE_ID_INTEL_IOAT_BWD3 0x0C53
38
39 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0 0x6f50
40 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1 0x6f51
41 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2 0x6f52
42 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3 0x6f53
43
44 #define PCI_DEVICE_ID_INTEL_IOAT_BDX0 0x6f20
45 #define PCI_DEVICE_ID_INTEL_IOAT_BDX1 0x6f21
46 #define PCI_DEVICE_ID_INTEL_IOAT_BDX2 0x6f22
47 #define PCI_DEVICE_ID_INTEL_IOAT_BDX3 0x6f23
48 #define PCI_DEVICE_ID_INTEL_IOAT_BDX4 0x6f24
49 #define PCI_DEVICE_ID_INTEL_IOAT_BDX5 0x6f25
50 #define PCI_DEVICE_ID_INTEL_IOAT_BDX6 0x6f26
51 #define PCI_DEVICE_ID_INTEL_IOAT_BDX7 0x6f27
52 #define PCI_DEVICE_ID_INTEL_IOAT_BDX8 0x6f2e
53 #define PCI_DEVICE_ID_INTEL_IOAT_BDX9 0x6f2f
54
55 #define PCI_DEVICE_ID_INTEL_IOAT_SKX 0x2021
56
57 #define PCI_DEVICE_ID_INTEL_IOAT_ICX 0x0b00
58
59 #define IOAT_VER_1_2 0x12
60 #define IOAT_VER_2_0 0x20
61 #define IOAT_VER_3_0 0x30
62 #define IOAT_VER_3_2 0x32
63 #define IOAT_VER_3_3 0x33
64 #define IOAT_VER_3_4 0x34
65
66
67 int system_has_dca_enabled(struct pci_dev *pdev);
68
69 #define IOAT_DESC_SZ 64
70
71 struct ioat_dma_descriptor {
72 uint32_t size;
73 union {
74 uint32_t ctl;
75 struct {
76 unsigned int int_en:1;
77 unsigned int src_snoop_dis:1;
78 unsigned int dest_snoop_dis:1;
79 unsigned int compl_write:1;
80 unsigned int fence:1;
81 unsigned int null:1;
82 unsigned int src_brk:1;
83 unsigned int dest_brk:1;
84 unsigned int bundle:1;
85 unsigned int dest_dca:1;
86 unsigned int hint:1;
87 unsigned int rsvd2:13;
88 #define IOAT_OP_COPY 0x00
89 unsigned int op:8;
90 } ctl_f;
91 };
92 uint64_t src_addr;
93 uint64_t dst_addr;
94 uint64_t next;
95 uint64_t rsv1;
96 uint64_t rsv2;
97
98 union {
99 uint64_t user1;
100 uint64_t tx_cnt;
101 };
102 uint64_t user2;
103 };
104
105 struct ioat_xor_descriptor {
106 uint32_t size;
107 union {
108 uint32_t ctl;
109 struct {
110 unsigned int int_en:1;
111 unsigned int src_snoop_dis:1;
112 unsigned int dest_snoop_dis:1;
113 unsigned int compl_write:1;
114 unsigned int fence:1;
115 unsigned int src_cnt:3;
116 unsigned int bundle:1;
117 unsigned int dest_dca:1;
118 unsigned int hint:1;
119 unsigned int rsvd:13;
120 #define IOAT_OP_XOR 0x87
121 #define IOAT_OP_XOR_VAL 0x88
122 unsigned int op:8;
123 } ctl_f;
124 };
125 uint64_t src_addr;
126 uint64_t dst_addr;
127 uint64_t next;
128 uint64_t src_addr2;
129 uint64_t src_addr3;
130 uint64_t src_addr4;
131 uint64_t src_addr5;
132 };
133
134 struct ioat_xor_ext_descriptor {
135 uint64_t src_addr6;
136 uint64_t src_addr7;
137 uint64_t src_addr8;
138 uint64_t next;
139 uint64_t rsvd[4];
140 };
141
142 struct ioat_pq_descriptor {
143 union {
144 uint32_t size;
145 uint32_t dwbes;
146 struct {
147 unsigned int rsvd:25;
148 unsigned int p_val_err:1;
149 unsigned int q_val_err:1;
150 unsigned int rsvd1:4;
151 unsigned int wbes:1;
152 } dwbes_f;
153 };
154 union {
155 uint32_t ctl;
156 struct {
157 unsigned int int_en:1;
158 unsigned int src_snoop_dis:1;
159 unsigned int dest_snoop_dis:1;
160 unsigned int compl_write:1;
161 unsigned int fence:1;
162 unsigned int src_cnt:3;
163 unsigned int bundle:1;
164 unsigned int dest_dca:1;
165 unsigned int hint:1;
166 unsigned int p_disable:1;
167 unsigned int q_disable:1;
168 unsigned int rsvd2:2;
169 unsigned int wb_en:1;
170 unsigned int prl_en:1;
171 unsigned int rsvd3:7;
172 #define IOAT_OP_PQ 0x89
173 #define IOAT_OP_PQ_VAL 0x8a
174 #define IOAT_OP_PQ_16S 0xa0
175 #define IOAT_OP_PQ_VAL_16S 0xa1
176 unsigned int op:8;
177 } ctl_f;
178 };
179 uint64_t src_addr;
180 uint64_t p_addr;
181 uint64_t next;
182 uint64_t src_addr2;
183 union {
184 uint64_t src_addr3;
185 uint64_t sed_addr;
186 };
187 uint8_t coef[8];
188 uint64_t q_addr;
189 };
190
191 struct ioat_pq_ext_descriptor {
192 uint64_t src_addr4;
193 uint64_t src_addr5;
194 uint64_t src_addr6;
195 uint64_t next;
196 uint64_t src_addr7;
197 uint64_t src_addr8;
198 uint64_t rsvd[2];
199 };
200
201 struct ioat_pq_update_descriptor {
202 uint32_t size;
203 union {
204 uint32_t ctl;
205 struct {
206 unsigned int int_en:1;
207 unsigned int src_snoop_dis:1;
208 unsigned int dest_snoop_dis:1;
209 unsigned int compl_write:1;
210 unsigned int fence:1;
211 unsigned int src_cnt:3;
212 unsigned int bundle:1;
213 unsigned int dest_dca:1;
214 unsigned int hint:1;
215 unsigned int p_disable:1;
216 unsigned int q_disable:1;
217 unsigned int rsvd:3;
218 unsigned int coef:8;
219 #define IOAT_OP_PQ_UP 0x8b
220 unsigned int op:8;
221 } ctl_f;
222 };
223 uint64_t src_addr;
224 uint64_t p_addr;
225 uint64_t next;
226 uint64_t src_addr2;
227 uint64_t p_src;
228 uint64_t q_src;
229 uint64_t q_addr;
230 };
231
232 struct ioat_raw_descriptor {
233 uint64_t field[8];
234 };
235
236 struct ioat_pq16a_descriptor {
237 uint8_t coef[8];
238 uint64_t src_addr3;
239 uint64_t src_addr4;
240 uint64_t src_addr5;
241 uint64_t src_addr6;
242 uint64_t src_addr7;
243 uint64_t src_addr8;
244 uint64_t src_addr9;
245 };
246
247 struct ioat_pq16b_descriptor {
248 uint64_t src_addr10;
249 uint64_t src_addr11;
250 uint64_t src_addr12;
251 uint64_t src_addr13;
252 uint64_t src_addr14;
253 uint64_t src_addr15;
254 uint64_t src_addr16;
255 uint64_t rsvd;
256 };
257
258 union ioat_sed_pq_descriptor {
259 struct ioat_pq16a_descriptor a;
260 struct ioat_pq16b_descriptor b;
261 };
262
263 #define SED_SIZE 64
264
265 struct ioat_sed_raw_descriptor {
266 uint64_t a[8];
267 uint64_t b[8];
268 uint64_t c[8];
269 };
270
271 #endif