root/drivers/hid/intel-ish-hid/ipc/hw-ish.h

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INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * H/W layer of ISHTP provider device (ISH)
   4  *
   5  * Copyright (c) 2014-2016, Intel Corporation.
   6  */
   7 
   8 #ifndef _ISHTP_HW_ISH_H_
   9 #define _ISHTP_HW_ISH_H_
  10 
  11 #include <linux/pci.h>
  12 #include <linux/interrupt.h>
  13 #include "hw-ish-regs.h"
  14 #include "ishtp-dev.h"
  15 
  16 #define CHV_DEVICE_ID           0x22D8
  17 #define BXT_Ax_DEVICE_ID        0x0AA2
  18 #define BXT_Bx_DEVICE_ID        0x1AA2
  19 #define APL_Ax_DEVICE_ID        0x5AA2
  20 #define SPT_Ax_DEVICE_ID        0x9D35
  21 #define CNL_Ax_DEVICE_ID        0x9DFC
  22 #define GLK_Ax_DEVICE_ID        0x31A2
  23 #define CNL_H_DEVICE_ID         0xA37C
  24 #define ICL_MOBILE_DEVICE_ID    0x34FC
  25 #define SPT_H_DEVICE_ID         0xA135
  26 #define CML_LP_DEVICE_ID        0x02FC
  27 #define CMP_H_DEVICE_ID         0x06FC
  28 #define EHL_Ax_DEVICE_ID        0x4BB3
  29 #define TGL_LP_DEVICE_ID        0xA0FC
  30 
  31 #define REVISION_ID_CHT_A0      0x6
  32 #define REVISION_ID_CHT_Ax_SI   0x0
  33 #define REVISION_ID_CHT_Bx_SI   0x10
  34 #define REVISION_ID_CHT_Kx_SI   0x20
  35 #define REVISION_ID_CHT_Dx_SI   0x30
  36 #define REVISION_ID_CHT_B0      0xB0
  37 #define REVISION_ID_SI_MASK     0x70
  38 
  39 struct ipc_rst_payload_type {
  40         uint16_t        reset_id;
  41         uint16_t        reserved;
  42 };
  43 
  44 struct time_sync_format {
  45         uint8_t ts1_source;
  46         uint8_t ts2_source;
  47         uint16_t reserved;
  48 } __packed;
  49 
  50 struct ipc_time_update_msg {
  51         uint64_t primary_host_time;
  52         struct time_sync_format sync_info;
  53         uint64_t secondary_host_time;
  54 } __packed;
  55 
  56 enum {
  57         HOST_UTC_TIME_USEC = 0,
  58         HOST_SYSTEM_TIME_USEC = 1
  59 };
  60 
  61 struct ish_hw {
  62         void __iomem *mem_addr;
  63 };
  64 
  65 /*
  66  * ISH FW status type
  67  */
  68 enum {
  69         FWSTS_AFTER_RESET               = 0,
  70         FWSTS_WAIT_FOR_HOST             = 4,
  71         FWSTS_START_KERNEL_DMA          = 5,
  72         FWSTS_FW_IS_RUNNING             = 7,
  73         FWSTS_SENSOR_APP_LOADED         = 8,
  74         FWSTS_SENSOR_APP_RUNNING        = 15
  75 };
  76 
  77 #define to_ish_hw(dev) (struct ish_hw *)((dev)->hw)
  78 
  79 irqreturn_t ish_irq_handler(int irq, void *dev_id);
  80 struct ishtp_device *ish_dev_init(struct pci_dev *pdev);
  81 int ish_hw_start(struct ishtp_device *dev);
  82 void ish_device_disable(struct ishtp_device *dev);
  83 int ish_disable_dma(struct ishtp_device *dev);
  84 
  85 #endif /* _ISHTP_HW_ISH_H_ */
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