drivers/spi/spi-armada-3700.c

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This source file includes following definitions.
spireg_read
spireg_write
a3700_spi_auto_cs_unset
a3700_spi_activate_cs
a3700_spi_deactivate_cs
a3700_spi_pin_mode_set
a3700_spi_fifo_mode_set
a3700_spi_mode_set
a3700_spi_clock_set
a3700_spi_bytelen_set
a3700_spi_fifo_flush
a3700_spi_init
a3700_spi_interrupt
a3700_spi_wait_completion
a3700_spi_transfer_wait
a3700_spi_fifo_thres_set
a3700_spi_transfer_setup
a3700_spi_set_cs
a3700_spi_header_set
a3700_is_wfifo_full
a3700_spi_fifo_write
a3700_is_rfifo_empty
a3700_spi_fifo_read
a3700_spi_transfer_abort_fifo
a3700_spi_prepare_message
a3700_spi_transfer_one_fifo
a3700_spi_transfer_one_full_duplex
a3700_spi_transfer_one
a3700_spi_unprepare_message
a3700_spi_probe
a3700_spi_remove
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Marvell Armada-3700 SPI controller driver
   4  *
   5  * Copyright (C) 2016 Marvell Ltd.
   6  *
   7  * Author: Wilson Ding <dingwei@marvell.com>
   8  * Author: Romain Perier <romain.perier@free-electrons.com>
   9  */
  10 
  11 #include <linux/clk.h>
  12 #include <linux/completion.h>
  13 #include <linux/delay.h>
  14 #include <linux/err.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_device.h>
  22 #include <linux/pinctrl/consumer.h>
  23 #include <linux/spi/spi.h>
  24 
  25 #define DRIVER_NAME                     "armada_3700_spi"
  26 
  27 #define A3700_SPI_MAX_SPEED_HZ          100000000
  28 #define A3700_SPI_MAX_PRESCALE          30
  29 #define A3700_SPI_TIMEOUT               10
  30 
  31 /* SPI Register Offest */
  32 #define A3700_SPI_IF_CTRL_REG           0x00
  33 #define A3700_SPI_IF_CFG_REG            0x04
  34 #define A3700_SPI_DATA_OUT_REG          0x08
  35 #define A3700_SPI_DATA_IN_REG           0x0C
  36 #define A3700_SPI_IF_INST_REG           0x10
  37 #define A3700_SPI_IF_ADDR_REG           0x14
  38 #define A3700_SPI_IF_RMODE_REG          0x18
  39 #define A3700_SPI_IF_HDR_CNT_REG        0x1C
  40 #define A3700_SPI_IF_DIN_CNT_REG        0x20
  41 #define A3700_SPI_IF_TIME_REG           0x24
  42 #define A3700_SPI_INT_STAT_REG          0x28
  43 #define A3700_SPI_INT_MASK_REG          0x2C
  44 
  45 /* A3700_SPI_IF_CTRL_REG */
  46 #define A3700_SPI_EN                    BIT(16)
  47 #define A3700_SPI_ADDR_NOT_CONFIG       BIT(12)
  48 #define A3700_SPI_WFIFO_OVERFLOW        BIT(11)
  49 #define A3700_SPI_WFIFO_UNDERFLOW       BIT(10)
  50 #define A3700_SPI_RFIFO_OVERFLOW        BIT(9)
  51 #define A3700_SPI_RFIFO_UNDERFLOW       BIT(8)
  52 #define A3700_SPI_WFIFO_FULL            BIT(7)
  53 #define A3700_SPI_WFIFO_EMPTY           BIT(6)
  54 #define A3700_SPI_RFIFO_FULL            BIT(5)
  55 #define A3700_SPI_RFIFO_EMPTY           BIT(4)
  56 #define A3700_SPI_WFIFO_RDY             BIT(3)
  57 #define A3700_SPI_RFIFO_RDY             BIT(2)
  58 #define A3700_SPI_XFER_RDY              BIT(1)
  59 #define A3700_SPI_XFER_DONE             BIT(0)
  60 
  61 /* A3700_SPI_IF_CFG_REG */
  62 #define A3700_SPI_WFIFO_THRS            BIT(28)
  63 #define A3700_SPI_RFIFO_THRS            BIT(24)
  64 #define A3700_SPI_AUTO_CS               BIT(20)
  65 #define A3700_SPI_DMA_RD_EN             BIT(18)
  66 #define A3700_SPI_FIFO_MODE             BIT(17)
  67 #define A3700_SPI_SRST                  BIT(16)
  68 #define A3700_SPI_XFER_START            BIT(15)
  69 #define A3700_SPI_XFER_STOP             BIT(14)
  70 #define A3700_SPI_INST_PIN              BIT(13)
  71 #define A3700_SPI_ADDR_PIN              BIT(12)
  72 #define A3700_SPI_DATA_PIN1             BIT(11)
  73 #define A3700_SPI_DATA_PIN0             BIT(10)
  74 #define A3700_SPI_FIFO_FLUSH            BIT(9)
  75 #define A3700_SPI_RW_EN                 BIT(8)
  76 #define A3700_SPI_CLK_POL               BIT(7)
  77 #define A3700_SPI_CLK_PHA               BIT(6)
  78 #define A3700_SPI_BYTE_LEN              BIT(5)
  79 #define A3700_SPI_CLK_PRESCALE          BIT(0)
  80 #define A3700_SPI_CLK_PRESCALE_MASK     (0x1f)
  81 #define A3700_SPI_CLK_EVEN_OFFS         (0x10)
  82 
  83 #define A3700_SPI_WFIFO_THRS_BIT        28
  84 #define A3700_SPI_RFIFO_THRS_BIT        24
  85 #define A3700_SPI_FIFO_THRS_MASK        0x7
  86 
  87 #define A3700_SPI_DATA_PIN_MASK         0x3
  88 
  89 /* A3700_SPI_IF_HDR_CNT_REG */
  90 #define A3700_SPI_DUMMY_CNT_BIT         12
  91 #define A3700_SPI_DUMMY_CNT_MASK        0x7
  92 #define A3700_SPI_RMODE_CNT_BIT         8
  93 #define A3700_SPI_RMODE_CNT_MASK        0x3
  94 #define A3700_SPI_ADDR_CNT_BIT          4
  95 #define A3700_SPI_ADDR_CNT_MASK         0x7
  96 #define A3700_SPI_INSTR_CNT_BIT         0
  97 #define A3700_SPI_INSTR_CNT_MASK        0x3
  98 
  99 /* A3700_SPI_IF_TIME_REG */
 100 #define A3700_SPI_CLK_CAPT_EDGE         BIT(7)
 101 
 102 struct a3700_spi {
 103         struct spi_master *master;
 104         void __iomem *base;
 105         struct clk *clk;
 106         unsigned int irq;
 107         unsigned int flags;
 108         bool xmit_data;
 109         const u8 *tx_buf;
 110         u8 *rx_buf;
 111         size_t buf_len;
 112         u8 byte_len;
 113         u32 wait_mask;
 114         struct completion done;
 115 };
 116 
 117 static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset)
 118 {
 119         return readl(a3700_spi->base + offset);
 120 }
 121 
 122 static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data)
 123 {
 124         writel(data, a3700_spi->base + offset);
 125 }
 126 
 127 static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi)
 128 {
 129         u32 val;
 130 
 131         val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 132         val &= ~A3700_SPI_AUTO_CS;
 133         spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 134 }
 135 
 136 static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs)
 137 {
 138         u32 val;
 139 
 140         val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
 141         val |= (A3700_SPI_EN << cs);
 142         spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
 143 }
 144 
 145 static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi,
 146                                     unsigned int cs)
 147 {
 148         u32 val;
 149 
 150         val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
 151         val &= ~(A3700_SPI_EN << cs);
 152         spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
 153 }
 154 
 155 static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi,
 156                                   unsigned int pin_mode, bool receiving)
 157 {
 158         u32 val;
 159 
 160         val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 161         val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN);
 162         val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1);
 163 
 164         switch (pin_mode) {
 165         case SPI_NBITS_SINGLE:
 166                 break;
 167         case SPI_NBITS_DUAL:
 168                 val |= A3700_SPI_DATA_PIN0;
 169                 break;
 170         case SPI_NBITS_QUAD:
 171                 val |= A3700_SPI_DATA_PIN1;
 172                 /* RX during address reception uses 4-pin */
 173                 if (receiving)
 174                         val |= A3700_SPI_ADDR_PIN;
 175                 break;
 176         default:
 177                 dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode);
 178                 return -EINVAL;
 179         }
 180 
 181         spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 182 
 183         return 0;
 184 }
 185 
 186 static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi, bool enable)
 187 {
 188         u32 val;
 189 
 190         val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 191         if (enable)
 192                 val |= A3700_SPI_FIFO_MODE;
 193         else
 194                 val &= ~A3700_SPI_FIFO_MODE;
 195         spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 196 }
 197 
 198 static void a3700_spi_mode_set(struct a3700_spi *a3700_spi,
 199                                unsigned int mode_bits)
 200 {
 201         u32 val;
 202 
 203         val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 204 
 205         if (mode_bits & SPI_CPOL)
 206                 val |= A3700_SPI_CLK_POL;
 207         else
 208                 val &= ~A3700_SPI_CLK_POL;
 209 
 210         if (mode_bits & SPI_CPHA)
 211                 val |= A3700_SPI_CLK_PHA;
 212         else
 213                 val &= ~A3700_SPI_CLK_PHA;
 214 
 215         spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 216 }
 217 
 218 static void a3700_spi_clock_set(struct a3700_spi *a3700_spi,
 219                                 unsigned int speed_hz)
 220 {
 221         u32 val;
 222         u32 prescale;
 223 
 224         prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz);
 225 
 226         /* For prescaler values over 15, we can only set it by steps of 2.
 227          * Starting from A3700_SPI_CLK_EVEN_OFFS, we set values from 0 up to
 228          * 30. We only use this range from 16 to 30.
 229          */
 230         if (prescale > 15)
 231                 prescale = A3700_SPI_CLK_EVEN_OFFS + DIV_ROUND_UP(prescale, 2);
 232 
 233         val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 234         val = val & ~A3700_SPI_CLK_PRESCALE_MASK;
 235 
 236         val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK);
 237         spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 238 
 239         if (prescale <= 2) {
 240                 val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG);
 241                 val |= A3700_SPI_CLK_CAPT_EDGE;
 242                 spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val);
 243         }
 244 }
 245 
 246 static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len)
 247 {
 248         u32 val;
 249 
 250         val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 251         if (len == 4)
 252                 val |= A3700_SPI_BYTE_LEN;
 253         else
 254                 val &= ~A3700_SPI_BYTE_LEN;
 255         spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 256 
 257         a3700_spi->byte_len = len;
 258 }
 259 
 260 static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi)
 261 {
 262         int timeout = A3700_SPI_TIMEOUT;
 263         u32 val;
 264 
 265         val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 266         val |= A3700_SPI_FIFO_FLUSH;
 267         spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 268 
 269         while (--timeout) {
 270                 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 271                 if (!(val & A3700_SPI_FIFO_FLUSH))
 272                         return 0;
 273                 udelay(1);
 274         }
 275 
 276         return -ETIMEDOUT;
 277 }
 278 
 279 static int a3700_spi_init(struct a3700_spi *a3700_spi)
 280 {
 281         struct spi_master *master = a3700_spi->master;
 282         u32 val;
 283         int i, ret = 0;
 284 
 285         /* Reset SPI unit */
 286         val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 287         val |= A3700_SPI_SRST;
 288         spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 289 
 290         udelay(A3700_SPI_TIMEOUT);
 291 
 292         val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 293         val &= ~A3700_SPI_SRST;
 294         spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 295 
 296         /* Disable AUTO_CS and deactivate all chip-selects */
 297         a3700_spi_auto_cs_unset(a3700_spi);
 298         for (i = 0; i < master->num_chipselect; i++)
 299                 a3700_spi_deactivate_cs(a3700_spi, i);
 300 
 301         /* Enable FIFO mode */
 302         a3700_spi_fifo_mode_set(a3700_spi, true);
 303 
 304         /* Set SPI mode */
 305         a3700_spi_mode_set(a3700_spi, master->mode_bits);
 306 
 307         /* Reset counters */
 308         spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
 309         spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0);
 310 
 311         /* Mask the interrupts and clear cause bits */
 312         spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
 313         spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U);
 314 
 315         return ret;
 316 }
 317 
 318 static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id)
 319 {
 320         struct spi_master *master = dev_id;
 321         struct a3700_spi *a3700_spi;
 322         u32 cause;
 323 
 324         a3700_spi = spi_master_get_devdata(master);
 325 
 326         /* Get interrupt causes */
 327         cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG);
 328 
 329         if (!cause || !(a3700_spi->wait_mask & cause))
 330                 return IRQ_NONE;
 331 
 332         /* mask and acknowledge the SPI interrupts */
 333         spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
 334         spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause);
 335 
 336         /* Wake up the transfer */
 337         complete(&a3700_spi->done);
 338 
 339         return IRQ_HANDLED;
 340 }
 341 
 342 static bool a3700_spi_wait_completion(struct spi_device *spi)
 343 {
 344         struct a3700_spi *a3700_spi;
 345         unsigned int timeout;
 346         unsigned int ctrl_reg;
 347         unsigned long timeout_jiffies;
 348 
 349         a3700_spi = spi_master_get_devdata(spi->master);
 350 
 351         /* SPI interrupt is edge-triggered, which means an interrupt will
 352          * be generated only when detecting a specific status bit changed
 353          * from '0' to '1'. So when we start waiting for a interrupt, we
 354          * need to check status bit in control reg first, if it is already 1,
 355          * then we do not need to wait for interrupt
 356          */
 357         ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
 358         if (a3700_spi->wait_mask & ctrl_reg)
 359                 return true;
 360 
 361         reinit_completion(&a3700_spi->done);
 362 
 363         spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG,
 364                      a3700_spi->wait_mask);
 365 
 366         timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT);
 367         timeout = wait_for_completion_timeout(&a3700_spi->done,
 368                                               timeout_jiffies);
 369 
 370         a3700_spi->wait_mask = 0;
 371 
 372         if (timeout)
 373                 return true;
 374 
 375         /* there might be the case that right after we checked the
 376          * status bits in this routine and before start to wait for
 377          * interrupt by wait_for_completion_timeout, the interrupt
 378          * happens, to avoid missing it we need to double check
 379          * status bits in control reg, if it is already 1, then
 380          * consider that we have the interrupt successfully and
 381          * return true.
 382          */
 383         ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
 384         if (a3700_spi->wait_mask & ctrl_reg)
 385                 return true;
 386 
 387         spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
 388 
 389         /* Timeout was reached */
 390         return false;
 391 }
 392 
 393 static bool a3700_spi_transfer_wait(struct spi_device *spi,
 394                                     unsigned int bit_mask)
 395 {
 396         struct a3700_spi *a3700_spi;
 397 
 398         a3700_spi = spi_master_get_devdata(spi->master);
 399         a3700_spi->wait_mask = bit_mask;
 400 
 401         return a3700_spi_wait_completion(spi);
 402 }
 403 
 404 static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi,
 405                                      unsigned int bytes)
 406 {
 407         u32 val;
 408 
 409         val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 410         val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT);
 411         val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT;
 412         val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT);
 413         val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT;
 414         spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 415 }
 416 
 417 static void a3700_spi_transfer_setup(struct spi_device *spi,
 418                                      struct spi_transfer *xfer)
 419 {
 420         struct a3700_spi *a3700_spi;
 421 
 422         a3700_spi = spi_master_get_devdata(spi->master);
 423 
 424         a3700_spi_clock_set(a3700_spi, xfer->speed_hz);
 425 
 426         /* Use 4 bytes long transfers. Each transfer method has its way to deal
 427          * with the remaining bytes for non 4-bytes aligned transfers.
 428          */
 429         a3700_spi_bytelen_set(a3700_spi, 4);
 430 
 431         /* Initialize the working buffers */
 432         a3700_spi->tx_buf  = xfer->tx_buf;
 433         a3700_spi->rx_buf  = xfer->rx_buf;
 434         a3700_spi->buf_len = xfer->len;
 435 }
 436 
 437 static void a3700_spi_set_cs(struct spi_device *spi, bool enable)
 438 {
 439         struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master);
 440 
 441         if (!enable)
 442                 a3700_spi_activate_cs(a3700_spi, spi->chip_select);
 443         else
 444                 a3700_spi_deactivate_cs(a3700_spi, spi->chip_select);
 445 }
 446 
 447 static void a3700_spi_header_set(struct a3700_spi *a3700_spi)
 448 {
 449         unsigned int addr_cnt;
 450         u32 val = 0;
 451 
 452         /* Clear the header registers */
 453         spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0);
 454         spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0);
 455         spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0);
 456         spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
 457 
 458         /* Set header counters */
 459         if (a3700_spi->tx_buf) {
 460                 /*
 461                  * when tx data is not 4 bytes aligned, there will be unexpected
 462                  * bytes out of SPI output register, since it always shifts out
 463                  * as whole 4 bytes. This might cause incorrect transaction with
 464                  * some devices. To avoid that, use SPI header count feature to
 465                  * transfer up to 3 bytes of data first, and then make the rest
 466                  * of data 4-byte aligned.
 467                  */
 468                 addr_cnt = a3700_spi->buf_len % 4;
 469                 if (addr_cnt) {
 470                         val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK)
 471                                 << A3700_SPI_ADDR_CNT_BIT;
 472                         spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);
 473 
 474                         /* Update the buffer length to be transferred */
 475                         a3700_spi->buf_len -= addr_cnt;
 476 
 477                         /* transfer 1~3 bytes through address count */
 478                         val = 0;
 479                         while (addr_cnt--) {
 480                                 val = (val << 8) | a3700_spi->tx_buf[0];
 481                                 a3700_spi->tx_buf++;
 482                         }
 483                         spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);
 484                 }
 485         }
 486 }
 487 
 488 static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi)
 489 {
 490         u32 val;
 491 
 492         val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
 493         return (val & A3700_SPI_WFIFO_FULL);
 494 }
 495 
 496 static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi)
 497 {
 498         u32 val;
 499 
 500         while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) {
 501                 val = *(u32 *)a3700_spi->tx_buf;
 502                 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
 503                 a3700_spi->buf_len -= 4;
 504                 a3700_spi->tx_buf += 4;
 505         }
 506 
 507         return 0;
 508 }
 509 
 510 static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi)
 511 {
 512         u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
 513 
 514         return (val & A3700_SPI_RFIFO_EMPTY);
 515 }
 516 
 517 static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi)
 518 {
 519         u32 val;
 520 
 521         while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) {
 522                 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
 523                 if (a3700_spi->buf_len >= 4) {
 524 
 525                         memcpy(a3700_spi->rx_buf, &val, 4);
 526 
 527                         a3700_spi->buf_len -= 4;
 528                         a3700_spi->rx_buf += 4;
 529                 } else {
 530                         /*
 531                          * When remain bytes is not larger than 4, we should
 532                          * avoid memory overwriting and just write the left rx
 533                          * buffer bytes.
 534                          */
 535                         while (a3700_spi->buf_len) {
 536                                 *a3700_spi->rx_buf = val & 0xff;
 537                                 val >>= 8;
 538 
 539                                 a3700_spi->buf_len--;
 540                                 a3700_spi->rx_buf++;
 541                         }
 542                 }
 543         }
 544 
 545         return 0;
 546 }
 547 
 548 static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi)
 549 {
 550         int timeout = A3700_SPI_TIMEOUT;
 551         u32 val;
 552 
 553         val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 554         val |= A3700_SPI_XFER_STOP;
 555         spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 556 
 557         while (--timeout) {
 558                 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 559                 if (!(val & A3700_SPI_XFER_START))
 560                         break;
 561                 udelay(1);
 562         }
 563 
 564         a3700_spi_fifo_flush(a3700_spi);
 565 
 566         val &= ~A3700_SPI_XFER_STOP;
 567         spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 568 }
 569 
 570 static int a3700_spi_prepare_message(struct spi_master *master,
 571                                      struct spi_message *message)
 572 {
 573         struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
 574         struct spi_device *spi = message->spi;
 575         int ret;
 576 
 577         ret = clk_enable(a3700_spi->clk);
 578         if (ret) {
 579                 dev_err(&spi->dev, "failed to enable clk with error %d\n", ret);
 580                 return ret;
 581         }
 582 
 583         /* Flush the FIFOs */
 584         ret = a3700_spi_fifo_flush(a3700_spi);
 585         if (ret)
 586                 return ret;
 587 
 588         a3700_spi_mode_set(a3700_spi, spi->mode);
 589 
 590         return 0;
 591 }
 592 
 593 static int a3700_spi_transfer_one_fifo(struct spi_master *master,
 594                                   struct spi_device *spi,
 595                                   struct spi_transfer *xfer)
 596 {
 597         struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
 598         int ret = 0, timeout = A3700_SPI_TIMEOUT;
 599         unsigned int nbits = 0, byte_len;
 600         u32 val;
 601 
 602         /* Make sure we use FIFO mode */
 603         a3700_spi_fifo_mode_set(a3700_spi, true);
 604 
 605         /* Configure FIFO thresholds */
 606         byte_len = xfer->bits_per_word >> 3;
 607         a3700_spi_fifo_thres_set(a3700_spi, byte_len);
 608 
 609         if (xfer->tx_buf)
 610                 nbits = xfer->tx_nbits;
 611         else if (xfer->rx_buf)
 612                 nbits = xfer->rx_nbits;
 613 
 614         a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false);
 615 
 616         /* Flush the FIFOs */
 617         a3700_spi_fifo_flush(a3700_spi);
 618 
 619         /* Transfer first bytes of data when buffer is not 4-byte aligned */
 620         a3700_spi_header_set(a3700_spi);
 621 
 622         if (xfer->rx_buf) {
 623                 /* Clear WFIFO, since it's last 2 bytes are shifted out during
 624                  * a read operation
 625                  */
 626                 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0);
 627 
 628                 /* Set read data length */
 629                 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,
 630                              a3700_spi->buf_len);
 631                 /* Start READ transfer */
 632                 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 633                 val &= ~A3700_SPI_RW_EN;
 634                 val |= A3700_SPI_XFER_START;
 635                 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 636         } else if (xfer->tx_buf) {
 637                 /* Start Write transfer */
 638                 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 639                 val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN);
 640                 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 641 
 642                 /*
 643                  * If there are data to be written to the SPI device, xmit_data
 644                  * flag is set true; otherwise the instruction in SPI_INSTR does
 645                  * not require data to be written to the SPI device, then
 646                  * xmit_data flag is set false.
 647                  */
 648                 a3700_spi->xmit_data = (a3700_spi->buf_len != 0);
 649         }
 650 
 651         while (a3700_spi->buf_len) {
 652                 if (a3700_spi->tx_buf) {
 653                         /* Wait wfifo ready */
 654                         if (!a3700_spi_transfer_wait(spi,
 655                                                      A3700_SPI_WFIFO_RDY)) {
 656                                 dev_err(&spi->dev,
 657                                         "wait wfifo ready timed out\n");
 658                                 ret = -ETIMEDOUT;
 659                                 goto error;
 660                         }
 661                         /* Fill up the wfifo */
 662                         ret = a3700_spi_fifo_write(a3700_spi);
 663                         if (ret)
 664                                 goto error;
 665                 } else if (a3700_spi->rx_buf) {
 666                         /* Wait rfifo ready */
 667                         if (!a3700_spi_transfer_wait(spi,
 668                                                      A3700_SPI_RFIFO_RDY)) {
 669                                 dev_err(&spi->dev,
 670                                         "wait rfifo ready timed out\n");
 671                                 ret = -ETIMEDOUT;
 672                                 goto error;
 673                         }
 674                         /* Drain out the rfifo */
 675                         ret = a3700_spi_fifo_read(a3700_spi);
 676                         if (ret)
 677                                 goto error;
 678                 }
 679         }
 680 
 681         /*
 682          * Stop a write transfer in fifo mode:
 683          *      - wait all the bytes in wfifo to be shifted out
 684          *       - set XFER_STOP bit
 685          *      - wait XFER_START bit clear
 686          *      - clear XFER_STOP bit
 687          * Stop a read transfer in fifo mode:
 688          *      - the hardware is to reset the XFER_START bit
 689          *         after the number of bytes indicated in DIN_CNT
 690          *         register
 691          *      - just wait XFER_START bit clear
 692          */
 693         if (a3700_spi->tx_buf) {
 694                 if (a3700_spi->xmit_data) {
 695                         /*
 696                          * If there are data written to the SPI device, wait
 697                          * until SPI_WFIFO_EMPTY is 1 to wait for all data to
 698                          * transfer out of write FIFO.
 699                          */
 700                         if (!a3700_spi_transfer_wait(spi,
 701                                                      A3700_SPI_WFIFO_EMPTY)) {
 702                                 dev_err(&spi->dev, "wait wfifo empty timed out\n");
 703                                 return -ETIMEDOUT;
 704                         }
 705                 }
 706 
 707                 if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) {
 708                         dev_err(&spi->dev, "wait xfer ready timed out\n");
 709                         return -ETIMEDOUT;
 710                 }
 711 
 712                 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 713                 val |= A3700_SPI_XFER_STOP;
 714                 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 715         }
 716 
 717         while (--timeout) {
 718                 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
 719                 if (!(val & A3700_SPI_XFER_START))
 720                         break;
 721                 udelay(1);
 722         }
 723 
 724         if (timeout == 0) {
 725                 dev_err(&spi->dev, "wait transfer start clear timed out\n");
 726                 ret = -ETIMEDOUT;
 727                 goto error;
 728         }
 729 
 730         val &= ~A3700_SPI_XFER_STOP;
 731         spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
 732         goto out;
 733 
 734 error:
 735         a3700_spi_transfer_abort_fifo(a3700_spi);
 736 out:
 737         spi_finalize_current_transfer(master);
 738 
 739         return ret;
 740 }
 741 
 742 static int a3700_spi_transfer_one_full_duplex(struct spi_master *master,
 743                                   struct spi_device *spi,
 744                                   struct spi_transfer *xfer)
 745 {
 746         struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
 747         u32 val;
 748 
 749         /* Disable FIFO mode */
 750         a3700_spi_fifo_mode_set(a3700_spi, false);
 751 
 752         while (a3700_spi->buf_len) {
 753 
 754                 /* When we have less than 4 bytes to transfer, switch to 1 byte
 755                  * mode. This is reset after each transfer
 756                  */
 757                 if (a3700_spi->buf_len < 4)
 758                         a3700_spi_bytelen_set(a3700_spi, 1);
 759 
 760                 if (a3700_spi->byte_len == 1)
 761                         val = *a3700_spi->tx_buf;
 762                 else
 763                         val = *(u32 *)a3700_spi->tx_buf;
 764 
 765                 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
 766 
 767                 /* Wait for all the data to be shifted in / out */
 768                 while (!(spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG) &
 769                                 A3700_SPI_XFER_DONE))
 770                         cpu_relax();
 771 
 772                 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
 773 
 774                 memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len);
 775 
 776                 a3700_spi->buf_len -= a3700_spi->byte_len;
 777                 a3700_spi->tx_buf += a3700_spi->byte_len;
 778                 a3700_spi->rx_buf += a3700_spi->byte_len;
 779 
 780         }
 781 
 782         spi_finalize_current_transfer(master);
 783 
 784         return 0;
 785 }
 786 
 787 static int a3700_spi_transfer_one(struct spi_master *master,
 788                                   struct spi_device *spi,
 789                                   struct spi_transfer *xfer)
 790 {
 791         a3700_spi_transfer_setup(spi, xfer);
 792 
 793         if (xfer->tx_buf && xfer->rx_buf)
 794                 return a3700_spi_transfer_one_full_duplex(master, spi, xfer);
 795 
 796         return a3700_spi_transfer_one_fifo(master, spi, xfer);
 797 }
 798 
 799 static int a3700_spi_unprepare_message(struct spi_master *master,
 800                                        struct spi_message *message)
 801 {
 802         struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
 803 
 804         clk_disable(a3700_spi->clk);
 805 
 806         return 0;
 807 }
 808 
 809 static const struct of_device_id a3700_spi_dt_ids[] = {
 810         { .compatible = "marvell,armada-3700-spi", .data = NULL },
 811         {},
 812 };
 813 
 814 MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids);
 815 
 816 static int a3700_spi_probe(struct platform_device *pdev)
 817 {
 818         struct device *dev = &pdev->dev;
 819         struct device_node *of_node = dev->of_node;
 820         struct spi_master *master;
 821         struct a3700_spi *spi;
 822         u32 num_cs = 0;
 823         int irq, ret = 0;
 824 
 825         master = spi_alloc_master(dev, sizeof(*spi));
 826         if (!master) {
 827                 dev_err(dev, "master allocation failed\n");
 828                 ret = -ENOMEM;
 829                 goto out;
 830         }
 831 
 832         if (of_property_read_u32(of_node, "num-cs", &num_cs)) {
 833                 dev_err(dev, "could not find num-cs\n");
 834                 ret = -ENXIO;
 835                 goto error;
 836         }
 837 
 838         master->bus_num = pdev->id;
 839         master->dev.of_node = of_node;
 840         master->mode_bits = SPI_MODE_3;
 841         master->num_chipselect = num_cs;
 842         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32);
 843         master->prepare_message =  a3700_spi_prepare_message;
 844         master->transfer_one = a3700_spi_transfer_one;
 845         master->unprepare_message = a3700_spi_unprepare_message;
 846         master->set_cs = a3700_spi_set_cs;
 847         master->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL |
 848                               SPI_RX_QUAD | SPI_TX_QUAD);
 849 
 850         platform_set_drvdata(pdev, master);
 851 
 852         spi = spi_master_get_devdata(master);
 853         memset(spi, 0, sizeof(struct a3700_spi));
 854 
 855         spi->master = master;
 856 
 857         spi->base = devm_platform_ioremap_resource(pdev, 0);
 858         if (IS_ERR(spi->base)) {
 859                 ret = PTR_ERR(spi->base);
 860                 goto error;
 861         }
 862 
 863         irq = platform_get_irq(pdev, 0);
 864         if (irq < 0) {
 865                 ret = -ENXIO;
 866                 goto error;
 867         }
 868         spi->irq = irq;
 869 
 870         init_completion(&spi->done);
 871 
 872         spi->clk = devm_clk_get(dev, NULL);
 873         if (IS_ERR(spi->clk)) {
 874                 dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk));
 875                 goto error;
 876         }
 877 
 878         ret = clk_prepare(spi->clk);
 879         if (ret) {
 880                 dev_err(dev, "could not prepare clk: %d\n", ret);
 881                 goto error;
 882         }
 883 
 884         master->max_speed_hz = min_t(unsigned long, A3700_SPI_MAX_SPEED_HZ,
 885                                         clk_get_rate(spi->clk));
 886         master->min_speed_hz = DIV_ROUND_UP(clk_get_rate(spi->clk),
 887                                                 A3700_SPI_MAX_PRESCALE);
 888 
 889         ret = a3700_spi_init(spi);
 890         if (ret)
 891                 goto error_clk;
 892 
 893         ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0,
 894                                dev_name(dev), master);
 895         if (ret) {
 896                 dev_err(dev, "could not request IRQ: %d\n", ret);
 897                 goto error_clk;
 898         }
 899 
 900         ret = devm_spi_register_master(dev, master);
 901         if (ret) {
 902                 dev_err(dev, "Failed to register master\n");
 903                 goto error_clk;
 904         }
 905 
 906         return 0;
 907 
 908 error_clk:
 909         clk_disable_unprepare(spi->clk);
 910 error:
 911         spi_master_put(master);
 912 out:
 913         return ret;
 914 }
 915 
 916 static int a3700_spi_remove(struct platform_device *pdev)
 917 {
 918         struct spi_master *master = platform_get_drvdata(pdev);
 919         struct a3700_spi *spi = spi_master_get_devdata(master);
 920 
 921         clk_unprepare(spi->clk);
 922 
 923         return 0;
 924 }
 925 
 926 static struct platform_driver a3700_spi_driver = {
 927         .driver = {
 928                 .name   = DRIVER_NAME,
 929                 .of_match_table = of_match_ptr(a3700_spi_dt_ids),
 930         },
 931         .probe          = a3700_spi_probe,
 932         .remove         = a3700_spi_remove,
 933 };
 934 
 935 module_platform_driver(a3700_spi_driver);
 936 
 937 MODULE_DESCRIPTION("Armada-3700 SPI driver");
 938 MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>");
 939 MODULE_LICENSE("GPL");
 940 MODULE_ALIAS("platform:" DRIVER_NAME);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/spi/spi-armada-3700.c

DEFINITIONS
