drivers/spi/spi-pl022.c

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This source file includes following definitions.
null_cs_control
internal_cs_control
pl022_cs_control
giveback
flush
restore_state
load_ssp_default_config
readwriter
next_transfer
unmap_free_dma_scatter
dma_callback
setup_dma_scatter
configure_dma
pl022_dma_probe
pl022_dma_autoprobe
terminate_dma
pl022_dma_remove
configure_dma
pl022_dma_autoprobe
pl022_dma_probe
pl022_dma_remove
pl022_interrupt_handler
set_up_next_transfer
pump_transfers
do_interrupt_dma_transfer
print_current_status
do_polling_transfer
pl022_transfer_one_message
pl022_unprepare_transfer_hardware
verify_controller_parameters
spi_rate
calculate_effective_freq
pl022_setup
pl022_cleanup
pl022_platform_data_dt_get
pl022_probe
pl022_remove
pl022_suspend
pl022_resume
pl022_runtime_suspend
pl022_runtime_resume
pl022_init
pl022_exit
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
   4  *
   5  * Copyright (C) 2008-2012 ST-Ericsson AB
   6  * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
   7  *
   8  * Author: Linus Walleij <linus.walleij@stericsson.com>
   9  *
  10  * Initial version inspired by:
  11  *      linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
  12  * Initial adoption to PL022 by:
  13  *      Sachin Verma <sachin.verma@st.com>
  14  */
  15 
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/device.h>
  19 #include <linux/ioport.h>
  20 #include <linux/errno.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/amba/pl022.h>
  28 #include <linux/io.h>
  29 #include <linux/slab.h>
  30 #include <linux/dmaengine.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/scatterlist.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/gpio.h>
  35 #include <linux/of_gpio.h>
  36 #include <linux/pinctrl/consumer.h>
  37 
  38 /*
  39  * This macro is used to define some register default values.
  40  * reg is masked with mask, the OR:ed with an (again masked)
  41  * val shifted sb steps to the left.
  42  */
  43 #define SSP_WRITE_BITS(reg, val, mask, sb) \
  44  ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
  45 
  46 /*
  47  * This macro is also used to define some default values.
  48  * It will just shift val by sb steps to the left and mask
  49  * the result with mask.
  50  */
  51 #define GEN_MASK_BITS(val, mask, sb) \
  52  (((val)<<(sb)) & (mask))
  53 
  54 #define DRIVE_TX                0
  55 #define DO_NOT_DRIVE_TX         1
  56 
  57 #define DO_NOT_QUEUE_DMA        0
  58 #define QUEUE_DMA               1
  59 
  60 #define RX_TRANSFER             1
  61 #define TX_TRANSFER             2
  62 
  63 /*
  64  * Macros to access SSP Registers with their offsets
  65  */
  66 #define SSP_CR0(r)      (r + 0x000)
  67 #define SSP_CR1(r)      (r + 0x004)
  68 #define SSP_DR(r)       (r + 0x008)
  69 #define SSP_SR(r)       (r + 0x00C)
  70 #define SSP_CPSR(r)     (r + 0x010)
  71 #define SSP_IMSC(r)     (r + 0x014)
  72 #define SSP_RIS(r)      (r + 0x018)
  73 #define SSP_MIS(r)      (r + 0x01C)
  74 #define SSP_ICR(r)      (r + 0x020)
  75 #define SSP_DMACR(r)    (r + 0x024)
  76 #define SSP_CSR(r)      (r + 0x030) /* vendor extension */
  77 #define SSP_ITCR(r)     (r + 0x080)
  78 #define SSP_ITIP(r)     (r + 0x084)
  79 #define SSP_ITOP(r)     (r + 0x088)
  80 #define SSP_TDR(r)      (r + 0x08C)
  81 
  82 #define SSP_PID0(r)     (r + 0xFE0)
  83 #define SSP_PID1(r)     (r + 0xFE4)
  84 #define SSP_PID2(r)     (r + 0xFE8)
  85 #define SSP_PID3(r)     (r + 0xFEC)
  86 
  87 #define SSP_CID0(r)     (r + 0xFF0)
  88 #define SSP_CID1(r)     (r + 0xFF4)
  89 #define SSP_CID2(r)     (r + 0xFF8)
  90 #define SSP_CID3(r)     (r + 0xFFC)
  91 
  92 /*
  93  * SSP Control Register 0  - SSP_CR0
  94  */
  95 #define SSP_CR0_MASK_DSS        (0x0FUL << 0)
  96 #define SSP_CR0_MASK_FRF        (0x3UL << 4)
  97 #define SSP_CR0_MASK_SPO        (0x1UL << 6)
  98 #define SSP_CR0_MASK_SPH        (0x1UL << 7)
  99 #define SSP_CR0_MASK_SCR        (0xFFUL << 8)
 100 
 101 /*
 102  * The ST version of this block moves som bits
 103  * in SSP_CR0 and extends it to 32 bits
 104  */
 105 #define SSP_CR0_MASK_DSS_ST     (0x1FUL << 0)
 106 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
 107 #define SSP_CR0_MASK_CSS_ST     (0x1FUL << 16)
 108 #define SSP_CR0_MASK_FRF_ST     (0x3UL << 21)
 109 
 110 /*
 111  * SSP Control Register 0  - SSP_CR1
 112  */
 113 #define SSP_CR1_MASK_LBM        (0x1UL << 0)
 114 #define SSP_CR1_MASK_SSE        (0x1UL << 1)
 115 #define SSP_CR1_MASK_MS         (0x1UL << 2)
 116 #define SSP_CR1_MASK_SOD        (0x1UL << 3)
 117 
 118 /*
 119  * The ST version of this block adds some bits
 120  * in SSP_CR1
 121  */
 122 #define SSP_CR1_MASK_RENDN_ST   (0x1UL << 4)
 123 #define SSP_CR1_MASK_TENDN_ST   (0x1UL << 5)
 124 #define SSP_CR1_MASK_MWAIT_ST   (0x1UL << 6)
 125 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
 126 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
 127 /* This one is only in the PL023 variant */
 128 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
 129 
 130 /*
 131  * SSP Status Register - SSP_SR
 132  */
 133 #define SSP_SR_MASK_TFE         (0x1UL << 0) /* Transmit FIFO empty */
 134 #define SSP_SR_MASK_TNF         (0x1UL << 1) /* Transmit FIFO not full */
 135 #define SSP_SR_MASK_RNE         (0x1UL << 2) /* Receive FIFO not empty */
 136 #define SSP_SR_MASK_RFF         (0x1UL << 3) /* Receive FIFO full */
 137 #define SSP_SR_MASK_BSY         (0x1UL << 4) /* Busy Flag */
 138 
 139 /*
 140  * SSP Clock Prescale Register  - SSP_CPSR
 141  */
 142 #define SSP_CPSR_MASK_CPSDVSR   (0xFFUL << 0)
 143 
 144 /*
 145  * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
 146  */
 147 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
 148 #define SSP_IMSC_MASK_RTIM  (0x1UL << 1) /* Receive timeout Interrupt mask */
 149 #define SSP_IMSC_MASK_RXIM  (0x1UL << 2) /* Receive FIFO Interrupt mask */
 150 #define SSP_IMSC_MASK_TXIM  (0x1UL << 3) /* Transmit FIFO Interrupt mask */
 151 
 152 /*
 153  * SSP Raw Interrupt Status Register - SSP_RIS
 154  */
 155 /* Receive Overrun Raw Interrupt status */
 156 #define SSP_RIS_MASK_RORRIS             (0x1UL << 0)
 157 /* Receive Timeout Raw Interrupt status */
 158 #define SSP_RIS_MASK_RTRIS              (0x1UL << 1)
 159 /* Receive FIFO Raw Interrupt status */
 160 #define SSP_RIS_MASK_RXRIS              (0x1UL << 2)
 161 /* Transmit FIFO Raw Interrupt status */
 162 #define SSP_RIS_MASK_TXRIS              (0x1UL << 3)
 163 
 164 /*
 165  * SSP Masked Interrupt Status Register - SSP_MIS
 166  */
 167 /* Receive Overrun Masked Interrupt status */
 168 #define SSP_MIS_MASK_RORMIS             (0x1UL << 0)
 169 /* Receive Timeout Masked Interrupt status */
 170 #define SSP_MIS_MASK_RTMIS              (0x1UL << 1)
 171 /* Receive FIFO Masked Interrupt status */
 172 #define SSP_MIS_MASK_RXMIS              (0x1UL << 2)
 173 /* Transmit FIFO Masked Interrupt status */
 174 #define SSP_MIS_MASK_TXMIS              (0x1UL << 3)
 175 
 176 /*
 177  * SSP Interrupt Clear Register - SSP_ICR
 178  */
 179 /* Receive Overrun Raw Clear Interrupt bit */
 180 #define SSP_ICR_MASK_RORIC              (0x1UL << 0)
 181 /* Receive Timeout Clear Interrupt bit */
 182 #define SSP_ICR_MASK_RTIC               (0x1UL << 1)
 183 
 184 /*
 185  * SSP DMA Control Register - SSP_DMACR
 186  */
 187 /* Receive DMA Enable bit */
 188 #define SSP_DMACR_MASK_RXDMAE           (0x1UL << 0)
 189 /* Transmit DMA Enable bit */
 190 #define SSP_DMACR_MASK_TXDMAE           (0x1UL << 1)
 191 
 192 /*
 193  * SSP Chip Select Control Register - SSP_CSR
 194  * (vendor extension)
 195  */
 196 #define SSP_CSR_CSVALUE_MASK            (0x1FUL << 0)
 197 
 198 /*
 199  * SSP Integration Test control Register - SSP_ITCR
 200  */
 201 #define SSP_ITCR_MASK_ITEN              (0x1UL << 0)
 202 #define SSP_ITCR_MASK_TESTFIFO          (0x1UL << 1)
 203 
 204 /*
 205  * SSP Integration Test Input Register - SSP_ITIP
 206  */
 207 #define ITIP_MASK_SSPRXD                 (0x1UL << 0)
 208 #define ITIP_MASK_SSPFSSIN               (0x1UL << 1)
 209 #define ITIP_MASK_SSPCLKIN               (0x1UL << 2)
 210 #define ITIP_MASK_RXDMAC                 (0x1UL << 3)
 211 #define ITIP_MASK_TXDMAC                 (0x1UL << 4)
 212 #define ITIP_MASK_SSPTXDIN               (0x1UL << 5)
 213 
 214 /*
 215  * SSP Integration Test output Register - SSP_ITOP
 216  */
 217 #define ITOP_MASK_SSPTXD                 (0x1UL << 0)
 218 #define ITOP_MASK_SSPFSSOUT              (0x1UL << 1)
 219 #define ITOP_MASK_SSPCLKOUT              (0x1UL << 2)
 220 #define ITOP_MASK_SSPOEn                 (0x1UL << 3)
 221 #define ITOP_MASK_SSPCTLOEn              (0x1UL << 4)
 222 #define ITOP_MASK_RORINTR                (0x1UL << 5)
 223 #define ITOP_MASK_RTINTR                 (0x1UL << 6)
 224 #define ITOP_MASK_RXINTR                 (0x1UL << 7)
 225 #define ITOP_MASK_TXINTR                 (0x1UL << 8)
 226 #define ITOP_MASK_INTR                   (0x1UL << 9)
 227 #define ITOP_MASK_RXDMABREQ              (0x1UL << 10)
 228 #define ITOP_MASK_RXDMASREQ              (0x1UL << 11)
 229 #define ITOP_MASK_TXDMABREQ              (0x1UL << 12)
 230 #define ITOP_MASK_TXDMASREQ              (0x1UL << 13)
 231 
 232 /*
 233  * SSP Test Data Register - SSP_TDR
 234  */
 235 #define TDR_MASK_TESTDATA               (0xFFFFFFFF)
 236 
 237 /*
 238  * Message State
 239  * we use the spi_message.state (void *) pointer to
 240  * hold a single state value, that's why all this
 241  * (void *) casting is done here.
 242  */
 243 #define STATE_START                     ((void *) 0)
 244 #define STATE_RUNNING                   ((void *) 1)
 245 #define STATE_DONE                      ((void *) 2)
 246 #define STATE_ERROR                     ((void *) -1)
 247 #define STATE_TIMEOUT                   ((void *) -2)
 248 
 249 /*
 250  * SSP State - Whether Enabled or Disabled
 251  */
 252 #define SSP_DISABLED                    (0)
 253 #define SSP_ENABLED                     (1)
 254 
 255 /*
 256  * SSP DMA State - Whether DMA Enabled or Disabled
 257  */
 258 #define SSP_DMA_DISABLED                (0)
 259 #define SSP_DMA_ENABLED                 (1)
 260 
 261 /*
 262  * SSP Clock Defaults
 263  */
 264 #define SSP_DEFAULT_CLKRATE 0x2
 265 #define SSP_DEFAULT_PRESCALE 0x40
 266 
 267 /*
 268  * SSP Clock Parameter ranges
 269  */
 270 #define CPSDVR_MIN 0x02
 271 #define CPSDVR_MAX 0xFE
 272 #define SCR_MIN 0x00
 273 #define SCR_MAX 0xFF
 274 
 275 /*
 276  * SSP Interrupt related Macros
 277  */
 278 #define DEFAULT_SSP_REG_IMSC  0x0UL
 279 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
 280 #define ENABLE_ALL_INTERRUPTS ( \
 281         SSP_IMSC_MASK_RORIM | \
 282         SSP_IMSC_MASK_RTIM | \
 283         SSP_IMSC_MASK_RXIM | \
 284         SSP_IMSC_MASK_TXIM \
 285 )
 286 
 287 #define CLEAR_ALL_INTERRUPTS  0x3
 288 
 289 #define SPI_POLLING_TIMEOUT 1000
 290 
 291 /*
 292  * The type of reading going on on this chip
 293  */
 294 enum ssp_reading {
 295         READING_NULL,
 296         READING_U8,
 297         READING_U16,
 298         READING_U32
 299 };
 300 
 301 /**
 302  * The type of writing going on on this chip
 303  */
 304 enum ssp_writing {
 305         WRITING_NULL,
 306         WRITING_U8,
 307         WRITING_U16,
 308         WRITING_U32
 309 };
 310 
 311 /**
 312  * struct vendor_data - vendor-specific config parameters
 313  * for PL022 derivates
 314  * @fifodepth: depth of FIFOs (both)
 315  * @max_bpw: maximum number of bits per word
 316  * @unidir: supports unidirection transfers
 317  * @extended_cr: 32 bit wide control register 0 with extra
 318  * features and extra features in CR1 as found in the ST variants
 319  * @pl023: supports a subset of the ST extensions called "PL023"
 320  * @internal_cs_ctrl: supports chip select control register
 321  */
 322 struct vendor_data {
 323         int fifodepth;
 324         int max_bpw;
 325         bool unidir;
 326         bool extended_cr;
 327         bool pl023;
 328         bool loopback;
 329         bool internal_cs_ctrl;
 330 };
 331 
 332 /**
 333  * struct pl022 - This is the private SSP driver data structure
 334  * @adev: AMBA device model hookup
 335  * @vendor: vendor data for the IP block
 336  * @phybase: the physical memory where the SSP device resides
 337  * @virtbase: the virtual memory where the SSP is mapped
 338  * @clk: outgoing clock "SPICLK" for the SPI bus
 339  * @master: SPI framework hookup
 340  * @master_info: controller-specific data from machine setup
 341  * @pump_transfers: Tasklet used in Interrupt Transfer mode
 342  * @cur_msg: Pointer to current spi_message being processed
 343  * @cur_transfer: Pointer to current spi_transfer
 344  * @cur_chip: pointer to current clients chip(assigned from controller_state)
 345  * @next_msg_cs_active: the next message in the queue has been examined
 346  *  and it was found that it uses the same chip select as the previous
 347  *  message, so we left it active after the previous transfer, and it's
 348  *  active already.
 349  * @tx: current position in TX buffer to be read
 350  * @tx_end: end position in TX buffer to be read
 351  * @rx: current position in RX buffer to be written
 352  * @rx_end: end position in RX buffer to be written
 353  * @read: the type of read currently going on
 354  * @write: the type of write currently going on
 355  * @exp_fifo_level: expected FIFO level
 356  * @dma_rx_channel: optional channel for RX DMA
 357  * @dma_tx_channel: optional channel for TX DMA
 358  * @sgt_rx: scattertable for the RX transfer
 359  * @sgt_tx: scattertable for the TX transfer
 360  * @dummypage: a dummy page used for driving data on the bus with DMA
 361  * @cur_cs: current chip select (gpio)
 362  * @chipselects: list of chipselects (gpios)
 363  */
 364 struct pl022 {
 365         struct amba_device              *adev;
 366         struct vendor_data              *vendor;
 367         resource_size_t                 phybase;
 368         void __iomem                    *virtbase;
 369         struct clk                      *clk;
 370         struct spi_master               *master;
 371         struct pl022_ssp_controller     *master_info;
 372         /* Message per-transfer pump */
 373         struct tasklet_struct           pump_transfers;
 374         struct spi_message              *cur_msg;
 375         struct spi_transfer             *cur_transfer;
 376         struct chip_data                *cur_chip;
 377         bool                            next_msg_cs_active;
 378         void                            *tx;
 379         void                            *tx_end;
 380         void                            *rx;
 381         void                            *rx_end;
 382         enum ssp_reading                read;
 383         enum ssp_writing                write;
 384         u32                             exp_fifo_level;
 385         enum ssp_rx_level_trig          rx_lev_trig;
 386         enum ssp_tx_level_trig          tx_lev_trig;
 387         /* DMA settings */
 388 #ifdef CONFIG_DMA_ENGINE
 389         struct dma_chan                 *dma_rx_channel;
 390         struct dma_chan                 *dma_tx_channel;
 391         struct sg_table                 sgt_rx;
 392         struct sg_table                 sgt_tx;
 393         char                            *dummypage;
 394         bool                            dma_running;
 395 #endif
 396         int cur_cs;
 397         int *chipselects;
 398 };
 399 
 400 /**
 401  * struct chip_data - To maintain runtime state of SSP for each client chip
 402  * @cr0: Value of control register CR0 of SSP - on later ST variants this
 403  *       register is 32 bits wide rather than just 16
 404  * @cr1: Value of control register CR1 of SSP
 405  * @dmacr: Value of DMA control Register of SSP
 406  * @cpsr: Value of Clock prescale register
 407  * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
 408  * @enable_dma: Whether to enable DMA or not
 409  * @read: function ptr to be used to read when doing xfer for this chip
 410  * @write: function ptr to be used to write when doing xfer for this chip
 411  * @cs_control: chip select callback provided by chip
 412  * @xfer_type: polling/interrupt/DMA
 413  *
 414  * Runtime state of the SSP controller, maintained per chip,
 415  * This would be set according to the current message that would be served
 416  */
 417 struct chip_data {
 418         u32 cr0;
 419         u16 cr1;
 420         u16 dmacr;
 421         u16 cpsr;
 422         u8 n_bytes;
 423         bool enable_dma;
 424         enum ssp_reading read;
 425         enum ssp_writing write;
 426         void (*cs_control) (u32 command);
 427         int xfer_type;
 428 };
 429 
 430 /**
 431  * null_cs_control - Dummy chip select function
 432  * @command: select/delect the chip
 433  *
 434  * If no chip select function is provided by client this is used as dummy
 435  * chip select
 436  */
 437 static void null_cs_control(u32 command)
 438 {
 439         pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
 440 }
 441 
 442 /**
 443  * internal_cs_control - Control chip select signals via SSP_CSR.
 444  * @pl022: SSP driver private data structure
 445  * @command: select/delect the chip
 446  *
 447  * Used on controller with internal chip select control via SSP_CSR register
 448  * (vendor extension). Each of the 5 LSB in the register controls one chip
 449  * select signal.
 450  */
 451 static void internal_cs_control(struct pl022 *pl022, u32 command)
 452 {
 453         u32 tmp;
 454 
 455         tmp = readw(SSP_CSR(pl022->virtbase));
 456         if (command == SSP_CHIP_SELECT)
 457                 tmp &= ~BIT(pl022->cur_cs);
 458         else
 459                 tmp |= BIT(pl022->cur_cs);
 460         writew(tmp, SSP_CSR(pl022->virtbase));
 461 }
 462 
 463 static void pl022_cs_control(struct pl022 *pl022, u32 command)
 464 {
 465         if (pl022->vendor->internal_cs_ctrl)
 466                 internal_cs_control(pl022, command);
 467         else if (gpio_is_valid(pl022->cur_cs))
 468                 gpio_set_value(pl022->cur_cs, command);
 469         else
 470                 pl022->cur_chip->cs_control(command);
 471 }
 472 
 473 /**
 474  * giveback - current spi_message is over, schedule next message and call
 475  * callback of this message. Assumes that caller already
 476  * set message->status; dma and pio irqs are blocked
 477  * @pl022: SSP driver private data structure
 478  */
 479 static void giveback(struct pl022 *pl022)
 480 {
 481         struct spi_transfer *last_transfer;
 482         pl022->next_msg_cs_active = false;
 483 
 484         last_transfer = list_last_entry(&pl022->cur_msg->transfers,
 485                                         struct spi_transfer, transfer_list);
 486 
 487         /* Delay if requested before any change in chip select */
 488         if (last_transfer->delay_usecs)
 489                 /*
 490                  * FIXME: This runs in interrupt context.
 491                  * Is this really smart?
 492                  */
 493                 udelay(last_transfer->delay_usecs);
 494 
 495         if (!last_transfer->cs_change) {
 496                 struct spi_message *next_msg;
 497 
 498                 /*
 499                  * cs_change was not set. We can keep the chip select
 500                  * enabled if there is message in the queue and it is
 501                  * for the same spi device.
 502                  *
 503                  * We cannot postpone this until pump_messages, because
 504                  * after calling msg->complete (below) the driver that
 505                  * sent the current message could be unloaded, which
 506                  * could invalidate the cs_control() callback...
 507                  */
 508                 /* get a pointer to the next message, if any */
 509                 next_msg = spi_get_next_queued_message(pl022->master);
 510 
 511                 /*
 512                  * see if the next and current messages point
 513                  * to the same spi device.
 514                  */
 515                 if (next_msg && next_msg->spi != pl022->cur_msg->spi)
 516                         next_msg = NULL;
 517                 if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
 518                         pl022_cs_control(pl022, SSP_CHIP_DESELECT);
 519                 else
 520                         pl022->next_msg_cs_active = true;
 521 
 522         }
 523 
 524         pl022->cur_msg = NULL;
 525         pl022->cur_transfer = NULL;
 526         pl022->cur_chip = NULL;
 527 
 528         /* disable the SPI/SSP operation */
 529         writew((readw(SSP_CR1(pl022->virtbase)) &
 530                 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
 531 
 532         spi_finalize_current_message(pl022->master);
 533 }
 534 
 535 /**
 536  * flush - flush the FIFO to reach a clean state
 537  * @pl022: SSP driver private data structure
 538  */
 539 static int flush(struct pl022 *pl022)
 540 {
 541         unsigned long limit = loops_per_jiffy << 1;
 542 
 543         dev_dbg(&pl022->adev->dev, "flush\n");
 544         do {
 545                 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
 546                         readw(SSP_DR(pl022->virtbase));
 547         } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
 548 
 549         pl022->exp_fifo_level = 0;
 550 
 551         return limit;
 552 }
 553 
 554 /**
 555  * restore_state - Load configuration of current chip
 556  * @pl022: SSP driver private data structure
 557  */
 558 static void restore_state(struct pl022 *pl022)
 559 {
 560         struct chip_data *chip = pl022->cur_chip;
 561 
 562         if (pl022->vendor->extended_cr)
 563                 writel(chip->cr0, SSP_CR0(pl022->virtbase));
 564         else
 565                 writew(chip->cr0, SSP_CR0(pl022->virtbase));
 566         writew(chip->cr1, SSP_CR1(pl022->virtbase));
 567         writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
 568         writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
 569         writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
 570         writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
 571 }
 572 
 573 /*
 574  * Default SSP Register Values
 575  */
 576 #define DEFAULT_SSP_REG_CR0 ( \
 577         GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0)    | \
 578         GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
 579         GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
 580         GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
 581         GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
 582 )
 583 
 584 /* ST versions have slightly different bit layout */
 585 #define DEFAULT_SSP_REG_CR0_ST ( \
 586         GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
 587         GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
 588         GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
 589         GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
 590         GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
 591         GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16)      | \
 592         GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
 593 )
 594 
 595 /* The PL023 version is slightly different again */
 596 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
 597         GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
 598         GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
 599         GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
 600         GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
 601 )
 602 
 603 #define DEFAULT_SSP_REG_CR1 ( \
 604         GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
 605         GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
 606         GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
 607         GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
 608 )
 609 
 610 /* ST versions extend this register to use all 16 bits */
 611 #define DEFAULT_SSP_REG_CR1_ST ( \
 612         DEFAULT_SSP_REG_CR1 | \
 613         GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
 614         GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
 615         GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
 616         GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
 617         GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
 618 )
 619 
 620 /*
 621  * The PL023 variant has further differences: no loopback mode, no microwire
 622  * support, and a new clock feedback delay setting.
 623  */
 624 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
 625         GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
 626         GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
 627         GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
 628         GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
 629         GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
 630         GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
 631         GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
 632         GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
 633 )
 634 
 635 #define DEFAULT_SSP_REG_CPSR ( \
 636         GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
 637 )
 638 
 639 #define DEFAULT_SSP_REG_DMACR (\
 640         GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
 641         GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
 642 )
 643 
 644 /**
 645  * load_ssp_default_config - Load default configuration for SSP
 646  * @pl022: SSP driver private data structure
 647  */
 648 static void load_ssp_default_config(struct pl022 *pl022)
 649 {
 650         if (pl022->vendor->pl023) {
 651                 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
 652                 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
 653         } else if (pl022->vendor->extended_cr) {
 654                 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
 655                 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
 656         } else {
 657                 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
 658                 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
 659         }
 660         writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
 661         writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
 662         writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
 663         writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
 664 }
 665 
 666 /**
 667  * This will write to TX and read from RX according to the parameters
 668  * set in pl022.
 669  */
 670 static void readwriter(struct pl022 *pl022)
 671 {
 672 
 673         /*
 674          * The FIFO depth is different between primecell variants.
 675          * I believe filling in too much in the FIFO might cause
 676          * errons in 8bit wide transfers on ARM variants (just 8 words
 677          * FIFO, means only 8x8 = 64 bits in FIFO) at least.
 678          *
 679          * To prevent this issue, the TX FIFO is only filled to the
 680          * unused RX FIFO fill length, regardless of what the TX
 681          * FIFO status flag indicates.
 682          */
 683         dev_dbg(&pl022->adev->dev,
 684                 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
 685                 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
 686 
 687         /* Read as much as you can */
 688         while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
 689                && (pl022->rx < pl022->rx_end)) {
 690                 switch (pl022->read) {
 691                 case READING_NULL:
 692                         readw(SSP_DR(pl022->virtbase));
 693                         break;
 694                 case READING_U8:
 695                         *(u8 *) (pl022->rx) =
 696                                 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
 697                         break;
 698                 case READING_U16:
 699                         *(u16 *) (pl022->rx) =
 700                                 (u16) readw(SSP_DR(pl022->virtbase));
 701                         break;
 702                 case READING_U32:
 703                         *(u32 *) (pl022->rx) =
 704                                 readl(SSP_DR(pl022->virtbase));
 705                         break;
 706                 }
 707                 pl022->rx += (pl022->cur_chip->n_bytes);
 708                 pl022->exp_fifo_level--;
 709         }
 710         /*
 711          * Write as much as possible up to the RX FIFO size
 712          */
 713         while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
 714                && (pl022->tx < pl022->tx_end)) {
 715                 switch (pl022->write) {
 716                 case WRITING_NULL:
 717                         writew(0x0, SSP_DR(pl022->virtbase));
 718                         break;
 719                 case WRITING_U8:
 720                         writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
 721                         break;
 722                 case WRITING_U16:
 723                         writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
 724                         break;
 725                 case WRITING_U32:
 726                         writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
 727                         break;
 728                 }
 729                 pl022->tx += (pl022->cur_chip->n_bytes);
 730                 pl022->exp_fifo_level++;
 731                 /*
 732                  * This inner reader takes care of things appearing in the RX
 733                  * FIFO as we're transmitting. This will happen a lot since the
 734                  * clock starts running when you put things into the TX FIFO,
 735                  * and then things are continuously clocked into the RX FIFO.
 736                  */
 737                 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
 738                        && (pl022->rx < pl022->rx_end)) {
 739                         switch (pl022->read) {
 740                         case READING_NULL:
 741                                 readw(SSP_DR(pl022->virtbase));
 742                                 break;
 743                         case READING_U8:
 744                                 *(u8 *) (pl022->rx) =
 745                                         readw(SSP_DR(pl022->virtbase)) & 0xFFU;
 746                                 break;
 747                         case READING_U16:
 748                                 *(u16 *) (pl022->rx) =
 749                                         (u16) readw(SSP_DR(pl022->virtbase));
 750                                 break;
 751                         case READING_U32:
 752                                 *(u32 *) (pl022->rx) =
 753                                         readl(SSP_DR(pl022->virtbase));
 754                                 break;
 755                         }
 756                         pl022->rx += (pl022->cur_chip->n_bytes);
 757                         pl022->exp_fifo_level--;
 758                 }
 759         }
 760         /*
 761          * When we exit here the TX FIFO should be full and the RX FIFO
 762          * should be empty
 763          */
 764 }
 765 
 766 /**
 767  * next_transfer - Move to the Next transfer in the current spi message
 768  * @pl022: SSP driver private data structure
 769  *
 770  * This function moves though the linked list of spi transfers in the
 771  * current spi message and returns with the state of current spi
 772  * message i.e whether its last transfer is done(STATE_DONE) or
 773  * Next transfer is ready(STATE_RUNNING)
 774  */
 775 static void *next_transfer(struct pl022 *pl022)
 776 {
 777         struct spi_message *msg = pl022->cur_msg;
 778         struct spi_transfer *trans = pl022->cur_transfer;
 779 
 780         /* Move to next transfer */
 781         if (trans->transfer_list.next != &msg->transfers) {
 782                 pl022->cur_transfer =
 783                     list_entry(trans->transfer_list.next,
 784                                struct spi_transfer, transfer_list);
 785                 return STATE_RUNNING;
 786         }
 787         return STATE_DONE;
 788 }
 789 
 790 /*
 791  * This DMA functionality is only compiled in if we have
 792  * access to the generic DMA devices/DMA engine.
 793  */
 794 #ifdef CONFIG_DMA_ENGINE
 795 static void unmap_free_dma_scatter(struct pl022 *pl022)
 796 {
 797         /* Unmap and free the SG tables */
 798         dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
 799                      pl022->sgt_tx.nents, DMA_TO_DEVICE);
 800         dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
 801                      pl022->sgt_rx.nents, DMA_FROM_DEVICE);
 802         sg_free_table(&pl022->sgt_rx);
 803         sg_free_table(&pl022->sgt_tx);
 804 }
 805 
 806 static void dma_callback(void *data)
 807 {
 808         struct pl022 *pl022 = data;
 809         struct spi_message *msg = pl022->cur_msg;
 810 
 811         BUG_ON(!pl022->sgt_rx.sgl);
 812 
 813 #ifdef VERBOSE_DEBUG
 814         /*
 815          * Optionally dump out buffers to inspect contents, this is
 816          * good if you want to convince yourself that the loopback
 817          * read/write contents are the same, when adopting to a new
 818          * DMA engine.
 819          */
 820         {
 821                 struct scatterlist *sg;
 822                 unsigned int i;
 823 
 824                 dma_sync_sg_for_cpu(&pl022->adev->dev,
 825                                     pl022->sgt_rx.sgl,
 826                                     pl022->sgt_rx.nents,
 827                                     DMA_FROM_DEVICE);
 828 
 829                 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
 830                         dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
 831                         print_hex_dump(KERN_ERR, "SPI RX: ",
 832                                        DUMP_PREFIX_OFFSET,
 833                                        16,
 834                                        1,
 835                                        sg_virt(sg),
 836                                        sg_dma_len(sg),
 837                                        1);
 838                 }
 839                 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
 840                         dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
 841                         print_hex_dump(KERN_ERR, "SPI TX: ",
 842                                        DUMP_PREFIX_OFFSET,
 843                                        16,
 844                                        1,
 845                                        sg_virt(sg),
 846                                        sg_dma_len(sg),
 847                                        1);
 848                 }
 849         }
 850 #endif
 851 
 852         unmap_free_dma_scatter(pl022);
 853 
 854         /* Update total bytes transferred */
 855         msg->actual_length += pl022->cur_transfer->len;
 856         /* Move to next transfer */
 857         msg->state = next_transfer(pl022);
 858         if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change)
 859                 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
 860         tasklet_schedule(&pl022->pump_transfers);
 861 }
 862 
 863 static void setup_dma_scatter(struct pl022 *pl022,
 864                               void *buffer,
 865                               unsigned int length,
 866                               struct sg_table *sgtab)
 867 {
 868         struct scatterlist *sg;
 869         int bytesleft = length;
 870         void *bufp = buffer;
 871         int mapbytes;
 872         int i;
 873 
 874         if (buffer) {
 875                 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
 876                         /*
 877                          * If there are less bytes left than what fits
 878                          * in the current page (plus page alignment offset)
 879                          * we just feed in this, else we stuff in as much
 880                          * as we can.
 881                          */
 882                         if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
 883                                 mapbytes = bytesleft;
 884                         else
 885                                 mapbytes = PAGE_SIZE - offset_in_page(bufp);
 886                         sg_set_page(sg, virt_to_page(bufp),
 887                                     mapbytes, offset_in_page(bufp));
 888                         bufp += mapbytes;
 889                         bytesleft -= mapbytes;
 890                         dev_dbg(&pl022->adev->dev,
 891                                 "set RX/TX target page @ %p, %d bytes, %d left\n",
 892                                 bufp, mapbytes, bytesleft);
 893                 }
 894         } else {
 895                 /* Map the dummy buffer on every page */
 896                 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
 897                         if (bytesleft < PAGE_SIZE)
 898                                 mapbytes = bytesleft;
 899                         else
 900                                 mapbytes = PAGE_SIZE;
 901                         sg_set_page(sg, virt_to_page(pl022->dummypage),
 902                                     mapbytes, 0);
 903                         bytesleft -= mapbytes;
 904                         dev_dbg(&pl022->adev->dev,
 905                                 "set RX/TX to dummy page %d bytes, %d left\n",
 906                                 mapbytes, bytesleft);
 907 
 908                 }
 909         }
 910         BUG_ON(bytesleft);
 911 }
 912 
 913 /**
 914  * configure_dma - configures the channels for the next transfer
 915  * @pl022: SSP driver's private data structure
 916  */
 917 static int configure_dma(struct pl022 *pl022)
 918 {
 919         struct dma_slave_config rx_conf = {
 920                 .src_addr = SSP_DR(pl022->phybase),
 921                 .direction = DMA_DEV_TO_MEM,
 922                 .device_fc = false,
 923         };
 924         struct dma_slave_config tx_conf = {
 925                 .dst_addr = SSP_DR(pl022->phybase),
 926                 .direction = DMA_MEM_TO_DEV,
 927                 .device_fc = false,
 928         };
 929         unsigned int pages;
 930         int ret;
 931         int rx_sglen, tx_sglen;
 932         struct dma_chan *rxchan = pl022->dma_rx_channel;
 933         struct dma_chan *txchan = pl022->dma_tx_channel;
 934         struct dma_async_tx_descriptor *rxdesc;
 935         struct dma_async_tx_descriptor *txdesc;
 936 
 937         /* Check that the channels are available */
 938         if (!rxchan || !txchan)
 939                 return -ENODEV;
 940 
 941         /*
 942          * If supplied, the DMA burstsize should equal the FIFO trigger level.
 943          * Notice that the DMA engine uses one-to-one mapping. Since we can
 944          * not trigger on 2 elements this needs explicit mapping rather than
 945          * calculation.
 946          */
 947         switch (pl022->rx_lev_trig) {
 948         case SSP_RX_1_OR_MORE_ELEM:
 949                 rx_conf.src_maxburst = 1;
 950                 break;
 951         case SSP_RX_4_OR_MORE_ELEM:
 952                 rx_conf.src_maxburst = 4;
 953                 break;
 954         case SSP_RX_8_OR_MORE_ELEM:
 955                 rx_conf.src_maxburst = 8;
 956                 break;
 957         case SSP_RX_16_OR_MORE_ELEM:
 958                 rx_conf.src_maxburst = 16;
 959                 break;
 960         case SSP_RX_32_OR_MORE_ELEM:
 961                 rx_conf.src_maxburst = 32;
 962                 break;
 963         default:
 964                 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
 965                 break;
 966         }
 967 
 968         switch (pl022->tx_lev_trig) {
 969         case SSP_TX_1_OR_MORE_EMPTY_LOC:
 970                 tx_conf.dst_maxburst = 1;
 971                 break;
 972         case SSP_TX_4_OR_MORE_EMPTY_LOC:
 973                 tx_conf.dst_maxburst = 4;
 974                 break;
 975         case SSP_TX_8_OR_MORE_EMPTY_LOC:
 976                 tx_conf.dst_maxburst = 8;
 977                 break;
 978         case SSP_TX_16_OR_MORE_EMPTY_LOC:
 979                 tx_conf.dst_maxburst = 16;
 980                 break;
 981         case SSP_TX_32_OR_MORE_EMPTY_LOC:
 982                 tx_conf.dst_maxburst = 32;
 983                 break;
 984         default:
 985                 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
 986                 break;
 987         }
 988 
 989         switch (pl022->read) {
 990         case READING_NULL:
 991                 /* Use the same as for writing */
 992                 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 993                 break;
 994         case READING_U8:
 995                 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 996                 break;
 997         case READING_U16:
 998                 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 999                 break;
1000         case READING_U32:
1001                 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1002                 break;
1003         }
1004 
1005         switch (pl022->write) {
1006         case WRITING_NULL:
1007                 /* Use the same as for reading */
1008                 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1009                 break;
1010         case WRITING_U8:
1011                 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1012                 break;
1013         case WRITING_U16:
1014                 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1015                 break;
1016         case WRITING_U32:
1017                 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1018                 break;
1019         }
1020 
1021         /* SPI pecularity: we need to read and write the same width */
1022         if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1023                 rx_conf.src_addr_width = tx_conf.dst_addr_width;
1024         if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1025                 tx_conf.dst_addr_width = rx_conf.src_addr_width;
1026         BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
1027 
1028         dmaengine_slave_config(rxchan, &rx_conf);
1029         dmaengine_slave_config(txchan, &tx_conf);
1030 
1031         /* Create sglists for the transfers */
1032         pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
1033         dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
1034 
1035         ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
1036         if (ret)
1037                 goto err_alloc_rx_sg;
1038 
1039         ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
1040         if (ret)
1041                 goto err_alloc_tx_sg;
1042 
1043         /* Fill in the scatterlists for the RX+TX buffers */
1044         setup_dma_scatter(pl022, pl022->rx,
1045                           pl022->cur_transfer->len, &pl022->sgt_rx);
1046         setup_dma_scatter(pl022, pl022->tx,
1047                           pl022->cur_transfer->len, &pl022->sgt_tx);
1048 
1049         /* Map DMA buffers */
1050         rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1051                            pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1052         if (!rx_sglen)
1053                 goto err_rx_sgmap;
1054 
1055         tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1056                            pl022->sgt_tx.nents, DMA_TO_DEVICE);
1057         if (!tx_sglen)
1058                 goto err_tx_sgmap;
1059 
1060         /* Send both scatterlists */
1061         rxdesc = dmaengine_prep_slave_sg(rxchan,
1062                                       pl022->sgt_rx.sgl,
1063                                       rx_sglen,
1064                                       DMA_DEV_TO_MEM,
1065                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1066         if (!rxdesc)
1067                 goto err_rxdesc;
1068 
1069         txdesc = dmaengine_prep_slave_sg(txchan,
1070                                       pl022->sgt_tx.sgl,
1071                                       tx_sglen,
1072                                       DMA_MEM_TO_DEV,
1073                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1074         if (!txdesc)
1075                 goto err_txdesc;
1076 
1077         /* Put the callback on the RX transfer only, that should finish last */
1078         rxdesc->callback = dma_callback;
1079         rxdesc->callback_param = pl022;
1080 
1081         /* Submit and fire RX and TX with TX last so we're ready to read! */
1082         dmaengine_submit(rxdesc);
1083         dmaengine_submit(txdesc);
1084         dma_async_issue_pending(rxchan);
1085         dma_async_issue_pending(txchan);
1086         pl022->dma_running = true;
1087 
1088         return 0;
1089 
1090 err_txdesc:
1091         dmaengine_terminate_all(txchan);
1092 err_rxdesc:
1093         dmaengine_terminate_all(rxchan);
1094         dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1095                      pl022->sgt_tx.nents, DMA_TO_DEVICE);
1096 err_tx_sgmap:
1097         dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1098                      pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1099 err_rx_sgmap:
1100         sg_free_table(&pl022->sgt_tx);
1101 err_alloc_tx_sg:
1102         sg_free_table(&pl022->sgt_rx);
1103 err_alloc_rx_sg:
1104         return -ENOMEM;
1105 }
1106 
1107 static int pl022_dma_probe(struct pl022 *pl022)
1108 {
1109         dma_cap_mask_t mask;
1110 
1111         /* Try to acquire a generic DMA engine slave channel */
1112         dma_cap_zero(mask);
1113         dma_cap_set(DMA_SLAVE, mask);
1114         /*
1115          * We need both RX and TX channels to do DMA, else do none
1116          * of them.
1117          */
1118         pl022->dma_rx_channel = dma_request_channel(mask,
1119                                             pl022->master_info->dma_filter,
1120                                             pl022->master_info->dma_rx_param);
1121         if (!pl022->dma_rx_channel) {
1122                 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
1123                 goto err_no_rxchan;
1124         }
1125 
1126         pl022->dma_tx_channel = dma_request_channel(mask,
1127                                             pl022->master_info->dma_filter,
1128                                             pl022->master_info->dma_tx_param);
1129         if (!pl022->dma_tx_channel) {
1130                 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
1131                 goto err_no_txchan;
1132         }
1133 
1134         pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1135         if (!pl022->dummypage)
1136                 goto err_no_dummypage;
1137 
1138         dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1139                  dma_chan_name(pl022->dma_rx_channel),
1140                  dma_chan_name(pl022->dma_tx_channel));
1141 
1142         return 0;
1143 
1144 err_no_dummypage:
1145         dma_release_channel(pl022->dma_tx_channel);
1146 err_no_txchan:
1147         dma_release_channel(pl022->dma_rx_channel);
1148         pl022->dma_rx_channel = NULL;
1149 err_no_rxchan:
1150         dev_err(&pl022->adev->dev,
1151                         "Failed to work in dma mode, work without dma!\n");
1152         return -ENODEV;
1153 }
1154 
1155 static int pl022_dma_autoprobe(struct pl022 *pl022)
1156 {
1157         struct device *dev = &pl022->adev->dev;
1158         struct dma_chan *chan;
1159         int err;
1160 
1161         /* automatically configure DMA channels from platform, normally using DT */
1162         chan = dma_request_slave_channel_reason(dev, "rx");
1163         if (IS_ERR(chan)) {
1164                 err = PTR_ERR(chan);
1165                 goto err_no_rxchan;
1166         }
1167 
1168         pl022->dma_rx_channel = chan;
1169 
1170         chan = dma_request_slave_channel_reason(dev, "tx");
1171         if (IS_ERR(chan)) {
1172                 err = PTR_ERR(chan);
1173                 goto err_no_txchan;
1174         }
1175 
1176         pl022->dma_tx_channel = chan;
1177 
1178         pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1179         if (!pl022->dummypage) {
1180                 err = -ENOMEM;
1181                 goto err_no_dummypage;
1182         }
1183 
1184         return 0;
1185 
1186 err_no_dummypage:
1187         dma_release_channel(pl022->dma_tx_channel);
1188         pl022->dma_tx_channel = NULL;
1189 err_no_txchan:
1190         dma_release_channel(pl022->dma_rx_channel);
1191         pl022->dma_rx_channel = NULL;
1192 err_no_rxchan:
1193         return err;
1194 }
1195                 
1196 static void terminate_dma(struct pl022 *pl022)
1197 {
1198         struct dma_chan *rxchan = pl022->dma_rx_channel;
1199         struct dma_chan *txchan = pl022->dma_tx_channel;
1200 
1201         dmaengine_terminate_all(rxchan);
1202         dmaengine_terminate_all(txchan);
1203         unmap_free_dma_scatter(pl022);
1204         pl022->dma_running = false;
1205 }
1206 
1207 static void pl022_dma_remove(struct pl022 *pl022)
1208 {
1209         if (pl022->dma_running)
1210                 terminate_dma(pl022);
1211         if (pl022->dma_tx_channel)
1212                 dma_release_channel(pl022->dma_tx_channel);
1213         if (pl022->dma_rx_channel)
1214                 dma_release_channel(pl022->dma_rx_channel);
1215         kfree(pl022->dummypage);
1216 }
1217 
1218 #else
1219 static inline int configure_dma(struct pl022 *pl022)
1220 {
1221         return -ENODEV;
1222 }
1223 
1224 static inline int pl022_dma_autoprobe(struct pl022 *pl022)
1225 {
1226         return 0;
1227 }
1228 
1229 static inline int pl022_dma_probe(struct pl022 *pl022)
1230 {
1231         return 0;
1232 }
1233 
1234 static inline void pl022_dma_remove(struct pl022 *pl022)
1235 {
1236 }
1237 #endif
1238 
1239 /**
1240  * pl022_interrupt_handler - Interrupt handler for SSP controller
1241  *
1242  * This function handles interrupts generated for an interrupt based transfer.
1243  * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1244  * current message's state as STATE_ERROR and schedule the tasklet
1245  * pump_transfers which will do the postprocessing of the current message by
1246  * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1247  * more data, and writes data in TX FIFO till it is not full. If we complete
1248  * the transfer we move to the next transfer and schedule the tasklet.
1249  */
1250 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1251 {
1252         struct pl022 *pl022 = dev_id;
1253         struct spi_message *msg = pl022->cur_msg;
1254         u16 irq_status = 0;
1255 
1256         if (unlikely(!msg)) {
1257                 dev_err(&pl022->adev->dev,
1258                         "bad message state in interrupt handler");
1259                 /* Never fail */
1260                 return IRQ_HANDLED;
1261         }
1262 
1263         /* Read the Interrupt Status Register */
1264         irq_status = readw(SSP_MIS(pl022->virtbase));
1265 
1266         if (unlikely(!irq_status))
1267                 return IRQ_NONE;
1268 
1269         /*
1270          * This handles the FIFO interrupts, the timeout
1271          * interrupts are flatly ignored, they cannot be
1272          * trusted.
1273          */
1274         if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1275                 /*
1276                  * Overrun interrupt - bail out since our Data has been
1277                  * corrupted
1278                  */
1279                 dev_err(&pl022->adev->dev, "FIFO overrun\n");
1280                 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1281                         dev_err(&pl022->adev->dev,
1282                                 "RXFIFO is full\n");
1283 
1284                 /*
1285                  * Disable and clear interrupts, disable SSP,
1286                  * mark message with bad status so it can be
1287                  * retried.
1288                  */
1289                 writew(DISABLE_ALL_INTERRUPTS,
1290                        SSP_IMSC(pl022->virtbase));
1291                 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1292                 writew((readw(SSP_CR1(pl022->virtbase)) &
1293                         (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1294                 msg->state = STATE_ERROR;
1295 
1296                 /* Schedule message queue handler */
1297                 tasklet_schedule(&pl022->pump_transfers);
1298                 return IRQ_HANDLED;
1299         }
1300 
1301         readwriter(pl022);
1302 
1303         if (pl022->tx == pl022->tx_end) {
1304                 /* Disable Transmit interrupt, enable receive interrupt */
1305                 writew((readw(SSP_IMSC(pl022->virtbase)) &
1306                        ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
1307                        SSP_IMSC(pl022->virtbase));
1308         }
1309 
1310         /*
1311          * Since all transactions must write as much as shall be read,
1312          * we can conclude the entire transaction once RX is complete.
1313          * At this point, all TX will always be finished.
1314          */
1315         if (pl022->rx >= pl022->rx_end) {
1316                 writew(DISABLE_ALL_INTERRUPTS,
1317                        SSP_IMSC(pl022->virtbase));
1318                 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1319                 if (unlikely(pl022->rx > pl022->rx_end)) {
1320                         dev_warn(&pl022->adev->dev, "read %u surplus "
1321                                  "bytes (did you request an odd "
1322                                  "number of bytes on a 16bit bus?)\n",
1323                                  (u32) (pl022->rx - pl022->rx_end));
1324                 }
1325                 /* Update total bytes transferred */
1326                 msg->actual_length += pl022->cur_transfer->len;
1327                 /* Move to next transfer */
1328                 msg->state = next_transfer(pl022);
1329                 if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change)
1330                         pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1331                 tasklet_schedule(&pl022->pump_transfers);
1332                 return IRQ_HANDLED;
1333         }
1334 
1335         return IRQ_HANDLED;
1336 }
1337 
1338 /**
1339  * This sets up the pointers to memory for the next message to
1340  * send out on the SPI bus.
1341  */
1342 static int set_up_next_transfer(struct pl022 *pl022,
1343                                 struct spi_transfer *transfer)
1344 {
1345         int residue;
1346 
1347         /* Sanity check the message for this bus width */
1348         residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1349         if (unlikely(residue != 0)) {
1350                 dev_err(&pl022->adev->dev,
1351                         "message of %u bytes to transmit but the current "
1352                         "chip bus has a data width of %u bytes!\n",
1353                         pl022->cur_transfer->len,
1354                         pl022->cur_chip->n_bytes);
1355                 dev_err(&pl022->adev->dev, "skipping this message\n");
1356                 return -EIO;
1357         }
1358         pl022->tx = (void *)transfer->tx_buf;
1359         pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1360         pl022->rx = (void *)transfer->rx_buf;
1361         pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1362         pl022->write =
1363             pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1364         pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1365         return 0;
1366 }
1367 
1368 /**
1369  * pump_transfers - Tasklet function which schedules next transfer
1370  * when running in interrupt or DMA transfer mode.
1371  * @data: SSP driver private data structure
1372  *
1373  */
1374 static void pump_transfers(unsigned long data)
1375 {
1376         struct pl022 *pl022 = (struct pl022 *) data;
1377         struct spi_message *message = NULL;
1378         struct spi_transfer *transfer = NULL;
1379         struct spi_transfer *previous = NULL;
1380 
1381         /* Get current state information */
1382         message = pl022->cur_msg;
1383         transfer = pl022->cur_transfer;
1384 
1385         /* Handle for abort */
1386         if (message->state == STATE_ERROR) {
1387                 message->status = -EIO;
1388                 giveback(pl022);
1389                 return;
1390         }
1391 
1392         /* Handle end of message */
1393         if (message->state == STATE_DONE) {
1394                 message->status = 0;
1395                 giveback(pl022);
1396                 return;
1397         }
1398 
1399         /* Delay if requested at end of transfer before CS change */
1400         if (message->state == STATE_RUNNING) {
1401                 previous = list_entry(transfer->transfer_list.prev,
1402                                         struct spi_transfer,
1403                                         transfer_list);
1404                 if (previous->delay_usecs)
1405                         /*
1406                          * FIXME: This runs in interrupt context.
1407                          * Is this really smart?
1408                          */
1409                         udelay(previous->delay_usecs);
1410 
1411                 /* Reselect chip select only if cs_change was requested */
1412                 if (previous->cs_change)
1413                         pl022_cs_control(pl022, SSP_CHIP_SELECT);
1414         } else {
1415                 /* STATE_START */
1416                 message->state = STATE_RUNNING;
1417         }
1418 
1419         if (set_up_next_transfer(pl022, transfer)) {
1420                 message->state = STATE_ERROR;
1421                 message->status = -EIO;
1422                 giveback(pl022);
1423                 return;
1424         }
1425         /* Flush the FIFOs and let's go! */
1426         flush(pl022);
1427 
1428         if (pl022->cur_chip->enable_dma) {
1429                 if (configure_dma(pl022)) {
1430                         dev_dbg(&pl022->adev->dev,
1431                                 "configuration of DMA failed, fall back to interrupt mode\n");
1432                         goto err_config_dma;
1433                 }
1434                 return;
1435         }
1436 
1437 err_config_dma:
1438         /* enable all interrupts except RX */
1439         writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
1440 }
1441 
1442 static void do_interrupt_dma_transfer(struct pl022 *pl022)
1443 {
1444         /*
1445          * Default is to enable all interrupts except RX -
1446          * this will be enabled once TX is complete
1447          */
1448         u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM);
1449 
1450         /* Enable target chip, if not already active */
1451         if (!pl022->next_msg_cs_active)
1452                 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1453 
1454         if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1455                 /* Error path */
1456                 pl022->cur_msg->state = STATE_ERROR;
1457                 pl022->cur_msg->status = -EIO;
1458                 giveback(pl022);
1459                 return;
1460         }
1461         /* If we're using DMA, set up DMA here */
1462         if (pl022->cur_chip->enable_dma) {
1463                 /* Configure DMA transfer */
1464                 if (configure_dma(pl022)) {
1465                         dev_dbg(&pl022->adev->dev,
1466                                 "configuration of DMA failed, fall back to interrupt mode\n");
1467                         goto err_config_dma;
1468                 }
1469                 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1470                 irqflags = DISABLE_ALL_INTERRUPTS;
1471         }
1472 err_config_dma:
1473         /* Enable SSP, turn on interrupts */
1474         writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1475                SSP_CR1(pl022->virtbase));
1476         writew(irqflags, SSP_IMSC(pl022->virtbase));
1477 }
1478 
1479 static void print_current_status(struct pl022 *pl022)
1480 {
1481         u32 read_cr0;
1482         u16 read_cr1, read_dmacr, read_sr;
1483 
1484         if (pl022->vendor->extended_cr)
1485                 read_cr0 = readl(SSP_CR0(pl022->virtbase));
1486         else
1487                 read_cr0 = readw(SSP_CR0(pl022->virtbase));
1488         read_cr1 = readw(SSP_CR1(pl022->virtbase));
1489         read_dmacr = readw(SSP_DMACR(pl022->virtbase));
1490         read_sr = readw(SSP_SR(pl022->virtbase));
1491 
1492         dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0);
1493         dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1);
1494         dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr);
1495         dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr);
1496         dev_warn(&pl022->adev->dev,
1497                         "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n",
1498                         pl022->exp_fifo_level,
1499                         pl022->vendor->fifodepth);
1500 
1501 }
1502 
1503 static void do_polling_transfer(struct pl022 *pl022)
1504 {
1505         struct spi_message *message = NULL;
1506         struct spi_transfer *transfer = NULL;
1507         struct spi_transfer *previous = NULL;
1508         unsigned long time, timeout;
1509 
1510         message = pl022->cur_msg;
1511 
1512         while (message->state != STATE_DONE) {
1513                 /* Handle for abort */
1514                 if (message->state == STATE_ERROR)
1515                         break;
1516                 transfer = pl022->cur_transfer;
1517 
1518                 /* Delay if requested at end of transfer */
1519                 if (message->state == STATE_RUNNING) {
1520                         previous =
1521                             list_entry(transfer->transfer_list.prev,
1522                                        struct spi_transfer, transfer_list);
1523                         if (previous->delay_usecs)
1524                                 udelay(previous->delay_usecs);
1525                         if (previous->cs_change)
1526                                 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1527                 } else {
1528                         /* STATE_START */
1529                         message->state = STATE_RUNNING;
1530                         if (!pl022->next_msg_cs_active)
1531                                 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1532                 }
1533 
1534                 /* Configuration Changing Per Transfer */
1535                 if (set_up_next_transfer(pl022, transfer)) {
1536                         /* Error path */
1537                         message->state = STATE_ERROR;
1538                         break;
1539                 }
1540                 /* Flush FIFOs and enable SSP */
1541                 flush(pl022);
1542                 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1543                        SSP_CR1(pl022->virtbase));
1544 
1545                 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1546 
1547                 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1548                 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1549                         time = jiffies;
1550                         readwriter(pl022);
1551                         if (time_after(time, timeout)) {
1552                                 dev_warn(&pl022->adev->dev,
1553                                 "%s: timeout!\n", __func__);
1554                                 message->state = STATE_TIMEOUT;
1555                                 print_current_status(pl022);
1556                                 goto out;
1557                         }
1558                         cpu_relax();
1559                 }
1560 
1561                 /* Update total byte transferred */
1562                 message->actual_length += pl022->cur_transfer->len;
1563                 /* Move to next transfer */
1564                 message->state = next_transfer(pl022);
1565                 if (message->state != STATE_DONE
1566                     && pl022->cur_transfer->cs_change)
1567                         pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1568         }
1569 out:
1570         /* Handle end of message */
1571         if (message->state == STATE_DONE)
1572                 message->status = 0;
1573         else if (message->state == STATE_TIMEOUT)
1574                 message->status = -EAGAIN;
1575         else
1576                 message->status = -EIO;
1577 
1578         giveback(pl022);
1579         return;
1580 }
1581 
1582 static int pl022_transfer_one_message(struct spi_master *master,
1583                                       struct spi_message *msg)
1584 {
1585         struct pl022 *pl022 = spi_master_get_devdata(master);
1586 
1587         /* Initial message state */
1588         pl022->cur_msg = msg;
1589         msg->state = STATE_START;
1590 
1591         pl022->cur_transfer = list_entry(msg->transfers.next,
1592                                          struct spi_transfer, transfer_list);
1593 
1594         /* Setup the SPI using the per chip configuration */
1595         pl022->cur_chip = spi_get_ctldata(msg->spi);
1596         pl022->cur_cs = pl022->chipselects[msg->spi->chip_select];
1597 
1598         restore_state(pl022);
1599         flush(pl022);
1600 
1601         if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1602                 do_polling_transfer(pl022);
1603         else
1604                 do_interrupt_dma_transfer(pl022);
1605 
1606         return 0;
1607 }
1608 
1609 static int pl022_unprepare_transfer_hardware(struct spi_master *master)
1610 {
1611         struct pl022 *pl022 = spi_master_get_devdata(master);
1612 
1613         /* nothing more to do - disable spi/ssp and power off */
1614         writew((readw(SSP_CR1(pl022->virtbase)) &
1615                 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1616 
1617         return 0;
1618 }
1619 
1620 static int verify_controller_parameters(struct pl022 *pl022,
1621                                 struct pl022_config_chip const *chip_info)
1622 {
1623         if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1624             || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1625                 dev_err(&pl022->adev->dev,
1626                         "interface is configured incorrectly\n");
1627                 return -EINVAL;
1628         }
1629         if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1630             (!pl022->vendor->unidir)) {
1631                 dev_err(&pl022->adev->dev,
1632                         "unidirectional mode not supported in this "
1633                         "hardware version\n");
1634                 return -EINVAL;
1635         }
1636         if ((chip_info->hierarchy != SSP_MASTER)
1637             && (chip_info->hierarchy != SSP_SLAVE)) {
1638                 dev_err(&pl022->adev->dev,
1639                         "hierarchy is configured incorrectly\n");
1640                 return -EINVAL;
1641         }
1642         if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1643             && (chip_info->com_mode != DMA_TRANSFER)
1644             && (chip_info->com_mode != POLLING_TRANSFER)) {
1645                 dev_err(&pl022->adev->dev,
1646                         "Communication mode is configured incorrectly\n");
1647                 return -EINVAL;
1648         }
1649         switch (chip_info->rx_lev_trig) {
1650         case SSP_RX_1_OR_MORE_ELEM:
1651         case SSP_RX_4_OR_MORE_ELEM:
1652         case SSP_RX_8_OR_MORE_ELEM:
1653                 /* These are always OK, all variants can handle this */
1654                 break;
1655         case SSP_RX_16_OR_MORE_ELEM:
1656                 if (pl022->vendor->fifodepth < 16) {
1657                         dev_err(&pl022->adev->dev,
1658                         "RX FIFO Trigger Level is configured incorrectly\n");
1659                         return -EINVAL;
1660                 }
1661                 break;
1662         case SSP_RX_32_OR_MORE_ELEM:
1663                 if (pl022->vendor->fifodepth < 32) {
1664                         dev_err(&pl022->adev->dev,
1665                         "RX FIFO Trigger Level is configured incorrectly\n");
1666                         return -EINVAL;
1667                 }
1668                 break;
1669         default:
1670                 dev_err(&pl022->adev->dev,
1671                         "RX FIFO Trigger Level is configured incorrectly\n");
1672                 return -EINVAL;
1673         }
1674         switch (chip_info->tx_lev_trig) {
1675         case SSP_TX_1_OR_MORE_EMPTY_LOC:
1676         case SSP_TX_4_OR_MORE_EMPTY_LOC:
1677         case SSP_TX_8_OR_MORE_EMPTY_LOC:
1678                 /* These are always OK, all variants can handle this */
1679                 break;
1680         case SSP_TX_16_OR_MORE_EMPTY_LOC:
1681                 if (pl022->vendor->fifodepth < 16) {
1682                         dev_err(&pl022->adev->dev,
1683                         "TX FIFO Trigger Level is configured incorrectly\n");
1684                         return -EINVAL;
1685                 }
1686                 break;
1687         case SSP_TX_32_OR_MORE_EMPTY_LOC:
1688                 if (pl022->vendor->fifodepth < 32) {
1689                         dev_err(&pl022->adev->dev,
1690                         "TX FIFO Trigger Level is configured incorrectly\n");
1691                         return -EINVAL;
1692                 }
1693                 break;
1694         default:
1695                 dev_err(&pl022->adev->dev,
1696                         "TX FIFO Trigger Level is configured incorrectly\n");
1697                 return -EINVAL;
1698         }
1699         if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1700                 if ((chip_info->ctrl_len < SSP_BITS_4)
1701                     || (chip_info->ctrl_len > SSP_BITS_32)) {
1702                         dev_err(&pl022->adev->dev,
1703                                 "CTRL LEN is configured incorrectly\n");
1704                         return -EINVAL;
1705                 }
1706                 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1707                     && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1708                         dev_err(&pl022->adev->dev,
1709                                 "Wait State is configured incorrectly\n");
1710                         return -EINVAL;
1711                 }
1712                 /* Half duplex is only available in the ST Micro version */
1713                 if (pl022->vendor->extended_cr) {
1714                         if ((chip_info->duplex !=
1715                              SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1716                             && (chip_info->duplex !=
1717                                 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
1718                                 dev_err(&pl022->adev->dev,
1719                                         "Microwire duplex mode is configured incorrectly\n");
1720                                 return -EINVAL;
1721                         }
1722                 } else {
1723                         if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1724                                 dev_err(&pl022->adev->dev,
1725                                         "Microwire half duplex mode requested,"
1726                                         " but this is only available in the"
1727                                         " ST version of PL022\n");
1728                         return -EINVAL;
1729                 }
1730         }
1731         return 0;
1732 }
1733 
1734 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
1735 {
1736         return rate / (cpsdvsr * (1 + scr));
1737 }
1738 
1739 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1740                                     ssp_clock_params * clk_freq)
1741 {
1742         /* Lets calculate the frequency parameters */
1743         u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
1744         u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
1745                 best_scr = 0, tmp, found = 0;
1746 
1747         rate = clk_get_rate(pl022->clk);
1748         /* cpsdvscr = 2 & scr 0 */
1749         max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
1750         /* cpsdvsr = 254 & scr = 255 */
1751         min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
1752 
1753         if (freq > max_tclk)
1754                 dev_warn(&pl022->adev->dev,
1755                         "Max speed that can be programmed is %d Hz, you requested %d\n",
1756                         max_tclk, freq);
1757 
1758         if (freq < min_tclk) {
1759                 dev_err(&pl022->adev->dev,
1760                         "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
1761                         freq, min_tclk);
1762                 return -EINVAL;
1763         }
1764 
1765         /*
1766          * best_freq will give closest possible available rate (<= requested
1767          * freq) for all values of scr & cpsdvsr.
1768          */
1769         while ((cpsdvsr <= CPSDVR_MAX) && !found) {
1770                 while (scr <= SCR_MAX) {
1771                         tmp = spi_rate(rate, cpsdvsr, scr);
1772 
1773                         if (tmp > freq) {
1774                                 /* we need lower freq */
1775                                 scr++;
1776                                 continue;
1777                         }
1778 
1779                         /*
1780                          * If found exact value, mark found and break.
1781                          * If found more closer value, update and break.
1782                          */
1783                         if (tmp > best_freq) {
1784                                 best_freq = tmp;
1785                                 best_cpsdvsr = cpsdvsr;
1786                                 best_scr = scr;
1787 
1788                                 if (tmp == freq)
1789                                         found = 1;
1790                         }
1791                         /*
1792                          * increased scr will give lower rates, which are not
1793                          * required
1794                          */
1795                         break;
1796                 }
1797                 cpsdvsr += 2;
1798                 scr = SCR_MIN;
1799         }
1800 
1801         WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1802                         freq);
1803 
1804         clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
1805         clk_freq->scr = (u8) (best_scr & 0xFF);
1806         dev_dbg(&pl022->adev->dev,
1807                 "SSP Target Frequency is: %u, Effective Frequency is %u\n",
1808                 freq, best_freq);
1809         dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1810                 clk_freq->cpsdvsr, clk_freq->scr);
1811 
1812         return 0;
1813 }
1814 
1815 /*
1816  * A piece of default chip info unless the platform
1817  * supplies it.
1818  */
1819 static const struct pl022_config_chip pl022_default_chip_info = {
1820         .com_mode = POLLING_TRANSFER,
1821         .iface = SSP_INTERFACE_MOTOROLA_SPI,
1822         .hierarchy = SSP_SLAVE,
1823         .slave_tx_disable = DO_NOT_DRIVE_TX,
1824         .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1825         .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1826         .ctrl_len = SSP_BITS_8,
1827         .wait_state = SSP_MWIRE_WAIT_ZERO,
1828         .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1829         .cs_control = null_cs_control,
1830 };
1831 
1832 /**
1833  * pl022_setup - setup function registered to SPI master framework
1834  * @spi: spi device which is requesting setup
1835  *
1836  * This function is registered to the SPI framework for this SPI master
1837  * controller. If it is the first time when setup is called by this device,
1838  * this function will initialize the runtime state for this chip and save
1839  * the same in the device structure. Else it will update the runtime info
1840  * with the updated chip info. Nothing is really being written to the
1841  * controller hardware here, that is not done until the actual transfer
1842  * commence.
1843  */
1844 static int pl022_setup(struct spi_device *spi)
1845 {
1846         struct pl022_config_chip const *chip_info;
1847         struct pl022_config_chip chip_info_dt;
1848         struct chip_data *chip;
1849         struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
1850         int status = 0;
1851         struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1852         unsigned int bits = spi->bits_per_word;
1853         u32 tmp;
1854         struct device_node *np = spi->dev.of_node;
1855 
1856         if (!spi->max_speed_hz)
1857                 return -EINVAL;
1858 
1859         /* Get controller_state if one is supplied */
1860         chip = spi_get_ctldata(spi);
1861 
1862         if (chip == NULL) {
1863                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1864                 if (!chip)
1865                         return -ENOMEM;
1866                 dev_dbg(&spi->dev,
1867                         "allocated memory for controller's runtime state\n");
1868         }
1869 
1870         /* Get controller data if one is supplied */
1871         chip_info = spi->controller_data;
1872 
1873         if (chip_info == NULL) {
1874                 if (np) {
1875                         chip_info_dt = pl022_default_chip_info;
1876 
1877                         chip_info_dt.hierarchy = SSP_MASTER;
1878                         of_property_read_u32(np, "pl022,interface",
1879                                 &chip_info_dt.iface);
1880                         of_property_read_u32(np, "pl022,com-mode",
1881                                 &chip_info_dt.com_mode);
1882                         of_property_read_u32(np, "pl022,rx-level-trig",
1883                                 &chip_info_dt.rx_lev_trig);
1884                         of_property_read_u32(np, "pl022,tx-level-trig",
1885                                 &chip_info_dt.tx_lev_trig);
1886                         of_property_read_u32(np, "pl022,ctrl-len",
1887                                 &chip_info_dt.ctrl_len);
1888                         of_property_read_u32(np, "pl022,wait-state",
1889                                 &chip_info_dt.wait_state);
1890                         of_property_read_u32(np, "pl022,duplex",
1891                                 &chip_info_dt.duplex);
1892 
1893                         chip_info = &chip_info_dt;
1894                 } else {
1895                         chip_info = &pl022_default_chip_info;
1896                         /* spi_board_info.controller_data not is supplied */
1897                         dev_dbg(&spi->dev,
1898                                 "using default controller_data settings\n");
1899                 }
1900         } else
1901                 dev_dbg(&spi->dev,
1902                         "using user supplied controller_data settings\n");
1903 
1904         /*
1905          * We can override with custom divisors, else we use the board
1906          * frequency setting
1907          */
1908         if ((0 == chip_info->clk_freq.cpsdvsr)
1909             && (0 == chip_info->clk_freq.scr)) {
1910                 status = calculate_effective_freq(pl022,
1911                                                   spi->max_speed_hz,
1912                                                   &clk_freq);
1913                 if (status < 0)
1914                         goto err_config_params;
1915         } else {
1916                 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1917                 if ((clk_freq.cpsdvsr % 2) != 0)
1918                         clk_freq.cpsdvsr =
1919                                 clk_freq.cpsdvsr - 1;
1920         }
1921         if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1922             || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1923                 status = -EINVAL;
1924                 dev_err(&spi->dev,
1925                         "cpsdvsr is configured incorrectly\n");
1926                 goto err_config_params;
1927         }
1928 
1929         status = verify_controller_parameters(pl022, chip_info);
1930         if (status) {
1931                 dev_err(&spi->dev, "controller data is incorrect");
1932                 goto err_config_params;
1933         }
1934 
1935         pl022->rx_lev_trig = chip_info->rx_lev_trig;
1936         pl022->tx_lev_trig = chip_info->tx_lev_trig;
1937 
1938         /* Now set controller state based on controller data */
1939         chip->xfer_type = chip_info->com_mode;
1940         if (!chip_info->cs_control) {
1941                 chip->cs_control = null_cs_control;
1942                 if (!gpio_is_valid(pl022->chipselects[spi->chip_select]))
1943                         dev_warn(&spi->dev,
1944                                  "invalid chip select\n");
1945         } else
1946                 chip->cs_control = chip_info->cs_control;
1947 
1948         /* Check bits per word with vendor specific range */
1949         if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
1950                 status = -ENOTSUPP;
1951                 dev_err(&spi->dev, "illegal data size for this controller!\n");
1952                 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
1953                                 pl022->vendor->max_bpw);
1954                 goto err_config_params;
1955         } else if (bits <= 8) {
1956                 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
1957                 chip->n_bytes = 1;
1958                 chip->read = READING_U8;
1959                 chip->write = WRITING_U8;
1960         } else if (bits <= 16) {
1961                 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1962                 chip->n_bytes = 2;
1963                 chip->read = READING_U16;
1964                 chip->write = WRITING_U16;
1965         } else {
1966                 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1967                 chip->n_bytes = 4;
1968                 chip->read = READING_U32;
1969                 chip->write = WRITING_U32;
1970         }
1971 
1972         /* Now Initialize all register settings required for this chip */
1973         chip->cr0 = 0;
1974         chip->cr1 = 0;
1975         chip->dmacr = 0;
1976         chip->cpsr = 0;
1977         if ((chip_info->com_mode == DMA_TRANSFER)
1978             && ((pl022->master_info)->enable_dma)) {
1979                 chip->enable_dma = true;
1980                 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
1981                 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1982                                SSP_DMACR_MASK_RXDMAE, 0);
1983                 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1984                                SSP_DMACR_MASK_TXDMAE, 1);
1985         } else {
1986                 chip->enable_dma = false;
1987                 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1988                 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1989                                SSP_DMACR_MASK_RXDMAE, 0);
1990                 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1991                                SSP_DMACR_MASK_TXDMAE, 1);
1992         }
1993 
1994         chip->cpsr = clk_freq.cpsdvsr;
1995 
1996         /* Special setup for the ST micro extended control registers */
1997         if (pl022->vendor->extended_cr) {
1998                 u32 etx;
1999 
2000                 if (pl022->vendor->pl023) {
2001                         /* These bits are only in the PL023 */
2002                         SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
2003                                        SSP_CR1_MASK_FBCLKDEL_ST, 13);
2004                 } else {
2005                         /* These bits are in the PL022 but not PL023 */
2006                         SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
2007                                        SSP_CR0_MASK_HALFDUP_ST, 5);
2008                         SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
2009                                        SSP_CR0_MASK_CSS_ST, 16);
2010                         SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2011                                        SSP_CR0_MASK_FRF_ST, 21);
2012                         SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
2013                                        SSP_CR1_MASK_MWAIT_ST, 6);
2014                 }
2015                 SSP_WRITE_BITS(chip->cr0, bits - 1,
2016                                SSP_CR0_MASK_DSS_ST, 0);
2017 
2018                 if (spi->mode & SPI_LSB_FIRST) {
2019                         tmp = SSP_RX_LSB;
2020                         etx = SSP_TX_LSB;
2021                 } else {
2022                         tmp = SSP_RX_MSB;
2023                         etx = SSP_TX_MSB;
2024                 }
2025                 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
2026                 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
2027                 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
2028                                SSP_CR1_MASK_RXIFLSEL_ST, 7);
2029                 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
2030                                SSP_CR1_MASK_TXIFLSEL_ST, 10);
2031         } else {
2032                 SSP_WRITE_BITS(chip->cr0, bits - 1,
2033                                SSP_CR0_MASK_DSS, 0);
2034                 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2035                                SSP_CR0_MASK_FRF, 4);
2036         }
2037 
2038         /* Stuff that is common for all versions */
2039         if (spi->mode & SPI_CPOL)
2040                 tmp = SSP_CLK_POL_IDLE_HIGH;
2041         else
2042                 tmp = SSP_CLK_POL_IDLE_LOW;
2043         SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
2044 
2045         if (spi->mode & SPI_CPHA)
2046                 tmp = SSP_CLK_SECOND_EDGE;
2047         else
2048                 tmp = SSP_CLK_FIRST_EDGE;
2049         SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
2050 
2051         SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
2052         /* Loopback is available on all versions except PL023 */
2053         if (pl022->vendor->loopback) {
2054                 if (spi->mode & SPI_LOOP)
2055                         tmp = LOOPBACK_ENABLED;
2056                 else
2057                         tmp = LOOPBACK_DISABLED;
2058                 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2059         }
2060         SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2061         SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2062         SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
2063                 3);
2064 
2065         /* Save controller_state */
2066         spi_set_ctldata(spi, chip);
2067         return status;
2068  err_config_params:
2069         spi_set_ctldata(spi, NULL);
2070         kfree(chip);
2071         return status;
2072 }
2073 
2074 /**
2075  * pl022_cleanup - cleanup function registered to SPI master framework
2076  * @spi: spi device which is requesting cleanup
2077  *
2078  * This function is registered to the SPI framework for this SPI master
2079  * controller. It will free the runtime state of chip.
2080  */
2081 static void pl022_cleanup(struct spi_device *spi)
2082 {
2083         struct chip_data *chip = spi_get_ctldata(spi);
2084 
2085         spi_set_ctldata(spi, NULL);
2086         kfree(chip);
2087 }
2088 
2089 static struct pl022_ssp_controller *
2090 pl022_platform_data_dt_get(struct device *dev)
2091 {
2092         struct device_node *np = dev->of_node;
2093         struct pl022_ssp_controller *pd;
2094         u32 tmp = 0;
2095 
2096         if (!np) {
2097                 dev_err(dev, "no dt node defined\n");
2098                 return NULL;
2099         }
2100 
2101         pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL);
2102         if (!pd)
2103                 return NULL;
2104 
2105         pd->bus_id = -1;
2106         pd->enable_dma = 1;
2107         of_property_read_u32(np, "num-cs", &tmp);
2108         pd->num_chipselect = tmp;
2109         of_property_read_u32(np, "pl022,autosuspend-delay",
2110                              &pd->autosuspend_delay);
2111         pd->rt = of_property_read_bool(np, "pl022,rt");
2112 
2113         return pd;
2114 }
2115 
2116 static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2117 {
2118         struct device *dev = &adev->dev;
2119         struct pl022_ssp_controller *platform_info =
2120                         dev_get_platdata(&adev->dev);
2121         struct spi_master *master;
2122         struct pl022 *pl022 = NULL;     /*Data for this driver */
2123         struct device_node *np = adev->dev.of_node;
2124         int status = 0, i, num_cs;
2125 
2126         dev_info(&adev->dev,
2127                  "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
2128         if (!platform_info && IS_ENABLED(CONFIG_OF))
2129                 platform_info = pl022_platform_data_dt_get(dev);
2130 
2131         if (!platform_info) {
2132                 dev_err(dev, "probe: no platform data defined\n");
2133                 return -ENODEV;
2134         }
2135 
2136         if (platform_info->num_chipselect) {
2137                 num_cs = platform_info->num_chipselect;
2138         } else {
2139                 dev_err(dev, "probe: no chip select defined\n");
2140                 return -ENODEV;
2141         }
2142 
2143         /* Allocate master with space for data */
2144         master = spi_alloc_master(dev, sizeof(struct pl022));
2145         if (master == NULL) {
2146                 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
2147                 return -ENOMEM;
2148         }
2149 
2150         pl022 = spi_master_get_devdata(master);
2151         pl022->master = master;
2152         pl022->master_info = platform_info;
2153         pl022->adev = adev;
2154         pl022->vendor = id->data;
2155         pl022->chipselects = devm_kcalloc(dev, num_cs, sizeof(int),
2156                                           GFP_KERNEL);
2157         if (!pl022->chipselects) {
2158                 status = -ENOMEM;
2159                 goto err_no_mem;
2160         }
2161 
2162         /*
2163          * Bus Number Which has been Assigned to this SSP controller
2164          * on this board
2165          */
2166         master->bus_num = platform_info->bus_id;
2167         master->num_chipselect = num_cs;
2168         master->cleanup = pl022_cleanup;
2169         master->setup = pl022_setup;
2170         master->auto_runtime_pm = true;
2171         master->transfer_one_message = pl022_transfer_one_message;
2172         master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
2173         master->rt = platform_info->rt;
2174         master->dev.of_node = dev->of_node;
2175 
2176         if (platform_info->num_chipselect && platform_info->chipselects) {
2177                 for (i = 0; i < num_cs; i++)
2178                         pl022->chipselects[i] = platform_info->chipselects[i];
2179         } else if (pl022->vendor->internal_cs_ctrl) {
2180                 for (i = 0; i < num_cs; i++)
2181                         pl022->chipselects[i] = i;
2182         } else if (IS_ENABLED(CONFIG_OF)) {
2183                 for (i = 0; i < num_cs; i++) {
2184                         int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
2185 
2186                         if (cs_gpio == -EPROBE_DEFER) {
2187                                 status = -EPROBE_DEFER;
2188                                 goto err_no_gpio;
2189                         }
2190 
2191                         pl022->chipselects[i] = cs_gpio;
2192 
2193                         if (gpio_is_valid(cs_gpio)) {
2194                                 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022"))
2195                                         dev_err(&adev->dev,
2196                                                 "could not request %d gpio\n",
2197                                                 cs_gpio);
2198                                 else if (gpio_direction_output(cs_gpio, 1))
2199                                         dev_err(&adev->dev,
2200                                                 "could not set gpio %d as output\n",
2201                                                 cs_gpio);
2202                         }
2203                 }
2204         }
2205 
2206         /*
2207          * Supports mode 0-3, loopback, and active low CS. Transfers are
2208          * always MS bit first on the original pl022.
2209          */
2210         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2211         if (pl022->vendor->extended_cr)
2212                 master->mode_bits |= SPI_LSB_FIRST;
2213 
2214         dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2215 
2216         status = amba_request_regions(adev, NULL);
2217         if (status)
2218                 goto err_no_ioregion;
2219 
2220         pl022->phybase = adev->res.start;
2221         pl022->virtbase = devm_ioremap(dev, adev->res.start,
2222                                        resource_size(&adev->res));
2223         if (pl022->virtbase == NULL) {
2224                 status = -ENOMEM;
2225                 goto err_no_ioremap;
2226         }
2227         dev_info(&adev->dev, "mapped registers from %pa to %p\n",
2228                 &adev->res.start, pl022->virtbase);
2229 
2230         pl022->clk = devm_clk_get(&adev->dev, NULL);
2231         if (IS_ERR(pl022->clk)) {
2232                 status = PTR_ERR(pl022->clk);
2233                 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2234                 goto err_no_clk;
2235         }
2236 
2237         status = clk_prepare_enable(pl022->clk);
2238         if (status) {
2239                 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
2240                 goto err_no_clk_en;
2241         }
2242 
2243         /* Initialize transfer pump */
2244         tasklet_init(&pl022->pump_transfers, pump_transfers,
2245                      (unsigned long)pl022);
2246 
2247         /* Disable SSP */
2248         writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2249                SSP_CR1(pl022->virtbase));
2250         load_ssp_default_config(pl022);
2251 
2252         status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler,
2253                                   0, "pl022", pl022);
2254         if (status < 0) {
2255                 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2256                 goto err_no_irq;
2257         }
2258 
2259         /* Get DMA channels, try autoconfiguration first */
2260         status = pl022_dma_autoprobe(pl022);
2261         if (status == -EPROBE_DEFER) {
2262                 dev_dbg(dev, "deferring probe to get DMA channel\n");
2263                 goto err_no_irq;
2264         }
2265 
2266         /* If that failed, use channels from platform_info */
2267         if (status == 0)
2268                 platform_info->enable_dma = 1;
2269         else if (platform_info->enable_dma) {
2270                 status = pl022_dma_probe(pl022);
2271                 if (status != 0)
2272                         platform_info->enable_dma = 0;
2273         }
2274 
2275         /* Register with the SPI framework */
2276         amba_set_drvdata(adev, pl022);
2277         status = devm_spi_register_master(&adev->dev, master);
2278         if (status != 0) {
2279                 dev_err(&adev->dev,
2280                         "probe - problem registering spi master\n");
2281                 goto err_spi_register;
2282         }
2283         dev_dbg(dev, "probe succeeded\n");
2284 
2285         /* let runtime pm put suspend */
2286         if (platform_info->autosuspend_delay > 0) {
2287                 dev_info(&adev->dev,
2288                         "will use autosuspend for runtime pm, delay %dms\n",
2289                         platform_info->autosuspend_delay);
2290                 pm_runtime_set_autosuspend_delay(dev,
2291                         platform_info->autosuspend_delay);
2292                 pm_runtime_use_autosuspend(dev);
2293         }
2294         pm_runtime_put(dev);
2295 
2296         return 0;
2297 
2298  err_spi_register:
2299         if (platform_info->enable_dma)
2300                 pl022_dma_remove(pl022);
2301  err_no_irq:
2302         clk_disable_unprepare(pl022->clk);
2303  err_no_clk_en:
2304  err_no_clk:
2305  err_no_ioremap:
2306         amba_release_regions(adev);
2307  err_no_ioregion:
2308  err_no_gpio:
2309  err_no_mem:
2310         spi_master_put(master);
2311         return status;
2312 }
2313 
2314 static int
2315 pl022_remove(struct amba_device *adev)
2316 {
2317         struct pl022 *pl022 = amba_get_drvdata(adev);
2318 
2319         if (!pl022)
2320                 return 0;
2321 
2322         /*
2323          * undo pm_runtime_put() in probe.  I assume that we're not
2324          * accessing the primecell here.
2325          */
2326         pm_runtime_get_noresume(&adev->dev);
2327 
2328         load_ssp_default_config(pl022);
2329         if (pl022->master_info->enable_dma)
2330                 pl022_dma_remove(pl022);
2331 
2332         clk_disable_unprepare(pl022->clk);
2333         amba_release_regions(adev);
2334         tasklet_disable(&pl022->pump_transfers);
2335         return 0;
2336 }
2337 
2338 #ifdef CONFIG_PM_SLEEP
2339 static int pl022_suspend(struct device *dev)
2340 {
2341         struct pl022 *pl022 = dev_get_drvdata(dev);
2342         int ret;
2343 
2344         ret = spi_master_suspend(pl022->master);
2345         if (ret)
2346                 return ret;
2347 
2348         ret = pm_runtime_force_suspend(dev);
2349         if (ret) {
2350                 spi_master_resume(pl022->master);
2351                 return ret;
2352         }
2353 
2354         pinctrl_pm_select_sleep_state(dev);
2355 
2356         dev_dbg(dev, "suspended\n");
2357         return 0;
2358 }
2359 
2360 static int pl022_resume(struct device *dev)
2361 {
2362         struct pl022 *pl022 = dev_get_drvdata(dev);
2363         int ret;
2364 
2365         ret = pm_runtime_force_resume(dev);
2366         if (ret)
2367                 dev_err(dev, "problem resuming\n");
2368 
2369         /* Start the queue running */
2370         ret = spi_master_resume(pl022->master);
2371         if (!ret)
2372                 dev_dbg(dev, "resumed\n");
2373 
2374         return ret;
2375 }
2376 #endif
2377 
2378 #ifdef CONFIG_PM
2379 static int pl022_runtime_suspend(struct device *dev)
2380 {
2381         struct pl022 *pl022 = dev_get_drvdata(dev);
2382 
2383         clk_disable_unprepare(pl022->clk);
2384         pinctrl_pm_select_idle_state(dev);
2385 
2386         return 0;
2387 }
2388 
2389 static int pl022_runtime_resume(struct device *dev)
2390 {
2391         struct pl022 *pl022 = dev_get_drvdata(dev);
2392 
2393         pinctrl_pm_select_default_state(dev);
2394         clk_prepare_enable(pl022->clk);
2395 
2396         return 0;
2397 }
2398 #endif
2399 
2400 static const struct dev_pm_ops pl022_dev_pm_ops = {
2401         SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
2402         SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
2403 };
2404 
2405 static struct vendor_data vendor_arm = {
2406         .fifodepth = 8,
2407         .max_bpw = 16,
2408         .unidir = false,
2409         .extended_cr = false,
2410         .pl023 = false,
2411         .loopback = true,
2412         .internal_cs_ctrl = false,
2413 };
2414 
2415 static struct vendor_data vendor_st = {
2416         .fifodepth = 32,
2417         .max_bpw = 32,
2418         .unidir = false,
2419         .extended_cr = true,
2420         .pl023 = false,
2421         .loopback = true,
2422         .internal_cs_ctrl = false,
2423 };
2424 
2425 static struct vendor_data vendor_st_pl023 = {
2426         .fifodepth = 32,
2427         .max_bpw = 32,
2428         .unidir = false,
2429         .extended_cr = true,
2430         .pl023 = true,
2431         .loopback = false,
2432         .internal_cs_ctrl = false,
2433 };
2434 
2435 static struct vendor_data vendor_lsi = {
2436         .fifodepth = 8,
2437         .max_bpw = 16,
2438         .unidir = false,
2439         .extended_cr = false,
2440         .pl023 = false,
2441         .loopback = true,
2442         .internal_cs_ctrl = true,
2443 };
2444 
2445 static const struct amba_id pl022_ids[] = {
2446         {
2447                 /*
2448                  * ARM PL022 variant, this has a 16bit wide
2449                  * and 8 locations deep TX/RX FIFO
2450                  */
2451                 .id     = 0x00041022,
2452                 .mask   = 0x000fffff,
2453                 .data   = &vendor_arm,
2454         },
2455         {
2456                 /*
2457                  * ST Micro derivative, this has 32bit wide
2458                  * and 32 locations deep TX/RX FIFO
2459                  */
2460                 .id     = 0x01080022,
2461                 .mask   = 0xffffffff,
2462                 .data   = &vendor_st,
2463         },
2464         {
2465                 /*
2466                  * ST-Ericsson derivative "PL023" (this is not
2467                  * an official ARM number), this is a PL022 SSP block
2468                  * stripped to SPI mode only, it has 32bit wide
2469                  * and 32 locations deep TX/RX FIFO but no extended
2470                  * CR0/CR1 register
2471                  */
2472                 .id     = 0x00080023,
2473                 .mask   = 0xffffffff,
2474                 .data   = &vendor_st_pl023,
2475         },
2476         {
2477                 /*
2478                  * PL022 variant that has a chip select control register whih
2479                  * allows control of 5 output signals nCS[0:4].
2480                  */
2481                 .id     = 0x000b6022,
2482                 .mask   = 0x000fffff,
2483                 .data   = &vendor_lsi,
2484         },
2485         { 0, 0 },
2486 };
2487 
2488 MODULE_DEVICE_TABLE(amba, pl022_ids);
2489 
2490 static struct amba_driver pl022_driver = {
2491         .drv = {
2492                 .name   = "ssp-pl022",
2493                 .pm     = &pl022_dev_pm_ops,
2494         },
2495         .id_table       = pl022_ids,
2496         .probe          = pl022_probe,
2497         .remove         = pl022_remove,
2498 };
2499 
2500 static int __init pl022_init(void)
2501 {
2502         return amba_driver_register(&pl022_driver);
2503 }
2504 subsys_initcall(pl022_init);
2505 
2506 static void __exit pl022_exit(void)
2507 {
2508         amba_driver_unregister(&pl022_driver);
2509 }
2510 module_exit(pl022_exit);
2511 
2512 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2513 MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2514 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/spi/spi-pl022.c

DEFINITIONS
