drivers/spi/spi-pxa2xx.c

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This source file includes following definitions.
lpss_get_config
is_lpss_ssp
is_quark_x1000_ssp
pxa2xx_spi_get_ssrc1_change_mask
pxa2xx_spi_get_rx_default_thre
pxa2xx_spi_txfifo_full
pxa2xx_spi_clear_rx_thre
pxa2xx_spi_set_rx_thre
pxa2xx_configure_sscr0
__lpss_ssp_read_priv
__lpss_ssp_write_priv
lpss_ssp_setup
lpss_ssp_select_cs
lpss_ssp_cs_control
cs_assert
cs_deassert
pxa2xx_spi_set_cs
pxa2xx_spi_flush
null_writer
null_reader
u8_writer
u8_reader
u16_writer
u16_reader
u32_writer
u32_reader
reset_sccr1
int_error_stop
int_transfer_complete
interrupt_transfer
handle_bad_msg
ssp_int
quark_x1000_get_clk_div
ssp_get_clk_div
pxa2xx_ssp_get_clk_div
pxa2xx_spi_can_dma
pxa2xx_spi_transfer_one
pxa2xx_spi_slave_abort
pxa2xx_spi_handle_err
pxa2xx_spi_unprepare_transfer
setup_cs
setup
cleanup
pxa2xx_spi_get_port_id
pxa2xx_spi_get_port_id
pxa2xx_spi_idma_filter
pxa2xx_spi_init_pdata
pxa2xx_spi_fw_translate_cs
pxa2xx_spi_max_dma_transfer_size
pxa2xx_spi_probe
pxa2xx_spi_remove
pxa2xx_spi_suspend
pxa2xx_spi_resume
pxa2xx_spi_runtime_suspend
pxa2xx_spi_runtime_resume
pxa2xx_spi_init
pxa2xx_spi_exit
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   4  * Copyright (C) 2013, Intel Corporation
   5  */
   6 
   7 #include <linux/bitops.h>
   8 #include <linux/init.h>
   9 #include <linux/module.h>
  10 #include <linux/device.h>
  11 #include <linux/ioport.h>
  12 #include <linux/errno.h>
  13 #include <linux/err.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/pci.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/spi/pxa2xx_spi.h>
  19 #include <linux/spi/spi.h>
  20 #include <linux/delay.h>
  21 #include <linux/gpio.h>
  22 #include <linux/gpio/consumer.h>
  23 #include <linux/slab.h>
  24 #include <linux/clk.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/acpi.h>
  27 #include <linux/of_device.h>
  28 
  29 #include "spi-pxa2xx.h"
  30 
  31 MODULE_AUTHOR("Stephen Street");
  32 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
  33 MODULE_LICENSE("GPL");
  34 MODULE_ALIAS("platform:pxa2xx-spi");
  35 
  36 #define TIMOUT_DFLT             1000
  37 
  38 /*
  39  * for testing SSCR1 changes that require SSP restart, basically
  40  * everything except the service and interrupt enables, the pxa270 developer
  41  * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
  42  * list, but the PXA255 dev man says all bits without really meaning the
  43  * service and interrupt enables
  44  */
  45 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  46                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  47                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  48                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  49                                 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
  50                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  51 
  52 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF   \
  53                                 | QUARK_X1000_SSCR1_EFWR        \
  54                                 | QUARK_X1000_SSCR1_RFT         \
  55                                 | QUARK_X1000_SSCR1_TFT         \
  56                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  57 
  58 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  59                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  60                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  61                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  62                                 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
  63                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  64 
  65 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE   BIT(24)
  66 #define LPSS_CS_CONTROL_SW_MODE                 BIT(0)
  67 #define LPSS_CS_CONTROL_CS_HIGH                 BIT(1)
  68 #define LPSS_CAPS_CS_EN_SHIFT                   9
  69 #define LPSS_CAPS_CS_EN_MASK                    (0xf << LPSS_CAPS_CS_EN_SHIFT)
  70 
  71 #define LPSS_PRIV_CLOCK_GATE 0x38
  72 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
  73 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
  74 
  75 struct lpss_config {
  76         /* LPSS offset from drv_data->ioaddr */
  77         unsigned offset;
  78         /* Register offsets from drv_data->lpss_base or -1 */
  79         int reg_general;
  80         int reg_ssp;
  81         int reg_cs_ctrl;
  82         int reg_capabilities;
  83         /* FIFO thresholds */
  84         u32 rx_threshold;
  85         u32 tx_threshold_lo;
  86         u32 tx_threshold_hi;
  87         /* Chip select control */
  88         unsigned cs_sel_shift;
  89         unsigned cs_sel_mask;
  90         unsigned cs_num;
  91         /* Quirks */
  92         unsigned cs_clk_stays_gated : 1;
  93 };
  94 
  95 /* Keep these sorted with enum pxa_ssp_type */
  96 static const struct lpss_config lpss_platforms[] = {
  97         {       /* LPSS_LPT_SSP */
  98                 .offset = 0x800,
  99                 .reg_general = 0x08,
 100                 .reg_ssp = 0x0c,
 101                 .reg_cs_ctrl = 0x18,
 102                 .reg_capabilities = -1,
 103                 .rx_threshold = 64,
 104                 .tx_threshold_lo = 160,
 105                 .tx_threshold_hi = 224,
 106         },
 107         {       /* LPSS_BYT_SSP */
 108                 .offset = 0x400,
 109                 .reg_general = 0x08,
 110                 .reg_ssp = 0x0c,
 111                 .reg_cs_ctrl = 0x18,
 112                 .reg_capabilities = -1,
 113                 .rx_threshold = 64,
 114                 .tx_threshold_lo = 160,
 115                 .tx_threshold_hi = 224,
 116         },
 117         {       /* LPSS_BSW_SSP */
 118                 .offset = 0x400,
 119                 .reg_general = 0x08,
 120                 .reg_ssp = 0x0c,
 121                 .reg_cs_ctrl = 0x18,
 122                 .reg_capabilities = -1,
 123                 .rx_threshold = 64,
 124                 .tx_threshold_lo = 160,
 125                 .tx_threshold_hi = 224,
 126                 .cs_sel_shift = 2,
 127                 .cs_sel_mask = 1 << 2,
 128                 .cs_num = 2,
 129         },
 130         {       /* LPSS_SPT_SSP */
 131                 .offset = 0x200,
 132                 .reg_general = -1,
 133                 .reg_ssp = 0x20,
 134                 .reg_cs_ctrl = 0x24,
 135                 .reg_capabilities = -1,
 136                 .rx_threshold = 1,
 137                 .tx_threshold_lo = 32,
 138                 .tx_threshold_hi = 56,
 139         },
 140         {       /* LPSS_BXT_SSP */
 141                 .offset = 0x200,
 142                 .reg_general = -1,
 143                 .reg_ssp = 0x20,
 144                 .reg_cs_ctrl = 0x24,
 145                 .reg_capabilities = 0xfc,
 146                 .rx_threshold = 1,
 147                 .tx_threshold_lo = 16,
 148                 .tx_threshold_hi = 48,
 149                 .cs_sel_shift = 8,
 150                 .cs_sel_mask = 3 << 8,
 151         },
 152         {       /* LPSS_CNL_SSP */
 153                 .offset = 0x200,
 154                 .reg_general = -1,
 155                 .reg_ssp = 0x20,
 156                 .reg_cs_ctrl = 0x24,
 157                 .reg_capabilities = 0xfc,
 158                 .rx_threshold = 1,
 159                 .tx_threshold_lo = 32,
 160                 .tx_threshold_hi = 56,
 161                 .cs_sel_shift = 8,
 162                 .cs_sel_mask = 3 << 8,
 163                 .cs_clk_stays_gated = true,
 164         },
 165 };
 166 
 167 static inline const struct lpss_config
 168 *lpss_get_config(const struct driver_data *drv_data)
 169 {
 170         return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
 171 }
 172 
 173 static bool is_lpss_ssp(const struct driver_data *drv_data)
 174 {
 175         switch (drv_data->ssp_type) {
 176         case LPSS_LPT_SSP:
 177         case LPSS_BYT_SSP:
 178         case LPSS_BSW_SSP:
 179         case LPSS_SPT_SSP:
 180         case LPSS_BXT_SSP:
 181         case LPSS_CNL_SSP:
 182                 return true;
 183         default:
 184                 return false;
 185         }
 186 }
 187 
 188 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
 189 {
 190         return drv_data->ssp_type == QUARK_X1000_SSP;
 191 }
 192 
 193 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
 194 {
 195         switch (drv_data->ssp_type) {
 196         case QUARK_X1000_SSP:
 197                 return QUARK_X1000_SSCR1_CHANGE_MASK;
 198         case CE4100_SSP:
 199                 return CE4100_SSCR1_CHANGE_MASK;
 200         default:
 201                 return SSCR1_CHANGE_MASK;
 202         }
 203 }
 204 
 205 static u32
 206 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
 207 {
 208         switch (drv_data->ssp_type) {
 209         case QUARK_X1000_SSP:
 210                 return RX_THRESH_QUARK_X1000_DFLT;
 211         case CE4100_SSP:
 212                 return RX_THRESH_CE4100_DFLT;
 213         default:
 214                 return RX_THRESH_DFLT;
 215         }
 216 }
 217 
 218 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
 219 {
 220         u32 mask;
 221 
 222         switch (drv_data->ssp_type) {
 223         case QUARK_X1000_SSP:
 224                 mask = QUARK_X1000_SSSR_TFL_MASK;
 225                 break;
 226         case CE4100_SSP:
 227                 mask = CE4100_SSSR_TFL_MASK;
 228                 break;
 229         default:
 230                 mask = SSSR_TFL_MASK;
 231                 break;
 232         }
 233 
 234         return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
 235 }
 236 
 237 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
 238                                      u32 *sccr1_reg)
 239 {
 240         u32 mask;
 241 
 242         switch (drv_data->ssp_type) {
 243         case QUARK_X1000_SSP:
 244                 mask = QUARK_X1000_SSCR1_RFT;
 245                 break;
 246         case CE4100_SSP:
 247                 mask = CE4100_SSCR1_RFT;
 248                 break;
 249         default:
 250                 mask = SSCR1_RFT;
 251                 break;
 252         }
 253         *sccr1_reg &= ~mask;
 254 }
 255 
 256 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
 257                                    u32 *sccr1_reg, u32 threshold)
 258 {
 259         switch (drv_data->ssp_type) {
 260         case QUARK_X1000_SSP:
 261                 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
 262                 break;
 263         case CE4100_SSP:
 264                 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
 265                 break;
 266         default:
 267                 *sccr1_reg |= SSCR1_RxTresh(threshold);
 268                 break;
 269         }
 270 }
 271 
 272 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
 273                                   u32 clk_div, u8 bits)
 274 {
 275         switch (drv_data->ssp_type) {
 276         case QUARK_X1000_SSP:
 277                 return clk_div
 278                         | QUARK_X1000_SSCR0_Motorola
 279                         | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
 280                         | SSCR0_SSE;
 281         default:
 282                 return clk_div
 283                         | SSCR0_Motorola
 284                         | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 285                         | SSCR0_SSE
 286                         | (bits > 16 ? SSCR0_EDSS : 0);
 287         }
 288 }
 289 
 290 /*
 291  * Read and write LPSS SSP private registers. Caller must first check that
 292  * is_lpss_ssp() returns true before these can be called.
 293  */
 294 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
 295 {
 296         WARN_ON(!drv_data->lpss_base);
 297         return readl(drv_data->lpss_base + offset);
 298 }
 299 
 300 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
 301                                   unsigned offset, u32 value)
 302 {
 303         WARN_ON(!drv_data->lpss_base);
 304         writel(value, drv_data->lpss_base + offset);
 305 }
 306 
 307 /*
 308  * lpss_ssp_setup - perform LPSS SSP specific setup
 309  * @drv_data: pointer to the driver private data
 310  *
 311  * Perform LPSS SSP specific setup. This function must be called first if
 312  * one is going to use LPSS SSP private registers.
 313  */
 314 static void lpss_ssp_setup(struct driver_data *drv_data)
 315 {
 316         const struct lpss_config *config;
 317         u32 value;
 318 
 319         config = lpss_get_config(drv_data);
 320         drv_data->lpss_base = drv_data->ioaddr + config->offset;
 321 
 322         /* Enable software chip select control */
 323         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 324         value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
 325         value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
 326         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 327 
 328         /* Enable multiblock DMA transfers */
 329         if (drv_data->controller_info->enable_dma) {
 330                 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
 331 
 332                 if (config->reg_general >= 0) {
 333                         value = __lpss_ssp_read_priv(drv_data,
 334                                                      config->reg_general);
 335                         value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
 336                         __lpss_ssp_write_priv(drv_data,
 337                                               config->reg_general, value);
 338                 }
 339         }
 340 }
 341 
 342 static void lpss_ssp_select_cs(struct spi_device *spi,
 343                                const struct lpss_config *config)
 344 {
 345         struct driver_data *drv_data =
 346                 spi_controller_get_devdata(spi->controller);
 347         u32 value, cs;
 348 
 349         if (!config->cs_sel_mask)
 350                 return;
 351 
 352         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 353 
 354         cs = spi->chip_select;
 355         cs <<= config->cs_sel_shift;
 356         if (cs != (value & config->cs_sel_mask)) {
 357                 /*
 358                  * When switching another chip select output active the
 359                  * output must be selected first and wait 2 ssp_clk cycles
 360                  * before changing state to active. Otherwise a short
 361                  * glitch will occur on the previous chip select since
 362                  * output select is latched but state control is not.
 363                  */
 364                 value &= ~config->cs_sel_mask;
 365                 value |= cs;
 366                 __lpss_ssp_write_priv(drv_data,
 367                                       config->reg_cs_ctrl, value);
 368                 ndelay(1000000000 /
 369                        (drv_data->controller->max_speed_hz / 2));
 370         }
 371 }
 372 
 373 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
 374 {
 375         struct driver_data *drv_data =
 376                 spi_controller_get_devdata(spi->controller);
 377         const struct lpss_config *config;
 378         u32 value;
 379 
 380         config = lpss_get_config(drv_data);
 381 
 382         if (enable)
 383                 lpss_ssp_select_cs(spi, config);
 384 
 385         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 386         if (enable)
 387                 value &= ~LPSS_CS_CONTROL_CS_HIGH;
 388         else
 389                 value |= LPSS_CS_CONTROL_CS_HIGH;
 390         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 391         if (config->cs_clk_stays_gated) {
 392                 u32 clkgate;
 393 
 394                 /*
 395                  * Changing CS alone when dynamic clock gating is on won't
 396                  * actually flip CS at that time. This ruins SPI transfers
 397                  * that specify delays, or have no data. Toggle the clock mode
 398                  * to force on briefly to poke the CS pin to move.
 399                  */
 400                 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
 401                 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
 402                         LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
 403 
 404                 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
 405                 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
 406         }
 407 }
 408 
 409 static void cs_assert(struct spi_device *spi)
 410 {
 411         struct chip_data *chip = spi_get_ctldata(spi);
 412         struct driver_data *drv_data =
 413                 spi_controller_get_devdata(spi->controller);
 414 
 415         if (drv_data->ssp_type == CE4100_SSP) {
 416                 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
 417                 return;
 418         }
 419 
 420         if (chip->cs_control) {
 421                 chip->cs_control(PXA2XX_CS_ASSERT);
 422                 return;
 423         }
 424 
 425         if (chip->gpiod_cs) {
 426                 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
 427                 return;
 428         }
 429 
 430         if (is_lpss_ssp(drv_data))
 431                 lpss_ssp_cs_control(spi, true);
 432 }
 433 
 434 static void cs_deassert(struct spi_device *spi)
 435 {
 436         struct chip_data *chip = spi_get_ctldata(spi);
 437         struct driver_data *drv_data =
 438                 spi_controller_get_devdata(spi->controller);
 439         unsigned long timeout;
 440 
 441         if (drv_data->ssp_type == CE4100_SSP)
 442                 return;
 443 
 444         /* Wait until SSP becomes idle before deasserting the CS */
 445         timeout = jiffies + msecs_to_jiffies(10);
 446         while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
 447                !time_after(jiffies, timeout))
 448                 cpu_relax();
 449 
 450         if (chip->cs_control) {
 451                 chip->cs_control(PXA2XX_CS_DEASSERT);
 452                 return;
 453         }
 454 
 455         if (chip->gpiod_cs) {
 456                 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
 457                 return;
 458         }
 459 
 460         if (is_lpss_ssp(drv_data))
 461                 lpss_ssp_cs_control(spi, false);
 462 }
 463 
 464 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
 465 {
 466         if (level)
 467                 cs_deassert(spi);
 468         else
 469                 cs_assert(spi);
 470 }
 471 
 472 int pxa2xx_spi_flush(struct driver_data *drv_data)
 473 {
 474         unsigned long limit = loops_per_jiffy << 1;
 475 
 476         do {
 477                 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 478                         pxa2xx_spi_read(drv_data, SSDR);
 479         } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
 480         write_SSSR_CS(drv_data, SSSR_ROR);
 481 
 482         return limit;
 483 }
 484 
 485 static int null_writer(struct driver_data *drv_data)
 486 {
 487         u8 n_bytes = drv_data->n_bytes;
 488 
 489         if (pxa2xx_spi_txfifo_full(drv_data)
 490                 || (drv_data->tx == drv_data->tx_end))
 491                 return 0;
 492 
 493         pxa2xx_spi_write(drv_data, SSDR, 0);
 494         drv_data->tx += n_bytes;
 495 
 496         return 1;
 497 }
 498 
 499 static int null_reader(struct driver_data *drv_data)
 500 {
 501         u8 n_bytes = drv_data->n_bytes;
 502 
 503         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 504                && (drv_data->rx < drv_data->rx_end)) {
 505                 pxa2xx_spi_read(drv_data, SSDR);
 506                 drv_data->rx += n_bytes;
 507         }
 508 
 509         return drv_data->rx == drv_data->rx_end;
 510 }
 511 
 512 static int u8_writer(struct driver_data *drv_data)
 513 {
 514         if (pxa2xx_spi_txfifo_full(drv_data)
 515                 || (drv_data->tx == drv_data->tx_end))
 516                 return 0;
 517 
 518         pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
 519         ++drv_data->tx;
 520 
 521         return 1;
 522 }
 523 
 524 static int u8_reader(struct driver_data *drv_data)
 525 {
 526         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 527                && (drv_data->rx < drv_data->rx_end)) {
 528                 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 529                 ++drv_data->rx;
 530         }
 531 
 532         return drv_data->rx == drv_data->rx_end;
 533 }
 534 
 535 static int u16_writer(struct driver_data *drv_data)
 536 {
 537         if (pxa2xx_spi_txfifo_full(drv_data)
 538                 || (drv_data->tx == drv_data->tx_end))
 539                 return 0;
 540 
 541         pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
 542         drv_data->tx += 2;
 543 
 544         return 1;
 545 }
 546 
 547 static int u16_reader(struct driver_data *drv_data)
 548 {
 549         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 550                && (drv_data->rx < drv_data->rx_end)) {
 551                 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 552                 drv_data->rx += 2;
 553         }
 554 
 555         return drv_data->rx == drv_data->rx_end;
 556 }
 557 
 558 static int u32_writer(struct driver_data *drv_data)
 559 {
 560         if (pxa2xx_spi_txfifo_full(drv_data)
 561                 || (drv_data->tx == drv_data->tx_end))
 562                 return 0;
 563 
 564         pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
 565         drv_data->tx += 4;
 566 
 567         return 1;
 568 }
 569 
 570 static int u32_reader(struct driver_data *drv_data)
 571 {
 572         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 573                && (drv_data->rx < drv_data->rx_end)) {
 574                 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 575                 drv_data->rx += 4;
 576         }
 577 
 578         return drv_data->rx == drv_data->rx_end;
 579 }
 580 
 581 static void reset_sccr1(struct driver_data *drv_data)
 582 {
 583         struct chip_data *chip =
 584                 spi_get_ctldata(drv_data->controller->cur_msg->spi);
 585         u32 sccr1_reg;
 586 
 587         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
 588         switch (drv_data->ssp_type) {
 589         case QUARK_X1000_SSP:
 590                 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
 591                 break;
 592         case CE4100_SSP:
 593                 sccr1_reg &= ~CE4100_SSCR1_RFT;
 594                 break;
 595         default:
 596                 sccr1_reg &= ~SSCR1_RFT;
 597                 break;
 598         }
 599         sccr1_reg |= chip->threshold;
 600         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 601 }
 602 
 603 static void int_error_stop(struct driver_data *drv_data, const char* msg)
 604 {
 605         /* Stop and reset SSP */
 606         write_SSSR_CS(drv_data, drv_data->clear_sr);
 607         reset_sccr1(drv_data);
 608         if (!pxa25x_ssp_comp(drv_data))
 609                 pxa2xx_spi_write(drv_data, SSTO, 0);
 610         pxa2xx_spi_flush(drv_data);
 611         pxa2xx_spi_write(drv_data, SSCR0,
 612                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
 613 
 614         dev_err(&drv_data->pdev->dev, "%s\n", msg);
 615 
 616         drv_data->controller->cur_msg->status = -EIO;
 617         spi_finalize_current_transfer(drv_data->controller);
 618 }
 619 
 620 static void int_transfer_complete(struct driver_data *drv_data)
 621 {
 622         /* Clear and disable interrupts */
 623         write_SSSR_CS(drv_data, drv_data->clear_sr);
 624         reset_sccr1(drv_data);
 625         if (!pxa25x_ssp_comp(drv_data))
 626                 pxa2xx_spi_write(drv_data, SSTO, 0);
 627 
 628         spi_finalize_current_transfer(drv_data->controller);
 629 }
 630 
 631 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 632 {
 633         u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
 634                        drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 635 
 636         u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
 637 
 638         if (irq_status & SSSR_ROR) {
 639                 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
 640                 return IRQ_HANDLED;
 641         }
 642 
 643         if (irq_status & SSSR_TUR) {
 644                 int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
 645                 return IRQ_HANDLED;
 646         }
 647 
 648         if (irq_status & SSSR_TINT) {
 649                 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
 650                 if (drv_data->read(drv_data)) {
 651                         int_transfer_complete(drv_data);
 652                         return IRQ_HANDLED;
 653                 }
 654         }
 655 
 656         /* Drain rx fifo, Fill tx fifo and prevent overruns */
 657         do {
 658                 if (drv_data->read(drv_data)) {
 659                         int_transfer_complete(drv_data);
 660                         return IRQ_HANDLED;
 661                 }
 662         } while (drv_data->write(drv_data));
 663 
 664         if (drv_data->read(drv_data)) {
 665                 int_transfer_complete(drv_data);
 666                 return IRQ_HANDLED;
 667         }
 668 
 669         if (drv_data->tx == drv_data->tx_end) {
 670                 u32 bytes_left;
 671                 u32 sccr1_reg;
 672 
 673                 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 674                 sccr1_reg &= ~SSCR1_TIE;
 675 
 676                 /*
 677                  * PXA25x_SSP has no timeout, set up rx threshould for the
 678                  * remaining RX bytes.
 679                  */
 680                 if (pxa25x_ssp_comp(drv_data)) {
 681                         u32 rx_thre;
 682 
 683                         pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
 684 
 685                         bytes_left = drv_data->rx_end - drv_data->rx;
 686                         switch (drv_data->n_bytes) {
 687                         case 4:
 688                                 bytes_left >>= 2;
 689                                 break;
 690                         case 2:
 691                                 bytes_left >>= 1;
 692                                 break;
 693                         }
 694 
 695                         rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
 696                         if (rx_thre > bytes_left)
 697                                 rx_thre = bytes_left;
 698 
 699                         pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
 700                 }
 701                 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 702         }
 703 
 704         /* We did something */
 705         return IRQ_HANDLED;
 706 }
 707 
 708 static void handle_bad_msg(struct driver_data *drv_data)
 709 {
 710         pxa2xx_spi_write(drv_data, SSCR0,
 711                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
 712         pxa2xx_spi_write(drv_data, SSCR1,
 713                          pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
 714         if (!pxa25x_ssp_comp(drv_data))
 715                 pxa2xx_spi_write(drv_data, SSTO, 0);
 716         write_SSSR_CS(drv_data, drv_data->clear_sr);
 717 
 718         dev_err(&drv_data->pdev->dev,
 719                 "bad message state in interrupt handler\n");
 720 }
 721 
 722 static irqreturn_t ssp_int(int irq, void *dev_id)
 723 {
 724         struct driver_data *drv_data = dev_id;
 725         u32 sccr1_reg;
 726         u32 mask = drv_data->mask_sr;
 727         u32 status;
 728 
 729         /*
 730          * The IRQ might be shared with other peripherals so we must first
 731          * check that are we RPM suspended or not. If we are we assume that
 732          * the IRQ was not for us (we shouldn't be RPM suspended when the
 733          * interrupt is enabled).
 734          */
 735         if (pm_runtime_suspended(&drv_data->pdev->dev))
 736                 return IRQ_NONE;
 737 
 738         /*
 739          * If the device is not yet in RPM suspended state and we get an
 740          * interrupt that is meant for another device, check if status bits
 741          * are all set to one. That means that the device is already
 742          * powered off.
 743          */
 744         status = pxa2xx_spi_read(drv_data, SSSR);
 745         if (status == ~0)
 746                 return IRQ_NONE;
 747 
 748         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 749 
 750         /* Ignore possible writes if we don't need to write */
 751         if (!(sccr1_reg & SSCR1_TIE))
 752                 mask &= ~SSSR_TFS;
 753 
 754         /* Ignore RX timeout interrupt if it is disabled */
 755         if (!(sccr1_reg & SSCR1_TINTE))
 756                 mask &= ~SSSR_TINT;
 757 
 758         if (!(status & mask))
 759                 return IRQ_NONE;
 760 
 761         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
 762         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 763 
 764         if (!drv_data->controller->cur_msg) {
 765                 handle_bad_msg(drv_data);
 766                 /* Never fail */
 767                 return IRQ_HANDLED;
 768         }
 769 
 770         return drv_data->transfer_handler(drv_data);
 771 }
 772 
 773 /*
 774  * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
 775  * input frequency by fractions of 2^24. It also has a divider by 5.
 776  *
 777  * There are formulas to get baud rate value for given input frequency and
 778  * divider parameters, such as DDS_CLK_RATE and SCR:
 779  *
 780  * Fsys = 200MHz
 781  *
 782  * Fssp = Fsys * DDS_CLK_RATE / 2^24                    (1)
 783  * Baud rate = Fsclk = Fssp / (2 * (SCR + 1))           (2)
 784  *
 785  * DDS_CLK_RATE either 2^n or 2^n / 5.
 786  * SCR is in range 0 .. 255
 787  *
 788  * Divisor = 5^i * 2^j * 2 * k
 789  *       i = [0, 1]      i = 1 iff j = 0 or j > 3
 790  *       j = [0, 23]     j = 0 iff i = 1
 791  *       k = [1, 256]
 792  * Special case: j = 0, i = 1: Divisor = 2 / 5
 793  *
 794  * Accordingly to the specification the recommended values for DDS_CLK_RATE
 795  * are:
 796  *      Case 1:         2^n, n = [0, 23]
 797  *      Case 2:         2^24 * 2 / 5 (0x666666)
 798  *      Case 3:         less than or equal to 2^24 / 5 / 16 (0x33333)
 799  *
 800  * In all cases the lowest possible value is better.
 801  *
 802  * The function calculates parameters for all cases and chooses the one closest
 803  * to the asked baud rate.
 804  */
 805 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
 806 {
 807         unsigned long xtal = 200000000;
 808         unsigned long fref = xtal / 2;          /* mandatory division by 2,
 809                                                    see (2) */
 810                                                 /* case 3 */
 811         unsigned long fref1 = fref / 2;         /* case 1 */
 812         unsigned long fref2 = fref * 2 / 5;     /* case 2 */
 813         unsigned long scale;
 814         unsigned long q, q1, q2;
 815         long r, r1, r2;
 816         u32 mul;
 817 
 818         /* Case 1 */
 819 
 820         /* Set initial value for DDS_CLK_RATE */
 821         mul = (1 << 24) >> 1;
 822 
 823         /* Calculate initial quot */
 824         q1 = DIV_ROUND_UP(fref1, rate);
 825 
 826         /* Scale q1 if it's too big */
 827         if (q1 > 256) {
 828                 /* Scale q1 to range [1, 512] */
 829                 scale = fls_long(q1 - 1);
 830                 if (scale > 9) {
 831                         q1 >>= scale - 9;
 832                         mul >>= scale - 9;
 833                 }
 834 
 835                 /* Round the result if we have a remainder */
 836                 q1 += q1 & 1;
 837         }
 838 
 839         /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
 840         scale = __ffs(q1);
 841         q1 >>= scale;
 842         mul >>= scale;
 843 
 844         /* Get the remainder */
 845         r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
 846 
 847         /* Case 2 */
 848 
 849         q2 = DIV_ROUND_UP(fref2, rate);
 850         r2 = abs(fref2 / q2 - rate);
 851 
 852         /*
 853          * Choose the best between two: less remainder we have the better. We
 854          * can't go case 2 if q2 is greater than 256 since SCR register can
 855          * hold only values 0 .. 255.
 856          */
 857         if (r2 >= r1 || q2 > 256) {
 858                 /* case 1 is better */
 859                 r = r1;
 860                 q = q1;
 861         } else {
 862                 /* case 2 is better */
 863                 r = r2;
 864                 q = q2;
 865                 mul = (1 << 24) * 2 / 5;
 866         }
 867 
 868         /* Check case 3 only if the divisor is big enough */
 869         if (fref / rate >= 80) {
 870                 u64 fssp;
 871                 u32 m;
 872 
 873                 /* Calculate initial quot */
 874                 q1 = DIV_ROUND_UP(fref, rate);
 875                 m = (1 << 24) / q1;
 876 
 877                 /* Get the remainder */
 878                 fssp = (u64)fref * m;
 879                 do_div(fssp, 1 << 24);
 880                 r1 = abs(fssp - rate);
 881 
 882                 /* Choose this one if it suits better */
 883                 if (r1 < r) {
 884                         /* case 3 is better */
 885                         q = 1;
 886                         mul = m;
 887                 }
 888         }
 889 
 890         *dds = mul;
 891         return q - 1;
 892 }
 893 
 894 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
 895 {
 896         unsigned long ssp_clk = drv_data->controller->max_speed_hz;
 897         const struct ssp_device *ssp = drv_data->ssp;
 898 
 899         rate = min_t(int, ssp_clk, rate);
 900 
 901         /*
 902          * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
 903          * that the SSP transmission rate can be greater than the device rate
 904          */
 905         if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
 906                 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
 907         else
 908                 return (DIV_ROUND_UP(ssp_clk, rate) - 1)  & 0xfff;
 909 }
 910 
 911 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
 912                                            int rate)
 913 {
 914         struct chip_data *chip =
 915                 spi_get_ctldata(drv_data->controller->cur_msg->spi);
 916         unsigned int clk_div;
 917 
 918         switch (drv_data->ssp_type) {
 919         case QUARK_X1000_SSP:
 920                 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
 921                 break;
 922         default:
 923                 clk_div = ssp_get_clk_div(drv_data, rate);
 924                 break;
 925         }
 926         return clk_div << 8;
 927 }
 928 
 929 static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
 930                                struct spi_device *spi,
 931                                struct spi_transfer *xfer)
 932 {
 933         struct chip_data *chip = spi_get_ctldata(spi);
 934 
 935         return chip->enable_dma &&
 936                xfer->len <= MAX_DMA_LEN &&
 937                xfer->len >= chip->dma_burst_size;
 938 }
 939 
 940 static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
 941                                    struct spi_device *spi,
 942                                    struct spi_transfer *transfer)
 943 {
 944         struct driver_data *drv_data = spi_controller_get_devdata(controller);
 945         struct spi_message *message = controller->cur_msg;
 946         struct chip_data *chip = spi_get_ctldata(spi);
 947         u32 dma_thresh = chip->dma_threshold;
 948         u32 dma_burst = chip->dma_burst_size;
 949         u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
 950         u32 clk_div;
 951         u8 bits;
 952         u32 speed;
 953         u32 cr0;
 954         u32 cr1;
 955         int err;
 956         int dma_mapped;
 957 
 958         /* Check if we can DMA this transfer */
 959         if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
 960 
 961                 /* reject already-mapped transfers; PIO won't always work */
 962                 if (message->is_dma_mapped
 963                                 || transfer->rx_dma || transfer->tx_dma) {
 964                         dev_err(&spi->dev,
 965                                 "Mapped transfer length of %u is greater than %d\n",
 966                                 transfer->len, MAX_DMA_LEN);
 967                         return -EINVAL;
 968                 }
 969 
 970                 /* warn ... we force this to PIO mode */
 971                 dev_warn_ratelimited(&spi->dev,
 972                                      "DMA disabled for transfer length %ld greater than %d\n",
 973                                      (long)transfer->len, MAX_DMA_LEN);
 974         }
 975 
 976         /* Setup the transfer state based on the type of transfer */
 977         if (pxa2xx_spi_flush(drv_data) == 0) {
 978                 dev_err(&spi->dev, "Flush failed\n");
 979                 return -EIO;
 980         }
 981         drv_data->n_bytes = chip->n_bytes;
 982         drv_data->tx = (void *)transfer->tx_buf;
 983         drv_data->tx_end = drv_data->tx + transfer->len;
 984         drv_data->rx = transfer->rx_buf;
 985         drv_data->rx_end = drv_data->rx + transfer->len;
 986         drv_data->write = drv_data->tx ? chip->write : null_writer;
 987         drv_data->read = drv_data->rx ? chip->read : null_reader;
 988 
 989         /* Change speed and bit per word on a per transfer */
 990         bits = transfer->bits_per_word;
 991         speed = transfer->speed_hz;
 992 
 993         clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
 994 
 995         if (bits <= 8) {
 996                 drv_data->n_bytes = 1;
 997                 drv_data->read = drv_data->read != null_reader ?
 998                                         u8_reader : null_reader;
 999                 drv_data->write = drv_data->write != null_writer ?
1000                                         u8_writer : null_writer;
1001         } else if (bits <= 16) {
1002                 drv_data->n_bytes = 2;
1003                 drv_data->read = drv_data->read != null_reader ?
1004                                         u16_reader : null_reader;
1005                 drv_data->write = drv_data->write != null_writer ?
1006                                         u16_writer : null_writer;
1007         } else if (bits <= 32) {
1008                 drv_data->n_bytes = 4;
1009                 drv_data->read = drv_data->read != null_reader ?
1010                                         u32_reader : null_reader;
1011                 drv_data->write = drv_data->write != null_writer ?
1012                                         u32_writer : null_writer;
1013         }
1014         /*
1015          * if bits/word is changed in dma mode, then must check the
1016          * thresholds and burst also
1017          */
1018         if (chip->enable_dma) {
1019                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1020                                                 spi,
1021                                                 bits, &dma_burst,
1022                                                 &dma_thresh))
1023                         dev_warn_ratelimited(&spi->dev,
1024                                              "DMA burst size reduced to match bits_per_word\n");
1025         }
1026 
1027         dma_mapped = controller->can_dma &&
1028                      controller->can_dma(controller, spi, transfer) &&
1029                      controller->cur_msg_mapped;
1030         if (dma_mapped) {
1031 
1032                 /* Ensure we have the correct interrupt handler */
1033                 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1034 
1035                 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1036                 if (err)
1037                         return err;
1038 
1039                 /* Clear status and start DMA engine */
1040                 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1041                 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1042 
1043                 pxa2xx_spi_dma_start(drv_data);
1044         } else {
1045                 /* Ensure we have the correct interrupt handler */
1046                 drv_data->transfer_handler = interrupt_transfer;
1047 
1048                 /* Clear status  */
1049                 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1050                 write_SSSR_CS(drv_data, drv_data->clear_sr);
1051         }
1052 
1053         /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1054         cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1055         if (!pxa25x_ssp_comp(drv_data))
1056                 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1057                         controller->max_speed_hz
1058                                 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1059                         dma_mapped ? "DMA" : "PIO");
1060         else
1061                 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1062                         controller->max_speed_hz / 2
1063                                 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1064                         dma_mapped ? "DMA" : "PIO");
1065 
1066         if (is_lpss_ssp(drv_data)) {
1067                 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1068                     != chip->lpss_rx_threshold)
1069                         pxa2xx_spi_write(drv_data, SSIRF,
1070                                          chip->lpss_rx_threshold);
1071                 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1072                     != chip->lpss_tx_threshold)
1073                         pxa2xx_spi_write(drv_data, SSITF,
1074                                          chip->lpss_tx_threshold);
1075         }
1076 
1077         if (is_quark_x1000_ssp(drv_data) &&
1078             (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1079                 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1080 
1081         /* see if we need to reload the config registers */
1082         if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1083             || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1084             != (cr1 & change_mask)) {
1085                 /* stop the SSP, and update the other bits */
1086                 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1087                 if (!pxa25x_ssp_comp(drv_data))
1088                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1089                 /* first set CR1 without interrupt and service enables */
1090                 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1091                 /* restart the SSP */
1092                 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1093 
1094         } else {
1095                 if (!pxa25x_ssp_comp(drv_data))
1096                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1097         }
1098 
1099         if (drv_data->ssp_type == MMP2_SSP) {
1100                 u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
1101                                         & SSSR_TFL_MASK) >> 8;
1102 
1103                 if (tx_level) {
1104                         /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
1105                         dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
1106                                                                 tx_level);
1107                         if (tx_level > transfer->len)
1108                                 tx_level = transfer->len;
1109                         drv_data->tx += tx_level;
1110                 }
1111         }
1112 
1113         if (spi_controller_is_slave(controller)) {
1114                 while (drv_data->write(drv_data))
1115                         ;
1116                 if (drv_data->gpiod_ready) {
1117                         gpiod_set_value(drv_data->gpiod_ready, 1);
1118                         udelay(1);
1119                         gpiod_set_value(drv_data->gpiod_ready, 0);
1120                 }
1121         }
1122 
1123         /*
1124          * Release the data by enabling service requests and interrupts,
1125          * without changing any mode bits
1126          */
1127         pxa2xx_spi_write(drv_data, SSCR1, cr1);
1128 
1129         return 1;
1130 }
1131 
1132 static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1133 {
1134         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1135 
1136         /* Stop and reset SSP */
1137         write_SSSR_CS(drv_data, drv_data->clear_sr);
1138         reset_sccr1(drv_data);
1139         if (!pxa25x_ssp_comp(drv_data))
1140                 pxa2xx_spi_write(drv_data, SSTO, 0);
1141         pxa2xx_spi_flush(drv_data);
1142         pxa2xx_spi_write(drv_data, SSCR0,
1143                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1144 
1145         dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
1146 
1147         drv_data->controller->cur_msg->status = -EINTR;
1148         spi_finalize_current_transfer(drv_data->controller);
1149 
1150         return 0;
1151 }
1152 
1153 static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1154                                  struct spi_message *msg)
1155 {
1156         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1157 
1158         /* Disable the SSP */
1159         pxa2xx_spi_write(drv_data, SSCR0,
1160                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1161         /* Clear and disable interrupts and service requests */
1162         write_SSSR_CS(drv_data, drv_data->clear_sr);
1163         pxa2xx_spi_write(drv_data, SSCR1,
1164                          pxa2xx_spi_read(drv_data, SSCR1)
1165                          & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1166         if (!pxa25x_ssp_comp(drv_data))
1167                 pxa2xx_spi_write(drv_data, SSTO, 0);
1168 
1169         /*
1170          * Stop the DMA if running. Note DMA callback handler may have unset
1171          * the dma_running already, which is fine as stopping is not needed
1172          * then but we shouldn't rely this flag for anything else than
1173          * stopping. For instance to differentiate between PIO and DMA
1174          * transfers.
1175          */
1176         if (atomic_read(&drv_data->dma_running))
1177                 pxa2xx_spi_dma_stop(drv_data);
1178 }
1179 
1180 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1181 {
1182         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1183 
1184         /* Disable the SSP now */
1185         pxa2xx_spi_write(drv_data, SSCR0,
1186                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1187 
1188         return 0;
1189 }
1190 
1191 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1192                     struct pxa2xx_spi_chip *chip_info)
1193 {
1194         struct driver_data *drv_data =
1195                 spi_controller_get_devdata(spi->controller);
1196         struct gpio_desc *gpiod;
1197         int err = 0;
1198 
1199         if (chip == NULL)
1200                 return 0;
1201 
1202         if (drv_data->cs_gpiods) {
1203                 gpiod = drv_data->cs_gpiods[spi->chip_select];
1204                 if (gpiod) {
1205                         chip->gpiod_cs = gpiod;
1206                         chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1207                         gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1208                 }
1209 
1210                 return 0;
1211         }
1212 
1213         if (chip_info == NULL)
1214                 return 0;
1215 
1216         /* NOTE: setup() can be called multiple times, possibly with
1217          * different chip_info, release previously requested GPIO
1218          */
1219         if (chip->gpiod_cs) {
1220                 gpiod_put(chip->gpiod_cs);
1221                 chip->gpiod_cs = NULL;
1222         }
1223 
1224         /* If (*cs_control) is provided, ignore GPIO chip select */
1225         if (chip_info->cs_control) {
1226                 chip->cs_control = chip_info->cs_control;
1227                 return 0;
1228         }
1229 
1230         if (gpio_is_valid(chip_info->gpio_cs)) {
1231                 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1232                 if (err) {
1233                         dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1234                                 chip_info->gpio_cs);
1235                         return err;
1236                 }
1237 
1238                 gpiod = gpio_to_desc(chip_info->gpio_cs);
1239                 chip->gpiod_cs = gpiod;
1240                 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1241 
1242                 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1243         }
1244 
1245         return err;
1246 }
1247 
1248 static int setup(struct spi_device *spi)
1249 {
1250         struct pxa2xx_spi_chip *chip_info;
1251         struct chip_data *chip;
1252         const struct lpss_config *config;
1253         struct driver_data *drv_data =
1254                 spi_controller_get_devdata(spi->controller);
1255         uint tx_thres, tx_hi_thres, rx_thres;
1256 
1257         switch (drv_data->ssp_type) {
1258         case QUARK_X1000_SSP:
1259                 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1260                 tx_hi_thres = 0;
1261                 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1262                 break;
1263         case CE4100_SSP:
1264                 tx_thres = TX_THRESH_CE4100_DFLT;
1265                 tx_hi_thres = 0;
1266                 rx_thres = RX_THRESH_CE4100_DFLT;
1267                 break;
1268         case LPSS_LPT_SSP:
1269         case LPSS_BYT_SSP:
1270         case LPSS_BSW_SSP:
1271         case LPSS_SPT_SSP:
1272         case LPSS_BXT_SSP:
1273         case LPSS_CNL_SSP:
1274                 config = lpss_get_config(drv_data);
1275                 tx_thres = config->tx_threshold_lo;
1276                 tx_hi_thres = config->tx_threshold_hi;
1277                 rx_thres = config->rx_threshold;
1278                 break;
1279         default:
1280                 tx_hi_thres = 0;
1281                 if (spi_controller_is_slave(drv_data->controller)) {
1282                         tx_thres = 1;
1283                         rx_thres = 2;
1284                 } else {
1285                         tx_thres = TX_THRESH_DFLT;
1286                         rx_thres = RX_THRESH_DFLT;
1287                 }
1288                 break;
1289         }
1290 
1291         /* Only alloc on first setup */
1292         chip = spi_get_ctldata(spi);
1293         if (!chip) {
1294                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1295                 if (!chip)
1296                         return -ENOMEM;
1297 
1298                 if (drv_data->ssp_type == CE4100_SSP) {
1299                         if (spi->chip_select > 4) {
1300                                 dev_err(&spi->dev,
1301                                         "failed setup: cs number must not be > 4.\n");
1302                                 kfree(chip);
1303                                 return -EINVAL;
1304                         }
1305 
1306                         chip->frm = spi->chip_select;
1307                 }
1308                 chip->enable_dma = drv_data->controller_info->enable_dma;
1309                 chip->timeout = TIMOUT_DFLT;
1310         }
1311 
1312         /* protocol drivers may change the chip settings, so...
1313          * if chip_info exists, use it */
1314         chip_info = spi->controller_data;
1315 
1316         /* chip_info isn't always needed */
1317         chip->cr1 = 0;
1318         if (chip_info) {
1319                 if (chip_info->timeout)
1320                         chip->timeout = chip_info->timeout;
1321                 if (chip_info->tx_threshold)
1322                         tx_thres = chip_info->tx_threshold;
1323                 if (chip_info->tx_hi_threshold)
1324                         tx_hi_thres = chip_info->tx_hi_threshold;
1325                 if (chip_info->rx_threshold)
1326                         rx_thres = chip_info->rx_threshold;
1327                 chip->dma_threshold = 0;
1328                 if (chip_info->enable_loopback)
1329                         chip->cr1 = SSCR1_LBM;
1330         }
1331         if (spi_controller_is_slave(drv_data->controller)) {
1332                 chip->cr1 |= SSCR1_SCFR;
1333                 chip->cr1 |= SSCR1_SCLKDIR;
1334                 chip->cr1 |= SSCR1_SFRMDIR;
1335                 chip->cr1 |= SSCR1_SPH;
1336         }
1337 
1338         chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1339         chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1340                                 | SSITF_TxHiThresh(tx_hi_thres);
1341 
1342         /* set dma burst and threshold outside of chip_info path so that if
1343          * chip_info goes away after setting chip->enable_dma, the
1344          * burst and threshold can still respond to changes in bits_per_word */
1345         if (chip->enable_dma) {
1346                 /* set up legal burst and threshold for dma */
1347                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1348                                                 spi->bits_per_word,
1349                                                 &chip->dma_burst_size,
1350                                                 &chip->dma_threshold)) {
1351                         dev_warn(&spi->dev,
1352                                  "in setup: DMA burst size reduced to match bits_per_word\n");
1353                 }
1354                 dev_dbg(&spi->dev,
1355                         "in setup: DMA burst size set to %u\n",
1356                         chip->dma_burst_size);
1357         }
1358 
1359         switch (drv_data->ssp_type) {
1360         case QUARK_X1000_SSP:
1361                 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1362                                    & QUARK_X1000_SSCR1_RFT)
1363                                    | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1364                                    & QUARK_X1000_SSCR1_TFT);
1365                 break;
1366         case CE4100_SSP:
1367                 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1368                         (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1369                 break;
1370         default:
1371                 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1372                         (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1373                 break;
1374         }
1375 
1376         chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1377         chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1378                         | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1379 
1380         if (spi->mode & SPI_LOOP)
1381                 chip->cr1 |= SSCR1_LBM;
1382 
1383         if (spi->bits_per_word <= 8) {
1384                 chip->n_bytes = 1;
1385                 chip->read = u8_reader;
1386                 chip->write = u8_writer;
1387         } else if (spi->bits_per_word <= 16) {
1388                 chip->n_bytes = 2;
1389                 chip->read = u16_reader;
1390                 chip->write = u16_writer;
1391         } else if (spi->bits_per_word <= 32) {
1392                 chip->n_bytes = 4;
1393                 chip->read = u32_reader;
1394                 chip->write = u32_writer;
1395         }
1396 
1397         spi_set_ctldata(spi, chip);
1398 
1399         if (drv_data->ssp_type == CE4100_SSP)
1400                 return 0;
1401 
1402         return setup_cs(spi, chip, chip_info);
1403 }
1404 
1405 static void cleanup(struct spi_device *spi)
1406 {
1407         struct chip_data *chip = spi_get_ctldata(spi);
1408         struct driver_data *drv_data =
1409                 spi_controller_get_devdata(spi->controller);
1410 
1411         if (!chip)
1412                 return;
1413 
1414         if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1415             chip->gpiod_cs)
1416                 gpiod_put(chip->gpiod_cs);
1417 
1418         kfree(chip);
1419 }
1420 
1421 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1422         { "INT33C0", LPSS_LPT_SSP },
1423         { "INT33C1", LPSS_LPT_SSP },
1424         { "INT3430", LPSS_LPT_SSP },
1425         { "INT3431", LPSS_LPT_SSP },
1426         { "80860F0E", LPSS_BYT_SSP },
1427         { "8086228E", LPSS_BSW_SSP },
1428         { },
1429 };
1430 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1431 
1432 /*
1433  * PCI IDs of compound devices that integrate both host controller and private
1434  * integrated DMA engine. Please note these are not used in module
1435  * autoloading and probing in this module but matching the LPSS SSP type.
1436  */
1437 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1438         /* SPT-LP */
1439         { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1440         { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1441         /* SPT-H */
1442         { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1443         { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1444         /* KBL-H */
1445         { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1446         { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1447         /* BXT A-Step */
1448         { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1449         { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1450         { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1451         /* BXT B-Step */
1452         { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1453         { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1454         { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1455         /* GLK */
1456         { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1457         { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1458         { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1459         /* ICL-LP */
1460         { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1461         { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1462         { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1463         /* EHL */
1464         { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
1465         { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
1466         { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
1467         /* JSL */
1468         { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP },
1469         { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP },
1470         { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP },
1471         /* APL */
1472         { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1473         { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1474         { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1475         /* CNL-LP */
1476         { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1477         { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1478         { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1479         /* CNL-H */
1480         { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1481         { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1482         { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1483         /* CML-LP */
1484         { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
1485         { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
1486         { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
1487         /* CML-H */
1488         { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP },
1489         { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP },
1490         { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP },
1491         /* TGL-LP */
1492         { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
1493         { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
1494         { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
1495         { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
1496         { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
1497         { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
1498         { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
1499         { },
1500 };
1501 
1502 static const struct of_device_id pxa2xx_spi_of_match[] = {
1503         { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1504         {},
1505 };
1506 MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1507 
1508 #ifdef CONFIG_ACPI
1509 
1510 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1511 {
1512         unsigned int devid;
1513         int port_id = -1;
1514 
1515         if (adev && adev->pnp.unique_id &&
1516             !kstrtouint(adev->pnp.unique_id, 0, &devid))
1517                 port_id = devid;
1518         return port_id;
1519 }
1520 
1521 #else /* !CONFIG_ACPI */
1522 
1523 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1524 {
1525         return -1;
1526 }
1527 
1528 #endif /* CONFIG_ACPI */
1529 
1530 
1531 #ifdef CONFIG_PCI
1532 
1533 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1534 {
1535         return param == chan->device->dev;
1536 }
1537 
1538 #endif /* CONFIG_PCI */
1539 
1540 static struct pxa2xx_spi_controller *
1541 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1542 {
1543         struct pxa2xx_spi_controller *pdata;
1544         struct acpi_device *adev;
1545         struct ssp_device *ssp;
1546         struct resource *res;
1547         const struct acpi_device_id *adev_id = NULL;
1548         const struct pci_device_id *pcidev_id = NULL;
1549         const struct of_device_id *of_id = NULL;
1550         enum pxa_ssp_type type;
1551 
1552         adev = ACPI_COMPANION(&pdev->dev);
1553 
1554         if (pdev->dev.of_node)
1555                 of_id = of_match_device(pdev->dev.driver->of_match_table,
1556                                         &pdev->dev);
1557         else if (dev_is_pci(pdev->dev.parent))
1558                 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1559                                          to_pci_dev(pdev->dev.parent));
1560         else if (adev)
1561                 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1562                                             &pdev->dev);
1563         else
1564                 return NULL;
1565 
1566         if (adev_id)
1567                 type = (enum pxa_ssp_type)adev_id->driver_data;
1568         else if (pcidev_id)
1569                 type = (enum pxa_ssp_type)pcidev_id->driver_data;
1570         else if (of_id)
1571                 type = (enum pxa_ssp_type)of_id->data;
1572         else
1573                 return NULL;
1574 
1575         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1576         if (!pdata)
1577                 return NULL;
1578 
1579         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1580         if (!res)
1581                 return NULL;
1582 
1583         ssp = &pdata->ssp;
1584 
1585         ssp->phys_base = res->start;
1586         ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1587         if (IS_ERR(ssp->mmio_base))
1588                 return NULL;
1589 
1590 #ifdef CONFIG_PCI
1591         if (pcidev_id) {
1592                 pdata->tx_param = pdev->dev.parent;
1593                 pdata->rx_param = pdev->dev.parent;
1594                 pdata->dma_filter = pxa2xx_spi_idma_filter;
1595         }
1596 #endif
1597 
1598         ssp->clk = devm_clk_get(&pdev->dev, NULL);
1599         if (IS_ERR(ssp->clk))
1600                 return NULL;
1601 
1602         ssp->irq = platform_get_irq(pdev, 0);
1603         if (ssp->irq < 0)
1604                 return NULL;
1605 
1606         ssp->type = type;
1607         ssp->pdev = pdev;
1608         ssp->port_id = pxa2xx_spi_get_port_id(adev);
1609 
1610         pdata->is_slave = of_property_read_bool(pdev->dev.of_node, "spi-slave");
1611         pdata->num_chipselect = 1;
1612         pdata->enable_dma = true;
1613         pdata->dma_burst_size = 1;
1614 
1615         return pdata;
1616 }
1617 
1618 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1619                                       unsigned int cs)
1620 {
1621         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1622 
1623         if (has_acpi_companion(&drv_data->pdev->dev)) {
1624                 switch (drv_data->ssp_type) {
1625                 /*
1626                  * For Atoms the ACPI DeviceSelection used by the Windows
1627                  * driver starts from 1 instead of 0 so translate it here
1628                  * to match what Linux expects.
1629                  */
1630                 case LPSS_BYT_SSP:
1631                 case LPSS_BSW_SSP:
1632                         return cs - 1;
1633 
1634                 default:
1635                         break;
1636                 }
1637         }
1638 
1639         return cs;
1640 }
1641 
1642 static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1643 {
1644         return MAX_DMA_LEN;
1645 }
1646 
1647 static int pxa2xx_spi_probe(struct platform_device *pdev)
1648 {
1649         struct device *dev = &pdev->dev;
1650         struct pxa2xx_spi_controller *platform_info;
1651         struct spi_controller *controller;
1652         struct driver_data *drv_data;
1653         struct ssp_device *ssp;
1654         const struct lpss_config *config;
1655         int status, count;
1656         u32 tmp;
1657 
1658         platform_info = dev_get_platdata(dev);
1659         if (!platform_info) {
1660                 platform_info = pxa2xx_spi_init_pdata(pdev);
1661                 if (!platform_info) {
1662                         dev_err(&pdev->dev, "missing platform data\n");
1663                         return -ENODEV;
1664                 }
1665         }
1666 
1667         ssp = pxa_ssp_request(pdev->id, pdev->name);
1668         if (!ssp)
1669                 ssp = &platform_info->ssp;
1670 
1671         if (!ssp->mmio_base) {
1672                 dev_err(&pdev->dev, "failed to get ssp\n");
1673                 return -ENODEV;
1674         }
1675 
1676         if (platform_info->is_slave)
1677                 controller = spi_alloc_slave(dev, sizeof(struct driver_data));
1678         else
1679                 controller = spi_alloc_master(dev, sizeof(struct driver_data));
1680 
1681         if (!controller) {
1682                 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1683                 pxa_ssp_free(ssp);
1684                 return -ENOMEM;
1685         }
1686         drv_data = spi_controller_get_devdata(controller);
1687         drv_data->controller = controller;
1688         drv_data->controller_info = platform_info;
1689         drv_data->pdev = pdev;
1690         drv_data->ssp = ssp;
1691 
1692         controller->dev.of_node = pdev->dev.of_node;
1693         /* the spi->mode bits understood by this driver: */
1694         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1695 
1696         controller->bus_num = ssp->port_id;
1697         controller->dma_alignment = DMA_ALIGNMENT;
1698         controller->cleanup = cleanup;
1699         controller->setup = setup;
1700         controller->set_cs = pxa2xx_spi_set_cs;
1701         controller->transfer_one = pxa2xx_spi_transfer_one;
1702         controller->slave_abort = pxa2xx_spi_slave_abort;
1703         controller->handle_err = pxa2xx_spi_handle_err;
1704         controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1705         controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1706         controller->auto_runtime_pm = true;
1707         controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1708 
1709         drv_data->ssp_type = ssp->type;
1710 
1711         drv_data->ioaddr = ssp->mmio_base;
1712         drv_data->ssdr_physical = ssp->phys_base + SSDR;
1713         if (pxa25x_ssp_comp(drv_data)) {
1714                 switch (drv_data->ssp_type) {
1715                 case QUARK_X1000_SSP:
1716                         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1717                         break;
1718                 default:
1719                         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1720                         break;
1721                 }
1722 
1723                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1724                 drv_data->dma_cr1 = 0;
1725                 drv_data->clear_sr = SSSR_ROR;
1726                 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1727         } else {
1728                 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1729                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1730                 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1731                 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1732                 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1733                                                 | SSSR_ROR | SSSR_TUR;
1734         }
1735 
1736         status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1737                         drv_data);
1738         if (status < 0) {
1739                 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1740                 goto out_error_controller_alloc;
1741         }
1742 
1743         /* Setup DMA if requested */
1744         if (platform_info->enable_dma) {
1745                 status = pxa2xx_spi_dma_setup(drv_data);
1746                 if (status) {
1747                         dev_warn(dev, "no DMA channels available, using PIO\n");
1748                         platform_info->enable_dma = false;
1749                 } else {
1750                         controller->can_dma = pxa2xx_spi_can_dma;
1751                         controller->max_dma_len = MAX_DMA_LEN;
1752                         controller->max_transfer_size =
1753                                 pxa2xx_spi_max_dma_transfer_size;
1754                 }
1755         }
1756 
1757         /* Enable SOC clock */
1758         status = clk_prepare_enable(ssp->clk);
1759         if (status)
1760                 goto out_error_dma_irq_alloc;
1761 
1762         controller->max_speed_hz = clk_get_rate(ssp->clk);
1763         /*
1764          * Set minimum speed for all other platforms than Intel Quark which is
1765          * able do under 1 Hz transfers.
1766          */
1767         if (!pxa25x_ssp_comp(drv_data))
1768                 controller->min_speed_hz =
1769                         DIV_ROUND_UP(controller->max_speed_hz, 4096);
1770         else if (!is_quark_x1000_ssp(drv_data))
1771                 controller->min_speed_hz =
1772                         DIV_ROUND_UP(controller->max_speed_hz, 512);
1773 
1774         /* Load default SSP configuration */
1775         pxa2xx_spi_write(drv_data, SSCR0, 0);
1776         switch (drv_data->ssp_type) {
1777         case QUARK_X1000_SSP:
1778                 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1779                       QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1780                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1781 
1782                 /* using the Motorola SPI protocol and use 8 bit frame */
1783                 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1784                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1785                 break;
1786         case CE4100_SSP:
1787                 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1788                       CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1789                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1790                 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1791                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1792                 break;
1793         default:
1794 
1795                 if (spi_controller_is_slave(controller)) {
1796                         tmp = SSCR1_SCFR |
1797                               SSCR1_SCLKDIR |
1798                               SSCR1_SFRMDIR |
1799                               SSCR1_RxTresh(2) |
1800                               SSCR1_TxTresh(1) |
1801                               SSCR1_SPH;
1802                 } else {
1803                         tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1804                               SSCR1_TxTresh(TX_THRESH_DFLT);
1805                 }
1806                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1807                 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1808                 if (!spi_controller_is_slave(controller))
1809                         tmp |= SSCR0_SCR(2);
1810                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1811                 break;
1812         }
1813 
1814         if (!pxa25x_ssp_comp(drv_data))
1815                 pxa2xx_spi_write(drv_data, SSTO, 0);
1816 
1817         if (!is_quark_x1000_ssp(drv_data))
1818                 pxa2xx_spi_write(drv_data, SSPSP, 0);
1819 
1820         if (is_lpss_ssp(drv_data)) {
1821                 lpss_ssp_setup(drv_data);
1822                 config = lpss_get_config(drv_data);
1823                 if (config->reg_capabilities >= 0) {
1824                         tmp = __lpss_ssp_read_priv(drv_data,
1825                                                    config->reg_capabilities);
1826                         tmp &= LPSS_CAPS_CS_EN_MASK;
1827                         tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1828                         platform_info->num_chipselect = ffz(tmp);
1829                 } else if (config->cs_num) {
1830                         platform_info->num_chipselect = config->cs_num;
1831                 }
1832         }
1833         controller->num_chipselect = platform_info->num_chipselect;
1834 
1835         count = gpiod_count(&pdev->dev, "cs");
1836         if (count > 0) {
1837                 int i;
1838 
1839                 controller->num_chipselect = max_t(int, count,
1840                         controller->num_chipselect);
1841 
1842                 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1843                         controller->num_chipselect, sizeof(struct gpio_desc *),
1844                         GFP_KERNEL);
1845                 if (!drv_data->cs_gpiods) {
1846                         status = -ENOMEM;
1847                         goto out_error_clock_enabled;
1848                 }
1849 
1850                 for (i = 0; i < controller->num_chipselect; i++) {
1851                         struct gpio_desc *gpiod;
1852 
1853                         gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1854                         if (IS_ERR(gpiod)) {
1855                                 /* Means use native chip select */
1856                                 if (PTR_ERR(gpiod) == -ENOENT)
1857                                         continue;
1858 
1859                                 status = PTR_ERR(gpiod);
1860                                 goto out_error_clock_enabled;
1861                         } else {
1862                                 drv_data->cs_gpiods[i] = gpiod;
1863                         }
1864                 }
1865         }
1866 
1867         if (platform_info->is_slave) {
1868                 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1869                                                 "ready", GPIOD_OUT_LOW);
1870                 if (IS_ERR(drv_data->gpiod_ready)) {
1871                         status = PTR_ERR(drv_data->gpiod_ready);
1872                         goto out_error_clock_enabled;
1873                 }
1874         }
1875 
1876         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1877         pm_runtime_use_autosuspend(&pdev->dev);
1878         pm_runtime_set_active(&pdev->dev);
1879         pm_runtime_enable(&pdev->dev);
1880 
1881         /* Register with the SPI framework */
1882         platform_set_drvdata(pdev, drv_data);
1883         status = spi_register_controller(controller);
1884         if (status != 0) {
1885                 dev_err(&pdev->dev, "problem registering spi controller\n");
1886                 goto out_error_pm_runtime_enabled;
1887         }
1888 
1889         return status;
1890 
1891 out_error_pm_runtime_enabled:
1892         pm_runtime_disable(&pdev->dev);
1893 
1894 out_error_clock_enabled:
1895         clk_disable_unprepare(ssp->clk);
1896 
1897 out_error_dma_irq_alloc:
1898         pxa2xx_spi_dma_release(drv_data);
1899         free_irq(ssp->irq, drv_data);
1900 
1901 out_error_controller_alloc:
1902         spi_controller_put(controller);
1903         pxa_ssp_free(ssp);
1904         return status;
1905 }
1906 
1907 static int pxa2xx_spi_remove(struct platform_device *pdev)
1908 {
1909         struct driver_data *drv_data = platform_get_drvdata(pdev);
1910         struct ssp_device *ssp;
1911 
1912         if (!drv_data)
1913                 return 0;
1914         ssp = drv_data->ssp;
1915 
1916         pm_runtime_get_sync(&pdev->dev);
1917 
1918         spi_unregister_controller(drv_data->controller);
1919 
1920         /* Disable the SSP at the peripheral and SOC level */
1921         pxa2xx_spi_write(drv_data, SSCR0, 0);
1922         clk_disable_unprepare(ssp->clk);
1923 
1924         /* Release DMA */
1925         if (drv_data->controller_info->enable_dma)
1926                 pxa2xx_spi_dma_release(drv_data);
1927 
1928         pm_runtime_put_noidle(&pdev->dev);
1929         pm_runtime_disable(&pdev->dev);
1930 
1931         /* Release IRQ */
1932         free_irq(ssp->irq, drv_data);
1933 
1934         /* Release SSP */
1935         pxa_ssp_free(ssp);
1936 
1937         return 0;
1938 }
1939 
1940 #ifdef CONFIG_PM_SLEEP
1941 static int pxa2xx_spi_suspend(struct device *dev)
1942 {
1943         struct driver_data *drv_data = dev_get_drvdata(dev);
1944         struct ssp_device *ssp = drv_data->ssp;
1945         int status;
1946 
1947         status = spi_controller_suspend(drv_data->controller);
1948         if (status != 0)
1949                 return status;
1950         pxa2xx_spi_write(drv_data, SSCR0, 0);
1951 
1952         if (!pm_runtime_suspended(dev))
1953                 clk_disable_unprepare(ssp->clk);
1954 
1955         return 0;
1956 }
1957 
1958 static int pxa2xx_spi_resume(struct device *dev)
1959 {
1960         struct driver_data *drv_data = dev_get_drvdata(dev);
1961         struct ssp_device *ssp = drv_data->ssp;
1962         int status;
1963 
1964         /* Enable the SSP clock */
1965         if (!pm_runtime_suspended(dev)) {
1966                 status = clk_prepare_enable(ssp->clk);
1967                 if (status)
1968                         return status;
1969         }
1970 
1971         /* Start the queue running */
1972         return spi_controller_resume(drv_data->controller);
1973 }
1974 #endif
1975 
1976 #ifdef CONFIG_PM
1977 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1978 {
1979         struct driver_data *drv_data = dev_get_drvdata(dev);
1980 
1981         clk_disable_unprepare(drv_data->ssp->clk);
1982         return 0;
1983 }
1984 
1985 static int pxa2xx_spi_runtime_resume(struct device *dev)
1986 {
1987         struct driver_data *drv_data = dev_get_drvdata(dev);
1988         int status;
1989 
1990         status = clk_prepare_enable(drv_data->ssp->clk);
1991         return status;
1992 }
1993 #endif
1994 
1995 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1996         SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1997         SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1998                            pxa2xx_spi_runtime_resume, NULL)
1999 };
2000 
2001 static struct platform_driver driver = {
2002         .driver = {
2003                 .name   = "pxa2xx-spi",
2004                 .pm     = &pxa2xx_spi_pm_ops,
2005                 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
2006                 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
2007         },
2008         .probe = pxa2xx_spi_probe,
2009         .remove = pxa2xx_spi_remove,
2010 };
2011 
2012 static int __init pxa2xx_spi_init(void)
2013 {
2014         return platform_driver_register(&driver);
2015 }
2016 subsys_initcall(pxa2xx_spi_init);
2017 
2018 static void __exit pxa2xx_spi_exit(void)
2019 {
2020         platform_driver_unregister(&driver);
2021 }
2022 module_exit(pxa2xx_spi_exit);
2023 
2024 MODULE_SOFTDEP("pre: dw_dmac");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/spi/spi-pxa2xx.c

DEFINITIONS
