This source file includes following definitions.
- dspi_pop_tx
- dspi_pop_tx_pushr
- dspi_push_rx
- dspi_tx_dma_callback
- dspi_rx_dma_callback
- dspi_next_xfer_dma_submit
- dspi_dma_xfer
- dspi_request_dma
- dspi_release_dma
- hz_to_spi_baud
- ns_delay_scale
- fifo_write
- cmd_fifo_write
- tx_fifo_write
- dspi_tcfq_write
- fifo_read
- dspi_tcfq_read
- dspi_eoq_write
- dspi_eoq_read
- dspi_rxtx
- dspi_poll
- dspi_interrupt
- dspi_transfer_one_message
- dspi_setup
- dspi_cleanup
- dspi_suspend
- dspi_resume
- dspi_init
- dspi_probe
- dspi_remove
1
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5
6
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dmaengine.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/regmap.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/spi-fsl-dspi.h>
20
21 #define DRIVER_NAME "fsl-dspi"
22
23 #ifdef CONFIG_M5441x
24 #define DSPI_FIFO_SIZE 16
25 #else
26 #define DSPI_FIFO_SIZE 4
27 #endif
28 #define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024)
29
30 #define SPI_MCR 0x00
31 #define SPI_MCR_MASTER BIT(31)
32 #define SPI_MCR_PCSIS (0x3F << 16)
33 #define SPI_MCR_CLR_TXF BIT(11)
34 #define SPI_MCR_CLR_RXF BIT(10)
35 #define SPI_MCR_XSPI BIT(3)
36
37 #define SPI_TCR 0x08
38 #define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16)
39
40 #define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4))
41 #define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27))
42 #define SPI_CTAR_CPOL BIT(26)
43 #define SPI_CTAR_CPHA BIT(25)
44 #define SPI_CTAR_LSBFE BIT(24)
45 #define SPI_CTAR_PCSSCK(x) (((x) << 22) & GENMASK(23, 22))
46 #define SPI_CTAR_PASC(x) (((x) << 20) & GENMASK(21, 20))
47 #define SPI_CTAR_PDT(x) (((x) << 18) & GENMASK(19, 18))
48 #define SPI_CTAR_PBR(x) (((x) << 16) & GENMASK(17, 16))
49 #define SPI_CTAR_CSSCK(x) (((x) << 12) & GENMASK(15, 12))
50 #define SPI_CTAR_ASC(x) (((x) << 8) & GENMASK(11, 8))
51 #define SPI_CTAR_DT(x) (((x) << 4) & GENMASK(7, 4))
52 #define SPI_CTAR_BR(x) ((x) & GENMASK(3, 0))
53 #define SPI_CTAR_SCALE_BITS 0xf
54
55 #define SPI_CTAR0_SLAVE 0x0c
56
57 #define SPI_SR 0x2c
58 #define SPI_SR_TCFQF BIT(31)
59 #define SPI_SR_EOQF BIT(28)
60 #define SPI_SR_TFUF BIT(27)
61 #define SPI_SR_TFFF BIT(25)
62 #define SPI_SR_CMDTCF BIT(23)
63 #define SPI_SR_SPEF BIT(21)
64 #define SPI_SR_RFOF BIT(19)
65 #define SPI_SR_TFIWF BIT(18)
66 #define SPI_SR_RFDF BIT(17)
67 #define SPI_SR_CMDFFF BIT(16)
68 #define SPI_SR_CLEAR (SPI_SR_TCFQF | SPI_SR_EOQF | \
69 SPI_SR_TFUF | SPI_SR_TFFF | \
70 SPI_SR_CMDTCF | SPI_SR_SPEF | \
71 SPI_SR_RFOF | SPI_SR_TFIWF | \
72 SPI_SR_RFDF | SPI_SR_CMDFFF)
73
74 #define SPI_RSER_TFFFE BIT(25)
75 #define SPI_RSER_TFFFD BIT(24)
76 #define SPI_RSER_RFDFE BIT(17)
77 #define SPI_RSER_RFDFD BIT(16)
78
79 #define SPI_RSER 0x30
80 #define SPI_RSER_TCFQE BIT(31)
81 #define SPI_RSER_EOQFE BIT(28)
82
83 #define SPI_PUSHR 0x34
84 #define SPI_PUSHR_CMD_CONT BIT(15)
85 #define SPI_PUSHR_CMD_CTAS(x) (((x) << 12 & GENMASK(14, 12)))
86 #define SPI_PUSHR_CMD_EOQ BIT(11)
87 #define SPI_PUSHR_CMD_CTCNT BIT(10)
88 #define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0))
89
90 #define SPI_PUSHR_SLAVE 0x34
91
92 #define SPI_POPR 0x38
93
94 #define SPI_TXFR0 0x3c
95 #define SPI_TXFR1 0x40
96 #define SPI_TXFR2 0x44
97 #define SPI_TXFR3 0x48
98 #define SPI_RXFR0 0x7c
99 #define SPI_RXFR1 0x80
100 #define SPI_RXFR2 0x84
101 #define SPI_RXFR3 0x88
102
103 #define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4))
104 #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
105 #define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
106
107 #define SPI_SREX 0x13c
108
109 #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
110 #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
111
112
113 #define PUSHR_CMD 0x0
114 #define PUSHR_TX 0x2
115
116 #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
117
118 struct chip_data {
119 u32 ctar_val;
120 u16 void_write_data;
121 };
122
123 enum dspi_trans_mode {
124 DSPI_EOQ_MODE = 0,
125 DSPI_TCFQ_MODE,
126 DSPI_DMA_MODE,
127 };
128
129 struct fsl_dspi_devtype_data {
130 enum dspi_trans_mode trans_mode;
131 u8 max_clock_factor;
132 bool xspi_mode;
133 };
134
135 static const struct fsl_dspi_devtype_data vf610_data = {
136 .trans_mode = DSPI_DMA_MODE,
137 .max_clock_factor = 2,
138 };
139
140 static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
141 .trans_mode = DSPI_TCFQ_MODE,
142 .max_clock_factor = 8,
143 .xspi_mode = true,
144 };
145
146 static const struct fsl_dspi_devtype_data ls2085a_data = {
147 .trans_mode = DSPI_TCFQ_MODE,
148 .max_clock_factor = 8,
149 };
150
151 static const struct fsl_dspi_devtype_data coldfire_data = {
152 .trans_mode = DSPI_EOQ_MODE,
153 .max_clock_factor = 8,
154 };
155
156 struct fsl_dspi_dma {
157
158 u32 curr_xfer_len;
159
160 u32 *tx_dma_buf;
161 struct dma_chan *chan_tx;
162 dma_addr_t tx_dma_phys;
163 struct completion cmd_tx_complete;
164 struct dma_async_tx_descriptor *tx_desc;
165
166 u32 *rx_dma_buf;
167 struct dma_chan *chan_rx;
168 dma_addr_t rx_dma_phys;
169 struct completion cmd_rx_complete;
170 struct dma_async_tx_descriptor *rx_desc;
171 };
172
173 struct fsl_dspi {
174 struct spi_controller *ctlr;
175 struct platform_device *pdev;
176
177 struct regmap *regmap;
178 struct regmap *regmap_pushr;
179 int irq;
180 struct clk *clk;
181
182 struct spi_transfer *cur_transfer;
183 struct spi_message *cur_msg;
184 struct chip_data *cur_chip;
185 size_t len;
186 const void *tx;
187 void *rx;
188 void *rx_end;
189 u16 void_write_data;
190 u16 tx_cmd;
191 u8 bits_per_word;
192 u8 bytes_per_word;
193 const struct fsl_dspi_devtype_data *devtype_data;
194
195 struct completion xfer_done;
196
197 struct fsl_dspi_dma *dma;
198 };
199
200 static u32 dspi_pop_tx(struct fsl_dspi *dspi)
201 {
202 u32 txdata = 0;
203
204 if (dspi->tx) {
205 if (dspi->bytes_per_word == 1)
206 txdata = *(u8 *)dspi->tx;
207 else if (dspi->bytes_per_word == 2)
208 txdata = *(u16 *)dspi->tx;
209 else
210 txdata = *(u32 *)dspi->tx;
211 dspi->tx += dspi->bytes_per_word;
212 }
213 dspi->len -= dspi->bytes_per_word;
214 return txdata;
215 }
216
217 static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
218 {
219 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
220
221 if (spi_controller_is_slave(dspi->ctlr))
222 return data;
223
224 if (dspi->len > 0)
225 cmd |= SPI_PUSHR_CMD_CONT;
226 return cmd << 16 | data;
227 }
228
229 static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
230 {
231 if (!dspi->rx)
232 return;
233
234
235 rxdata &= (1 << dspi->bits_per_word) - 1;
236
237 if (dspi->bytes_per_word == 1)
238 *(u8 *)dspi->rx = rxdata;
239 else if (dspi->bytes_per_word == 2)
240 *(u16 *)dspi->rx = rxdata;
241 else
242 *(u32 *)dspi->rx = rxdata;
243 dspi->rx += dspi->bytes_per_word;
244 }
245
246 static void dspi_tx_dma_callback(void *arg)
247 {
248 struct fsl_dspi *dspi = arg;
249 struct fsl_dspi_dma *dma = dspi->dma;
250
251 complete(&dma->cmd_tx_complete);
252 }
253
254 static void dspi_rx_dma_callback(void *arg)
255 {
256 struct fsl_dspi *dspi = arg;
257 struct fsl_dspi_dma *dma = dspi->dma;
258 int i;
259
260 if (dspi->rx) {
261 for (i = 0; i < dma->curr_xfer_len; i++)
262 dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
263 }
264
265 complete(&dma->cmd_rx_complete);
266 }
267
268 static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
269 {
270 struct device *dev = &dspi->pdev->dev;
271 struct fsl_dspi_dma *dma = dspi->dma;
272 int time_left;
273 int i;
274
275 for (i = 0; i < dma->curr_xfer_len; i++)
276 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
277
278 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
279 dma->tx_dma_phys,
280 dma->curr_xfer_len *
281 DMA_SLAVE_BUSWIDTH_4_BYTES,
282 DMA_MEM_TO_DEV,
283 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
284 if (!dma->tx_desc) {
285 dev_err(dev, "Not able to get desc for DMA xfer\n");
286 return -EIO;
287 }
288
289 dma->tx_desc->callback = dspi_tx_dma_callback;
290 dma->tx_desc->callback_param = dspi;
291 if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
292 dev_err(dev, "DMA submit failed\n");
293 return -EINVAL;
294 }
295
296 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
297 dma->rx_dma_phys,
298 dma->curr_xfer_len *
299 DMA_SLAVE_BUSWIDTH_4_BYTES,
300 DMA_DEV_TO_MEM,
301 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
302 if (!dma->rx_desc) {
303 dev_err(dev, "Not able to get desc for DMA xfer\n");
304 return -EIO;
305 }
306
307 dma->rx_desc->callback = dspi_rx_dma_callback;
308 dma->rx_desc->callback_param = dspi;
309 if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
310 dev_err(dev, "DMA submit failed\n");
311 return -EINVAL;
312 }
313
314 reinit_completion(&dspi->dma->cmd_rx_complete);
315 reinit_completion(&dspi->dma->cmd_tx_complete);
316
317 dma_async_issue_pending(dma->chan_rx);
318 dma_async_issue_pending(dma->chan_tx);
319
320 if (spi_controller_is_slave(dspi->ctlr)) {
321 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
322 return 0;
323 }
324
325 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
326 DMA_COMPLETION_TIMEOUT);
327 if (time_left == 0) {
328 dev_err(dev, "DMA tx timeout\n");
329 dmaengine_terminate_all(dma->chan_tx);
330 dmaengine_terminate_all(dma->chan_rx);
331 return -ETIMEDOUT;
332 }
333
334 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
335 DMA_COMPLETION_TIMEOUT);
336 if (time_left == 0) {
337 dev_err(dev, "DMA rx timeout\n");
338 dmaengine_terminate_all(dma->chan_tx);
339 dmaengine_terminate_all(dma->chan_rx);
340 return -ETIMEDOUT;
341 }
342
343 return 0;
344 }
345
346 static int dspi_dma_xfer(struct fsl_dspi *dspi)
347 {
348 struct spi_message *message = dspi->cur_msg;
349 struct device *dev = &dspi->pdev->dev;
350 struct fsl_dspi_dma *dma = dspi->dma;
351 int curr_remaining_bytes;
352 int bytes_per_buffer;
353 int ret = 0;
354
355 curr_remaining_bytes = dspi->len;
356 bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE;
357 while (curr_remaining_bytes) {
358
359 dma->curr_xfer_len = curr_remaining_bytes
360 / dspi->bytes_per_word;
361 if (dma->curr_xfer_len > bytes_per_buffer)
362 dma->curr_xfer_len = bytes_per_buffer;
363
364 ret = dspi_next_xfer_dma_submit(dspi);
365 if (ret) {
366 dev_err(dev, "DMA transfer failed\n");
367 goto exit;
368
369 } else {
370 const int len =
371 dma->curr_xfer_len * dspi->bytes_per_word;
372 curr_remaining_bytes -= len;
373 message->actual_length += len;
374 if (curr_remaining_bytes < 0)
375 curr_remaining_bytes = 0;
376 }
377 }
378
379 exit:
380 return ret;
381 }
382
383 static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
384 {
385 struct device *dev = &dspi->pdev->dev;
386 struct dma_slave_config cfg;
387 struct fsl_dspi_dma *dma;
388 int ret;
389
390 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
391 if (!dma)
392 return -ENOMEM;
393
394 dma->chan_rx = dma_request_slave_channel(dev, "rx");
395 if (!dma->chan_rx) {
396 dev_err(dev, "rx dma channel not available\n");
397 ret = -ENODEV;
398 return ret;
399 }
400
401 dma->chan_tx = dma_request_slave_channel(dev, "tx");
402 if (!dma->chan_tx) {
403 dev_err(dev, "tx dma channel not available\n");
404 ret = -ENODEV;
405 goto err_tx_channel;
406 }
407
408 dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
409 &dma->tx_dma_phys, GFP_KERNEL);
410 if (!dma->tx_dma_buf) {
411 ret = -ENOMEM;
412 goto err_tx_dma_buf;
413 }
414
415 dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
416 &dma->rx_dma_phys, GFP_KERNEL);
417 if (!dma->rx_dma_buf) {
418 ret = -ENOMEM;
419 goto err_rx_dma_buf;
420 }
421
422 cfg.src_addr = phy_addr + SPI_POPR;
423 cfg.dst_addr = phy_addr + SPI_PUSHR;
424 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
425 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
426 cfg.src_maxburst = 1;
427 cfg.dst_maxburst = 1;
428
429 cfg.direction = DMA_DEV_TO_MEM;
430 ret = dmaengine_slave_config(dma->chan_rx, &cfg);
431 if (ret) {
432 dev_err(dev, "can't configure rx dma channel\n");
433 ret = -EINVAL;
434 goto err_slave_config;
435 }
436
437 cfg.direction = DMA_MEM_TO_DEV;
438 ret = dmaengine_slave_config(dma->chan_tx, &cfg);
439 if (ret) {
440 dev_err(dev, "can't configure tx dma channel\n");
441 ret = -EINVAL;
442 goto err_slave_config;
443 }
444
445 dspi->dma = dma;
446 init_completion(&dma->cmd_tx_complete);
447 init_completion(&dma->cmd_rx_complete);
448
449 return 0;
450
451 err_slave_config:
452 dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
453 dma->rx_dma_buf, dma->rx_dma_phys);
454 err_rx_dma_buf:
455 dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
456 dma->tx_dma_buf, dma->tx_dma_phys);
457 err_tx_dma_buf:
458 dma_release_channel(dma->chan_tx);
459 err_tx_channel:
460 dma_release_channel(dma->chan_rx);
461
462 devm_kfree(dev, dma);
463 dspi->dma = NULL;
464
465 return ret;
466 }
467
468 static void dspi_release_dma(struct fsl_dspi *dspi)
469 {
470 struct fsl_dspi_dma *dma = dspi->dma;
471 struct device *dev = &dspi->pdev->dev;
472
473 if (!dma)
474 return;
475
476 if (dma->chan_tx) {
477 dma_unmap_single(dev, dma->tx_dma_phys,
478 DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
479 dma_release_channel(dma->chan_tx);
480 }
481
482 if (dma->chan_rx) {
483 dma_unmap_single(dev, dma->rx_dma_phys,
484 DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
485 dma_release_channel(dma->chan_rx);
486 }
487 }
488
489 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
490 unsigned long clkrate)
491 {
492
493 int pbr_tbl[4] = {2, 3, 5, 7};
494 int brs[16] = { 2, 4, 6, 8,
495 16, 32, 64, 128,
496 256, 512, 1024, 2048,
497 4096, 8192, 16384, 32768 };
498 int scale_needed, scale, minscale = INT_MAX;
499 int i, j;
500
501 scale_needed = clkrate / speed_hz;
502 if (clkrate % speed_hz)
503 scale_needed++;
504
505 for (i = 0; i < ARRAY_SIZE(brs); i++)
506 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
507 scale = brs[i] * pbr_tbl[j];
508 if (scale >= scale_needed) {
509 if (scale < minscale) {
510 minscale = scale;
511 *br = i;
512 *pbr = j;
513 }
514 break;
515 }
516 }
517
518 if (minscale == INT_MAX) {
519 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
520 speed_hz, clkrate);
521 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
522 *br = ARRAY_SIZE(brs) - 1;
523 }
524 }
525
526 static void ns_delay_scale(char *psc, char *sc, int delay_ns,
527 unsigned long clkrate)
528 {
529 int scale_needed, scale, minscale = INT_MAX;
530 int pscale_tbl[4] = {1, 3, 5, 7};
531 u32 remainder;
532 int i, j;
533
534 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
535 &remainder);
536 if (remainder)
537 scale_needed++;
538
539 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
540 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
541 scale = pscale_tbl[i] * (2 << j);
542 if (scale >= scale_needed) {
543 if (scale < minscale) {
544 minscale = scale;
545 *psc = i;
546 *sc = j;
547 }
548 break;
549 }
550 }
551
552 if (minscale == INT_MAX) {
553 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
554 delay_ns, clkrate);
555 *psc = ARRAY_SIZE(pscale_tbl) - 1;
556 *sc = SPI_CTAR_SCALE_BITS;
557 }
558 }
559
560 static void fifo_write(struct fsl_dspi *dspi)
561 {
562 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi));
563 }
564
565 static void cmd_fifo_write(struct fsl_dspi *dspi)
566 {
567 u16 cmd = dspi->tx_cmd;
568
569 if (dspi->len > 0)
570 cmd |= SPI_PUSHR_CMD_CONT;
571 regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd);
572 }
573
574 static void tx_fifo_write(struct fsl_dspi *dspi, u16 txdata)
575 {
576 regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata);
577 }
578
579 static void dspi_tcfq_write(struct fsl_dspi *dspi)
580 {
581
582 dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
583
584 if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) {
585
586
587
588 u32 data = dspi_pop_tx(dspi);
589
590 cmd_fifo_write(dspi);
591 tx_fifo_write(dspi, data & 0xFFFF);
592 tx_fifo_write(dspi, data >> 16);
593 } else {
594
595
596
597 fifo_write(dspi);
598 }
599 }
600
601 static u32 fifo_read(struct fsl_dspi *dspi)
602 {
603 u32 rxdata = 0;
604
605 regmap_read(dspi->regmap, SPI_POPR, &rxdata);
606 return rxdata;
607 }
608
609 static void dspi_tcfq_read(struct fsl_dspi *dspi)
610 {
611 dspi_push_rx(dspi, fifo_read(dspi));
612 }
613
614 static void dspi_eoq_write(struct fsl_dspi *dspi)
615 {
616 int fifo_size = DSPI_FIFO_SIZE;
617 u16 xfer_cmd = dspi->tx_cmd;
618
619
620 while (dspi->len && fifo_size--) {
621 dspi->tx_cmd = xfer_cmd;
622
623 if (dspi->len == dspi->bytes_per_word || fifo_size == 0)
624 dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ;
625
626 if (fifo_size == (DSPI_FIFO_SIZE - 1))
627 dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
628
629 fifo_write(dspi);
630 }
631 }
632
633 static void dspi_eoq_read(struct fsl_dspi *dspi)
634 {
635 int fifo_size = DSPI_FIFO_SIZE;
636
637
638 while ((dspi->rx < dspi->rx_end) && fifo_size--)
639 dspi_push_rx(dspi, fifo_read(dspi));
640 }
641
642 static int dspi_rxtx(struct fsl_dspi *dspi)
643 {
644 struct spi_message *msg = dspi->cur_msg;
645 enum dspi_trans_mode trans_mode;
646 u16 spi_tcnt;
647 u32 spi_tcr;
648
649
650
651
652 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
653 spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
654
655 msg->actual_length += spi_tcnt * dspi->bytes_per_word;
656
657 trans_mode = dspi->devtype_data->trans_mode;
658 if (trans_mode == DSPI_EOQ_MODE)
659 dspi_eoq_read(dspi);
660 else if (trans_mode == DSPI_TCFQ_MODE)
661 dspi_tcfq_read(dspi);
662
663 if (!dspi->len)
664
665 return 0;
666
667 if (trans_mode == DSPI_EOQ_MODE)
668 dspi_eoq_write(dspi);
669 else if (trans_mode == DSPI_TCFQ_MODE)
670 dspi_tcfq_write(dspi);
671
672 return -EINPROGRESS;
673 }
674
675 static int dspi_poll(struct fsl_dspi *dspi)
676 {
677 int tries = 1000;
678 u32 spi_sr;
679
680 do {
681 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
682 regmap_write(dspi->regmap, SPI_SR, spi_sr);
683
684 if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF))
685 break;
686 } while (--tries);
687
688 if (!tries)
689 return -ETIMEDOUT;
690
691 return dspi_rxtx(dspi);
692 }
693
694 static irqreturn_t dspi_interrupt(int irq, void *dev_id)
695 {
696 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
697 u32 spi_sr;
698
699 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
700 regmap_write(dspi->regmap, SPI_SR, spi_sr);
701
702 if (!(spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)))
703 return IRQ_NONE;
704
705 if (dspi_rxtx(dspi) == 0)
706 complete(&dspi->xfer_done);
707
708 return IRQ_HANDLED;
709 }
710
711 static int dspi_transfer_one_message(struct spi_controller *ctlr,
712 struct spi_message *message)
713 {
714 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
715 struct spi_device *spi = message->spi;
716 enum dspi_trans_mode trans_mode;
717 struct spi_transfer *transfer;
718 int status = 0;
719
720 message->actual_length = 0;
721
722 list_for_each_entry(transfer, &message->transfers, transfer_list) {
723 dspi->cur_transfer = transfer;
724 dspi->cur_msg = message;
725 dspi->cur_chip = spi_get_ctldata(spi);
726
727 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
728 SPI_PUSHR_CMD_PCS(spi->chip_select);
729 if (list_is_last(&dspi->cur_transfer->transfer_list,
730 &dspi->cur_msg->transfers)) {
731
732
733
734 if (transfer->cs_change)
735 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
736 } else {
737
738
739
740
741
742 if (!transfer->cs_change)
743 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
744 }
745
746 dspi->void_write_data = dspi->cur_chip->void_write_data;
747
748 dspi->tx = transfer->tx_buf;
749 dspi->rx = transfer->rx_buf;
750 dspi->rx_end = dspi->rx + transfer->len;
751 dspi->len = transfer->len;
752
753 dspi->bits_per_word = transfer->bits_per_word;
754 if (transfer->bits_per_word <= 8)
755 dspi->bytes_per_word = 1;
756 else if (transfer->bits_per_word <= 16)
757 dspi->bytes_per_word = 2;
758 else
759 dspi->bytes_per_word = 4;
760
761 regmap_update_bits(dspi->regmap, SPI_MCR,
762 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
763 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
764 regmap_write(dspi->regmap, SPI_CTAR(0),
765 dspi->cur_chip->ctar_val |
766 SPI_FRAME_BITS(transfer->bits_per_word));
767 if (dspi->devtype_data->xspi_mode)
768 regmap_write(dspi->regmap, SPI_CTARE(0),
769 SPI_FRAME_EBITS(transfer->bits_per_word) |
770 SPI_CTARE_DTCP(1));
771
772 trans_mode = dspi->devtype_data->trans_mode;
773 switch (trans_mode) {
774 case DSPI_EOQ_MODE:
775 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
776 dspi_eoq_write(dspi);
777 break;
778 case DSPI_TCFQ_MODE:
779 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
780 dspi_tcfq_write(dspi);
781 break;
782 case DSPI_DMA_MODE:
783 regmap_write(dspi->regmap, SPI_RSER,
784 SPI_RSER_TFFFE | SPI_RSER_TFFFD |
785 SPI_RSER_RFDFE | SPI_RSER_RFDFD);
786 status = dspi_dma_xfer(dspi);
787 break;
788 default:
789 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
790 trans_mode);
791 status = -EINVAL;
792 goto out;
793 }
794
795 if (!dspi->irq) {
796 do {
797 status = dspi_poll(dspi);
798 } while (status == -EINPROGRESS);
799 } else if (trans_mode != DSPI_DMA_MODE) {
800 wait_for_completion(&dspi->xfer_done);
801 reinit_completion(&dspi->xfer_done);
802 }
803
804 if (transfer->delay_usecs)
805 udelay(transfer->delay_usecs);
806 }
807
808 out:
809 message->status = status;
810 spi_finalize_current_message(ctlr);
811
812 return status;
813 }
814
815 static int dspi_setup(struct spi_device *spi)
816 {
817 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
818 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
819 u32 cs_sck_delay = 0, sck_cs_delay = 0;
820 struct fsl_dspi_platform_data *pdata;
821 unsigned char pasc = 0, asc = 0;
822 struct chip_data *chip;
823 unsigned long clkrate;
824
825
826 chip = spi_get_ctldata(spi);
827 if (chip == NULL) {
828 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
829 if (!chip)
830 return -ENOMEM;
831 }
832
833 pdata = dev_get_platdata(&dspi->pdev->dev);
834
835 if (!pdata) {
836 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
837 &cs_sck_delay);
838
839 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
840 &sck_cs_delay);
841 } else {
842 cs_sck_delay = pdata->cs_sck_delay;
843 sck_cs_delay = pdata->sck_cs_delay;
844 }
845
846 chip->void_write_data = 0;
847
848 clkrate = clk_get_rate(dspi->clk);
849 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
850
851
852 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
853
854
855 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
856
857 chip->ctar_val = 0;
858 if (spi->mode & SPI_CPOL)
859 chip->ctar_val |= SPI_CTAR_CPOL;
860 if (spi->mode & SPI_CPHA)
861 chip->ctar_val |= SPI_CTAR_CPHA;
862
863 if (!spi_controller_is_slave(dspi->ctlr)) {
864 chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
865 SPI_CTAR_CSSCK(cssck) |
866 SPI_CTAR_PASC(pasc) |
867 SPI_CTAR_ASC(asc) |
868 SPI_CTAR_PBR(pbr) |
869 SPI_CTAR_BR(br);
870
871 if (spi->mode & SPI_LSB_FIRST)
872 chip->ctar_val |= SPI_CTAR_LSBFE;
873 }
874
875 spi_set_ctldata(spi, chip);
876
877 return 0;
878 }
879
880 static void dspi_cleanup(struct spi_device *spi)
881 {
882 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
883
884 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
885 spi->controller->bus_num, spi->chip_select);
886
887 kfree(chip);
888 }
889
890 static const struct of_device_id fsl_dspi_dt_ids[] = {
891 { .compatible = "fsl,vf610-dspi", .data = &vf610_data, },
892 { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, },
893 { .compatible = "fsl,ls2085a-dspi", .data = &ls2085a_data, },
894 { }
895 };
896 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
897
898 #ifdef CONFIG_PM_SLEEP
899 static int dspi_suspend(struct device *dev)
900 {
901 struct spi_controller *ctlr = dev_get_drvdata(dev);
902 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
903
904 spi_controller_suspend(ctlr);
905 clk_disable_unprepare(dspi->clk);
906
907 pinctrl_pm_select_sleep_state(dev);
908
909 return 0;
910 }
911
912 static int dspi_resume(struct device *dev)
913 {
914 struct spi_controller *ctlr = dev_get_drvdata(dev);
915 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
916 int ret;
917
918 pinctrl_pm_select_default_state(dev);
919
920 ret = clk_prepare_enable(dspi->clk);
921 if (ret)
922 return ret;
923 spi_controller_resume(ctlr);
924
925 return 0;
926 }
927 #endif
928
929 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
930
931 static const struct regmap_range dspi_volatile_ranges[] = {
932 regmap_reg_range(SPI_MCR, SPI_TCR),
933 regmap_reg_range(SPI_SR, SPI_SR),
934 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
935 };
936
937 static const struct regmap_access_table dspi_volatile_table = {
938 .yes_ranges = dspi_volatile_ranges,
939 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
940 };
941
942 static const struct regmap_config dspi_regmap_config = {
943 .reg_bits = 32,
944 .val_bits = 32,
945 .reg_stride = 4,
946 .max_register = 0x88,
947 .volatile_table = &dspi_volatile_table,
948 };
949
950 static const struct regmap_range dspi_xspi_volatile_ranges[] = {
951 regmap_reg_range(SPI_MCR, SPI_TCR),
952 regmap_reg_range(SPI_SR, SPI_SR),
953 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
954 regmap_reg_range(SPI_SREX, SPI_SREX),
955 };
956
957 static const struct regmap_access_table dspi_xspi_volatile_table = {
958 .yes_ranges = dspi_xspi_volatile_ranges,
959 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
960 };
961
962 static const struct regmap_config dspi_xspi_regmap_config[] = {
963 {
964 .reg_bits = 32,
965 .val_bits = 32,
966 .reg_stride = 4,
967 .max_register = 0x13c,
968 .volatile_table = &dspi_xspi_volatile_table,
969 },
970 {
971 .name = "pushr",
972 .reg_bits = 16,
973 .val_bits = 16,
974 .reg_stride = 2,
975 .max_register = 0x2,
976 },
977 };
978
979 static void dspi_init(struct fsl_dspi *dspi)
980 {
981 unsigned int mcr = SPI_MCR_PCSIS;
982
983 if (dspi->devtype_data->xspi_mode)
984 mcr |= SPI_MCR_XSPI;
985 if (!spi_controller_is_slave(dspi->ctlr))
986 mcr |= SPI_MCR_MASTER;
987
988 regmap_write(dspi->regmap, SPI_MCR, mcr);
989 regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
990 if (dspi->devtype_data->xspi_mode)
991 regmap_write(dspi->regmap, SPI_CTARE(0),
992 SPI_CTARE_FMSZE(0) | SPI_CTARE_DTCP(1));
993 }
994
995 static int dspi_probe(struct platform_device *pdev)
996 {
997 struct device_node *np = pdev->dev.of_node;
998 const struct regmap_config *regmap_config;
999 struct fsl_dspi_platform_data *pdata;
1000 struct spi_controller *ctlr;
1001 int ret, cs_num, bus_num;
1002 struct fsl_dspi *dspi;
1003 struct resource *res;
1004 void __iomem *base;
1005
1006 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
1007 if (!ctlr)
1008 return -ENOMEM;
1009
1010 dspi = spi_controller_get_devdata(ctlr);
1011 dspi->pdev = pdev;
1012 dspi->ctlr = ctlr;
1013
1014 ctlr->setup = dspi_setup;
1015 ctlr->transfer_one_message = dspi_transfer_one_message;
1016 ctlr->dev.of_node = pdev->dev.of_node;
1017
1018 ctlr->cleanup = dspi_cleanup;
1019 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1020
1021 pdata = dev_get_platdata(&pdev->dev);
1022 if (pdata) {
1023 ctlr->num_chipselect = pdata->cs_num;
1024 ctlr->bus_num = pdata->bus_num;
1025
1026 dspi->devtype_data = &coldfire_data;
1027 } else {
1028
1029 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1030 if (ret < 0) {
1031 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1032 goto out_ctlr_put;
1033 }
1034 ctlr->num_chipselect = cs_num;
1035
1036 ret = of_property_read_u32(np, "bus-num", &bus_num);
1037 if (ret < 0) {
1038 dev_err(&pdev->dev, "can't get bus-num\n");
1039 goto out_ctlr_put;
1040 }
1041 ctlr->bus_num = bus_num;
1042
1043 if (of_property_read_bool(np, "spi-slave"))
1044 ctlr->slave = true;
1045
1046 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1047 if (!dspi->devtype_data) {
1048 dev_err(&pdev->dev, "can't get devtype_data\n");
1049 ret = -EFAULT;
1050 goto out_ctlr_put;
1051 }
1052 }
1053
1054 if (dspi->devtype_data->xspi_mode)
1055 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1056 else
1057 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1058
1059 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1060 base = devm_ioremap_resource(&pdev->dev, res);
1061 if (IS_ERR(base)) {
1062 ret = PTR_ERR(base);
1063 goto out_ctlr_put;
1064 }
1065
1066 if (dspi->devtype_data->xspi_mode)
1067 regmap_config = &dspi_xspi_regmap_config[0];
1068 else
1069 regmap_config = &dspi_regmap_config;
1070 dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1071 if (IS_ERR(dspi->regmap)) {
1072 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1073 PTR_ERR(dspi->regmap));
1074 ret = PTR_ERR(dspi->regmap);
1075 goto out_ctlr_put;
1076 }
1077
1078 if (dspi->devtype_data->xspi_mode) {
1079 dspi->regmap_pushr = devm_regmap_init_mmio(
1080 &pdev->dev, base + SPI_PUSHR,
1081 &dspi_xspi_regmap_config[1]);
1082 if (IS_ERR(dspi->regmap_pushr)) {
1083 dev_err(&pdev->dev,
1084 "failed to init pushr regmap: %ld\n",
1085 PTR_ERR(dspi->regmap_pushr));
1086 ret = PTR_ERR(dspi->regmap_pushr);
1087 goto out_ctlr_put;
1088 }
1089 }
1090
1091 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
1092 if (IS_ERR(dspi->clk)) {
1093 ret = PTR_ERR(dspi->clk);
1094 dev_err(&pdev->dev, "unable to get clock\n");
1095 goto out_ctlr_put;
1096 }
1097 ret = clk_prepare_enable(dspi->clk);
1098 if (ret)
1099 goto out_ctlr_put;
1100
1101 dspi_init(dspi);
1102
1103 dspi->irq = platform_get_irq(pdev, 0);
1104 if (dspi->irq <= 0) {
1105 dev_info(&pdev->dev,
1106 "can't get platform irq, using poll mode\n");
1107 dspi->irq = 0;
1108 goto poll_mode;
1109 }
1110
1111 ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt,
1112 IRQF_SHARED, pdev->name, dspi);
1113 if (ret < 0) {
1114 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1115 goto out_clk_put;
1116 }
1117
1118 init_completion(&dspi->xfer_done);
1119
1120 poll_mode:
1121 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1122 ret = dspi_request_dma(dspi, res->start);
1123 if (ret < 0) {
1124 dev_err(&pdev->dev, "can't get dma channels\n");
1125 goto out_clk_put;
1126 }
1127 }
1128
1129 ctlr->max_speed_hz =
1130 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1131
1132 platform_set_drvdata(pdev, ctlr);
1133
1134 ret = spi_register_controller(ctlr);
1135 if (ret != 0) {
1136 dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
1137 goto out_clk_put;
1138 }
1139
1140 return ret;
1141
1142 out_clk_put:
1143 clk_disable_unprepare(dspi->clk);
1144 out_ctlr_put:
1145 spi_controller_put(ctlr);
1146
1147 return ret;
1148 }
1149
1150 static int dspi_remove(struct platform_device *pdev)
1151 {
1152 struct spi_controller *ctlr = platform_get_drvdata(pdev);
1153 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
1154
1155
1156 dspi_release_dma(dspi);
1157 clk_disable_unprepare(dspi->clk);
1158 spi_unregister_controller(dspi->ctlr);
1159
1160 return 0;
1161 }
1162
1163 static struct platform_driver fsl_dspi_driver = {
1164 .driver.name = DRIVER_NAME,
1165 .driver.of_match_table = fsl_dspi_dt_ids,
1166 .driver.owner = THIS_MODULE,
1167 .driver.pm = &dspi_pm,
1168 .probe = dspi_probe,
1169 .remove = dspi_remove,
1170 };
1171 module_platform_driver(fsl_dspi_driver);
1172
1173 MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1174 MODULE_LICENSE("GPL");
1175 MODULE_ALIAS("platform:" DRIVER_NAME);