drivers/spi/spi-sun6i.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
sun6i_spi_read
sun6i_spi_write
sun6i_spi_get_tx_fifo_count
sun6i_spi_enable_interrupt
sun6i_spi_disable_interrupt
sun6i_spi_drain_fifo
sun6i_spi_fill_fifo
sun6i_spi_set_cs
sun6i_spi_max_transfer_size
sun6i_spi_transfer_one
sun6i_spi_handler
sun6i_spi_runtime_resume
sun6i_spi_runtime_suspend
sun6i_spi_probe
sun6i_spi_remove
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2012 - 2014 Allwinner Tech
   4  * Pan Nan <pannan@allwinnertech.com>
   5  *
   6  * Copyright (C) 2014 Maxime Ripard
   7  * Maxime Ripard <maxime.ripard@free-electrons.com>
   8  */
   9 
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/device.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/module.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/reset.h>
  20 
  21 #include <linux/spi/spi.h>
  22 
  23 #define SUN6I_FIFO_DEPTH                128
  24 #define SUN8I_FIFO_DEPTH                64
  25 
  26 #define SUN6I_GBL_CTL_REG               0x04
  27 #define SUN6I_GBL_CTL_BUS_ENABLE                BIT(0)
  28 #define SUN6I_GBL_CTL_MASTER                    BIT(1)
  29 #define SUN6I_GBL_CTL_TP                        BIT(7)
  30 #define SUN6I_GBL_CTL_RST                       BIT(31)
  31 
  32 #define SUN6I_TFR_CTL_REG               0x08
  33 #define SUN6I_TFR_CTL_CPHA                      BIT(0)
  34 #define SUN6I_TFR_CTL_CPOL                      BIT(1)
  35 #define SUN6I_TFR_CTL_SPOL                      BIT(2)
  36 #define SUN6I_TFR_CTL_CS_MASK                   0x30
  37 #define SUN6I_TFR_CTL_CS(cs)                    (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
  38 #define SUN6I_TFR_CTL_CS_MANUAL                 BIT(6)
  39 #define SUN6I_TFR_CTL_CS_LEVEL                  BIT(7)
  40 #define SUN6I_TFR_CTL_DHB                       BIT(8)
  41 #define SUN6I_TFR_CTL_FBS                       BIT(12)
  42 #define SUN6I_TFR_CTL_XCH                       BIT(31)
  43 
  44 #define SUN6I_INT_CTL_REG               0x10
  45 #define SUN6I_INT_CTL_RF_RDY                    BIT(0)
  46 #define SUN6I_INT_CTL_TF_ERQ                    BIT(4)
  47 #define SUN6I_INT_CTL_RF_OVF                    BIT(8)
  48 #define SUN6I_INT_CTL_TC                        BIT(12)
  49 
  50 #define SUN6I_INT_STA_REG               0x14
  51 
  52 #define SUN6I_FIFO_CTL_REG              0x18
  53 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK   0xff
  54 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS   0
  55 #define SUN6I_FIFO_CTL_RF_RST                   BIT(15)
  56 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK   0xff
  57 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS   16
  58 #define SUN6I_FIFO_CTL_TF_RST                   BIT(31)
  59 
  60 #define SUN6I_FIFO_STA_REG              0x1c
  61 #define SUN6I_FIFO_STA_RF_CNT_MASK              0x7f
  62 #define SUN6I_FIFO_STA_RF_CNT_BITS              0
  63 #define SUN6I_FIFO_STA_TF_CNT_MASK              0x7f
  64 #define SUN6I_FIFO_STA_TF_CNT_BITS              16
  65 
  66 #define SUN6I_CLK_CTL_REG               0x24
  67 #define SUN6I_CLK_CTL_CDR2_MASK                 0xff
  68 #define SUN6I_CLK_CTL_CDR2(div)                 (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
  69 #define SUN6I_CLK_CTL_CDR1_MASK                 0xf
  70 #define SUN6I_CLK_CTL_CDR1(div)                 (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
  71 #define SUN6I_CLK_CTL_DRS                       BIT(12)
  72 
  73 #define SUN6I_MAX_XFER_SIZE             0xffffff
  74 
  75 #define SUN6I_BURST_CNT_REG             0x30
  76 #define SUN6I_BURST_CNT(cnt)                    ((cnt) & SUN6I_MAX_XFER_SIZE)
  77 
  78 #define SUN6I_XMIT_CNT_REG              0x34
  79 #define SUN6I_XMIT_CNT(cnt)                     ((cnt) & SUN6I_MAX_XFER_SIZE)
  80 
  81 #define SUN6I_BURST_CTL_CNT_REG         0x38
  82 #define SUN6I_BURST_CTL_CNT_STC(cnt)            ((cnt) & SUN6I_MAX_XFER_SIZE)
  83 
  84 #define SUN6I_TXDATA_REG                0x200
  85 #define SUN6I_RXDATA_REG                0x300
  86 
  87 struct sun6i_spi {
  88         struct spi_master       *master;
  89         void __iomem            *base_addr;
  90         struct clk              *hclk;
  91         struct clk              *mclk;
  92         struct reset_control    *rstc;
  93 
  94         struct completion       done;
  95 
  96         const u8                *tx_buf;
  97         u8                      *rx_buf;
  98         int                     len;
  99         unsigned long           fifo_depth;
 100 };
 101 
 102 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
 103 {
 104         return readl(sspi->base_addr + reg);
 105 }
 106 
 107 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
 108 {
 109         writel(value, sspi->base_addr + reg);
 110 }
 111 
 112 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
 113 {
 114         u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
 115 
 116         reg >>= SUN6I_FIFO_STA_TF_CNT_BITS;
 117 
 118         return reg & SUN6I_FIFO_STA_TF_CNT_MASK;
 119 }
 120 
 121 static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask)
 122 {
 123         u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
 124 
 125         reg |= mask;
 126         sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
 127 }
 128 
 129 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
 130 {
 131         u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
 132 
 133         reg &= ~mask;
 134         sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
 135 }
 136 
 137 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
 138 {
 139         u32 reg, cnt;
 140         u8 byte;
 141 
 142         /* See how much data is available */
 143         reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
 144         reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
 145         cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
 146 
 147         if (len > cnt)
 148                 len = cnt;
 149 
 150         while (len--) {
 151                 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
 152                 if (sspi->rx_buf)
 153                         *sspi->rx_buf++ = byte;
 154         }
 155 }
 156 
 157 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
 158 {
 159         u32 cnt;
 160         u8 byte;
 161 
 162         /* See how much data we can fit */
 163         cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
 164 
 165         len = min3(len, (int)cnt, sspi->len);
 166 
 167         while (len--) {
 168                 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
 169                 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
 170                 sspi->len--;
 171         }
 172 }
 173 
 174 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
 175 {
 176         struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
 177         u32 reg;
 178 
 179         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 180         reg &= ~SUN6I_TFR_CTL_CS_MASK;
 181         reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
 182 
 183         if (enable)
 184                 reg |= SUN6I_TFR_CTL_CS_LEVEL;
 185         else
 186                 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
 187 
 188         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
 189 }
 190 
 191 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
 192 {
 193         return SUN6I_MAX_XFER_SIZE - 1;
 194 }
 195 
 196 static int sun6i_spi_transfer_one(struct spi_master *master,
 197                                   struct spi_device *spi,
 198                                   struct spi_transfer *tfr)
 199 {
 200         struct sun6i_spi *sspi = spi_master_get_devdata(master);
 201         unsigned int mclk_rate, div, timeout;
 202         unsigned int start, end, tx_time;
 203         unsigned int trig_level;
 204         unsigned int tx_len = 0;
 205         int ret = 0;
 206         u32 reg;
 207 
 208         if (tfr->len > SUN6I_MAX_XFER_SIZE)
 209                 return -EINVAL;
 210 
 211         reinit_completion(&sspi->done);
 212         sspi->tx_buf = tfr->tx_buf;
 213         sspi->rx_buf = tfr->rx_buf;
 214         sspi->len = tfr->len;
 215 
 216         /* Clear pending interrupts */
 217         sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
 218 
 219         /* Reset FIFO */
 220         sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
 221                         SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
 222 
 223         /*
 224          * Setup FIFO interrupt trigger level
 225          * Here we choose 3/4 of the full fifo depth, as it's the hardcoded
 226          * value used in old generation of Allwinner SPI controller.
 227          * (See spi-sun4i.c)
 228          */
 229         trig_level = sspi->fifo_depth / 4 * 3;
 230         sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
 231                         (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
 232                         (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));
 233 
 234         /*
 235          * Setup the transfer control register: Chip Select,
 236          * polarities, etc.
 237          */
 238         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 239 
 240         if (spi->mode & SPI_CPOL)
 241                 reg |= SUN6I_TFR_CTL_CPOL;
 242         else
 243                 reg &= ~SUN6I_TFR_CTL_CPOL;
 244 
 245         if (spi->mode & SPI_CPHA)
 246                 reg |= SUN6I_TFR_CTL_CPHA;
 247         else
 248                 reg &= ~SUN6I_TFR_CTL_CPHA;
 249 
 250         if (spi->mode & SPI_LSB_FIRST)
 251                 reg |= SUN6I_TFR_CTL_FBS;
 252         else
 253                 reg &= ~SUN6I_TFR_CTL_FBS;
 254 
 255         /*
 256          * If it's a TX only transfer, we don't want to fill the RX
 257          * FIFO with bogus data
 258          */
 259         if (sspi->rx_buf)
 260                 reg &= ~SUN6I_TFR_CTL_DHB;
 261         else
 262                 reg |= SUN6I_TFR_CTL_DHB;
 263 
 264         /* We want to control the chip select manually */
 265         reg |= SUN6I_TFR_CTL_CS_MANUAL;
 266 
 267         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
 268 
 269         /* Ensure that we have a parent clock fast enough */
 270         mclk_rate = clk_get_rate(sspi->mclk);
 271         if (mclk_rate < (2 * tfr->speed_hz)) {
 272                 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
 273                 mclk_rate = clk_get_rate(sspi->mclk);
 274         }
 275 
 276         /*
 277          * Setup clock divider.
 278          *
 279          * We have two choices there. Either we can use the clock
 280          * divide rate 1, which is calculated thanks to this formula:
 281          * SPI_CLK = MOD_CLK / (2 ^ cdr)
 282          * Or we can use CDR2, which is calculated with the formula:
 283          * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
 284          * Wether we use the former or the latter is set through the
 285          * DRS bit.
 286          *
 287          * First try CDR2, and if we can't reach the expected
 288          * frequency, fall back to CDR1.
 289          */
 290         div = mclk_rate / (2 * tfr->speed_hz);
 291         if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
 292                 if (div > 0)
 293                         div--;
 294 
 295                 reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
 296         } else {
 297                 div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
 298                 reg = SUN6I_CLK_CTL_CDR1(div);
 299         }
 300 
 301         sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
 302 
 303         /* Setup the transfer now... */
 304         if (sspi->tx_buf)
 305                 tx_len = tfr->len;
 306 
 307         /* Setup the counters */
 308         sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
 309         sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
 310         sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
 311                         SUN6I_BURST_CTL_CNT_STC(tx_len));
 312 
 313         /* Fill the TX FIFO */
 314         sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);
 315 
 316         /* Enable the interrupts */
 317         sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
 318         sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC |
 319                                          SUN6I_INT_CTL_RF_RDY);
 320         if (tx_len > sspi->fifo_depth)
 321                 sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
 322 
 323         /* Start the transfer */
 324         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 325         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
 326 
 327         tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
 328         start = jiffies;
 329         timeout = wait_for_completion_timeout(&sspi->done,
 330                                               msecs_to_jiffies(tx_time));
 331         end = jiffies;
 332         if (!timeout) {
 333                 dev_warn(&master->dev,
 334                          "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
 335                          dev_name(&spi->dev), tfr->len, tfr->speed_hz,
 336                          jiffies_to_msecs(end - start), tx_time);
 337                 ret = -ETIMEDOUT;
 338                 goto out;
 339         }
 340 
 341 out:
 342         sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
 343 
 344         return ret;
 345 }
 346 
 347 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
 348 {
 349         struct sun6i_spi *sspi = dev_id;
 350         u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
 351 
 352         /* Transfer complete */
 353         if (status & SUN6I_INT_CTL_TC) {
 354                 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
 355                 sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
 356                 complete(&sspi->done);
 357                 return IRQ_HANDLED;
 358         }
 359 
 360         /* Receive FIFO 3/4 full */
 361         if (status & SUN6I_INT_CTL_RF_RDY) {
 362                 sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
 363                 /* Only clear the interrupt _after_ draining the FIFO */
 364                 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
 365                 return IRQ_HANDLED;
 366         }
 367 
 368         /* Transmit FIFO 3/4 empty */
 369         if (status & SUN6I_INT_CTL_TF_ERQ) {
 370                 sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
 371 
 372                 if (!sspi->len)
 373                         /* nothing left to transmit */
 374                         sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
 375 
 376                 /* Only clear the interrupt _after_ re-seeding the FIFO */
 377                 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
 378 
 379                 return IRQ_HANDLED;
 380         }
 381 
 382         return IRQ_NONE;
 383 }
 384 
 385 static int sun6i_spi_runtime_resume(struct device *dev)
 386 {
 387         struct spi_master *master = dev_get_drvdata(dev);
 388         struct sun6i_spi *sspi = spi_master_get_devdata(master);
 389         int ret;
 390 
 391         ret = clk_prepare_enable(sspi->hclk);
 392         if (ret) {
 393                 dev_err(dev, "Couldn't enable AHB clock\n");
 394                 goto out;
 395         }
 396 
 397         ret = clk_prepare_enable(sspi->mclk);
 398         if (ret) {
 399                 dev_err(dev, "Couldn't enable module clock\n");
 400                 goto err;
 401         }
 402 
 403         ret = reset_control_deassert(sspi->rstc);
 404         if (ret) {
 405                 dev_err(dev, "Couldn't deassert the device from reset\n");
 406                 goto err2;
 407         }
 408 
 409         sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
 410                         SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
 411 
 412         return 0;
 413 
 414 err2:
 415         clk_disable_unprepare(sspi->mclk);
 416 err:
 417         clk_disable_unprepare(sspi->hclk);
 418 out:
 419         return ret;
 420 }
 421 
 422 static int sun6i_spi_runtime_suspend(struct device *dev)
 423 {
 424         struct spi_master *master = dev_get_drvdata(dev);
 425         struct sun6i_spi *sspi = spi_master_get_devdata(master);
 426 
 427         reset_control_assert(sspi->rstc);
 428         clk_disable_unprepare(sspi->mclk);
 429         clk_disable_unprepare(sspi->hclk);
 430 
 431         return 0;
 432 }
 433 
 434 static int sun6i_spi_probe(struct platform_device *pdev)
 435 {
 436         struct spi_master *master;
 437         struct sun6i_spi *sspi;
 438         int ret = 0, irq;
 439 
 440         master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
 441         if (!master) {
 442                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
 443                 return -ENOMEM;
 444         }
 445 
 446         platform_set_drvdata(pdev, master);
 447         sspi = spi_master_get_devdata(master);
 448 
 449         sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
 450         if (IS_ERR(sspi->base_addr)) {
 451                 ret = PTR_ERR(sspi->base_addr);
 452                 goto err_free_master;
 453         }
 454 
 455         irq = platform_get_irq(pdev, 0);
 456         if (irq < 0) {
 457                 ret = -ENXIO;
 458                 goto err_free_master;
 459         }
 460 
 461         ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
 462                                0, "sun6i-spi", sspi);
 463         if (ret) {
 464                 dev_err(&pdev->dev, "Cannot request IRQ\n");
 465                 goto err_free_master;
 466         }
 467 
 468         sspi->master = master;
 469         sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
 470 
 471         master->max_speed_hz = 100 * 1000 * 1000;
 472         master->min_speed_hz = 3 * 1000;
 473         master->set_cs = sun6i_spi_set_cs;
 474         master->transfer_one = sun6i_spi_transfer_one;
 475         master->num_chipselect = 4;
 476         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 477         master->bits_per_word_mask = SPI_BPW_MASK(8);
 478         master->dev.of_node = pdev->dev.of_node;
 479         master->auto_runtime_pm = true;
 480         master->max_transfer_size = sun6i_spi_max_transfer_size;
 481 
 482         sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
 483         if (IS_ERR(sspi->hclk)) {
 484                 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
 485                 ret = PTR_ERR(sspi->hclk);
 486                 goto err_free_master;
 487         }
 488 
 489         sspi->mclk = devm_clk_get(&pdev->dev, "mod");
 490         if (IS_ERR(sspi->mclk)) {
 491                 dev_err(&pdev->dev, "Unable to acquire module clock\n");
 492                 ret = PTR_ERR(sspi->mclk);
 493                 goto err_free_master;
 494         }
 495 
 496         init_completion(&sspi->done);
 497 
 498         sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 499         if (IS_ERR(sspi->rstc)) {
 500                 dev_err(&pdev->dev, "Couldn't get reset controller\n");
 501                 ret = PTR_ERR(sspi->rstc);
 502                 goto err_free_master;
 503         }
 504 
 505         /*
 506          * This wake-up/shutdown pattern is to be able to have the
 507          * device woken up, even if runtime_pm is disabled
 508          */
 509         ret = sun6i_spi_runtime_resume(&pdev->dev);
 510         if (ret) {
 511                 dev_err(&pdev->dev, "Couldn't resume the device\n");
 512                 goto err_free_master;
 513         }
 514 
 515         pm_runtime_set_active(&pdev->dev);
 516         pm_runtime_enable(&pdev->dev);
 517         pm_runtime_idle(&pdev->dev);
 518 
 519         ret = devm_spi_register_master(&pdev->dev, master);
 520         if (ret) {
 521                 dev_err(&pdev->dev, "cannot register SPI master\n");
 522                 goto err_pm_disable;
 523         }
 524 
 525         return 0;
 526 
 527 err_pm_disable:
 528         pm_runtime_disable(&pdev->dev);
 529         sun6i_spi_runtime_suspend(&pdev->dev);
 530 err_free_master:
 531         spi_master_put(master);
 532         return ret;
 533 }
 534 
 535 static int sun6i_spi_remove(struct platform_device *pdev)
 536 {
 537         pm_runtime_force_suspend(&pdev->dev);
 538 
 539         return 0;
 540 }
 541 
 542 static const struct of_device_id sun6i_spi_match[] = {
 543         { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
 544         { .compatible = "allwinner,sun8i-h3-spi",  .data = (void *)SUN8I_FIFO_DEPTH },
 545         {}
 546 };
 547 MODULE_DEVICE_TABLE(of, sun6i_spi_match);
 548 
 549 static const struct dev_pm_ops sun6i_spi_pm_ops = {
 550         .runtime_resume         = sun6i_spi_runtime_resume,
 551         .runtime_suspend        = sun6i_spi_runtime_suspend,
 552 };
 553 
 554 static struct platform_driver sun6i_spi_driver = {
 555         .probe  = sun6i_spi_probe,
 556         .remove = sun6i_spi_remove,
 557         .driver = {
 558                 .name           = "sun6i-spi",
 559                 .of_match_table = sun6i_spi_match,
 560                 .pm             = &sun6i_spi_pm_ops,
 561         },
 562 };
 563 module_platform_driver(sun6i_spi_driver);
 564 
 565 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
 566 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 567 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
 568 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/spi/spi-sun6i.c

DEFINITIONS
