drivers/spi/spi-omap2-mcspi.c

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This source file includes following definitions.
mcspi_write_reg
mcspi_read_reg
mcspi_write_cs_reg
mcspi_read_cs_reg
mcspi_cached_chconf0
mcspi_write_chconf0
mcspi_bytes_per_word
omap2_mcspi_set_dma_req
omap2_mcspi_set_enable
omap2_mcspi_set_cs
omap2_mcspi_set_mode
omap2_mcspi_set_fifo
mcspi_wait_for_reg_bit
mcspi_wait_for_completion
omap2_mcspi_rx_callback
omap2_mcspi_tx_callback
omap2_mcspi_tx_dma
omap2_mcspi_rx_dma
omap2_mcspi_txrx_dma
omap2_mcspi_txrx_pio
omap2_mcspi_calc_divisor
omap2_mcspi_setup_transfer
omap2_mcspi_request_dma
omap2_mcspi_release_dma
omap2_mcspi_setup
omap2_mcspi_cleanup
omap2_mcspi_irq_handler
omap2_mcspi_slave_abort
omap2_mcspi_transfer_one
omap2_mcspi_prepare_message
omap2_mcspi_can_dma
omap2_mcspi_controller_setup
omap_mcspi_runtime_resume
omap2_mcspi_probe
omap2_mcspi_remove
omap2_mcspi_suspend
omap2_mcspi_resume
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * OMAP2 McSPI controller driver
   4  *
   5  * Copyright (C) 2005, 2006 Nokia Corporation
   6  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   7  *              Juha Yrj�l� <juha.yrjola@nokia.com>
   8  */
   9 
  10 #include <linux/kernel.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/module.h>
  13 #include <linux/device.h>
  14 #include <linux/delay.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/pinctrl/consumer.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22 #include <linux/slab.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/gcd.h>
  27 #include <linux/iopoll.h>
  28 
  29 #include <linux/spi/spi.h>
  30 #include <linux/gpio.h>
  31 
  32 #include <linux/platform_data/spi-omap2-mcspi.h>
  33 
  34 #define OMAP2_MCSPI_MAX_FREQ            48000000
  35 #define OMAP2_MCSPI_MAX_DIVIDER         4096
  36 #define OMAP2_MCSPI_MAX_FIFODEPTH       64
  37 #define OMAP2_MCSPI_MAX_FIFOWCNT        0xFFFF
  38 #define SPI_AUTOSUSPEND_TIMEOUT         2000
  39 
  40 #define OMAP2_MCSPI_REVISION            0x00
  41 #define OMAP2_MCSPI_SYSSTATUS           0x14
  42 #define OMAP2_MCSPI_IRQSTATUS           0x18
  43 #define OMAP2_MCSPI_IRQENABLE           0x1c
  44 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  45 #define OMAP2_MCSPI_SYST                0x24
  46 #define OMAP2_MCSPI_MODULCTRL           0x28
  47 #define OMAP2_MCSPI_XFERLEVEL           0x7c
  48 
  49 /* per-channel banks, 0x14 bytes each, first is: */
  50 #define OMAP2_MCSPI_CHCONF0             0x2c
  51 #define OMAP2_MCSPI_CHSTAT0             0x30
  52 #define OMAP2_MCSPI_CHCTRL0             0x34
  53 #define OMAP2_MCSPI_TX0                 0x38
  54 #define OMAP2_MCSPI_RX0                 0x3c
  55 
  56 /* per-register bitmasks: */
  57 #define OMAP2_MCSPI_IRQSTATUS_EOW       BIT(17)
  58 
  59 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  60 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  61 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  62 
  63 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  64 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  65 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  66 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  67 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  68 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  69 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  70 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  71 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  72 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  73 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  74 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  75 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  76 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  77 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  78 #define OMAP2_MCSPI_CHCONF_FFET         BIT(27)
  79 #define OMAP2_MCSPI_CHCONF_FFER         BIT(28)
  80 #define OMAP2_MCSPI_CHCONF_CLKG         BIT(29)
  81 
  82 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  83 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  84 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  85 #define OMAP2_MCSPI_CHSTAT_TXFFE        BIT(3)
  86 
  87 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  88 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK  (0xff << 8)
  89 
  90 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
  91 
  92 /* We have 2 DMA channels per CS, one for RX and one for TX */
  93 struct omap2_mcspi_dma {
  94         struct dma_chan *dma_tx;
  95         struct dma_chan *dma_rx;
  96 
  97         struct completion dma_tx_completion;
  98         struct completion dma_rx_completion;
  99 
 100         char dma_rx_ch_name[14];
 101         char dma_tx_ch_name[14];
 102 };
 103 
 104 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 105  * cache operations; better heuristics consider wordsize and bitrate.
 106  */
 107 #define DMA_MIN_BYTES                   160
 108 
 109 
 110 /*
 111  * Used for context save and restore, structure members to be updated whenever
 112  * corresponding registers are modified.
 113  */
 114 struct omap2_mcspi_regs {
 115         u32 modulctrl;
 116         u32 wakeupenable;
 117         struct list_head cs;
 118 };
 119 
 120 struct omap2_mcspi {
 121         struct completion       txdone;
 122         struct spi_master       *master;
 123         /* Virtual base address of the controller */
 124         void __iomem            *base;
 125         unsigned long           phys;
 126         /* SPI1 has 4 channels, while SPI2 has 2 */
 127         struct omap2_mcspi_dma  *dma_channels;
 128         struct device           *dev;
 129         struct omap2_mcspi_regs ctx;
 130         int                     fifo_depth;
 131         bool                    slave_aborted;
 132         unsigned int            pin_dir:1;
 133 };
 134 
 135 struct omap2_mcspi_cs {
 136         void __iomem            *base;
 137         unsigned long           phys;
 138         int                     word_len;
 139         u16                     mode;
 140         struct list_head        node;
 141         /* Context save and restore shadow register */
 142         u32                     chconf0, chctrl0;
 143 };
 144 
 145 static inline void mcspi_write_reg(struct spi_master *master,
 146                 int idx, u32 val)
 147 {
 148         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 149 
 150         writel_relaxed(val, mcspi->base + idx);
 151 }
 152 
 153 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 154 {
 155         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 156 
 157         return readl_relaxed(mcspi->base + idx);
 158 }
 159 
 160 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 161                 int idx, u32 val)
 162 {
 163         struct omap2_mcspi_cs   *cs = spi->controller_state;
 164 
 165         writel_relaxed(val, cs->base +  idx);
 166 }
 167 
 168 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 169 {
 170         struct omap2_mcspi_cs   *cs = spi->controller_state;
 171 
 172         return readl_relaxed(cs->base + idx);
 173 }
 174 
 175 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 176 {
 177         struct omap2_mcspi_cs *cs = spi->controller_state;
 178 
 179         return cs->chconf0;
 180 }
 181 
 182 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 183 {
 184         struct omap2_mcspi_cs *cs = spi->controller_state;
 185 
 186         cs->chconf0 = val;
 187         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 188         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 189 }
 190 
 191 static inline int mcspi_bytes_per_word(int word_len)
 192 {
 193         if (word_len <= 8)
 194                 return 1;
 195         else if (word_len <= 16)
 196                 return 2;
 197         else /* word_len <= 32 */
 198                 return 4;
 199 }
 200 
 201 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 202                 int is_read, int enable)
 203 {
 204         u32 l, rw;
 205 
 206         l = mcspi_cached_chconf0(spi);
 207 
 208         if (is_read) /* 1 is read, 0 write */
 209                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 210         else
 211                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 212 
 213         if (enable)
 214                 l |= rw;
 215         else
 216                 l &= ~rw;
 217 
 218         mcspi_write_chconf0(spi, l);
 219 }
 220 
 221 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 222 {
 223         struct omap2_mcspi_cs *cs = spi->controller_state;
 224         u32 l;
 225 
 226         l = cs->chctrl0;
 227         if (enable)
 228                 l |= OMAP2_MCSPI_CHCTRL_EN;
 229         else
 230                 l &= ~OMAP2_MCSPI_CHCTRL_EN;
 231         cs->chctrl0 = l;
 232         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
 233         /* Flash post-writes */
 234         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 235 }
 236 
 237 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
 238 {
 239         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 240         u32 l;
 241 
 242         /* The controller handles the inverted chip selects
 243          * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
 244          * the inversion from the core spi_set_cs function.
 245          */
 246         if (spi->mode & SPI_CS_HIGH)
 247                 enable = !enable;
 248 
 249         if (spi->controller_state) {
 250                 int err = pm_runtime_get_sync(mcspi->dev);
 251                 if (err < 0) {
 252                         pm_runtime_put_noidle(mcspi->dev);
 253                         dev_err(mcspi->dev, "failed to get sync: %d\n", err);
 254                         return;
 255                 }
 256 
 257                 l = mcspi_cached_chconf0(spi);
 258 
 259                 if (enable)
 260                         l &= ~OMAP2_MCSPI_CHCONF_FORCE;
 261                 else
 262                         l |= OMAP2_MCSPI_CHCONF_FORCE;
 263 
 264                 mcspi_write_chconf0(spi, l);
 265 
 266                 pm_runtime_mark_last_busy(mcspi->dev);
 267                 pm_runtime_put_autosuspend(mcspi->dev);
 268         }
 269 }
 270 
 271 static void omap2_mcspi_set_mode(struct spi_master *master)
 272 {
 273         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
 274         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 275         u32 l;
 276 
 277         /*
 278          * Choose master or slave mode
 279          */
 280         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 281         l &= ~(OMAP2_MCSPI_MODULCTRL_STEST);
 282         if (spi_controller_is_slave(master)) {
 283                 l |= (OMAP2_MCSPI_MODULCTRL_MS);
 284         } else {
 285                 l &= ~(OMAP2_MCSPI_MODULCTRL_MS);
 286                 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
 287         }
 288         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 289 
 290         ctx->modulctrl = l;
 291 }
 292 
 293 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
 294                                 struct spi_transfer *t, int enable)
 295 {
 296         struct spi_master *master = spi->master;
 297         struct omap2_mcspi_cs *cs = spi->controller_state;
 298         struct omap2_mcspi *mcspi;
 299         unsigned int wcnt;
 300         int max_fifo_depth, bytes_per_word;
 301         u32 chconf, xferlevel;
 302 
 303         mcspi = spi_master_get_devdata(master);
 304 
 305         chconf = mcspi_cached_chconf0(spi);
 306         if (enable) {
 307                 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
 308                 if (t->len % bytes_per_word != 0)
 309                         goto disable_fifo;
 310 
 311                 if (t->rx_buf != NULL && t->tx_buf != NULL)
 312                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
 313                 else
 314                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
 315 
 316                 wcnt = t->len / bytes_per_word;
 317                 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
 318                         goto disable_fifo;
 319 
 320                 xferlevel = wcnt << 16;
 321                 if (t->rx_buf != NULL) {
 322                         chconf |= OMAP2_MCSPI_CHCONF_FFER;
 323                         xferlevel |= (bytes_per_word - 1) << 8;
 324                 }
 325 
 326                 if (t->tx_buf != NULL) {
 327                         chconf |= OMAP2_MCSPI_CHCONF_FFET;
 328                         xferlevel |= bytes_per_word - 1;
 329                 }
 330 
 331                 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
 332                 mcspi_write_chconf0(spi, chconf);
 333                 mcspi->fifo_depth = max_fifo_depth;
 334 
 335                 return;
 336         }
 337 
 338 disable_fifo:
 339         if (t->rx_buf != NULL)
 340                 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
 341 
 342         if (t->tx_buf != NULL)
 343                 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
 344 
 345         mcspi_write_chconf0(spi, chconf);
 346         mcspi->fifo_depth = 0;
 347 }
 348 
 349 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 350 {
 351         u32 val;
 352 
 353         return readl_poll_timeout(reg, val, val & bit, 1, MSEC_PER_SEC);
 354 }
 355 
 356 static int mcspi_wait_for_completion(struct  omap2_mcspi *mcspi,
 357                                      struct completion *x)
 358 {
 359         if (spi_controller_is_slave(mcspi->master)) {
 360                 if (wait_for_completion_interruptible(x) ||
 361                     mcspi->slave_aborted)
 362                         return -EINTR;
 363         } else {
 364                 wait_for_completion(x);
 365         }
 366 
 367         return 0;
 368 }
 369 
 370 static void omap2_mcspi_rx_callback(void *data)
 371 {
 372         struct spi_device *spi = data;
 373         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 374         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 375 
 376         /* We must disable the DMA RX request */
 377         omap2_mcspi_set_dma_req(spi, 1, 0);
 378 
 379         complete(&mcspi_dma->dma_rx_completion);
 380 }
 381 
 382 static void omap2_mcspi_tx_callback(void *data)
 383 {
 384         struct spi_device *spi = data;
 385         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 386         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 387 
 388         /* We must disable the DMA TX request */
 389         omap2_mcspi_set_dma_req(spi, 0, 0);
 390 
 391         complete(&mcspi_dma->dma_tx_completion);
 392 }
 393 
 394 static void omap2_mcspi_tx_dma(struct spi_device *spi,
 395                                 struct spi_transfer *xfer,
 396                                 struct dma_slave_config cfg)
 397 {
 398         struct omap2_mcspi      *mcspi;
 399         struct omap2_mcspi_dma  *mcspi_dma;
 400 
 401         mcspi = spi_master_get_devdata(spi->master);
 402         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 403 
 404         if (mcspi_dma->dma_tx) {
 405                 struct dma_async_tx_descriptor *tx;
 406 
 407                 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
 408 
 409                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
 410                                              xfer->tx_sg.nents,
 411                                              DMA_MEM_TO_DEV,
 412                                              DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 413                 if (tx) {
 414                         tx->callback = omap2_mcspi_tx_callback;
 415                         tx->callback_param = spi;
 416                         dmaengine_submit(tx);
 417                 } else {
 418                         /* FIXME: fall back to PIO? */
 419                 }
 420         }
 421         dma_async_issue_pending(mcspi_dma->dma_tx);
 422         omap2_mcspi_set_dma_req(spi, 0, 1);
 423 
 424 }
 425 
 426 static unsigned
 427 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
 428                                 struct dma_slave_config cfg,
 429                                 unsigned es)
 430 {
 431         struct omap2_mcspi      *mcspi;
 432         struct omap2_mcspi_dma  *mcspi_dma;
 433         unsigned int            count, transfer_reduction = 0;
 434         struct scatterlist      *sg_out[2];
 435         int                     nb_sizes = 0, out_mapped_nents[2], ret, x;
 436         size_t                  sizes[2];
 437         u32                     l;
 438         int                     elements = 0;
 439         int                     word_len, element_count;
 440         struct omap2_mcspi_cs   *cs = spi->controller_state;
 441         void __iomem            *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 442 
 443         mcspi = spi_master_get_devdata(spi->master);
 444         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 445         count = xfer->len;
 446 
 447         /*
 448          *  In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
 449          *  it mentions reducing DMA transfer length by one element in master
 450          *  normal mode.
 451          */
 452         if (mcspi->fifo_depth == 0)
 453                 transfer_reduction = es;
 454 
 455         word_len = cs->word_len;
 456         l = mcspi_cached_chconf0(spi);
 457 
 458         if (word_len <= 8)
 459                 element_count = count;
 460         else if (word_len <= 16)
 461                 element_count = count >> 1;
 462         else /* word_len <= 32 */
 463                 element_count = count >> 2;
 464 
 465         if (mcspi_dma->dma_rx) {
 466                 struct dma_async_tx_descriptor *tx;
 467 
 468                 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
 469 
 470                 /*
 471                  *  Reduce DMA transfer length by one more if McSPI is
 472                  *  configured in turbo mode.
 473                  */
 474                 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
 475                         transfer_reduction += es;
 476 
 477                 if (transfer_reduction) {
 478                         /* Split sgl into two. The second sgl won't be used. */
 479                         sizes[0] = count - transfer_reduction;
 480                         sizes[1] = transfer_reduction;
 481                         nb_sizes = 2;
 482                 } else {
 483                         /*
 484                          * Don't bother splitting the sgl. This essentially
 485                          * clones the original sgl.
 486                          */
 487                         sizes[0] = count;
 488                         nb_sizes = 1;
 489                 }
 490 
 491                 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents,
 492                                0, nb_sizes,
 493                                sizes,
 494                                sg_out, out_mapped_nents,
 495                                GFP_KERNEL);
 496 
 497                 if (ret < 0) {
 498                         dev_err(&spi->dev, "sg_split failed\n");
 499                         return 0;
 500                 }
 501 
 502                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx,
 503                                              sg_out[0],
 504                                              out_mapped_nents[0],
 505                                              DMA_DEV_TO_MEM,
 506                                              DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 507                 if (tx) {
 508                         tx->callback = omap2_mcspi_rx_callback;
 509                         tx->callback_param = spi;
 510                         dmaengine_submit(tx);
 511                 } else {
 512                                 /* FIXME: fall back to PIO? */
 513                 }
 514         }
 515 
 516         dma_async_issue_pending(mcspi_dma->dma_rx);
 517         omap2_mcspi_set_dma_req(spi, 1, 1);
 518 
 519         ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion);
 520         if (ret || mcspi->slave_aborted) {
 521                 dmaengine_terminate_sync(mcspi_dma->dma_rx);
 522                 omap2_mcspi_set_dma_req(spi, 1, 0);
 523                 return 0;
 524         }
 525 
 526         for (x = 0; x < nb_sizes; x++)
 527                 kfree(sg_out[x]);
 528 
 529         if (mcspi->fifo_depth > 0)
 530                 return count;
 531 
 532         /*
 533          *  Due to the DMA transfer length reduction the missing bytes must
 534          *  be read manually to receive all of the expected data.
 535          */
 536         omap2_mcspi_set_enable(spi, 0);
 537 
 538         elements = element_count - 1;
 539 
 540         if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 541                 elements--;
 542 
 543                 if (!mcspi_wait_for_reg_bit(chstat_reg,
 544                                             OMAP2_MCSPI_CHSTAT_RXS)) {
 545                         u32 w;
 546 
 547                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 548                         if (word_len <= 8)
 549                                 ((u8 *)xfer->rx_buf)[elements++] = w;
 550                         else if (word_len <= 16)
 551                                 ((u16 *)xfer->rx_buf)[elements++] = w;
 552                         else /* word_len <= 32 */
 553                                 ((u32 *)xfer->rx_buf)[elements++] = w;
 554                 } else {
 555                         int bytes_per_word = mcspi_bytes_per_word(word_len);
 556                         dev_err(&spi->dev, "DMA RX penultimate word empty\n");
 557                         count -= (bytes_per_word << 1);
 558                         omap2_mcspi_set_enable(spi, 1);
 559                         return count;
 560                 }
 561         }
 562         if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
 563                 u32 w;
 564 
 565                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 566                 if (word_len <= 8)
 567                         ((u8 *)xfer->rx_buf)[elements] = w;
 568                 else if (word_len <= 16)
 569                         ((u16 *)xfer->rx_buf)[elements] = w;
 570                 else /* word_len <= 32 */
 571                         ((u32 *)xfer->rx_buf)[elements] = w;
 572         } else {
 573                 dev_err(&spi->dev, "DMA RX last word empty\n");
 574                 count -= mcspi_bytes_per_word(word_len);
 575         }
 576         omap2_mcspi_set_enable(spi, 1);
 577         return count;
 578 }
 579 
 580 static unsigned
 581 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 582 {
 583         struct omap2_mcspi      *mcspi;
 584         struct omap2_mcspi_cs   *cs = spi->controller_state;
 585         struct omap2_mcspi_dma  *mcspi_dma;
 586         unsigned int            count;
 587         u8                      *rx;
 588         const u8                *tx;
 589         struct dma_slave_config cfg;
 590         enum dma_slave_buswidth width;
 591         unsigned es;
 592         void __iomem            *chstat_reg;
 593         void __iomem            *irqstat_reg;
 594         int                     wait_res;
 595 
 596         mcspi = spi_master_get_devdata(spi->master);
 597         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 598 
 599         if (cs->word_len <= 8) {
 600                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 601                 es = 1;
 602         } else if (cs->word_len <= 16) {
 603                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 604                 es = 2;
 605         } else {
 606                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 607                 es = 4;
 608         }
 609 
 610         count = xfer->len;
 611 
 612         memset(&cfg, 0, sizeof(cfg));
 613         cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
 614         cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
 615         cfg.src_addr_width = width;
 616         cfg.dst_addr_width = width;
 617         cfg.src_maxburst = 1;
 618         cfg.dst_maxburst = 1;
 619 
 620         rx = xfer->rx_buf;
 621         tx = xfer->tx_buf;
 622 
 623         mcspi->slave_aborted = false;
 624         reinit_completion(&mcspi_dma->dma_tx_completion);
 625         reinit_completion(&mcspi_dma->dma_rx_completion);
 626         reinit_completion(&mcspi->txdone);
 627         if (tx) {
 628                 /* Enable EOW IRQ to know end of tx in slave mode */
 629                 if (spi_controller_is_slave(spi->master))
 630                         mcspi_write_reg(spi->master,
 631                                         OMAP2_MCSPI_IRQENABLE,
 632                                         OMAP2_MCSPI_IRQSTATUS_EOW);
 633                 omap2_mcspi_tx_dma(spi, xfer, cfg);
 634         }
 635 
 636         if (rx != NULL)
 637                 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
 638 
 639         if (tx != NULL) {
 640                 int ret;
 641 
 642                 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion);
 643                 if (ret || mcspi->slave_aborted) {
 644                         dmaengine_terminate_sync(mcspi_dma->dma_tx);
 645                         omap2_mcspi_set_dma_req(spi, 0, 0);
 646                         return 0;
 647                 }
 648 
 649                 if (spi_controller_is_slave(mcspi->master)) {
 650                         ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone);
 651                         if (ret || mcspi->slave_aborted)
 652                                 return 0;
 653                 }
 654 
 655                 if (mcspi->fifo_depth > 0) {
 656                         irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
 657 
 658                         if (mcspi_wait_for_reg_bit(irqstat_reg,
 659                                                 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
 660                                 dev_err(&spi->dev, "EOW timed out\n");
 661 
 662                         mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
 663                                         OMAP2_MCSPI_IRQSTATUS_EOW);
 664                 }
 665 
 666                 /* for TX_ONLY mode, be sure all words have shifted out */
 667                 if (rx == NULL) {
 668                         chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 669                         if (mcspi->fifo_depth > 0) {
 670                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 671                                                 OMAP2_MCSPI_CHSTAT_TXFFE);
 672                                 if (wait_res < 0)
 673                                         dev_err(&spi->dev, "TXFFE timed out\n");
 674                         } else {
 675                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 676                                                 OMAP2_MCSPI_CHSTAT_TXS);
 677                                 if (wait_res < 0)
 678                                         dev_err(&spi->dev, "TXS timed out\n");
 679                         }
 680                         if (wait_res >= 0 &&
 681                                 (mcspi_wait_for_reg_bit(chstat_reg,
 682                                         OMAP2_MCSPI_CHSTAT_EOT) < 0))
 683                                 dev_err(&spi->dev, "EOT timed out\n");
 684                 }
 685         }
 686         return count;
 687 }
 688 
 689 static unsigned
 690 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 691 {
 692         struct omap2_mcspi_cs   *cs = spi->controller_state;
 693         unsigned int            count, c;
 694         u32                     l;
 695         void __iomem            *base = cs->base;
 696         void __iomem            *tx_reg;
 697         void __iomem            *rx_reg;
 698         void __iomem            *chstat_reg;
 699         int                     word_len;
 700 
 701         count = xfer->len;
 702         c = count;
 703         word_len = cs->word_len;
 704 
 705         l = mcspi_cached_chconf0(spi);
 706 
 707         /* We store the pre-calculated register addresses on stack to speed
 708          * up the transfer loop. */
 709         tx_reg          = base + OMAP2_MCSPI_TX0;
 710         rx_reg          = base + OMAP2_MCSPI_RX0;
 711         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 712 
 713         if (c < (word_len>>3))
 714                 return 0;
 715 
 716         if (word_len <= 8) {
 717                 u8              *rx;
 718                 const u8        *tx;
 719 
 720                 rx = xfer->rx_buf;
 721                 tx = xfer->tx_buf;
 722 
 723                 do {
 724                         c -= 1;
 725                         if (tx != NULL) {
 726                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 727                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 728                                         dev_err(&spi->dev, "TXS timed out\n");
 729                                         goto out;
 730                                 }
 731                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
 732                                                 word_len, *tx);
 733                                 writel_relaxed(*tx++, tx_reg);
 734                         }
 735                         if (rx != NULL) {
 736                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 737                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 738                                         dev_err(&spi->dev, "RXS timed out\n");
 739                                         goto out;
 740                                 }
 741 
 742                                 if (c == 1 && tx == NULL &&
 743                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 744                                         omap2_mcspi_set_enable(spi, 0);
 745                                         *rx++ = readl_relaxed(rx_reg);
 746                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
 747                                                     word_len, *(rx - 1));
 748                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 749                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 750                                                 dev_err(&spi->dev,
 751                                                         "RXS timed out\n");
 752                                                 goto out;
 753                                         }
 754                                         c = 0;
 755                                 } else if (c == 0 && tx == NULL) {
 756                                         omap2_mcspi_set_enable(spi, 0);
 757                                 }
 758 
 759                                 *rx++ = readl_relaxed(rx_reg);
 760                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
 761                                                 word_len, *(rx - 1));
 762                         }
 763                 } while (c);
 764         } else if (word_len <= 16) {
 765                 u16             *rx;
 766                 const u16       *tx;
 767 
 768                 rx = xfer->rx_buf;
 769                 tx = xfer->tx_buf;
 770                 do {
 771                         c -= 2;
 772                         if (tx != NULL) {
 773                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 774                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 775                                         dev_err(&spi->dev, "TXS timed out\n");
 776                                         goto out;
 777                                 }
 778                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
 779                                                 word_len, *tx);
 780                                 writel_relaxed(*tx++, tx_reg);
 781                         }
 782                         if (rx != NULL) {
 783                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 784                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 785                                         dev_err(&spi->dev, "RXS timed out\n");
 786                                         goto out;
 787                                 }
 788 
 789                                 if (c == 2 && tx == NULL &&
 790                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 791                                         omap2_mcspi_set_enable(spi, 0);
 792                                         *rx++ = readl_relaxed(rx_reg);
 793                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
 794                                                     word_len, *(rx - 1));
 795                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 796                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 797                                                 dev_err(&spi->dev,
 798                                                         "RXS timed out\n");
 799                                                 goto out;
 800                                         }
 801                                         c = 0;
 802                                 } else if (c == 0 && tx == NULL) {
 803                                         omap2_mcspi_set_enable(spi, 0);
 804                                 }
 805 
 806                                 *rx++ = readl_relaxed(rx_reg);
 807                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
 808                                                 word_len, *(rx - 1));
 809                         }
 810                 } while (c >= 2);
 811         } else if (word_len <= 32) {
 812                 u32             *rx;
 813                 const u32       *tx;
 814 
 815                 rx = xfer->rx_buf;
 816                 tx = xfer->tx_buf;
 817                 do {
 818                         c -= 4;
 819                         if (tx != NULL) {
 820                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 821                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 822                                         dev_err(&spi->dev, "TXS timed out\n");
 823                                         goto out;
 824                                 }
 825                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
 826                                                 word_len, *tx);
 827                                 writel_relaxed(*tx++, tx_reg);
 828                         }
 829                         if (rx != NULL) {
 830                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 831                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 832                                         dev_err(&spi->dev, "RXS timed out\n");
 833                                         goto out;
 834                                 }
 835 
 836                                 if (c == 4 && tx == NULL &&
 837                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 838                                         omap2_mcspi_set_enable(spi, 0);
 839                                         *rx++ = readl_relaxed(rx_reg);
 840                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
 841                                                     word_len, *(rx - 1));
 842                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 843                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 844                                                 dev_err(&spi->dev,
 845                                                         "RXS timed out\n");
 846                                                 goto out;
 847                                         }
 848                                         c = 0;
 849                                 } else if (c == 0 && tx == NULL) {
 850                                         omap2_mcspi_set_enable(spi, 0);
 851                                 }
 852 
 853                                 *rx++ = readl_relaxed(rx_reg);
 854                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
 855                                                 word_len, *(rx - 1));
 856                         }
 857                 } while (c >= 4);
 858         }
 859 
 860         /* for TX_ONLY mode, be sure all words have shifted out */
 861         if (xfer->rx_buf == NULL) {
 862                 if (mcspi_wait_for_reg_bit(chstat_reg,
 863                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 864                         dev_err(&spi->dev, "TXS timed out\n");
 865                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 866                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 867                         dev_err(&spi->dev, "EOT timed out\n");
 868 
 869                 /* disable chan to purge rx datas received in TX_ONLY transfer,
 870                  * otherwise these rx datas will affect the direct following
 871                  * RX_ONLY transfer.
 872                  */
 873                 omap2_mcspi_set_enable(spi, 0);
 874         }
 875 out:
 876         omap2_mcspi_set_enable(spi, 1);
 877         return count - c;
 878 }
 879 
 880 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
 881 {
 882         u32 div;
 883 
 884         for (div = 0; div < 15; div++)
 885                 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
 886                         return div;
 887 
 888         return 15;
 889 }
 890 
 891 /* called only when no transfer is active to this device */
 892 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 893                 struct spi_transfer *t)
 894 {
 895         struct omap2_mcspi_cs *cs = spi->controller_state;
 896         struct omap2_mcspi *mcspi;
 897         u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
 898         u8 word_len = spi->bits_per_word;
 899         u32 speed_hz = spi->max_speed_hz;
 900 
 901         mcspi = spi_master_get_devdata(spi->master);
 902 
 903         if (t != NULL && t->bits_per_word)
 904                 word_len = t->bits_per_word;
 905 
 906         cs->word_len = word_len;
 907 
 908         if (t && t->speed_hz)
 909                 speed_hz = t->speed_hz;
 910 
 911         speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
 912         if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
 913                 clkd = omap2_mcspi_calc_divisor(speed_hz);
 914                 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
 915                 clkg = 0;
 916         } else {
 917                 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
 918                 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
 919                 clkd = (div - 1) & 0xf;
 920                 extclk = (div - 1) >> 4;
 921                 clkg = OMAP2_MCSPI_CHCONF_CLKG;
 922         }
 923 
 924         l = mcspi_cached_chconf0(spi);
 925 
 926         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 927          * REVISIT: this controller could support SPI_3WIRE mode.
 928          */
 929         if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
 930                 l &= ~OMAP2_MCSPI_CHCONF_IS;
 931                 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
 932                 l |= OMAP2_MCSPI_CHCONF_DPE0;
 933         } else {
 934                 l |= OMAP2_MCSPI_CHCONF_IS;
 935                 l |= OMAP2_MCSPI_CHCONF_DPE1;
 936                 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
 937         }
 938 
 939         /* wordlength */
 940         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 941         l |= (word_len - 1) << 7;
 942 
 943         /* set chipselect polarity; manage with FORCE */
 944         if (!(spi->mode & SPI_CS_HIGH))
 945                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 946         else
 947                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 948 
 949         /* set clock divisor */
 950         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 951         l |= clkd << 2;
 952 
 953         /* set clock granularity */
 954         l &= ~OMAP2_MCSPI_CHCONF_CLKG;
 955         l |= clkg;
 956         if (clkg) {
 957                 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
 958                 cs->chctrl0 |= extclk << 8;
 959                 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
 960         }
 961 
 962         /* set SPI mode 0..3 */
 963         if (spi->mode & SPI_CPOL)
 964                 l |= OMAP2_MCSPI_CHCONF_POL;
 965         else
 966                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 967         if (spi->mode & SPI_CPHA)
 968                 l |= OMAP2_MCSPI_CHCONF_PHA;
 969         else
 970                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 971 
 972         mcspi_write_chconf0(spi, l);
 973 
 974         cs->mode = spi->mode;
 975 
 976         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 977                         speed_hz,
 978                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 979                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 980 
 981         return 0;
 982 }
 983 
 984 /*
 985  * Note that we currently allow DMA only if we get a channel
 986  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
 987  */
 988 static int omap2_mcspi_request_dma(struct omap2_mcspi *mcspi,
 989                                    struct omap2_mcspi_dma *mcspi_dma)
 990 {
 991         int ret = 0;
 992 
 993         mcspi_dma->dma_rx = dma_request_chan(mcspi->dev,
 994                                              mcspi_dma->dma_rx_ch_name);
 995         if (IS_ERR(mcspi_dma->dma_rx)) {
 996                 ret = PTR_ERR(mcspi_dma->dma_rx);
 997                 mcspi_dma->dma_rx = NULL;
 998                 goto no_dma;
 999         }
1000 
1001         mcspi_dma->dma_tx = dma_request_chan(mcspi->dev,
1002                                              mcspi_dma->dma_tx_ch_name);
1003         if (IS_ERR(mcspi_dma->dma_tx)) {
1004                 ret = PTR_ERR(mcspi_dma->dma_tx);
1005                 mcspi_dma->dma_tx = NULL;
1006                 dma_release_channel(mcspi_dma->dma_rx);
1007                 mcspi_dma->dma_rx = NULL;
1008         }
1009 
1010         init_completion(&mcspi_dma->dma_rx_completion);
1011         init_completion(&mcspi_dma->dma_tx_completion);
1012 
1013 no_dma:
1014         return ret;
1015 }
1016 
1017 static void omap2_mcspi_release_dma(struct spi_master *master)
1018 {
1019         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1020         struct omap2_mcspi_dma  *mcspi_dma;
1021         int i;
1022 
1023         for (i = 0; i < master->num_chipselect; i++) {
1024                 mcspi_dma = &mcspi->dma_channels[i];
1025 
1026                 if (mcspi_dma->dma_rx) {
1027                         dma_release_channel(mcspi_dma->dma_rx);
1028                         mcspi_dma->dma_rx = NULL;
1029                 }
1030                 if (mcspi_dma->dma_tx) {
1031                         dma_release_channel(mcspi_dma->dma_tx);
1032                         mcspi_dma->dma_tx = NULL;
1033                 }
1034         }
1035 }
1036 
1037 static int omap2_mcspi_setup(struct spi_device *spi)
1038 {
1039         int                     ret;
1040         struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
1041         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1042         struct omap2_mcspi_cs   *cs = spi->controller_state;
1043 
1044         if (!cs) {
1045                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
1046                 if (!cs)
1047                         return -ENOMEM;
1048                 cs->base = mcspi->base + spi->chip_select * 0x14;
1049                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1050                 cs->mode = 0;
1051                 cs->chconf0 = 0;
1052                 cs->chctrl0 = 0;
1053                 spi->controller_state = cs;
1054                 /* Link this to context save list */
1055                 list_add_tail(&cs->node, &ctx->cs);
1056 
1057                 if (gpio_is_valid(spi->cs_gpio)) {
1058                         ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1059                         if (ret) {
1060                                 dev_err(&spi->dev, "failed to request gpio\n");
1061                                 return ret;
1062                         }
1063                         gpio_direction_output(spi->cs_gpio,
1064                                          !(spi->mode & SPI_CS_HIGH));
1065                 }
1066         }
1067 
1068         ret = pm_runtime_get_sync(mcspi->dev);
1069         if (ret < 0) {
1070                 pm_runtime_put_noidle(mcspi->dev);
1071 
1072                 return ret;
1073         }
1074 
1075         ret = omap2_mcspi_setup_transfer(spi, NULL);
1076         pm_runtime_mark_last_busy(mcspi->dev);
1077         pm_runtime_put_autosuspend(mcspi->dev);
1078 
1079         return ret;
1080 }
1081 
1082 static void omap2_mcspi_cleanup(struct spi_device *spi)
1083 {
1084         struct omap2_mcspi_cs   *cs;
1085 
1086         if (spi->controller_state) {
1087                 /* Unlink controller state from context save list */
1088                 cs = spi->controller_state;
1089                 list_del(&cs->node);
1090 
1091                 kfree(cs);
1092         }
1093 
1094         if (gpio_is_valid(spi->cs_gpio))
1095                 gpio_free(spi->cs_gpio);
1096 }
1097 
1098 static irqreturn_t omap2_mcspi_irq_handler(int irq, void *data)
1099 {
1100         struct omap2_mcspi *mcspi = data;
1101         u32 irqstat;
1102 
1103         irqstat = mcspi_read_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS);
1104         if (!irqstat)
1105                 return IRQ_NONE;
1106 
1107         /* Disable IRQ and wakeup slave xfer task */
1108         mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQENABLE, 0);
1109         if (irqstat & OMAP2_MCSPI_IRQSTATUS_EOW)
1110                 complete(&mcspi->txdone);
1111 
1112         return IRQ_HANDLED;
1113 }
1114 
1115 static int omap2_mcspi_slave_abort(struct spi_master *master)
1116 {
1117         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1118         struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels;
1119 
1120         mcspi->slave_aborted = true;
1121         complete(&mcspi_dma->dma_rx_completion);
1122         complete(&mcspi_dma->dma_tx_completion);
1123         complete(&mcspi->txdone);
1124 
1125         return 0;
1126 }
1127 
1128 static int omap2_mcspi_transfer_one(struct spi_master *master,
1129                                     struct spi_device *spi,
1130                                     struct spi_transfer *t)
1131 {
1132 
1133         /* We only enable one channel at a time -- the one whose message is
1134          * -- although this controller would gladly
1135          * arbitrate among multiple channels.  This corresponds to "single
1136          * channel" master mode.  As a side effect, we need to manage the
1137          * chipselect with the FORCE bit ... CS != channel enable.
1138          */
1139 
1140         struct omap2_mcspi              *mcspi;
1141         struct omap2_mcspi_dma          *mcspi_dma;
1142         struct omap2_mcspi_cs           *cs;
1143         struct omap2_mcspi_device_config *cd;
1144         int                             par_override = 0;
1145         int                             status = 0;
1146         u32                             chconf;
1147 
1148         mcspi = spi_master_get_devdata(master);
1149         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1150         cs = spi->controller_state;
1151         cd = spi->controller_data;
1152 
1153         /*
1154          * The slave driver could have changed spi->mode in which case
1155          * it will be different from cs->mode (the current hardware setup).
1156          * If so, set par_override (even though its not a parity issue) so
1157          * omap2_mcspi_setup_transfer will be called to configure the hardware
1158          * with the correct mode on the first iteration of the loop below.
1159          */
1160         if (spi->mode != cs->mode)
1161                 par_override = 1;
1162 
1163         omap2_mcspi_set_enable(spi, 0);
1164 
1165         if (gpio_is_valid(spi->cs_gpio))
1166                 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1167 
1168         if (par_override ||
1169             (t->speed_hz != spi->max_speed_hz) ||
1170             (t->bits_per_word != spi->bits_per_word)) {
1171                 par_override = 1;
1172                 status = omap2_mcspi_setup_transfer(spi, t);
1173                 if (status < 0)
1174                         goto out;
1175                 if (t->speed_hz == spi->max_speed_hz &&
1176                     t->bits_per_word == spi->bits_per_word)
1177                         par_override = 0;
1178         }
1179         if (cd && cd->cs_per_word) {
1180                 chconf = mcspi->ctx.modulctrl;
1181                 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1182                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1183                 mcspi->ctx.modulctrl =
1184                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1185         }
1186 
1187         chconf = mcspi_cached_chconf0(spi);
1188         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1189         chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1190 
1191         if (t->tx_buf == NULL)
1192                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1193         else if (t->rx_buf == NULL)
1194                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1195 
1196         if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1197                 /* Turbo mode is for more than one word */
1198                 if (t->len > ((cs->word_len + 7) >> 3))
1199                         chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1200         }
1201 
1202         mcspi_write_chconf0(spi, chconf);
1203 
1204         if (t->len) {
1205                 unsigned        count;
1206 
1207                 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1208                     master->cur_msg_mapped &&
1209                     master->can_dma(master, spi, t))
1210                         omap2_mcspi_set_fifo(spi, t, 1);
1211 
1212                 omap2_mcspi_set_enable(spi, 1);
1213 
1214                 /* RX_ONLY mode needs dummy data in TX reg */
1215                 if (t->tx_buf == NULL)
1216                         writel_relaxed(0, cs->base
1217                                         + OMAP2_MCSPI_TX0);
1218 
1219                 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1220                     master->cur_msg_mapped &&
1221                     master->can_dma(master, spi, t))
1222                         count = omap2_mcspi_txrx_dma(spi, t);
1223                 else
1224                         count = omap2_mcspi_txrx_pio(spi, t);
1225 
1226                 if (count != t->len) {
1227                         status = -EIO;
1228                         goto out;
1229                 }
1230         }
1231 
1232         omap2_mcspi_set_enable(spi, 0);
1233 
1234         if (mcspi->fifo_depth > 0)
1235                 omap2_mcspi_set_fifo(spi, t, 0);
1236 
1237 out:
1238         /* Restore defaults if they were overriden */
1239         if (par_override) {
1240                 par_override = 0;
1241                 status = omap2_mcspi_setup_transfer(spi, NULL);
1242         }
1243 
1244         if (cd && cd->cs_per_word) {
1245                 chconf = mcspi->ctx.modulctrl;
1246                 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1247                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1248                 mcspi->ctx.modulctrl =
1249                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1250         }
1251 
1252         omap2_mcspi_set_enable(spi, 0);
1253 
1254         if (gpio_is_valid(spi->cs_gpio))
1255                 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1256 
1257         if (mcspi->fifo_depth > 0 && t)
1258                 omap2_mcspi_set_fifo(spi, t, 0);
1259 
1260         return status;
1261 }
1262 
1263 static int omap2_mcspi_prepare_message(struct spi_master *master,
1264                                        struct spi_message *msg)
1265 {
1266         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1267         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1268         struct omap2_mcspi_cs   *cs;
1269 
1270         /* Only a single channel can have the FORCE bit enabled
1271          * in its chconf0 register.
1272          * Scan all channels and disable them except the current one.
1273          * A FORCE can remain from a last transfer having cs_change enabled
1274          */
1275         list_for_each_entry(cs, &ctx->cs, node) {
1276                 if (msg->spi->controller_state == cs)
1277                         continue;
1278 
1279                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1280                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1281                         writel_relaxed(cs->chconf0,
1282                                         cs->base + OMAP2_MCSPI_CHCONF0);
1283                         readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1284                 }
1285         }
1286 
1287         return 0;
1288 }
1289 
1290 static bool omap2_mcspi_can_dma(struct spi_master *master,
1291                                 struct spi_device *spi,
1292                                 struct spi_transfer *xfer)
1293 {
1294         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1295         struct omap2_mcspi_dma *mcspi_dma =
1296                 &mcspi->dma_channels[spi->chip_select];
1297 
1298         if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx)
1299                 return false;
1300 
1301         if (spi_controller_is_slave(master))
1302                 return true;
1303 
1304         master->dma_rx = mcspi_dma->dma_rx;
1305         master->dma_tx = mcspi_dma->dma_tx;
1306 
1307         return (xfer->len >= DMA_MIN_BYTES);
1308 }
1309 
1310 static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi)
1311 {
1312         struct spi_master       *master = mcspi->master;
1313         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1314         int                     ret = 0;
1315 
1316         ret = pm_runtime_get_sync(mcspi->dev);
1317         if (ret < 0) {
1318                 pm_runtime_put_noidle(mcspi->dev);
1319 
1320                 return ret;
1321         }
1322 
1323         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1324                         OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1325         ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1326 
1327         omap2_mcspi_set_mode(master);
1328         pm_runtime_mark_last_busy(mcspi->dev);
1329         pm_runtime_put_autosuspend(mcspi->dev);
1330         return 0;
1331 }
1332 
1333 /*
1334  * When SPI wake up from off-mode, CS is in activate state. If it was in
1335  * inactive state when driver was suspend, then force it to inactive state at
1336  * wake up.
1337  */
1338 static int omap_mcspi_runtime_resume(struct device *dev)
1339 {
1340         struct spi_master *master = dev_get_drvdata(dev);
1341         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1342         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1343         struct omap2_mcspi_cs *cs;
1344 
1345         /* McSPI: context restore */
1346         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
1347         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
1348 
1349         list_for_each_entry(cs, &ctx->cs, node) {
1350                 /*
1351                  * We need to toggle CS state for OMAP take this
1352                  * change in account.
1353                  */
1354                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1355                         cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1356                         writel_relaxed(cs->chconf0,
1357                                        cs->base + OMAP2_MCSPI_CHCONF0);
1358                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1359                         writel_relaxed(cs->chconf0,
1360                                        cs->base + OMAP2_MCSPI_CHCONF0);
1361                 } else {
1362                         writel_relaxed(cs->chconf0,
1363                                        cs->base + OMAP2_MCSPI_CHCONF0);
1364                 }
1365         }
1366 
1367         return 0;
1368 }
1369 
1370 static struct omap2_mcspi_platform_config omap2_pdata = {
1371         .regs_offset = 0,
1372 };
1373 
1374 static struct omap2_mcspi_platform_config omap4_pdata = {
1375         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1376 };
1377 
1378 static const struct of_device_id omap_mcspi_of_match[] = {
1379         {
1380                 .compatible = "ti,omap2-mcspi",
1381                 .data = &omap2_pdata,
1382         },
1383         {
1384                 .compatible = "ti,omap4-mcspi",
1385                 .data = &omap4_pdata,
1386         },
1387         { },
1388 };
1389 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1390 
1391 static int omap2_mcspi_probe(struct platform_device *pdev)
1392 {
1393         struct spi_master       *master;
1394         const struct omap2_mcspi_platform_config *pdata;
1395         struct omap2_mcspi      *mcspi;
1396         struct resource         *r;
1397         int                     status = 0, i;
1398         u32                     regs_offset = 0;
1399         struct device_node      *node = pdev->dev.of_node;
1400         const struct of_device_id *match;
1401 
1402         if (of_property_read_bool(node, "spi-slave"))
1403                 master = spi_alloc_slave(&pdev->dev, sizeof(*mcspi));
1404         else
1405                 master = spi_alloc_master(&pdev->dev, sizeof(*mcspi));
1406         if (!master)
1407                 return -ENOMEM;
1408 
1409         /* the spi->mode bits understood by this driver: */
1410         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1411         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1412         master->setup = omap2_mcspi_setup;
1413         master->auto_runtime_pm = true;
1414         master->prepare_message = omap2_mcspi_prepare_message;
1415         master->can_dma = omap2_mcspi_can_dma;
1416         master->transfer_one = omap2_mcspi_transfer_one;
1417         master->set_cs = omap2_mcspi_set_cs;
1418         master->cleanup = omap2_mcspi_cleanup;
1419         master->slave_abort = omap2_mcspi_slave_abort;
1420         master->dev.of_node = node;
1421         master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1422         master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1423 
1424         platform_set_drvdata(pdev, master);
1425 
1426         mcspi = spi_master_get_devdata(master);
1427         mcspi->master = master;
1428 
1429         match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1430         if (match) {
1431                 u32 num_cs = 1; /* default number of chipselect */
1432                 pdata = match->data;
1433 
1434                 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1435                 master->num_chipselect = num_cs;
1436                 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1437                         mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1438         } else {
1439                 pdata = dev_get_platdata(&pdev->dev);
1440                 master->num_chipselect = pdata->num_cs;
1441                 mcspi->pin_dir = pdata->pin_dir;
1442         }
1443         regs_offset = pdata->regs_offset;
1444 
1445         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1446         mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1447         if (IS_ERR(mcspi->base)) {
1448                 status = PTR_ERR(mcspi->base);
1449                 goto free_master;
1450         }
1451         mcspi->phys = r->start + regs_offset;
1452         mcspi->base += regs_offset;
1453 
1454         mcspi->dev = &pdev->dev;
1455 
1456         INIT_LIST_HEAD(&mcspi->ctx.cs);
1457 
1458         mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1459                                            sizeof(struct omap2_mcspi_dma),
1460                                            GFP_KERNEL);
1461         if (mcspi->dma_channels == NULL) {
1462                 status = -ENOMEM;
1463                 goto free_master;
1464         }
1465 
1466         for (i = 0; i < master->num_chipselect; i++) {
1467                 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1468                 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1469 
1470                 status = omap2_mcspi_request_dma(mcspi,
1471                                                  &mcspi->dma_channels[i]);
1472                 if (status == -EPROBE_DEFER)
1473                         goto free_master;
1474         }
1475 
1476         status = platform_get_irq(pdev, 0);
1477         if (status == -EPROBE_DEFER)
1478                 goto free_master;
1479         if (status < 0) {
1480                 dev_err(&pdev->dev, "no irq resource found\n");
1481                 goto free_master;
1482         }
1483         init_completion(&mcspi->txdone);
1484         status = devm_request_irq(&pdev->dev, status,
1485                                   omap2_mcspi_irq_handler, 0, pdev->name,
1486                                   mcspi);
1487         if (status) {
1488                 dev_err(&pdev->dev, "Cannot request IRQ");
1489                 goto free_master;
1490         }
1491 
1492         pm_runtime_use_autosuspend(&pdev->dev);
1493         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1494         pm_runtime_enable(&pdev->dev);
1495 
1496         status = omap2_mcspi_controller_setup(mcspi);
1497         if (status < 0)
1498                 goto disable_pm;
1499 
1500         status = devm_spi_register_controller(&pdev->dev, master);
1501         if (status < 0)
1502                 goto disable_pm;
1503 
1504         return status;
1505 
1506 disable_pm:
1507         pm_runtime_dont_use_autosuspend(&pdev->dev);
1508         pm_runtime_put_sync(&pdev->dev);
1509         pm_runtime_disable(&pdev->dev);
1510 free_master:
1511         omap2_mcspi_release_dma(master);
1512         spi_master_put(master);
1513         return status;
1514 }
1515 
1516 static int omap2_mcspi_remove(struct platform_device *pdev)
1517 {
1518         struct spi_master *master = platform_get_drvdata(pdev);
1519         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1520 
1521         omap2_mcspi_release_dma(master);
1522 
1523         pm_runtime_dont_use_autosuspend(mcspi->dev);
1524         pm_runtime_put_sync(mcspi->dev);
1525         pm_runtime_disable(&pdev->dev);
1526 
1527         return 0;
1528 }
1529 
1530 /* work with hotplug and coldplug */
1531 MODULE_ALIAS("platform:omap2_mcspi");
1532 
1533 static int __maybe_unused omap2_mcspi_suspend(struct device *dev)
1534 {
1535         struct spi_master *master = dev_get_drvdata(dev);
1536         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1537         int error;
1538 
1539         error = pinctrl_pm_select_sleep_state(dev);
1540         if (error)
1541                 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1542                          __func__, error);
1543 
1544         error = spi_master_suspend(master);
1545         if (error)
1546                 dev_warn(mcspi->dev, "%s: master suspend failed: %i\n",
1547                          __func__, error);
1548 
1549         return pm_runtime_force_suspend(dev);
1550 }
1551 
1552 static int __maybe_unused omap2_mcspi_resume(struct device *dev)
1553 {
1554         struct spi_master *master = dev_get_drvdata(dev);
1555         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1556         int error;
1557 
1558         error = pinctrl_pm_select_default_state(dev);
1559         if (error)
1560                 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1561                          __func__, error);
1562 
1563         error = spi_master_resume(master);
1564         if (error)
1565                 dev_warn(mcspi->dev, "%s: master resume failed: %i\n",
1566                          __func__, error);
1567 
1568         return pm_runtime_force_resume(dev);
1569 }
1570 
1571 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1572         SET_SYSTEM_SLEEP_PM_OPS(omap2_mcspi_suspend,
1573                                 omap2_mcspi_resume)
1574         .runtime_resume = omap_mcspi_runtime_resume,
1575 };
1576 
1577 static struct platform_driver omap2_mcspi_driver = {
1578         .driver = {
1579                 .name =         "omap2_mcspi",
1580                 .pm =           &omap2_mcspi_pm_ops,
1581                 .of_match_table = omap_mcspi_of_match,
1582         },
1583         .probe =        omap2_mcspi_probe,
1584         .remove =       omap2_mcspi_remove,
1585 };
1586 
1587 module_platform_driver(omap2_mcspi_driver);
1588 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/spi/spi-omap2-mcspi.c

DEFINITIONS
