root/drivers/spi/spi-mxs.c

DEFINITIONS

1. mxs_spi_setup_transfer
2. mxs_spi_cs_to_reg
3. mxs_ssp_wait
4. mxs_ssp_dma_irq_callback
5. mxs_ssp_irq_handler
6. mxs_spi_txrx_dma
7. mxs_spi_txrx_pio
8. mxs_spi_transfer_one
9. mxs_spi_runtime_suspend
10. mxs_spi_runtime_resume
11. mxs_spi_suspend
12. mxs_spi_resume
13. mxs_spi_probe
14. mxs_spi_remove

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Freescale MXS SPI master driver
   4 //
   5 // Copyright 2012 DENX Software Engineering, GmbH.
   6 // Copyright 2012 Freescale Semiconductor, Inc.
   7 // Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   8 //
   9 // Rework and transition to new API by:
  10 // Marek Vasut <marex@denx.de>
  11 //
  12 // Based on previous attempt by:
  13 // Fabio Estevam <fabio.estevam@freescale.com>
  14 //
  15 // Based on code from U-Boot bootloader by:
  16 // Marek Vasut <marex@denx.de>
  17 //
  18 // Based on spi-stmp.c, which is:
  19 // Author: Dmitry Pervushin <dimka@embeddedalley.com>
  20 
  21 #include <linux/kernel.h>
  22 #include <linux/ioport.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_gpio.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/delay.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/dmaengine.h>
  31 #include <linux/highmem.h>
  32 #include <linux/clk.h>
  33 #include <linux/err.h>
  34 #include <linux/completion.h>
  35 #include <linux/gpio.h>
  36 #include <linux/regulator/consumer.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/module.h>
  39 #include <linux/stmp_device.h>
  40 #include <linux/spi/spi.h>
  41 #include <linux/spi/mxs-spi.h>
  42 #include <trace/events/spi.h>
  43 
  44 #define DRIVER_NAME             "mxs-spi"
  45 
  46 /* Use 10S timeout for very long transfers, it should suffice. */
  47 #define SSP_TIMEOUT             10000
  48 
  49 #define SG_MAXLEN               0xff00
  50 
  51 /*
  52  * Flags for txrx functions.  More efficient that using an argument register for
  53  * each one.
  54  */
  55 #define TXRX_WRITE              (1<<0)  /* This is a write */
  56 #define TXRX_DEASSERT_CS        (1<<1)  /* De-assert CS at end of txrx */
  57 
  58 struct mxs_spi {
  59         struct mxs_ssp          ssp;
  60         struct completion       c;
  61         unsigned int            sck;    /* Rate requested (vs actual) */
  62 };
  63 
  64 static int mxs_spi_setup_transfer(struct spi_device *dev,
  65                                   const struct spi_transfer *t)
  66 {
  67         struct mxs_spi *spi = spi_master_get_devdata(dev->master);
  68         struct mxs_ssp *ssp = &spi->ssp;
  69         const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
  70 
  71         if (hz == 0) {
  72                 dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
  73                 return -EINVAL;
  74         }
  75 
  76         if (hz != spi->sck) {
  77                 mxs_ssp_set_clk_rate(ssp, hz);
  78                 /*
  79                  * Save requested rate, hz, rather than the actual rate,
  80                  * ssp->clk_rate.  Otherwise we would set the rate every transfer
  81                  * when the actual rate is not quite the same as requested rate.
  82                  */
  83                 spi->sck = hz;
  84                 /*
  85                  * Perhaps we should return an error if the actual clock is
  86                  * nowhere close to what was requested?
  87                  */
  88         }
  89 
  90         writel(BM_SSP_CTRL0_LOCK_CS,
  91                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  92 
  93         writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
  94                BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
  95                ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
  96                ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
  97                ssp->base + HW_SSP_CTRL1(ssp));
  98 
  99         writel(0x0, ssp->base + HW_SSP_CMD0);
 100         writel(0x0, ssp->base + HW_SSP_CMD1);
 101 
 102         return 0;
 103 }
 104 
 105 static u32 mxs_spi_cs_to_reg(unsigned cs)
 106 {
 107         u32 select = 0;
 108 
 109         /*
 110          * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
 111          *
 112          * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
 113          * in HW_SSP_CTRL0 register do have multiple usage, please refer to
 114          * the datasheet for further details. In SPI mode, they are used to
 115          * toggle the chip-select lines (nCS pins).
 116          */
 117         if (cs & 1)
 118                 select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
 119         if (cs & 2)
 120                 select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
 121 
 122         return select;
 123 }
 124 
 125 static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
 126 {
 127         const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
 128         struct mxs_ssp *ssp = &spi->ssp;
 129         u32 reg;
 130 
 131         do {
 132                 reg = readl_relaxed(ssp->base + offset);
 133 
 134                 if (!set)
 135                         reg = ~reg;
 136 
 137                 reg &= mask;
 138 
 139                 if (reg == mask)
 140                         return 0;
 141         } while (time_before(jiffies, timeout));
 142 
 143         return -ETIMEDOUT;
 144 }
 145 
 146 static void mxs_ssp_dma_irq_callback(void *param)
 147 {
 148         struct mxs_spi *spi = param;
 149 
 150         complete(&spi->c);
 151 }
 152 
 153 static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
 154 {
 155         struct mxs_ssp *ssp = dev_id;
 156 
 157         dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
 158                 __func__, __LINE__,
 159                 readl(ssp->base + HW_SSP_CTRL1(ssp)),
 160                 readl(ssp->base + HW_SSP_STATUS(ssp)));
 161         return IRQ_HANDLED;
 162 }
 163 
 164 static int mxs_spi_txrx_dma(struct mxs_spi *spi,
 165                             unsigned char *buf, int len,
 166                             unsigned int flags)
 167 {
 168         struct mxs_ssp *ssp = &spi->ssp;
 169         struct dma_async_tx_descriptor *desc = NULL;
 170         const bool vmalloced_buf = is_vmalloc_addr(buf);
 171         const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
 172         const int sgs = DIV_ROUND_UP(len, desc_len);
 173         int sg_count;
 174         int min, ret;
 175         u32 ctrl0;
 176         struct page *vm_page;
 177         struct {
 178                 u32                     pio[4];
 179                 struct scatterlist      sg;
 180         } *dma_xfer;
 181 
 182         if (!len)
 183                 return -EINVAL;
 184 
 185         dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
 186         if (!dma_xfer)
 187                 return -ENOMEM;
 188 
 189         reinit_completion(&spi->c);
 190 
 191         /* Chip select was already programmed into CTRL0 */
 192         ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
 193         ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
 194                  BM_SSP_CTRL0_READ);
 195         ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
 196 
 197         if (!(flags & TXRX_WRITE))
 198                 ctrl0 |= BM_SSP_CTRL0_READ;
 199 
 200         /* Queue the DMA data transfer. */
 201         for (sg_count = 0; sg_count < sgs; sg_count++) {
 202                 /* Prepare the transfer descriptor. */
 203                 min = min(len, desc_len);
 204 
 205                 /*
 206                  * De-assert CS on last segment if flag is set (i.e., no more
 207                  * transfers will follow)
 208                  */
 209                 if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
 210                         ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
 211 
 212                 if (ssp->devid == IMX23_SSP) {
 213                         ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
 214                         ctrl0 |= min;
 215                 }
 216 
 217                 dma_xfer[sg_count].pio[0] = ctrl0;
 218                 dma_xfer[sg_count].pio[3] = min;
 219 
 220                 if (vmalloced_buf) {
 221                         vm_page = vmalloc_to_page(buf);
 222                         if (!vm_page) {
 223                                 ret = -ENOMEM;
 224                                 goto err_vmalloc;
 225                         }
 226 
 227                         sg_init_table(&dma_xfer[sg_count].sg, 1);
 228                         sg_set_page(&dma_xfer[sg_count].sg, vm_page,
 229                                     min, offset_in_page(buf));
 230                 } else {
 231                         sg_init_one(&dma_xfer[sg_count].sg, buf, min);
 232                 }
 233 
 234                 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
 235                         (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 236 
 237                 len -= min;
 238                 buf += min;
 239 
 240                 /* Queue the PIO register write transfer. */
 241                 desc = dmaengine_prep_slave_sg(ssp->dmach,
 242                                 (struct scatterlist *)dma_xfer[sg_count].pio,
 243                                 (ssp->devid == IMX23_SSP) ? 1 : 4,
 244                                 DMA_TRANS_NONE,
 245                                 sg_count ? DMA_PREP_INTERRUPT : 0);
 246                 if (!desc) {
 247                         dev_err(ssp->dev,
 248                                 "Failed to get PIO reg. write descriptor.\n");
 249                         ret = -EINVAL;
 250                         goto err_mapped;
 251                 }
 252 
 253                 desc = dmaengine_prep_slave_sg(ssp->dmach,
 254                                 &dma_xfer[sg_count].sg, 1,
 255                                 (flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
 256                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 257 
 258                 if (!desc) {
 259                         dev_err(ssp->dev,
 260                                 "Failed to get DMA data write descriptor.\n");
 261                         ret = -EINVAL;
 262                         goto err_mapped;
 263                 }
 264         }
 265 
 266         /*
 267          * The last descriptor must have this callback,
 268          * to finish the DMA transaction.
 269          */
 270         desc->callback = mxs_ssp_dma_irq_callback;
 271         desc->callback_param = spi;
 272 
 273         /* Start the transfer. */
 274         dmaengine_submit(desc);
 275         dma_async_issue_pending(ssp->dmach);
 276 
 277         if (!wait_for_completion_timeout(&spi->c,
 278                                          msecs_to_jiffies(SSP_TIMEOUT))) {
 279                 dev_err(ssp->dev, "DMA transfer timeout\n");
 280                 ret = -ETIMEDOUT;
 281                 dmaengine_terminate_all(ssp->dmach);
 282                 goto err_vmalloc;
 283         }
 284 
 285         ret = 0;
 286 
 287 err_vmalloc:
 288         while (--sg_count >= 0) {
 289 err_mapped:
 290                 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
 291                         (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 292         }
 293 
 294         kfree(dma_xfer);
 295 
 296         return ret;
 297 }
 298 
 299 static int mxs_spi_txrx_pio(struct mxs_spi *spi,
 300                             unsigned char *buf, int len,
 301                             unsigned int flags)
 302 {
 303         struct mxs_ssp *ssp = &spi->ssp;
 304 
 305         writel(BM_SSP_CTRL0_IGNORE_CRC,
 306                ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 307 
 308         while (len--) {
 309                 if (len == 0 && (flags & TXRX_DEASSERT_CS))
 310                         writel(BM_SSP_CTRL0_IGNORE_CRC,
 311                                ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 312 
 313                 if (ssp->devid == IMX23_SSP) {
 314                         writel(BM_SSP_CTRL0_XFER_COUNT,
 315                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 316                         writel(1,
 317                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 318                 } else {
 319                         writel(1, ssp->base + HW_SSP_XFER_SIZE);
 320                 }
 321 
 322                 if (flags & TXRX_WRITE)
 323                         writel(BM_SSP_CTRL0_READ,
 324                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 325                 else
 326                         writel(BM_SSP_CTRL0_READ,
 327                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 328 
 329                 writel(BM_SSP_CTRL0_RUN,
 330                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 331 
 332                 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
 333                         return -ETIMEDOUT;
 334 
 335                 if (flags & TXRX_WRITE)
 336                         writel(*buf, ssp->base + HW_SSP_DATA(ssp));
 337 
 338                 writel(BM_SSP_CTRL0_DATA_XFER,
 339                              ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 340 
 341                 if (!(flags & TXRX_WRITE)) {
 342                         if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
 343                                                 BM_SSP_STATUS_FIFO_EMPTY, 0))
 344                                 return -ETIMEDOUT;
 345 
 346                         *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
 347                 }
 348 
 349                 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
 350                         return -ETIMEDOUT;
 351 
 352                 buf++;
 353         }
 354 
 355         if (len <= 0)
 356                 return 0;
 357 
 358         return -ETIMEDOUT;
 359 }
 360 
 361 static int mxs_spi_transfer_one(struct spi_master *master,
 362                                 struct spi_message *m)
 363 {
 364         struct mxs_spi *spi = spi_master_get_devdata(master);
 365         struct mxs_ssp *ssp = &spi->ssp;
 366         struct spi_transfer *t;
 367         unsigned int flag;
 368         int status = 0;
 369 
 370         /* Program CS register bits here, it will be used for all transfers. */
 371         writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
 372                ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 373         writel(mxs_spi_cs_to_reg(m->spi->chip_select),
 374                ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 375 
 376         list_for_each_entry(t, &m->transfers, transfer_list) {
 377 
 378                 trace_spi_transfer_start(m, t);
 379 
 380                 status = mxs_spi_setup_transfer(m->spi, t);
 381                 if (status)
 382                         break;
 383 
 384                 /* De-assert on last transfer, inverted by cs_change flag */
 385                 flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
 386                        TXRX_DEASSERT_CS : 0;
 387 
 388                 /*
 389                  * Small blocks can be transfered via PIO.
 390                  * Measured by empiric means:
 391                  *
 392                  * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
 393                  *
 394                  * DMA only: 2.164808 seconds, 473.0KB/s
 395                  * Combined: 1.676276 seconds, 610.9KB/s
 396                  */
 397                 if (t->len < 32) {
 398                         writel(BM_SSP_CTRL1_DMA_ENABLE,
 399                                 ssp->base + HW_SSP_CTRL1(ssp) +
 400                                 STMP_OFFSET_REG_CLR);
 401 
 402                         if (t->tx_buf)
 403                                 status = mxs_spi_txrx_pio(spi,
 404                                                 (void *)t->tx_buf,
 405                                                 t->len, flag | TXRX_WRITE);
 406                         if (t->rx_buf)
 407                                 status = mxs_spi_txrx_pio(spi,
 408                                                 t->rx_buf, t->len,
 409                                                 flag);
 410                 } else {
 411                         writel(BM_SSP_CTRL1_DMA_ENABLE,
 412                                 ssp->base + HW_SSP_CTRL1(ssp) +
 413                                 STMP_OFFSET_REG_SET);
 414 
 415                         if (t->tx_buf)
 416                                 status = mxs_spi_txrx_dma(spi,
 417                                                 (void *)t->tx_buf, t->len,
 418                                                 flag | TXRX_WRITE);
 419                         if (t->rx_buf)
 420                                 status = mxs_spi_txrx_dma(spi,
 421                                                 t->rx_buf, t->len,
 422                                                 flag);
 423                 }
 424 
 425                 trace_spi_transfer_stop(m, t);
 426 
 427                 if (status) {
 428                         stmp_reset_block(ssp->base);
 429                         break;
 430                 }
 431 
 432                 m->actual_length += t->len;
 433         }
 434 
 435         m->status = status;
 436         spi_finalize_current_message(master);
 437 
 438         return status;
 439 }
 440 
 441 static int mxs_spi_runtime_suspend(struct device *dev)
 442 {
 443         struct spi_master *master = dev_get_drvdata(dev);
 444         struct mxs_spi *spi = spi_master_get_devdata(master);
 445         struct mxs_ssp *ssp = &spi->ssp;
 446         int ret;
 447 
 448         clk_disable_unprepare(ssp->clk);
 449 
 450         ret = pinctrl_pm_select_idle_state(dev);
 451         if (ret) {
 452                 int ret2 = clk_prepare_enable(ssp->clk);
 453 
 454                 if (ret2)
 455                         dev_warn(dev, "Failed to reenable clock after failing pinctrl request (pinctrl: %d, clk: %d)\n",
 456                                  ret, ret2);
 457         }
 458 
 459         return ret;
 460 }
 461 
 462 static int mxs_spi_runtime_resume(struct device *dev)
 463 {
 464         struct spi_master *master = dev_get_drvdata(dev);
 465         struct mxs_spi *spi = spi_master_get_devdata(master);
 466         struct mxs_ssp *ssp = &spi->ssp;
 467         int ret;
 468 
 469         ret = pinctrl_pm_select_default_state(dev);
 470         if (ret)
 471                 return ret;
 472 
 473         ret = clk_prepare_enable(ssp->clk);
 474         if (ret)
 475                 pinctrl_pm_select_idle_state(dev);
 476 
 477         return ret;
 478 }
 479 
 480 static int __maybe_unused mxs_spi_suspend(struct device *dev)
 481 {
 482         struct spi_master *master = dev_get_drvdata(dev);
 483         int ret;
 484 
 485         ret = spi_master_suspend(master);
 486         if (ret)
 487                 return ret;
 488 
 489         if (!pm_runtime_suspended(dev))
 490                 return mxs_spi_runtime_suspend(dev);
 491         else
 492                 return 0;
 493 }
 494 
 495 static int __maybe_unused mxs_spi_resume(struct device *dev)
 496 {
 497         struct spi_master *master = dev_get_drvdata(dev);
 498         int ret;
 499 
 500         if (!pm_runtime_suspended(dev))
 501                 ret = mxs_spi_runtime_resume(dev);
 502         else
 503                 ret = 0;
 504         if (ret)
 505                 return ret;
 506 
 507         ret = spi_master_resume(master);
 508         if (ret < 0 && !pm_runtime_suspended(dev))
 509                 mxs_spi_runtime_suspend(dev);
 510 
 511         return ret;
 512 }
 513 
 514 static const struct dev_pm_ops mxs_spi_pm = {
 515         SET_RUNTIME_PM_OPS(mxs_spi_runtime_suspend,
 516                            mxs_spi_runtime_resume, NULL)
 517         SET_SYSTEM_SLEEP_PM_OPS(mxs_spi_suspend, mxs_spi_resume)
 518 };
 519 
 520 static const struct of_device_id mxs_spi_dt_ids[] = {
 521         { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
 522         { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
 523         { /* sentinel */ }
 524 };
 525 MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
 526 
 527 static int mxs_spi_probe(struct platform_device *pdev)
 528 {
 529         const struct of_device_id *of_id =
 530                         of_match_device(mxs_spi_dt_ids, &pdev->dev);
 531         struct device_node *np = pdev->dev.of_node;
 532         struct spi_master *master;
 533         struct mxs_spi *spi;
 534         struct mxs_ssp *ssp;
 535         struct clk *clk;
 536         void __iomem *base;
 537         int devid, clk_freq;
 538         int ret = 0, irq_err;
 539 
 540         /*
 541          * Default clock speed for the SPI core. 160MHz seems to
 542          * work reasonably well with most SPI flashes, so use this
 543          * as a default. Override with "clock-frequency" DT prop.
 544          */
 545         const int clk_freq_default = 160000000;
 546 
 547         irq_err = platform_get_irq(pdev, 0);
 548         if (irq_err < 0)
 549                 return irq_err;
 550 
 551         base = devm_platform_ioremap_resource(pdev, 0);
 552         if (IS_ERR(base))
 553                 return PTR_ERR(base);
 554 
 555         clk = devm_clk_get(&pdev->dev, NULL);
 556         if (IS_ERR(clk))
 557                 return PTR_ERR(clk);
 558 
 559         devid = (enum mxs_ssp_id) of_id->data;
 560         ret = of_property_read_u32(np, "clock-frequency",
 561                                    &clk_freq);
 562         if (ret)
 563                 clk_freq = clk_freq_default;
 564 
 565         master = spi_alloc_master(&pdev->dev, sizeof(*spi));
 566         if (!master)
 567                 return -ENOMEM;
 568 
 569         platform_set_drvdata(pdev, master);
 570 
 571         master->transfer_one_message = mxs_spi_transfer_one;
 572         master->bits_per_word_mask = SPI_BPW_MASK(8);
 573         master->mode_bits = SPI_CPOL | SPI_CPHA;
 574         master->num_chipselect = 3;
 575         master->dev.of_node = np;
 576         master->flags = SPI_MASTER_HALF_DUPLEX;
 577         master->auto_runtime_pm = true;
 578 
 579         spi = spi_master_get_devdata(master);
 580         ssp = &spi->ssp;
 581         ssp->dev = &pdev->dev;
 582         ssp->clk = clk;
 583         ssp->base = base;
 584         ssp->devid = devid;
 585 
 586         init_completion(&spi->c);
 587 
 588         ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
 589                                dev_name(&pdev->dev), ssp);
 590         if (ret)
 591                 goto out_master_free;
 592 
 593         ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
 594         if (!ssp->dmach) {
 595                 dev_err(ssp->dev, "Failed to request DMA\n");
 596                 ret = -ENODEV;
 597                 goto out_master_free;
 598         }
 599 
 600         pm_runtime_enable(ssp->dev);
 601         if (!pm_runtime_enabled(ssp->dev)) {
 602                 ret = mxs_spi_runtime_resume(ssp->dev);
 603                 if (ret < 0) {
 604                         dev_err(ssp->dev, "runtime resume failed\n");
 605                         goto out_dma_release;
 606                 }
 607         }
 608 
 609         ret = pm_runtime_get_sync(ssp->dev);
 610         if (ret < 0) {
 611                 dev_err(ssp->dev, "runtime_get_sync failed\n");
 612                 goto out_pm_runtime_disable;
 613         }
 614 
 615         clk_set_rate(ssp->clk, clk_freq);
 616 
 617         ret = stmp_reset_block(ssp->base);
 618         if (ret)
 619                 goto out_pm_runtime_put;
 620 
 621         ret = devm_spi_register_master(&pdev->dev, master);
 622         if (ret) {
 623                 dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
 624                 goto out_pm_runtime_put;
 625         }
 626 
 627         pm_runtime_put(ssp->dev);
 628 
 629         return 0;
 630 
 631 out_pm_runtime_put:
 632         pm_runtime_put(ssp->dev);
 633 out_pm_runtime_disable:
 634         pm_runtime_disable(ssp->dev);
 635 out_dma_release:
 636         dma_release_channel(ssp->dmach);
 637 out_master_free:
 638         spi_master_put(master);
 639         return ret;
 640 }
 641 
 642 static int mxs_spi_remove(struct platform_device *pdev)
 643 {
 644         struct spi_master *master;
 645         struct mxs_spi *spi;
 646         struct mxs_ssp *ssp;
 647 
 648         master = platform_get_drvdata(pdev);
 649         spi = spi_master_get_devdata(master);
 650         ssp = &spi->ssp;
 651 
 652         pm_runtime_disable(&pdev->dev);
 653         if (!pm_runtime_status_suspended(&pdev->dev))
 654                 mxs_spi_runtime_suspend(&pdev->dev);
 655 
 656         dma_release_channel(ssp->dmach);
 657 
 658         return 0;
 659 }
 660 
 661 static struct platform_driver mxs_spi_driver = {
 662         .probe  = mxs_spi_probe,
 663         .remove = mxs_spi_remove,
 664         .driver = {
 665                 .name   = DRIVER_NAME,
 666                 .of_match_table = mxs_spi_dt_ids,
 667                 .pm = &mxs_spi_pm,
 668         },
 669 };
 670 
 671 module_platform_driver(mxs_spi_driver);
 672 
 673 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
 674 MODULE_DESCRIPTION("MXS SPI master driver");
 675 MODULE_LICENSE("GPL");
 676 MODULE_ALIAS("platform:mxs-spi");