root/drivers/spi/spi-fsl-spi.c

DEFINITIONS

1. fsl_spi_get_type
2. fsl_spi_change_mode
3. fsl_spi_chipselect
4. fsl_spi_qe_cpu_set_shifts
5. fsl_spi_grlib_set_shifts
6. mspi_apply_cpu_mode_quirks
7. mspi_apply_qe_mode_quirks
8. fsl_spi_setup_transfer
9. fsl_spi_cpu_bufs
10. fsl_spi_bufs
11. fsl_spi_do_one_msg
12. fsl_spi_setup
13. fsl_spi_cleanup
14. fsl_spi_cpu_irq
15. fsl_spi_irq
16. fsl_spi_grlib_cs_control
17. fsl_spi_grlib_probe
18. fsl_spi_probe
19. fsl_spi_cs_control
20. of_fsl_spi_probe
21. of_fsl_spi_remove
22. plat_mpc8xxx_spi_probe
23. plat_mpc8xxx_spi_remove
24. legacy_driver_register
25. legacy_driver_unregister
26. legacy_driver_register
27. legacy_driver_unregister
28. fsl_spi_init
29. fsl_spi_exit

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Freescale SPI controller driver.
   4  *
   5  * Maintainer: Kumar Gala
   6  *
   7  * Copyright (C) 2006 Polycom, Inc.
   8  * Copyright 2010 Freescale Semiconductor, Inc.
   9  *
  10  * CPM SPI and QE buffer descriptors mode support:
  11  * Copyright (c) 2009  MontaVista Software, Inc.
  12  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  13  *
  14  * GRLIB support:
  15  * Copyright (c) 2012 Aeroflex Gaisler AB.
  16  * Author: Andreas Larsson <andreas@gaisler.com>
  17  */
  18 #include <linux/delay.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/fsl_devices.h>
  21 #include <linux/gpio/consumer.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/spi/spi.h>
  34 #include <linux/spi/spi_bitbang.h>
  35 #include <linux/types.h>
  36 
  37 #ifdef CONFIG_FSL_SOC
  38 #include <sysdev/fsl_soc.h>
  39 #endif
  40 
  41 /* Specific to the MPC8306/MPC8309 */
  42 #define IMMR_SPI_CS_OFFSET 0x14c
  43 #define SPI_BOOT_SEL_BIT   0x80000000
  44 
  45 #include "spi-fsl-lib.h"
  46 #include "spi-fsl-cpm.h"
  47 #include "spi-fsl-spi.h"
  48 
  49 #define TYPE_FSL        0
  50 #define TYPE_GRLIB      1
  51 
  52 struct fsl_spi_match_data {
  53         int type;
  54 };
  55 
  56 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
  57         .type = TYPE_FSL,
  58 };
  59 
  60 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
  61         .type = TYPE_GRLIB,
  62 };
  63 
  64 static const struct of_device_id of_fsl_spi_match[] = {
  65         {
  66                 .compatible = "fsl,spi",
  67                 .data = &of_fsl_spi_fsl_config,
  68         },
  69         {
  70                 .compatible = "aeroflexgaisler,spictrl",
  71                 .data = &of_fsl_spi_grlib_config,
  72         },
  73         {}
  74 };
  75 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
  76 
  77 static int fsl_spi_get_type(struct device *dev)
  78 {
  79         const struct of_device_id *match;
  80 
  81         if (dev->of_node) {
  82                 match = of_match_node(of_fsl_spi_match, dev->of_node);
  83                 if (match && match->data)
  84                         return ((struct fsl_spi_match_data *)match->data)->type;
  85         }
  86         return TYPE_FSL;
  87 }
  88 
  89 static void fsl_spi_change_mode(struct spi_device *spi)
  90 {
  91         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
  92         struct spi_mpc8xxx_cs *cs = spi->controller_state;
  93         struct fsl_spi_reg *reg_base = mspi->reg_base;
  94         __be32 __iomem *mode = &reg_base->mode;
  95         unsigned long flags;
  96 
  97         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
  98                 return;
  99 
 100         /* Turn off IRQs locally to minimize time that SPI is disabled. */
 101         local_irq_save(flags);
 102 
 103         /* Turn off SPI unit prior changing mode */
 104         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
 105 
 106         /* When in CPM mode, we need to reinit tx and rx. */
 107         if (mspi->flags & SPI_CPM_MODE) {
 108                 fsl_spi_cpm_reinit_txrx(mspi);
 109         }
 110         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 111         local_irq_restore(flags);
 112 }
 113 
 114 static void fsl_spi_chipselect(struct spi_device *spi, int value)
 115 {
 116         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 117         struct fsl_spi_platform_data *pdata;
 118         bool pol = spi->mode & SPI_CS_HIGH;
 119         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 120 
 121         pdata = spi->dev.parent->parent->platform_data;
 122 
 123         if (value == BITBANG_CS_INACTIVE) {
 124                 if (pdata->cs_control)
 125                         pdata->cs_control(spi, !pol);
 126         }
 127 
 128         if (value == BITBANG_CS_ACTIVE) {
 129                 mpc8xxx_spi->rx_shift = cs->rx_shift;
 130                 mpc8xxx_spi->tx_shift = cs->tx_shift;
 131                 mpc8xxx_spi->get_rx = cs->get_rx;
 132                 mpc8xxx_spi->get_tx = cs->get_tx;
 133 
 134                 fsl_spi_change_mode(spi);
 135 
 136                 if (pdata->cs_control)
 137                         pdata->cs_control(spi, pol);
 138         }
 139 }
 140 
 141 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
 142                                       int bits_per_word, int msb_first)
 143 {
 144         *rx_shift = 0;
 145         *tx_shift = 0;
 146         if (msb_first) {
 147                 if (bits_per_word <= 8) {
 148                         *rx_shift = 16;
 149                         *tx_shift = 24;
 150                 } else if (bits_per_word <= 16) {
 151                         *rx_shift = 16;
 152                         *tx_shift = 16;
 153                 }
 154         } else {
 155                 if (bits_per_word <= 8)
 156                         *rx_shift = 8;
 157         }
 158 }
 159 
 160 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
 161                                      int bits_per_word, int msb_first)
 162 {
 163         *rx_shift = 0;
 164         *tx_shift = 0;
 165         if (bits_per_word <= 16) {
 166                 if (msb_first) {
 167                         *rx_shift = 16; /* LSB in bit 16 */
 168                         *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
 169                 } else {
 170                         *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
 171                 }
 172         }
 173 }
 174 
 175 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
 176                                 struct spi_device *spi,
 177                                 struct mpc8xxx_spi *mpc8xxx_spi,
 178                                 int bits_per_word)
 179 {
 180         cs->rx_shift = 0;
 181         cs->tx_shift = 0;
 182         if (bits_per_word <= 8) {
 183                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
 184                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
 185         } else if (bits_per_word <= 16) {
 186                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
 187                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
 188         } else if (bits_per_word <= 32) {
 189                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 190                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 191         } else
 192                 return -EINVAL;
 193 
 194         if (mpc8xxx_spi->set_shifts)
 195                 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
 196                                         bits_per_word,
 197                                         !(spi->mode & SPI_LSB_FIRST));
 198 
 199         mpc8xxx_spi->rx_shift = cs->rx_shift;
 200         mpc8xxx_spi->tx_shift = cs->tx_shift;
 201         mpc8xxx_spi->get_rx = cs->get_rx;
 202         mpc8xxx_spi->get_tx = cs->get_tx;
 203 
 204         return bits_per_word;
 205 }
 206 
 207 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
 208                                 struct spi_device *spi,
 209                                 int bits_per_word)
 210 {
 211         /* QE uses Little Endian for words > 8
 212          * so transform all words > 8 into 8 bits
 213          * Unfortnatly that doesn't work for LSB so
 214          * reject these for now */
 215         /* Note: 32 bits word, LSB works iff
 216          * tfcr/rfcr is set to CPMFCR_GBL */
 217         if (spi->mode & SPI_LSB_FIRST &&
 218             bits_per_word > 8)
 219                 return -EINVAL;
 220         if (bits_per_word > 8)
 221                 return 8; /* pretend its 8 bits */
 222         return bits_per_word;
 223 }
 224 
 225 static int fsl_spi_setup_transfer(struct spi_device *spi,
 226                                         struct spi_transfer *t)
 227 {
 228         struct mpc8xxx_spi *mpc8xxx_spi;
 229         int bits_per_word = 0;
 230         u8 pm;
 231         u32 hz = 0;
 232         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 233 
 234         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 235 
 236         if (t) {
 237                 bits_per_word = t->bits_per_word;
 238                 hz = t->speed_hz;
 239         }
 240 
 241         /* spi_transfer level calls that work per-word */
 242         if (!bits_per_word)
 243                 bits_per_word = spi->bits_per_word;
 244 
 245         if (!hz)
 246                 hz = spi->max_speed_hz;
 247 
 248         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
 249                 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
 250                                                            mpc8xxx_spi,
 251                                                            bits_per_word);
 252         else if (mpc8xxx_spi->flags & SPI_QE)
 253                 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
 254                                                           bits_per_word);
 255 
 256         if (bits_per_word < 0)
 257                 return bits_per_word;
 258 
 259         if (bits_per_word == 32)
 260                 bits_per_word = 0;
 261         else
 262                 bits_per_word = bits_per_word - 1;
 263 
 264         /* mask out bits we are going to set */
 265         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 266                                   | SPMODE_PM(0xF));
 267 
 268         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 269 
 270         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 271                 cs->hw_mode |= SPMODE_DIV16;
 272                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
 273                 WARN_ONCE(pm > 16,
 274                           "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
 275                           dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
 276                 if (pm > 16)
 277                         pm = 16;
 278         } else {
 279                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
 280         }
 281         if (pm)
 282                 pm--;
 283 
 284         cs->hw_mode |= SPMODE_PM(pm);
 285 
 286         fsl_spi_change_mode(spi);
 287         return 0;
 288 }
 289 
 290 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
 291                                 struct spi_transfer *t, unsigned int len)
 292 {
 293         u32 word;
 294         struct fsl_spi_reg *reg_base = mspi->reg_base;
 295 
 296         mspi->count = len;
 297 
 298         /* enable rx ints */
 299         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 300 
 301         /* transmit word */
 302         word = mspi->get_tx(mspi);
 303         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 304 
 305         return 0;
 306 }
 307 
 308 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
 309                             bool is_dma_mapped)
 310 {
 311         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 312         struct fsl_spi_reg *reg_base;
 313         unsigned int len = t->len;
 314         u8 bits_per_word;
 315         int ret;
 316 
 317         reg_base = mpc8xxx_spi->reg_base;
 318         bits_per_word = spi->bits_per_word;
 319         if (t->bits_per_word)
 320                 bits_per_word = t->bits_per_word;
 321 
 322         if (bits_per_word > 8) {
 323                 /* invalid length? */
 324                 if (len & 1)
 325                         return -EINVAL;
 326                 len /= 2;
 327         }
 328         if (bits_per_word > 16) {
 329                 /* invalid length? */
 330                 if (len & 1)
 331                         return -EINVAL;
 332                 len /= 2;
 333         }
 334 
 335         mpc8xxx_spi->tx = t->tx_buf;
 336         mpc8xxx_spi->rx = t->rx_buf;
 337 
 338         reinit_completion(&mpc8xxx_spi->done);
 339 
 340         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 341                 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
 342         else
 343                 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
 344         if (ret)
 345                 return ret;
 346 
 347         wait_for_completion(&mpc8xxx_spi->done);
 348 
 349         /* disable rx ints */
 350         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 351 
 352         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 353                 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
 354 
 355         return mpc8xxx_spi->count;
 356 }
 357 
 358 static int fsl_spi_do_one_msg(struct spi_master *master,
 359                               struct spi_message *m)
 360 {
 361         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 362         struct spi_device *spi = m->spi;
 363         struct spi_transfer *t, *first;
 364         unsigned int cs_change;
 365         const int nsecs = 50;
 366         int status, last_bpw;
 367 
 368         /*
 369          * In CPU mode, optimize large byte transfers to use larger
 370          * bits_per_word values to reduce number of interrupts taken.
 371          */
 372         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
 373                 list_for_each_entry(t, &m->transfers, transfer_list) {
 374                         if (t->len < 256 || t->bits_per_word != 8)
 375                                 continue;
 376                         if ((t->len & 3) == 0)
 377                                 t->bits_per_word = 32;
 378                         else if ((t->len & 1) == 0)
 379                                 t->bits_per_word = 16;
 380                 }
 381         }
 382 
 383         /* Don't allow changes if CS is active */
 384         cs_change = 1;
 385         list_for_each_entry(t, &m->transfers, transfer_list) {
 386                 if (cs_change)
 387                         first = t;
 388                 cs_change = t->cs_change;
 389                 if (first->speed_hz != t->speed_hz) {
 390                         dev_err(&spi->dev,
 391                                 "speed_hz cannot change while CS is active\n");
 392                         return -EINVAL;
 393                 }
 394         }
 395 
 396         last_bpw = -1;
 397         cs_change = 1;
 398         status = -EINVAL;
 399         list_for_each_entry(t, &m->transfers, transfer_list) {
 400                 if (cs_change || last_bpw != t->bits_per_word)
 401                         status = fsl_spi_setup_transfer(spi, t);
 402                 if (status < 0)
 403                         break;
 404                 last_bpw = t->bits_per_word;
 405 
 406                 if (cs_change) {
 407                         fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
 408                         ndelay(nsecs);
 409                 }
 410                 cs_change = t->cs_change;
 411                 if (t->len)
 412                         status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
 413                 if (status) {
 414                         status = -EMSGSIZE;
 415                         break;
 416                 }
 417                 m->actual_length += t->len;
 418 
 419                 if (t->delay_usecs)
 420                         udelay(t->delay_usecs);
 421 
 422                 if (cs_change) {
 423                         ndelay(nsecs);
 424                         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 425                         ndelay(nsecs);
 426                 }
 427         }
 428 
 429         m->status = status;
 430 
 431         if (status || !cs_change) {
 432                 ndelay(nsecs);
 433                 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 434         }
 435 
 436         fsl_spi_setup_transfer(spi, NULL);
 437         spi_finalize_current_message(master);
 438         return 0;
 439 }
 440 
 441 static int fsl_spi_setup(struct spi_device *spi)
 442 {
 443         struct mpc8xxx_spi *mpc8xxx_spi;
 444         struct fsl_spi_reg *reg_base;
 445         int retval;
 446         u32 hw_mode;
 447         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 448 
 449         if (!spi->max_speed_hz)
 450                 return -EINVAL;
 451 
 452         if (!cs) {
 453                 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 454                 if (!cs)
 455                         return -ENOMEM;
 456                 spi_set_ctldata(spi, cs);
 457         }
 458         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 459 
 460         reg_base = mpc8xxx_spi->reg_base;
 461 
 462         hw_mode = cs->hw_mode; /* Save original settings */
 463         cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 464         /* mask out bits we are going to set */
 465         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 466                          | SPMODE_REV | SPMODE_LOOP);
 467 
 468         if (spi->mode & SPI_CPHA)
 469                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 470         if (spi->mode & SPI_CPOL)
 471                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 472         if (!(spi->mode & SPI_LSB_FIRST))
 473                 cs->hw_mode |= SPMODE_REV;
 474         if (spi->mode & SPI_LOOP)
 475                 cs->hw_mode |= SPMODE_LOOP;
 476 
 477         retval = fsl_spi_setup_transfer(spi, NULL);
 478         if (retval < 0) {
 479                 cs->hw_mode = hw_mode; /* Restore settings */
 480                 return retval;
 481         }
 482 
 483         /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
 484         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 485 
 486         return 0;
 487 }
 488 
 489 static void fsl_spi_cleanup(struct spi_device *spi)
 490 {
 491         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 492 
 493         kfree(cs);
 494         spi_set_ctldata(spi, NULL);
 495 }
 496 
 497 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 498 {
 499         struct fsl_spi_reg *reg_base = mspi->reg_base;
 500 
 501         /* We need handle RX first */
 502         if (events & SPIE_NE) {
 503                 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 504 
 505                 if (mspi->rx)
 506                         mspi->get_rx(rx_data, mspi);
 507         }
 508 
 509         if ((events & SPIE_NF) == 0)
 510                 /* spin until TX is done */
 511                 while (((events =
 512                         mpc8xxx_spi_read_reg(&reg_base->event)) &
 513                                                 SPIE_NF) == 0)
 514                         cpu_relax();
 515 
 516         /* Clear the events */
 517         mpc8xxx_spi_write_reg(&reg_base->event, events);
 518 
 519         mspi->count -= 1;
 520         if (mspi->count) {
 521                 u32 word = mspi->get_tx(mspi);
 522 
 523                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 524         } else {
 525                 complete(&mspi->done);
 526         }
 527 }
 528 
 529 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
 530 {
 531         struct mpc8xxx_spi *mspi = context_data;
 532         irqreturn_t ret = IRQ_NONE;
 533         u32 events;
 534         struct fsl_spi_reg *reg_base = mspi->reg_base;
 535 
 536         /* Get interrupt events(tx/rx) */
 537         events = mpc8xxx_spi_read_reg(&reg_base->event);
 538         if (events)
 539                 ret = IRQ_HANDLED;
 540 
 541         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
 542 
 543         if (mspi->flags & SPI_CPM_MODE)
 544                 fsl_spi_cpm_irq(mspi, events);
 545         else
 546                 fsl_spi_cpu_irq(mspi, events);
 547 
 548         return ret;
 549 }
 550 
 551 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
 552 {
 553         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 554         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
 555         u32 slvsel;
 556         u16 cs = spi->chip_select;
 557 
 558         if (spi->cs_gpiod) {
 559                 gpiod_set_value(spi->cs_gpiod, on);
 560         } else if (cs < mpc8xxx_spi->native_chipselects) {
 561                 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
 562                 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
 563                 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
 564         }
 565 }
 566 
 567 static void fsl_spi_grlib_probe(struct device *dev)
 568 {
 569         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 570         struct spi_master *master = dev_get_drvdata(dev);
 571         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 572         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
 573         int mbits;
 574         u32 capabilities;
 575 
 576         capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
 577 
 578         mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
 579         mbits = SPCAP_MAXWLEN(capabilities);
 580         if (mbits)
 581                 mpc8xxx_spi->max_bits_per_word = mbits + 1;
 582 
 583         mpc8xxx_spi->native_chipselects = 0;
 584         if (SPCAP_SSEN(capabilities)) {
 585                 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
 586                 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
 587         }
 588         master->num_chipselect = mpc8xxx_spi->native_chipselects;
 589         pdata->cs_control = fsl_spi_grlib_cs_control;
 590 }
 591 
 592 static struct spi_master * fsl_spi_probe(struct device *dev,
 593                 struct resource *mem, unsigned int irq)
 594 {
 595         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 596         struct spi_master *master;
 597         struct mpc8xxx_spi *mpc8xxx_spi;
 598         struct fsl_spi_reg *reg_base;
 599         u32 regval;
 600         int ret = 0;
 601 
 602         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 603         if (master == NULL) {
 604                 ret = -ENOMEM;
 605                 goto err;
 606         }
 607 
 608         dev_set_drvdata(dev, master);
 609 
 610         mpc8xxx_spi_probe(dev, mem, irq);
 611 
 612         master->setup = fsl_spi_setup;
 613         master->cleanup = fsl_spi_cleanup;
 614         master->transfer_one_message = fsl_spi_do_one_msg;
 615         master->use_gpio_descriptors = true;
 616 
 617         mpc8xxx_spi = spi_master_get_devdata(master);
 618         mpc8xxx_spi->max_bits_per_word = 32;
 619         mpc8xxx_spi->type = fsl_spi_get_type(dev);
 620 
 621         ret = fsl_spi_cpm_init(mpc8xxx_spi);
 622         if (ret)
 623                 goto err_cpm_init;
 624 
 625         mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
 626         if (IS_ERR(mpc8xxx_spi->reg_base)) {
 627                 ret = PTR_ERR(mpc8xxx_spi->reg_base);
 628                 goto err_probe;
 629         }
 630 
 631         if (mpc8xxx_spi->type == TYPE_GRLIB)
 632                 fsl_spi_grlib_probe(dev);
 633 
 634         master->bits_per_word_mask =
 635                 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
 636                 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
 637 
 638         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 639                 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
 640 
 641         if (mpc8xxx_spi->set_shifts)
 642                 /* 8 bits per word and MSB first */
 643                 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
 644                                         &mpc8xxx_spi->tx_shift, 8, 1);
 645 
 646         /* Register for SPI Interrupt */
 647         ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
 648                                0, "fsl_spi", mpc8xxx_spi);
 649 
 650         if (ret != 0)
 651                 goto err_probe;
 652 
 653         reg_base = mpc8xxx_spi->reg_base;
 654 
 655         /* SPI controller initializations */
 656         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 657         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 658         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 659         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 660 
 661         /* Enable SPI interface */
 662         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 663         if (mpc8xxx_spi->max_bits_per_word < 8) {
 664                 regval &= ~SPMODE_LEN(0xF);
 665                 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
 666         }
 667         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 668                 regval |= SPMODE_OP;
 669 
 670         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 671 
 672         ret = devm_spi_register_master(dev, master);
 673         if (ret < 0)
 674                 goto err_probe;
 675 
 676         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
 677                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
 678 
 679         return master;
 680 
 681 err_probe:
 682         fsl_spi_cpm_free(mpc8xxx_spi);
 683 err_cpm_init:
 684         spi_master_put(master);
 685 err:
 686         return ERR_PTR(ret);
 687 }
 688 
 689 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
 690 {
 691         if (spi->cs_gpiod) {
 692                 gpiod_set_value(spi->cs_gpiod, on);
 693         } else {
 694                 struct device *dev = spi->dev.parent->parent;
 695                 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 696                 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 697 
 698                 if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
 699                         return;
 700                 iowrite32be(on ? SPI_BOOT_SEL_BIT : 0, pinfo->immr_spi_cs);
 701         }
 702 }
 703 
 704 static int of_fsl_spi_probe(struct platform_device *ofdev)
 705 {
 706         struct device *dev = &ofdev->dev;
 707         struct device_node *np = ofdev->dev.of_node;
 708         struct spi_master *master;
 709         struct resource mem;
 710         int irq = 0, type;
 711         int ret = -ENOMEM;
 712 
 713         ret = of_mpc8xxx_spi_probe(ofdev);
 714         if (ret)
 715                 return ret;
 716 
 717         type = fsl_spi_get_type(&ofdev->dev);
 718         if (type == TYPE_FSL) {
 719                 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 720 #if IS_ENABLED(CONFIG_FSL_SOC)
 721                 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 722                 bool spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
 723 
 724                 if (spisel_boot) {
 725                         pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
 726                         if (!pinfo->immr_spi_cs) {
 727                                 ret = -ENOMEM;
 728                                 goto err;
 729                         }
 730                 }
 731 #endif
 732                 /*
 733                  * Handle the case where we have one hardwired (always selected)
 734                  * device on the first "chipselect". Else we let the core code
 735                  * handle any GPIOs or native chip selects and assign the
 736                  * appropriate callback for dealing with the CS lines. This isn't
 737                  * supported on the GRLIB variant.
 738                  */
 739                 ret = gpiod_count(dev, "cs");
 740                 if (ret <= 0)
 741                         pdata->max_chipselect = 1;
 742                 else
 743                         pdata->cs_control = fsl_spi_cs_control;
 744         }
 745 
 746         ret = of_address_to_resource(np, 0, &mem);
 747         if (ret)
 748                 goto err;
 749 
 750         irq = platform_get_irq(ofdev, 0);
 751         if (irq < 0) {
 752                 ret = irq;
 753                 goto err;
 754         }
 755 
 756         master = fsl_spi_probe(dev, &mem, irq);
 757         if (IS_ERR(master)) {
 758                 ret = PTR_ERR(master);
 759                 goto err;
 760         }
 761 
 762         return 0;
 763 
 764 err:
 765         return ret;
 766 }
 767 
 768 static int of_fsl_spi_remove(struct platform_device *ofdev)
 769 {
 770         struct spi_master *master = platform_get_drvdata(ofdev);
 771         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 772 
 773         fsl_spi_cpm_free(mpc8xxx_spi);
 774         return 0;
 775 }
 776 
 777 static struct platform_driver of_fsl_spi_driver = {
 778         .driver = {
 779                 .name = "fsl_spi",
 780                 .of_match_table = of_fsl_spi_match,
 781         },
 782         .probe          = of_fsl_spi_probe,
 783         .remove         = of_fsl_spi_remove,
 784 };
 785 
 786 #ifdef CONFIG_MPC832x_RDB
 787 /*
 788  * XXX XXX XXX
 789  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
 790  * only. The driver should go away soon, since newer MPC8323E-RDB's device
 791  * tree can work with OpenFirmware driver. But for now we support old trees
 792  * as well.
 793  */
 794 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
 795 {
 796         struct resource *mem;
 797         int irq;
 798         struct spi_master *master;
 799 
 800         if (!dev_get_platdata(&pdev->dev))
 801                 return -EINVAL;
 802 
 803         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 804         if (!mem)
 805                 return -EINVAL;
 806 
 807         irq = platform_get_irq(pdev, 0);
 808         if (irq <= 0)
 809                 return -EINVAL;
 810 
 811         master = fsl_spi_probe(&pdev->dev, mem, irq);
 812         return PTR_ERR_OR_ZERO(master);
 813 }
 814 
 815 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
 816 {
 817         struct spi_master *master = platform_get_drvdata(pdev);
 818         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 819 
 820         fsl_spi_cpm_free(mpc8xxx_spi);
 821 
 822         return 0;
 823 }
 824 
 825 MODULE_ALIAS("platform:mpc8xxx_spi");
 826 static struct platform_driver mpc8xxx_spi_driver = {
 827         .probe = plat_mpc8xxx_spi_probe,
 828         .remove = plat_mpc8xxx_spi_remove,
 829         .driver = {
 830                 .name = "mpc8xxx_spi",
 831         },
 832 };
 833 
 834 static bool legacy_driver_failed;
 835 
 836 static void __init legacy_driver_register(void)
 837 {
 838         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
 839 }
 840 
 841 static void __exit legacy_driver_unregister(void)
 842 {
 843         if (legacy_driver_failed)
 844                 return;
 845         platform_driver_unregister(&mpc8xxx_spi_driver);
 846 }
 847 #else
 848 static void __init legacy_driver_register(void) {}
 849 static void __exit legacy_driver_unregister(void) {}
 850 #endif /* CONFIG_MPC832x_RDB */
 851 
 852 static int __init fsl_spi_init(void)
 853 {
 854         legacy_driver_register();
 855         return platform_driver_register(&of_fsl_spi_driver);
 856 }
 857 module_init(fsl_spi_init);
 858 
 859 static void __exit fsl_spi_exit(void)
 860 {
 861         platform_driver_unregister(&of_fsl_spi_driver);
 862         legacy_driver_unregister();
 863 }
 864 module_exit(fsl_spi_exit);
 865 
 866 MODULE_AUTHOR("Kumar Gala");
 867 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
 868 MODULE_LICENSE("GPL");