drivers/spi/spi-sh-msiof.c

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This source file includes following definitions.
sh_msiof_read
sh_msiof_write
sh_msiof_modify_ctr_wait
sh_msiof_spi_irq
sh_msiof_spi_reset_regs
sh_msiof_spi_set_clk_regs
sh_msiof_get_delay_bit
sh_msiof_spi_get_dtdl_and_syncdl
sh_msiof_spi_set_pin_regs
sh_msiof_spi_set_mode_regs
sh_msiof_reset_str
sh_msiof_spi_write_fifo_8
sh_msiof_spi_write_fifo_16
sh_msiof_spi_write_fifo_16u
sh_msiof_spi_write_fifo_32
sh_msiof_spi_write_fifo_32u
sh_msiof_spi_write_fifo_s32
sh_msiof_spi_write_fifo_s32u
sh_msiof_spi_read_fifo_8
sh_msiof_spi_read_fifo_16
sh_msiof_spi_read_fifo_16u
sh_msiof_spi_read_fifo_32
sh_msiof_spi_read_fifo_32u
sh_msiof_spi_read_fifo_s32
sh_msiof_spi_read_fifo_s32u
sh_msiof_spi_setup
sh_msiof_prepare_message
sh_msiof_spi_start
sh_msiof_spi_stop
sh_msiof_slave_abort
sh_msiof_wait_for_completion
sh_msiof_spi_txrx_once
sh_msiof_dma_complete
sh_msiof_dma_once
copy_bswap32
copy_wswap32
copy_plain32
sh_msiof_transfer_one
sh_msiof_spi_parse_dt
sh_msiof_spi_parse_dt
sh_msiof_get_cs_gpios
sh_msiof_request_dma_chan
sh_msiof_request_dma
sh_msiof_release_dma
sh_msiof_spi_probe
sh_msiof_spi_remove
sh_msiof_spi_suspend
sh_msiof_spi_resume
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SuperH MSIOF SPI Controller Interface
   4  *
   5  * Copyright (c) 2009 Magnus Damm
   6  * Copyright (C) 2014 Renesas Electronics Corporation
   7  * Copyright (C) 2014-2017 Glider bvba
   8  */
   9 
  10 #include <linux/bitmap.h>
  11 #include <linux/clk.h>
  12 #include <linux/completion.h>
  13 #include <linux/delay.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/err.h>
  17 #include <linux/gpio.h>
  18 #include <linux/gpio/consumer.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/iopoll.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/sh_dma.h>
  29 
  30 #include <linux/spi/sh_msiof.h>
  31 #include <linux/spi/spi.h>
  32 
  33 #include <asm/unaligned.h>
  34 
  35 struct sh_msiof_chipdata {
  36         u32 bits_per_word_mask;
  37         u16 tx_fifo_size;
  38         u16 rx_fifo_size;
  39         u16 ctlr_flags;
  40         u16 min_div_pow;
  41 };
  42 
  43 struct sh_msiof_spi_priv {
  44         struct spi_controller *ctlr;
  45         void __iomem *mapbase;
  46         struct clk *clk;
  47         struct platform_device *pdev;
  48         struct sh_msiof_spi_info *info;
  49         struct completion done;
  50         struct completion done_txdma;
  51         unsigned int tx_fifo_size;
  52         unsigned int rx_fifo_size;
  53         unsigned int min_div_pow;
  54         void *tx_dma_page;
  55         void *rx_dma_page;
  56         dma_addr_t tx_dma_addr;
  57         dma_addr_t rx_dma_addr;
  58         unsigned short unused_ss;
  59         bool native_cs_inited;
  60         bool native_cs_high;
  61         bool slave_aborted;
  62 };
  63 
  64 #define MAX_SS  3       /* Maximum number of native chip selects */
  65 
  66 #define TMDR1   0x00    /* Transmit Mode Register 1 */
  67 #define TMDR2   0x04    /* Transmit Mode Register 2 */
  68 #define TMDR3   0x08    /* Transmit Mode Register 3 */
  69 #define RMDR1   0x10    /* Receive Mode Register 1 */
  70 #define RMDR2   0x14    /* Receive Mode Register 2 */
  71 #define RMDR3   0x18    /* Receive Mode Register 3 */
  72 #define TSCR    0x20    /* Transmit Clock Select Register */
  73 #define RSCR    0x22    /* Receive Clock Select Register (SH, A1, APE6) */
  74 #define CTR     0x28    /* Control Register */
  75 #define FCTR    0x30    /* FIFO Control Register */
  76 #define STR     0x40    /* Status Register */
  77 #define IER     0x44    /* Interrupt Enable Register */
  78 #define TDR1    0x48    /* Transmit Control Data Register 1 (SH, A1) */
  79 #define TDR2    0x4c    /* Transmit Control Data Register 2 (SH, A1) */
  80 #define TFDR    0x50    /* Transmit FIFO Data Register */
  81 #define RDR1    0x58    /* Receive Control Data Register 1 (SH, A1) */
  82 #define RDR2    0x5c    /* Receive Control Data Register 2 (SH, A1) */
  83 #define RFDR    0x60    /* Receive FIFO Data Register */
  84 
  85 /* TMDR1 and RMDR1 */
  86 #define MDR1_TRMD          BIT(31)  /* Transfer Mode (1 = Master mode) */
  87 #define MDR1_SYNCMD_MASK   GENMASK(29, 28) /* SYNC Mode */
  88 #define MDR1_SYNCMD_SPI    (2 << 28)/*   Level mode/SPI */
  89 #define MDR1_SYNCMD_LR     (3 << 28)/*   L/R mode */
  90 #define MDR1_SYNCAC_SHIFT  25       /* Sync Polarity (1 = Active-low) */
  91 #define MDR1_BITLSB_SHIFT  24       /* MSB/LSB First (1 = LSB first) */
  92 #define MDR1_DTDL_SHIFT    20       /* Data Pin Bit Delay for MSIOF_SYNC */
  93 #define MDR1_SYNCDL_SHIFT  16       /* Frame Sync Signal Timing Delay */
  94 #define MDR1_FLD_MASK      GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
  95 #define MDR1_FLD_SHIFT     2
  96 #define MDR1_XXSTP         BIT(0)   /* Transmission/Reception Stop on FIFO */
  97 /* TMDR1 */
  98 #define TMDR1_PCON         BIT(30)  /* Transfer Signal Connection */
  99 #define TMDR1_SYNCCH_MASK  GENMASK(27, 26) /* Sync Signal Channel Select */
 100 #define TMDR1_SYNCCH_SHIFT 26       /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
 101 
 102 /* TMDR2 and RMDR2 */
 103 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
 104 #define MDR2_WDLEN1(i)  (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
 105 #define MDR2_GRPMASK1   BIT(0)      /* Group Output Mask 1 (SH, A1) */
 106 
 107 /* TSCR and RSCR */
 108 #define SCR_BRPS_MASK   GENMASK(12, 8) /* Prescaler Setting (1-32) */
 109 #define SCR_BRPS(i)     (((i) - 1) << 8)
 110 #define SCR_BRDV_MASK   GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */
 111 #define SCR_BRDV_DIV_2  0
 112 #define SCR_BRDV_DIV_4  1
 113 #define SCR_BRDV_DIV_8  2
 114 #define SCR_BRDV_DIV_16 3
 115 #define SCR_BRDV_DIV_32 4
 116 #define SCR_BRDV_DIV_1  7
 117 
 118 /* CTR */
 119 #define CTR_TSCKIZ_MASK GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */
 120 #define CTR_TSCKIZ_SCK  BIT(31)   /*   Disable SCK when TX disabled */
 121 #define CTR_TSCKIZ_POL_SHIFT 30   /*   Transmit Clock Polarity */
 122 #define CTR_RSCKIZ_MASK GENMASK(29, 28) /* Receive Clock Polarity Select */
 123 #define CTR_RSCKIZ_SCK  BIT(29)   /*   Must match CTR_TSCKIZ_SCK */
 124 #define CTR_RSCKIZ_POL_SHIFT 28   /*   Receive Clock Polarity */
 125 #define CTR_TEDG_SHIFT       27   /* Transmit Timing (1 = falling edge) */
 126 #define CTR_REDG_SHIFT       26   /* Receive Timing (1 = falling edge) */
 127 #define CTR_TXDIZ_MASK  GENMASK(23, 22) /* Pin Output When TX is Disabled */
 128 #define CTR_TXDIZ_LOW   (0 << 22) /*   0 */
 129 #define CTR_TXDIZ_HIGH  (1 << 22) /*   1 */
 130 #define CTR_TXDIZ_HIZ   (2 << 22) /*   High-impedance */
 131 #define CTR_TSCKE       BIT(15)   /* Transmit Serial Clock Output Enable */
 132 #define CTR_TFSE        BIT(14)   /* Transmit Frame Sync Signal Output Enable */
 133 #define CTR_TXE         BIT(9)    /* Transmit Enable */
 134 #define CTR_RXE         BIT(8)    /* Receive Enable */
 135 #define CTR_TXRST       BIT(1)    /* Transmit Reset */
 136 #define CTR_RXRST       BIT(0)    /* Receive Reset */
 137 
 138 /* FCTR */
 139 #define FCTR_TFWM_MASK  GENMASK(31, 29) /* Transmit FIFO Watermark */
 140 #define FCTR_TFWM_64    (0 << 29) /*  Transfer Request when 64 empty stages */
 141 #define FCTR_TFWM_32    (1 << 29) /*  Transfer Request when 32 empty stages */
 142 #define FCTR_TFWM_24    (2 << 29) /*  Transfer Request when 24 empty stages */
 143 #define FCTR_TFWM_16    (3 << 29) /*  Transfer Request when 16 empty stages */
 144 #define FCTR_TFWM_12    (4 << 29) /*  Transfer Request when 12 empty stages */
 145 #define FCTR_TFWM_8     (5 << 29) /*  Transfer Request when 8 empty stages */
 146 #define FCTR_TFWM_4     (6 << 29) /*  Transfer Request when 4 empty stages */
 147 #define FCTR_TFWM_1     (7 << 29) /*  Transfer Request when 1 empty stage */
 148 #define FCTR_TFUA_MASK  GENMASK(26, 20) /* Transmit FIFO Usable Area */
 149 #define FCTR_TFUA_SHIFT 20
 150 #define FCTR_TFUA(i)    ((i) << FCTR_TFUA_SHIFT)
 151 #define FCTR_RFWM_MASK  GENMASK(15, 13) /* Receive FIFO Watermark */
 152 #define FCTR_RFWM_1     (0 << 13) /*  Transfer Request when 1 valid stages */
 153 #define FCTR_RFWM_4     (1 << 13) /*  Transfer Request when 4 valid stages */
 154 #define FCTR_RFWM_8     (2 << 13) /*  Transfer Request when 8 valid stages */
 155 #define FCTR_RFWM_16    (3 << 13) /*  Transfer Request when 16 valid stages */
 156 #define FCTR_RFWM_32    (4 << 13) /*  Transfer Request when 32 valid stages */
 157 #define FCTR_RFWM_64    (5 << 13) /*  Transfer Request when 64 valid stages */
 158 #define FCTR_RFWM_128   (6 << 13) /*  Transfer Request when 128 valid stages */
 159 #define FCTR_RFWM_256   (7 << 13) /*  Transfer Request when 256 valid stages */
 160 #define FCTR_RFUA_MASK  GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */
 161 #define FCTR_RFUA_SHIFT 4
 162 #define FCTR_RFUA(i)    ((i) << FCTR_RFUA_SHIFT)
 163 
 164 /* STR */
 165 #define STR_TFEMP       BIT(29) /* Transmit FIFO Empty */
 166 #define STR_TDREQ       BIT(28) /* Transmit Data Transfer Request */
 167 #define STR_TEOF        BIT(23) /* Frame Transmission End */
 168 #define STR_TFSERR      BIT(21) /* Transmit Frame Synchronization Error */
 169 #define STR_TFOVF       BIT(20) /* Transmit FIFO Overflow */
 170 #define STR_TFUDF       BIT(19) /* Transmit FIFO Underflow */
 171 #define STR_RFFUL       BIT(13) /* Receive FIFO Full */
 172 #define STR_RDREQ       BIT(12) /* Receive Data Transfer Request */
 173 #define STR_REOF        BIT(7)  /* Frame Reception End */
 174 #define STR_RFSERR      BIT(5)  /* Receive Frame Synchronization Error */
 175 #define STR_RFUDF       BIT(4)  /* Receive FIFO Underflow */
 176 #define STR_RFOVF       BIT(3)  /* Receive FIFO Overflow */
 177 
 178 /* IER */
 179 #define IER_TDMAE       BIT(31) /* Transmit Data DMA Transfer Req. Enable */
 180 #define IER_TFEMPE      BIT(29) /* Transmit FIFO Empty Enable */
 181 #define IER_TDREQE      BIT(28) /* Transmit Data Transfer Request Enable */
 182 #define IER_TEOFE       BIT(23) /* Frame Transmission End Enable */
 183 #define IER_TFSERRE     BIT(21) /* Transmit Frame Sync Error Enable */
 184 #define IER_TFOVFE      BIT(20) /* Transmit FIFO Overflow Enable */
 185 #define IER_TFUDFE      BIT(19) /* Transmit FIFO Underflow Enable */
 186 #define IER_RDMAE       BIT(15) /* Receive Data DMA Transfer Req. Enable */
 187 #define IER_RFFULE      BIT(13) /* Receive FIFO Full Enable */
 188 #define IER_RDREQE      BIT(12) /* Receive Data Transfer Request Enable */
 189 #define IER_REOFE       BIT(7)  /* Frame Reception End Enable */
 190 #define IER_RFSERRE     BIT(5)  /* Receive Frame Sync Error Enable */
 191 #define IER_RFUDFE      BIT(4)  /* Receive FIFO Underflow Enable */
 192 #define IER_RFOVFE      BIT(3)  /* Receive FIFO Overflow Enable */
 193 
 194 
 195 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
 196 {
 197         switch (reg_offs) {
 198         case TSCR:
 199         case RSCR:
 200                 return ioread16(p->mapbase + reg_offs);
 201         default:
 202                 return ioread32(p->mapbase + reg_offs);
 203         }
 204 }
 205 
 206 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
 207                            u32 value)
 208 {
 209         switch (reg_offs) {
 210         case TSCR:
 211         case RSCR:
 212                 iowrite16(value, p->mapbase + reg_offs);
 213                 break;
 214         default:
 215                 iowrite32(value, p->mapbase + reg_offs);
 216                 break;
 217         }
 218 }
 219 
 220 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
 221                                     u32 clr, u32 set)
 222 {
 223         u32 mask = clr | set;
 224         u32 data;
 225 
 226         data = sh_msiof_read(p, CTR);
 227         data &= ~clr;
 228         data |= set;
 229         sh_msiof_write(p, CTR, data);
 230 
 231         return readl_poll_timeout_atomic(p->mapbase + CTR, data,
 232                                          (data & mask) == set, 1, 100);
 233 }
 234 
 235 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
 236 {
 237         struct sh_msiof_spi_priv *p = data;
 238 
 239         /* just disable the interrupt and wake up */
 240         sh_msiof_write(p, IER, 0);
 241         complete(&p->done);
 242 
 243         return IRQ_HANDLED;
 244 }
 245 
 246 static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
 247 {
 248         u32 mask = CTR_TXRST | CTR_RXRST;
 249         u32 data;
 250 
 251         data = sh_msiof_read(p, CTR);
 252         data |= mask;
 253         sh_msiof_write(p, CTR, data);
 254 
 255         readl_poll_timeout_atomic(p->mapbase + CTR, data, !(data & mask), 1,
 256                                   100);
 257 }
 258 
 259 static const u32 sh_msiof_spi_div_array[] = {
 260         SCR_BRDV_DIV_1, SCR_BRDV_DIV_2,  SCR_BRDV_DIV_4,
 261         SCR_BRDV_DIV_8, SCR_BRDV_DIV_16, SCR_BRDV_DIV_32,
 262 };
 263 
 264 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
 265                                       unsigned long parent_rate, u32 spi_hz)
 266 {
 267         unsigned long div;
 268         u32 brps, scr;
 269         unsigned int div_pow = p->min_div_pow;
 270 
 271         if (!spi_hz || !parent_rate) {
 272                 WARN(1, "Invalid clock rate parameters %lu and %u\n",
 273                      parent_rate, spi_hz);
 274                 return;
 275         }
 276 
 277         div = DIV_ROUND_UP(parent_rate, spi_hz);
 278         if (div <= 1024) {
 279                 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
 280                 if (!div_pow && div <= 32 && div > 2)
 281                         div_pow = 1;
 282 
 283                 if (div_pow)
 284                         brps = (div + 1) >> div_pow;
 285                 else
 286                         brps = div;
 287 
 288                 for (; brps > 32; div_pow++)
 289                         brps = (brps + 1) >> 1;
 290         } else {
 291                 /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
 292                 dev_err(&p->pdev->dev,
 293                         "Requested SPI transfer rate %d is too low\n", spi_hz);
 294                 div_pow = 5;
 295                 brps = 32;
 296         }
 297 
 298         scr = sh_msiof_spi_div_array[div_pow] | SCR_BRPS(brps);
 299         sh_msiof_write(p, TSCR, scr);
 300         if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
 301                 sh_msiof_write(p, RSCR, scr);
 302 }
 303 
 304 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
 305 {
 306         /*
 307          * DTDL/SYNCDL bit      : p->info->dtdl or p->info->syncdl
 308          * b'000                : 0
 309          * b'001                : 100
 310          * b'010                : 200
 311          * b'011 (SYNCDL only)  : 300
 312          * b'101                : 50
 313          * b'110                : 150
 314          */
 315         if (dtdl_or_syncdl % 100)
 316                 return dtdl_or_syncdl / 100 + 5;
 317         else
 318                 return dtdl_or_syncdl / 100;
 319 }
 320 
 321 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
 322 {
 323         u32 val;
 324 
 325         if (!p->info)
 326                 return 0;
 327 
 328         /* check if DTDL and SYNCDL is allowed value */
 329         if (p->info->dtdl > 200 || p->info->syncdl > 300) {
 330                 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
 331                 return 0;
 332         }
 333 
 334         /* check if the sum of DTDL and SYNCDL becomes an integer value  */
 335         if ((p->info->dtdl + p->info->syncdl) % 100) {
 336                 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
 337                 return 0;
 338         }
 339 
 340         val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
 341         val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
 342 
 343         return val;
 344 }
 345 
 346 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
 347                                       u32 cpol, u32 cpha,
 348                                       u32 tx_hi_z, u32 lsb_first, u32 cs_high)
 349 {
 350         u32 tmp;
 351         int edge;
 352 
 353         /*
 354          * CPOL CPHA     TSCKIZ RSCKIZ TEDG REDG
 355          *    0    0         10     10    1    1
 356          *    0    1         10     10    0    0
 357          *    1    0         11     11    0    0
 358          *    1    1         11     11    1    1
 359          */
 360         tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
 361         tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
 362         tmp |= lsb_first << MDR1_BITLSB_SHIFT;
 363         tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
 364         if (spi_controller_is_slave(p->ctlr)) {
 365                 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON);
 366         } else {
 367                 sh_msiof_write(p, TMDR1,
 368                                tmp | MDR1_TRMD | TMDR1_PCON |
 369                                (ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT);
 370         }
 371         if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) {
 372                 /* These bits are reserved if RX needs TX */
 373                 tmp &= ~0x0000ffff;
 374         }
 375         sh_msiof_write(p, RMDR1, tmp);
 376 
 377         tmp = 0;
 378         tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
 379         tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
 380 
 381         edge = cpol ^ !cpha;
 382 
 383         tmp |= edge << CTR_TEDG_SHIFT;
 384         tmp |= edge << CTR_REDG_SHIFT;
 385         tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
 386         sh_msiof_write(p, CTR, tmp);
 387 }
 388 
 389 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
 390                                        const void *tx_buf, void *rx_buf,
 391                                        u32 bits, u32 words)
 392 {
 393         u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
 394 
 395         if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
 396                 sh_msiof_write(p, TMDR2, dr2);
 397         else
 398                 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
 399 
 400         if (rx_buf)
 401                 sh_msiof_write(p, RMDR2, dr2);
 402 }
 403 
 404 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
 405 {
 406         sh_msiof_write(p, STR,
 407                        sh_msiof_read(p, STR) & ~(STR_TDREQ | STR_RDREQ));
 408 }
 409 
 410 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
 411                                       const void *tx_buf, int words, int fs)
 412 {
 413         const u8 *buf_8 = tx_buf;
 414         int k;
 415 
 416         for (k = 0; k < words; k++)
 417                 sh_msiof_write(p, TFDR, buf_8[k] << fs);
 418 }
 419 
 420 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
 421                                        const void *tx_buf, int words, int fs)
 422 {
 423         const u16 *buf_16 = tx_buf;
 424         int k;
 425 
 426         for (k = 0; k < words; k++)
 427                 sh_msiof_write(p, TFDR, buf_16[k] << fs);
 428 }
 429 
 430 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
 431                                         const void *tx_buf, int words, int fs)
 432 {
 433         const u16 *buf_16 = tx_buf;
 434         int k;
 435 
 436         for (k = 0; k < words; k++)
 437                 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
 438 }
 439 
 440 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
 441                                        const void *tx_buf, int words, int fs)
 442 {
 443         const u32 *buf_32 = tx_buf;
 444         int k;
 445 
 446         for (k = 0; k < words; k++)
 447                 sh_msiof_write(p, TFDR, buf_32[k] << fs);
 448 }
 449 
 450 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
 451                                         const void *tx_buf, int words, int fs)
 452 {
 453         const u32 *buf_32 = tx_buf;
 454         int k;
 455 
 456         for (k = 0; k < words; k++)
 457                 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
 458 }
 459 
 460 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
 461                                         const void *tx_buf, int words, int fs)
 462 {
 463         const u32 *buf_32 = tx_buf;
 464         int k;
 465 
 466         for (k = 0; k < words; k++)
 467                 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
 468 }
 469 
 470 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
 471                                          const void *tx_buf, int words, int fs)
 472 {
 473         const u32 *buf_32 = tx_buf;
 474         int k;
 475 
 476         for (k = 0; k < words; k++)
 477                 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
 478 }
 479 
 480 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
 481                                      void *rx_buf, int words, int fs)
 482 {
 483         u8 *buf_8 = rx_buf;
 484         int k;
 485 
 486         for (k = 0; k < words; k++)
 487                 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
 488 }
 489 
 490 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
 491                                       void *rx_buf, int words, int fs)
 492 {
 493         u16 *buf_16 = rx_buf;
 494         int k;
 495 
 496         for (k = 0; k < words; k++)
 497                 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
 498 }
 499 
 500 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
 501                                        void *rx_buf, int words, int fs)
 502 {
 503         u16 *buf_16 = rx_buf;
 504         int k;
 505 
 506         for (k = 0; k < words; k++)
 507                 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
 508 }
 509 
 510 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
 511                                       void *rx_buf, int words, int fs)
 512 {
 513         u32 *buf_32 = rx_buf;
 514         int k;
 515 
 516         for (k = 0; k < words; k++)
 517                 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
 518 }
 519 
 520 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
 521                                        void *rx_buf, int words, int fs)
 522 {
 523         u32 *buf_32 = rx_buf;
 524         int k;
 525 
 526         for (k = 0; k < words; k++)
 527                 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
 528 }
 529 
 530 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
 531                                        void *rx_buf, int words, int fs)
 532 {
 533         u32 *buf_32 = rx_buf;
 534         int k;
 535 
 536         for (k = 0; k < words; k++)
 537                 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
 538 }
 539 
 540 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
 541                                        void *rx_buf, int words, int fs)
 542 {
 543         u32 *buf_32 = rx_buf;
 544         int k;
 545 
 546         for (k = 0; k < words; k++)
 547                 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
 548 }
 549 
 550 static int sh_msiof_spi_setup(struct spi_device *spi)
 551 {
 552         struct sh_msiof_spi_priv *p =
 553                 spi_controller_get_devdata(spi->controller);
 554         u32 clr, set, tmp;
 555 
 556         if (spi->cs_gpiod || spi_controller_is_slave(p->ctlr))
 557                 return 0;
 558 
 559         if (p->native_cs_inited &&
 560             (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
 561                 return 0;
 562 
 563         /* Configure native chip select mode/polarity early */
 564         clr = MDR1_SYNCMD_MASK;
 565         set = MDR1_SYNCMD_SPI;
 566         if (spi->mode & SPI_CS_HIGH)
 567                 clr |= BIT(MDR1_SYNCAC_SHIFT);
 568         else
 569                 set |= BIT(MDR1_SYNCAC_SHIFT);
 570         pm_runtime_get_sync(&p->pdev->dev);
 571         tmp = sh_msiof_read(p, TMDR1) & ~clr;
 572         sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
 573         tmp = sh_msiof_read(p, RMDR1) & ~clr;
 574         sh_msiof_write(p, RMDR1, tmp | set);
 575         pm_runtime_put(&p->pdev->dev);
 576         p->native_cs_high = spi->mode & SPI_CS_HIGH;
 577         p->native_cs_inited = true;
 578         return 0;
 579 }
 580 
 581 static int sh_msiof_prepare_message(struct spi_controller *ctlr,
 582                                     struct spi_message *msg)
 583 {
 584         struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
 585         const struct spi_device *spi = msg->spi;
 586         u32 ss, cs_high;
 587 
 588         /* Configure pins before asserting CS */
 589         if (spi->cs_gpiod) {
 590                 ss = p->unused_ss;
 591                 cs_high = p->native_cs_high;
 592         } else {
 593                 ss = spi->chip_select;
 594                 cs_high = !!(spi->mode & SPI_CS_HIGH);
 595         }
 596         sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL),
 597                                   !!(spi->mode & SPI_CPHA),
 598                                   !!(spi->mode & SPI_3WIRE),
 599                                   !!(spi->mode & SPI_LSB_FIRST), cs_high);
 600         return 0;
 601 }
 602 
 603 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
 604 {
 605         bool slave = spi_controller_is_slave(p->ctlr);
 606         int ret = 0;
 607 
 608         /* setup clock and rx/tx signals */
 609         if (!slave)
 610                 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
 611         if (rx_buf && !ret)
 612                 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
 613         if (!ret)
 614                 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
 615 
 616         /* start by setting frame bit */
 617         if (!ret && !slave)
 618                 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
 619 
 620         return ret;
 621 }
 622 
 623 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
 624 {
 625         bool slave = spi_controller_is_slave(p->ctlr);
 626         int ret = 0;
 627 
 628         /* shut down frame, rx/tx and clock signals */
 629         if (!slave)
 630                 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
 631         if (!ret)
 632                 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
 633         if (rx_buf && !ret)
 634                 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
 635         if (!ret && !slave)
 636                 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
 637 
 638         return ret;
 639 }
 640 
 641 static int sh_msiof_slave_abort(struct spi_controller *ctlr)
 642 {
 643         struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
 644 
 645         p->slave_aborted = true;
 646         complete(&p->done);
 647         complete(&p->done_txdma);
 648         return 0;
 649 }
 650 
 651 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
 652                                         struct completion *x)
 653 {
 654         if (spi_controller_is_slave(p->ctlr)) {
 655                 if (wait_for_completion_interruptible(x) ||
 656                     p->slave_aborted) {
 657                         dev_dbg(&p->pdev->dev, "interrupted\n");
 658                         return -EINTR;
 659                 }
 660         } else {
 661                 if (!wait_for_completion_timeout(x, HZ)) {
 662                         dev_err(&p->pdev->dev, "timeout\n");
 663                         return -ETIMEDOUT;
 664                 }
 665         }
 666 
 667         return 0;
 668 }
 669 
 670 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
 671                                   void (*tx_fifo)(struct sh_msiof_spi_priv *,
 672                                                   const void *, int, int),
 673                                   void (*rx_fifo)(struct sh_msiof_spi_priv *,
 674                                                   void *, int, int),
 675                                   const void *tx_buf, void *rx_buf,
 676                                   int words, int bits)
 677 {
 678         int fifo_shift;
 679         int ret;
 680 
 681         /* limit maximum word transfer to rx/tx fifo size */
 682         if (tx_buf)
 683                 words = min_t(int, words, p->tx_fifo_size);
 684         if (rx_buf)
 685                 words = min_t(int, words, p->rx_fifo_size);
 686 
 687         /* the fifo contents need shifting */
 688         fifo_shift = 32 - bits;
 689 
 690         /* default FIFO watermarks for PIO */
 691         sh_msiof_write(p, FCTR, 0);
 692 
 693         /* setup msiof transfer mode registers */
 694         sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
 695         sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
 696 
 697         /* write tx fifo */
 698         if (tx_buf)
 699                 tx_fifo(p, tx_buf, words, fifo_shift);
 700 
 701         reinit_completion(&p->done);
 702         p->slave_aborted = false;
 703 
 704         ret = sh_msiof_spi_start(p, rx_buf);
 705         if (ret) {
 706                 dev_err(&p->pdev->dev, "failed to start hardware\n");
 707                 goto stop_ier;
 708         }
 709 
 710         /* wait for tx fifo to be emptied / rx fifo to be filled */
 711         ret = sh_msiof_wait_for_completion(p, &p->done);
 712         if (ret)
 713                 goto stop_reset;
 714 
 715         /* read rx fifo */
 716         if (rx_buf)
 717                 rx_fifo(p, rx_buf, words, fifo_shift);
 718 
 719         /* clear status bits */
 720         sh_msiof_reset_str(p);
 721 
 722         ret = sh_msiof_spi_stop(p, rx_buf);
 723         if (ret) {
 724                 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
 725                 return ret;
 726         }
 727 
 728         return words;
 729 
 730 stop_reset:
 731         sh_msiof_reset_str(p);
 732         sh_msiof_spi_stop(p, rx_buf);
 733 stop_ier:
 734         sh_msiof_write(p, IER, 0);
 735         return ret;
 736 }
 737 
 738 static void sh_msiof_dma_complete(void *arg)
 739 {
 740         complete(arg);
 741 }
 742 
 743 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
 744                              void *rx, unsigned int len)
 745 {
 746         u32 ier_bits = 0;
 747         struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
 748         dma_cookie_t cookie;
 749         int ret;
 750 
 751         /* First prepare and submit the DMA request(s), as this may fail */
 752         if (rx) {
 753                 ier_bits |= IER_RDREQE | IER_RDMAE;
 754                 desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx,
 755                                         p->rx_dma_addr, len, DMA_DEV_TO_MEM,
 756                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 757                 if (!desc_rx)
 758                         return -EAGAIN;
 759 
 760                 desc_rx->callback = sh_msiof_dma_complete;
 761                 desc_rx->callback_param = &p->done;
 762                 cookie = dmaengine_submit(desc_rx);
 763                 if (dma_submit_error(cookie))
 764                         return cookie;
 765         }
 766 
 767         if (tx) {
 768                 ier_bits |= IER_TDREQE | IER_TDMAE;
 769                 dma_sync_single_for_device(p->ctlr->dma_tx->device->dev,
 770                                            p->tx_dma_addr, len, DMA_TO_DEVICE);
 771                 desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx,
 772                                         p->tx_dma_addr, len, DMA_MEM_TO_DEV,
 773                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 774                 if (!desc_tx) {
 775                         ret = -EAGAIN;
 776                         goto no_dma_tx;
 777                 }
 778 
 779                 desc_tx->callback = sh_msiof_dma_complete;
 780                 desc_tx->callback_param = &p->done_txdma;
 781                 cookie = dmaengine_submit(desc_tx);
 782                 if (dma_submit_error(cookie)) {
 783                         ret = cookie;
 784                         goto no_dma_tx;
 785                 }
 786         }
 787 
 788         /* 1 stage FIFO watermarks for DMA */
 789         sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
 790 
 791         /* setup msiof transfer mode registers (32-bit words) */
 792         sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
 793 
 794         sh_msiof_write(p, IER, ier_bits);
 795 
 796         reinit_completion(&p->done);
 797         if (tx)
 798                 reinit_completion(&p->done_txdma);
 799         p->slave_aborted = false;
 800 
 801         /* Now start DMA */
 802         if (rx)
 803                 dma_async_issue_pending(p->ctlr->dma_rx);
 804         if (tx)
 805                 dma_async_issue_pending(p->ctlr->dma_tx);
 806 
 807         ret = sh_msiof_spi_start(p, rx);
 808         if (ret) {
 809                 dev_err(&p->pdev->dev, "failed to start hardware\n");
 810                 goto stop_dma;
 811         }
 812 
 813         if (tx) {
 814                 /* wait for tx DMA completion */
 815                 ret = sh_msiof_wait_for_completion(p, &p->done_txdma);
 816                 if (ret)
 817                         goto stop_reset;
 818         }
 819 
 820         if (rx) {
 821                 /* wait for rx DMA completion */
 822                 ret = sh_msiof_wait_for_completion(p, &p->done);
 823                 if (ret)
 824                         goto stop_reset;
 825 
 826                 sh_msiof_write(p, IER, 0);
 827         } else {
 828                 /* wait for tx fifo to be emptied */
 829                 sh_msiof_write(p, IER, IER_TEOFE);
 830                 ret = sh_msiof_wait_for_completion(p, &p->done);
 831                 if (ret)
 832                         goto stop_reset;
 833         }
 834 
 835         /* clear status bits */
 836         sh_msiof_reset_str(p);
 837 
 838         ret = sh_msiof_spi_stop(p, rx);
 839         if (ret) {
 840                 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
 841                 return ret;
 842         }
 843 
 844         if (rx)
 845                 dma_sync_single_for_cpu(p->ctlr->dma_rx->device->dev,
 846                                         p->rx_dma_addr, len, DMA_FROM_DEVICE);
 847 
 848         return 0;
 849 
 850 stop_reset:
 851         sh_msiof_reset_str(p);
 852         sh_msiof_spi_stop(p, rx);
 853 stop_dma:
 854         if (tx)
 855                 dmaengine_terminate_all(p->ctlr->dma_tx);
 856 no_dma_tx:
 857         if (rx)
 858                 dmaengine_terminate_all(p->ctlr->dma_rx);
 859         sh_msiof_write(p, IER, 0);
 860         return ret;
 861 }
 862 
 863 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
 864 {
 865         /* src or dst can be unaligned, but not both */
 866         if ((unsigned long)src & 3) {
 867                 while (words--) {
 868                         *dst++ = swab32(get_unaligned(src));
 869                         src++;
 870                 }
 871         } else if ((unsigned long)dst & 3) {
 872                 while (words--) {
 873                         put_unaligned(swab32(*src++), dst);
 874                         dst++;
 875                 }
 876         } else {
 877                 while (words--)
 878                         *dst++ = swab32(*src++);
 879         }
 880 }
 881 
 882 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
 883 {
 884         /* src or dst can be unaligned, but not both */
 885         if ((unsigned long)src & 3) {
 886                 while (words--) {
 887                         *dst++ = swahw32(get_unaligned(src));
 888                         src++;
 889                 }
 890         } else if ((unsigned long)dst & 3) {
 891                 while (words--) {
 892                         put_unaligned(swahw32(*src++), dst);
 893                         dst++;
 894                 }
 895         } else {
 896                 while (words--)
 897                         *dst++ = swahw32(*src++);
 898         }
 899 }
 900 
 901 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
 902 {
 903         memcpy(dst, src, words * 4);
 904 }
 905 
 906 static int sh_msiof_transfer_one(struct spi_controller *ctlr,
 907                                  struct spi_device *spi,
 908                                  struct spi_transfer *t)
 909 {
 910         struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
 911         void (*copy32)(u32 *, const u32 *, unsigned int);
 912         void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
 913         void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
 914         const void *tx_buf = t->tx_buf;
 915         void *rx_buf = t->rx_buf;
 916         unsigned int len = t->len;
 917         unsigned int bits = t->bits_per_word;
 918         unsigned int bytes_per_word;
 919         unsigned int words;
 920         int n;
 921         bool swab;
 922         int ret;
 923 
 924         /* reset registers */
 925         sh_msiof_spi_reset_regs(p);
 926 
 927         /* setup clocks (clock already enabled in chipselect()) */
 928         if (!spi_controller_is_slave(p->ctlr))
 929                 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
 930 
 931         while (ctlr->dma_tx && len > 15) {
 932                 /*
 933                  *  DMA supports 32-bit words only, hence pack 8-bit and 16-bit
 934                  *  words, with byte resp. word swapping.
 935                  */
 936                 unsigned int l = 0;
 937 
 938                 if (tx_buf)
 939                         l = min(round_down(len, 4), p->tx_fifo_size * 4);
 940                 if (rx_buf)
 941                         l = min(round_down(len, 4), p->rx_fifo_size * 4);
 942 
 943                 if (bits <= 8) {
 944                         copy32 = copy_bswap32;
 945                 } else if (bits <= 16) {
 946                         copy32 = copy_wswap32;
 947                 } else {
 948                         copy32 = copy_plain32;
 949                 }
 950 
 951                 if (tx_buf)
 952                         copy32(p->tx_dma_page, tx_buf, l / 4);
 953 
 954                 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
 955                 if (ret == -EAGAIN) {
 956                         dev_warn_once(&p->pdev->dev,
 957                                 "DMA not available, falling back to PIO\n");
 958                         break;
 959                 }
 960                 if (ret)
 961                         return ret;
 962 
 963                 if (rx_buf) {
 964                         copy32(rx_buf, p->rx_dma_page, l / 4);
 965                         rx_buf += l;
 966                 }
 967                 if (tx_buf)
 968                         tx_buf += l;
 969 
 970                 len -= l;
 971                 if (!len)
 972                         return 0;
 973         }
 974 
 975         if (bits <= 8 && len > 15) {
 976                 bits = 32;
 977                 swab = true;
 978         } else {
 979                 swab = false;
 980         }
 981 
 982         /* setup bytes per word and fifo read/write functions */
 983         if (bits <= 8) {
 984                 bytes_per_word = 1;
 985                 tx_fifo = sh_msiof_spi_write_fifo_8;
 986                 rx_fifo = sh_msiof_spi_read_fifo_8;
 987         } else if (bits <= 16) {
 988                 bytes_per_word = 2;
 989                 if ((unsigned long)tx_buf & 0x01)
 990                         tx_fifo = sh_msiof_spi_write_fifo_16u;
 991                 else
 992                         tx_fifo = sh_msiof_spi_write_fifo_16;
 993 
 994                 if ((unsigned long)rx_buf & 0x01)
 995                         rx_fifo = sh_msiof_spi_read_fifo_16u;
 996                 else
 997                         rx_fifo = sh_msiof_spi_read_fifo_16;
 998         } else if (swab) {
 999                 bytes_per_word = 4;
1000                 if ((unsigned long)tx_buf & 0x03)
1001                         tx_fifo = sh_msiof_spi_write_fifo_s32u;
1002                 else
1003                         tx_fifo = sh_msiof_spi_write_fifo_s32;
1004 
1005                 if ((unsigned long)rx_buf & 0x03)
1006                         rx_fifo = sh_msiof_spi_read_fifo_s32u;
1007                 else
1008                         rx_fifo = sh_msiof_spi_read_fifo_s32;
1009         } else {
1010                 bytes_per_word = 4;
1011                 if ((unsigned long)tx_buf & 0x03)
1012                         tx_fifo = sh_msiof_spi_write_fifo_32u;
1013                 else
1014                         tx_fifo = sh_msiof_spi_write_fifo_32;
1015 
1016                 if ((unsigned long)rx_buf & 0x03)
1017                         rx_fifo = sh_msiof_spi_read_fifo_32u;
1018                 else
1019                         rx_fifo = sh_msiof_spi_read_fifo_32;
1020         }
1021 
1022         /* transfer in fifo sized chunks */
1023         words = len / bytes_per_word;
1024 
1025         while (words > 0) {
1026                 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
1027                                            words, bits);
1028                 if (n < 0)
1029                         return n;
1030 
1031                 if (tx_buf)
1032                         tx_buf += n * bytes_per_word;
1033                 if (rx_buf)
1034                         rx_buf += n * bytes_per_word;
1035                 words -= n;
1036 
1037                 if (words == 0 && (len % bytes_per_word)) {
1038                         words = len % bytes_per_word;
1039                         bits = t->bits_per_word;
1040                         bytes_per_word = 1;
1041                         tx_fifo = sh_msiof_spi_write_fifo_8;
1042                         rx_fifo = sh_msiof_spi_read_fifo_8;
1043                 }
1044         }
1045 
1046         return 0;
1047 }
1048 
1049 static const struct sh_msiof_chipdata sh_data = {
1050         .bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32),
1051         .tx_fifo_size = 64,
1052         .rx_fifo_size = 64,
1053         .ctlr_flags = 0,
1054         .min_div_pow = 0,
1055 };
1056 
1057 static const struct sh_msiof_chipdata rcar_gen2_data = {
1058         .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1059                               SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1060         .tx_fifo_size = 64,
1061         .rx_fifo_size = 64,
1062         .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1063         .min_div_pow = 0,
1064 };
1065 
1066 static const struct sh_msiof_chipdata rcar_gen3_data = {
1067         .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1068                               SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1069         .tx_fifo_size = 64,
1070         .rx_fifo_size = 64,
1071         .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1072         .min_div_pow = 1,
1073 };
1074 
1075 static const struct of_device_id sh_msiof_match[] = {
1076         { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1077         { .compatible = "renesas,msiof-r8a7743",   .data = &rcar_gen2_data },
1078         { .compatible = "renesas,msiof-r8a7745",   .data = &rcar_gen2_data },
1079         { .compatible = "renesas,msiof-r8a7790",   .data = &rcar_gen2_data },
1080         { .compatible = "renesas,msiof-r8a7791",   .data = &rcar_gen2_data },
1081         { .compatible = "renesas,msiof-r8a7792",   .data = &rcar_gen2_data },
1082         { .compatible = "renesas,msiof-r8a7793",   .data = &rcar_gen2_data },
1083         { .compatible = "renesas,msiof-r8a7794",   .data = &rcar_gen2_data },
1084         { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1085         { .compatible = "renesas,msiof-r8a7796",   .data = &rcar_gen3_data },
1086         { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1087         { .compatible = "renesas,sh-msiof",        .data = &sh_data }, /* Deprecated */
1088         {},
1089 };
1090 MODULE_DEVICE_TABLE(of, sh_msiof_match);
1091 
1092 #ifdef CONFIG_OF
1093 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1094 {
1095         struct sh_msiof_spi_info *info;
1096         struct device_node *np = dev->of_node;
1097         u32 num_cs = 1;
1098 
1099         info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
1100         if (!info)
1101                 return NULL;
1102 
1103         info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
1104                                                             : MSIOF_SPI_MASTER;
1105 
1106         /* Parse the MSIOF properties */
1107         if (info->mode == MSIOF_SPI_MASTER)
1108                 of_property_read_u32(np, "num-cs", &num_cs);
1109         of_property_read_u32(np, "renesas,tx-fifo-size",
1110                                         &info->tx_fifo_override);
1111         of_property_read_u32(np, "renesas,rx-fifo-size",
1112                                         &info->rx_fifo_override);
1113         of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1114         of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1115 
1116         info->num_chipselect = num_cs;
1117 
1118         return info;
1119 }
1120 #else
1121 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1122 {
1123         return NULL;
1124 }
1125 #endif
1126 
1127 static int sh_msiof_get_cs_gpios(struct sh_msiof_spi_priv *p)
1128 {
1129         struct device *dev = &p->pdev->dev;
1130         unsigned int used_ss_mask = 0;
1131         unsigned int cs_gpios = 0;
1132         unsigned int num_cs, i;
1133         int ret;
1134 
1135         ret = gpiod_count(dev, "cs");
1136         if (ret <= 0)
1137                 return 0;
1138 
1139         num_cs = max_t(unsigned int, ret, p->ctlr->num_chipselect);
1140         for (i = 0; i < num_cs; i++) {
1141                 struct gpio_desc *gpiod;
1142 
1143                 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1144                 if (!IS_ERR(gpiod)) {
1145                         devm_gpiod_put(dev, gpiod);
1146                         cs_gpios++;
1147                         continue;
1148                 }
1149 
1150                 if (PTR_ERR(gpiod) != -ENOENT)
1151                         return PTR_ERR(gpiod);
1152 
1153                 if (i >= MAX_SS) {
1154                         dev_err(dev, "Invalid native chip select %d\n", i);
1155                         return -EINVAL;
1156                 }
1157                 used_ss_mask |= BIT(i);
1158         }
1159         p->unused_ss = ffz(used_ss_mask);
1160         if (cs_gpios && p->unused_ss >= MAX_SS) {
1161                 dev_err(dev, "No unused native chip select available\n");
1162                 return -EINVAL;
1163         }
1164         return 0;
1165 }
1166 
1167 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1168         enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1169 {
1170         dma_cap_mask_t mask;
1171         struct dma_chan *chan;
1172         struct dma_slave_config cfg;
1173         int ret;
1174 
1175         dma_cap_zero(mask);
1176         dma_cap_set(DMA_SLAVE, mask);
1177 
1178         chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1179                                 (void *)(unsigned long)id, dev,
1180                                 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1181         if (!chan) {
1182                 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1183                 return NULL;
1184         }
1185 
1186         memset(&cfg, 0, sizeof(cfg));
1187         cfg.direction = dir;
1188         if (dir == DMA_MEM_TO_DEV) {
1189                 cfg.dst_addr = port_addr;
1190                 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1191         } else {
1192                 cfg.src_addr = port_addr;
1193                 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1194         }
1195 
1196         ret = dmaengine_slave_config(chan, &cfg);
1197         if (ret) {
1198                 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1199                 dma_release_channel(chan);
1200                 return NULL;
1201         }
1202 
1203         return chan;
1204 }
1205 
1206 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1207 {
1208         struct platform_device *pdev = p->pdev;
1209         struct device *dev = &pdev->dev;
1210         const struct sh_msiof_spi_info *info = p->info;
1211         unsigned int dma_tx_id, dma_rx_id;
1212         const struct resource *res;
1213         struct spi_controller *ctlr;
1214         struct device *tx_dev, *rx_dev;
1215 
1216         if (dev->of_node) {
1217                 /* In the OF case we will get the slave IDs from the DT */
1218                 dma_tx_id = 0;
1219                 dma_rx_id = 0;
1220         } else if (info && info->dma_tx_id && info->dma_rx_id) {
1221                 dma_tx_id = info->dma_tx_id;
1222                 dma_rx_id = info->dma_rx_id;
1223         } else {
1224                 /* The driver assumes no error */
1225                 return 0;
1226         }
1227 
1228         /* The DMA engine uses the second register set, if present */
1229         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1230         if (!res)
1231                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1232 
1233         ctlr = p->ctlr;
1234         ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1235                                                  dma_tx_id, res->start + TFDR);
1236         if (!ctlr->dma_tx)
1237                 return -ENODEV;
1238 
1239         ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1240                                                  dma_rx_id, res->start + RFDR);
1241         if (!ctlr->dma_rx)
1242                 goto free_tx_chan;
1243 
1244         p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1245         if (!p->tx_dma_page)
1246                 goto free_rx_chan;
1247 
1248         p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1249         if (!p->rx_dma_page)
1250                 goto free_tx_page;
1251 
1252         tx_dev = ctlr->dma_tx->device->dev;
1253         p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1254                                         DMA_TO_DEVICE);
1255         if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1256                 goto free_rx_page;
1257 
1258         rx_dev = ctlr->dma_rx->device->dev;
1259         p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1260                                         DMA_FROM_DEVICE);
1261         if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1262                 goto unmap_tx_page;
1263 
1264         dev_info(dev, "DMA available");
1265         return 0;
1266 
1267 unmap_tx_page:
1268         dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1269 free_rx_page:
1270         free_page((unsigned long)p->rx_dma_page);
1271 free_tx_page:
1272         free_page((unsigned long)p->tx_dma_page);
1273 free_rx_chan:
1274         dma_release_channel(ctlr->dma_rx);
1275 free_tx_chan:
1276         dma_release_channel(ctlr->dma_tx);
1277         ctlr->dma_tx = NULL;
1278         return -ENODEV;
1279 }
1280 
1281 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1282 {
1283         struct spi_controller *ctlr = p->ctlr;
1284 
1285         if (!ctlr->dma_tx)
1286                 return;
1287 
1288         dma_unmap_single(ctlr->dma_rx->device->dev, p->rx_dma_addr, PAGE_SIZE,
1289                          DMA_FROM_DEVICE);
1290         dma_unmap_single(ctlr->dma_tx->device->dev, p->tx_dma_addr, PAGE_SIZE,
1291                          DMA_TO_DEVICE);
1292         free_page((unsigned long)p->rx_dma_page);
1293         free_page((unsigned long)p->tx_dma_page);
1294         dma_release_channel(ctlr->dma_rx);
1295         dma_release_channel(ctlr->dma_tx);
1296 }
1297 
1298 static int sh_msiof_spi_probe(struct platform_device *pdev)
1299 {
1300         struct spi_controller *ctlr;
1301         const struct sh_msiof_chipdata *chipdata;
1302         struct sh_msiof_spi_info *info;
1303         struct sh_msiof_spi_priv *p;
1304         int i;
1305         int ret;
1306 
1307         chipdata = of_device_get_match_data(&pdev->dev);
1308         if (chipdata) {
1309                 info = sh_msiof_spi_parse_dt(&pdev->dev);
1310         } else {
1311                 chipdata = (const void *)pdev->id_entry->driver_data;
1312                 info = dev_get_platdata(&pdev->dev);
1313         }
1314 
1315         if (!info) {
1316                 dev_err(&pdev->dev, "failed to obtain device info\n");
1317                 return -ENXIO;
1318         }
1319 
1320         if (info->mode == MSIOF_SPI_SLAVE)
1321                 ctlr = spi_alloc_slave(&pdev->dev,
1322                                        sizeof(struct sh_msiof_spi_priv));
1323         else
1324                 ctlr = spi_alloc_master(&pdev->dev,
1325                                         sizeof(struct sh_msiof_spi_priv));
1326         if (ctlr == NULL)
1327                 return -ENOMEM;
1328 
1329         p = spi_controller_get_devdata(ctlr);
1330 
1331         platform_set_drvdata(pdev, p);
1332         p->ctlr = ctlr;
1333         p->info = info;
1334         p->min_div_pow = chipdata->min_div_pow;
1335 
1336         init_completion(&p->done);
1337         init_completion(&p->done_txdma);
1338 
1339         p->clk = devm_clk_get(&pdev->dev, NULL);
1340         if (IS_ERR(p->clk)) {
1341                 dev_err(&pdev->dev, "cannot get clock\n");
1342                 ret = PTR_ERR(p->clk);
1343                 goto err1;
1344         }
1345 
1346         i = platform_get_irq(pdev, 0);
1347         if (i < 0) {
1348                 ret = i;
1349                 goto err1;
1350         }
1351 
1352         p->mapbase = devm_platform_ioremap_resource(pdev, 0);
1353         if (IS_ERR(p->mapbase)) {
1354                 ret = PTR_ERR(p->mapbase);
1355                 goto err1;
1356         }
1357 
1358         ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1359                                dev_name(&pdev->dev), p);
1360         if (ret) {
1361                 dev_err(&pdev->dev, "unable to request irq\n");
1362                 goto err1;
1363         }
1364 
1365         p->pdev = pdev;
1366         pm_runtime_enable(&pdev->dev);
1367 
1368         /* Platform data may override FIFO sizes */
1369         p->tx_fifo_size = chipdata->tx_fifo_size;
1370         p->rx_fifo_size = chipdata->rx_fifo_size;
1371         if (p->info->tx_fifo_override)
1372                 p->tx_fifo_size = p->info->tx_fifo_override;
1373         if (p->info->rx_fifo_override)
1374                 p->rx_fifo_size = p->info->rx_fifo_override;
1375 
1376         /* Setup GPIO chip selects */
1377         ctlr->num_chipselect = p->info->num_chipselect;
1378         ret = sh_msiof_get_cs_gpios(p);
1379         if (ret)
1380                 goto err1;
1381 
1382         /* init controller code */
1383         ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1384         ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1385         ctlr->flags = chipdata->ctlr_flags;
1386         ctlr->bus_num = pdev->id;
1387         ctlr->dev.of_node = pdev->dev.of_node;
1388         ctlr->setup = sh_msiof_spi_setup;
1389         ctlr->prepare_message = sh_msiof_prepare_message;
1390         ctlr->slave_abort = sh_msiof_slave_abort;
1391         ctlr->bits_per_word_mask = chipdata->bits_per_word_mask;
1392         ctlr->auto_runtime_pm = true;
1393         ctlr->transfer_one = sh_msiof_transfer_one;
1394         ctlr->use_gpio_descriptors = true;
1395 
1396         ret = sh_msiof_request_dma(p);
1397         if (ret < 0)
1398                 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1399 
1400         ret = devm_spi_register_controller(&pdev->dev, ctlr);
1401         if (ret < 0) {
1402                 dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1403                 goto err2;
1404         }
1405 
1406         return 0;
1407 
1408  err2:
1409         sh_msiof_release_dma(p);
1410         pm_runtime_disable(&pdev->dev);
1411  err1:
1412         spi_controller_put(ctlr);
1413         return ret;
1414 }
1415 
1416 static int sh_msiof_spi_remove(struct platform_device *pdev)
1417 {
1418         struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1419 
1420         sh_msiof_release_dma(p);
1421         pm_runtime_disable(&pdev->dev);
1422         return 0;
1423 }
1424 
1425 static const struct platform_device_id spi_driver_ids[] = {
1426         { "spi_sh_msiof",       (kernel_ulong_t)&sh_data },
1427         {},
1428 };
1429 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1430 
1431 #ifdef CONFIG_PM_SLEEP
1432 static int sh_msiof_spi_suspend(struct device *dev)
1433 {
1434         struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
1435 
1436         return spi_controller_suspend(p->ctlr);
1437 }
1438 
1439 static int sh_msiof_spi_resume(struct device *dev)
1440 {
1441         struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
1442 
1443         return spi_controller_resume(p->ctlr);
1444 }
1445 
1446 static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
1447                          sh_msiof_spi_resume);
1448 #define DEV_PM_OPS      &sh_msiof_spi_pm_ops
1449 #else
1450 #define DEV_PM_OPS      NULL
1451 #endif /* CONFIG_PM_SLEEP */
1452 
1453 static struct platform_driver sh_msiof_spi_drv = {
1454         .probe          = sh_msiof_spi_probe,
1455         .remove         = sh_msiof_spi_remove,
1456         .id_table       = spi_driver_ids,
1457         .driver         = {
1458                 .name           = "spi_sh_msiof",
1459                 .pm             = DEV_PM_OPS,
1460                 .of_match_table = of_match_ptr(sh_msiof_match),
1461         },
1462 };
1463 module_platform_driver(sh_msiof_spi_drv);
1464 
1465 MODULE_DESCRIPTION("SuperH MSIOF SPI Controller Interface Driver");
1466 MODULE_AUTHOR("Magnus Damm");
1467 MODULE_LICENSE("GPL v2");
1468 MODULE_ALIAS("platform:spi_sh_msiof");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/spi/spi-sh-msiof.c

DEFINITIONS
