1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Mix this utility code with some glue code to get one of several types of
4 * simple SPI master driver. Two do polled word-at-a-time I/O:
5 *
6 * - GPIO/parport bitbangers. Provide chipselect() and txrx_word[](),
7 * expanding the per-word routines from the inline templates below.
8 *
9 * - Drivers for controllers resembling bare shift registers. Provide
10 * chipselect() and txrx_word[](), with custom setup()/cleanup() methods
11 * that use your controller's clock and chipselect registers.
12 *
13 * Some hardware works well with requests at spi_transfer scope:
14 *
15 * - Drivers leveraging smarter hardware, with fifos or DMA; or for half
16 * duplex (MicroWire) controllers. Provide chipselect() and txrx_bufs(),
17 * and custom setup()/cleanup() methods.
18 */
19
20 /*
21 * The code that knows what GPIO pins do what should have declared four
22 * functions, ideally as inlines, before including this header:
23 *
24 * void setsck(struct spi_device *, int is_on);
25 * void setmosi(struct spi_device *, int is_on);
26 * int getmiso(struct spi_device *);
27 * void spidelay(unsigned);
28 *
29 * setsck()'s is_on parameter is a zero/nonzero boolean.
30 *
31 * setmosi()'s is_on parameter is a zero/nonzero boolean.
32 *
33 * getmiso() is required to return 0 or 1 only. Any other value is invalid
34 * and will result in improper operation.
35 *
36 * A non-inlined routine would call bitbang_txrx_*() routines. The
37 * main loop could easily compile down to a handful of instructions,
38 * especially if the delay is a NOP (to run at peak speed).
39 *
40 * Since this is software, the timings may not be exactly what your board's
41 * chips need ... there may be several reasons you'd need to tweak timings
42 * in these routines, not just to make it faster or slower to match a
43 * particular CPU clock rate.
44 */
45
46 static inline u32
47 bitbang_txrx_be_cpha0(struct spi_device *spi,
48 unsigned nsecs, unsigned cpol, unsigned flags,
49 u32 word, u8 bits)
50 {
51 /* if (cpol == 0) this is SPI_MODE_0; else this is SPI_MODE_2 */
52
53 u32 oldbit = (!(word & (1<<(bits-1)))) << 31;
54 /* clock starts at inactive polarity */
55 for (word <<= (32 - bits); likely(bits); bits--) {
56
57 /* setup MSB (to slave) on trailing edge */
58 if ((flags & SPI_MASTER_NO_TX) == 0) {
59 if ((word & (1 << 31)) != oldbit) {
60 setmosi(spi, word & (1 << 31));
61 oldbit = word & (1 << 31);
62 }
63 }
64 spidelay(nsecs); /* T(setup) */
65
66 setsck(spi, !cpol);
67 spidelay(nsecs);
68
69 /* sample MSB (from slave) on leading edge */
70 word <<= 1;
71 if ((flags & SPI_MASTER_NO_RX) == 0)
72 word |= getmiso(spi);
73 setsck(spi, cpol);
74 }
75 return word;
76 }
77
78 static inline u32
79 bitbang_txrx_be_cpha1(struct spi_device *spi,
80 unsigned nsecs, unsigned cpol, unsigned flags,
81 u32 word, u8 bits)
82 {
83 /* if (cpol == 0) this is SPI_MODE_1; else this is SPI_MODE_3 */
84
85 u32 oldbit = (!(word & (1<<(bits-1)))) << 31;
86 /* clock starts at inactive polarity */
87 for (word <<= (32 - bits); likely(bits); bits--) {
88
89 /* setup MSB (to slave) on leading edge */
90 setsck(spi, !cpol);
91 if ((flags & SPI_MASTER_NO_TX) == 0) {
92 if ((word & (1 << 31)) != oldbit) {
93 setmosi(spi, word & (1 << 31));
94 oldbit = word & (1 << 31);
95 }
96 }
97 spidelay(nsecs); /* T(setup) */
98
99 setsck(spi, cpol);
100 spidelay(nsecs);
101
102 /* sample MSB (from slave) on trailing edge */
103 word <<= 1;
104 if ((flags & SPI_MASTER_NO_RX) == 0)
105 word |= getmiso(spi);
106 }
107 return word;
108 }