drivers/mtd/nand/raw/vf610

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
chip_to_nfc
vf610_nfc_read
vf610_nfc_write
vf610_nfc_set
vf610_nfc_clear
vf610_nfc_set_field
vf610_nfc_kernel_is_little_endian
vf610_nfc_rd_from_sram
vf610_nfc_wr_to_sram
vf610_nfc_clear_status
vf610_nfc_done
vf610_nfc_irq
vf610_nfc_ecc_mode
vf610_nfc_transfer_size
vf610_nfc_run
vf610_get_next_instr
vf610_nfc_cmd
vf610_nfc_select_target
vf610_nfc_exec_op
vf610_nfc_correct_data
vf610_nfc_fill_row
vf610_nfc_read_page
vf610_nfc_write_page
vf610_nfc_read_page_raw
vf610_nfc_write_page_raw
vf610_nfc_read_oob
vf610_nfc_write_oob
vf610_nfc_preinit_controller
vf610_nfc_init_controller
vf610_nfc_attach_chip
vf610_nfc_probe
vf610_nfc_remove
vf610_nfc_suspend
vf610_nfc_resume
   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
   4  *
   5  * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
   6  * Jason ported to M54418TWR and MVFA5 (VF610).
   7  * Authors: Stefan Agner <stefan.agner@toradex.com>
   8  *          Bill Pringlemeir <bpringlemeir@nbsps.com>
   9  *          Shaohui Xie <b21989@freescale.com>
  10  *          Jason Jin <Jason.jin@freescale.com>
  11  *
  12  * Based on original driver mpc5121_nfc.c.
  13  *
  14  * Limitations:
  15  * - Untested on MPC5125 and M54418.
  16  * - DMA and pipelining not used.
  17  * - 2K pages or less.
  18  * - HW ECC: Only 2K page with 64+ OOB.
  19  * - HW ECC: Only 24 and 32-bit error correction implemented.
  20  */
  21 
  22 #include <linux/module.h>
  23 #include <linux/bitops.h>
  24 #include <linux/clk.h>
  25 #include <linux/delay.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/rawnand.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/of_device.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/slab.h>
  35 #include <linux/swab.h>
  36 
  37 #define DRV_NAME                "vf610_nfc"
  38 
  39 /* Register Offsets */
  40 #define NFC_FLASH_CMD1                  0x3F00
  41 #define NFC_FLASH_CMD2                  0x3F04
  42 #define NFC_COL_ADDR                    0x3F08
  43 #define NFC_ROW_ADDR                    0x3F0c
  44 #define NFC_ROW_ADDR_INC                0x3F14
  45 #define NFC_FLASH_STATUS1               0x3F18
  46 #define NFC_FLASH_STATUS2               0x3F1c
  47 #define NFC_CACHE_SWAP                  0x3F28
  48 #define NFC_SECTOR_SIZE                 0x3F2c
  49 #define NFC_FLASH_CONFIG                0x3F30
  50 #define NFC_IRQ_STATUS                  0x3F38
  51 
  52 /* Addresses for NFC MAIN RAM BUFFER areas */
  53 #define NFC_MAIN_AREA(n)                ((n) *  0x1000)
  54 
  55 #define PAGE_2K                         0x0800
  56 #define OOB_64                          0x0040
  57 #define OOB_MAX                         0x0100
  58 
  59 /* NFC_CMD2[CODE] controller cycle bit masks */
  60 #define COMMAND_CMD_BYTE1               BIT(14)
  61 #define COMMAND_CAR_BYTE1               BIT(13)
  62 #define COMMAND_CAR_BYTE2               BIT(12)
  63 #define COMMAND_RAR_BYTE1               BIT(11)
  64 #define COMMAND_RAR_BYTE2               BIT(10)
  65 #define COMMAND_RAR_BYTE3               BIT(9)
  66 #define COMMAND_NADDR_BYTES(x)          GENMASK(13, 13 - (x) + 1)
  67 #define COMMAND_WRITE_DATA              BIT(8)
  68 #define COMMAND_CMD_BYTE2               BIT(7)
  69 #define COMMAND_RB_HANDSHAKE            BIT(6)
  70 #define COMMAND_READ_DATA               BIT(5)
  71 #define COMMAND_CMD_BYTE3               BIT(4)
  72 #define COMMAND_READ_STATUS             BIT(3)
  73 #define COMMAND_READ_ID                 BIT(2)
  74 
  75 /* NFC ECC mode define */
  76 #define ECC_BYPASS                      0
  77 #define ECC_45_BYTE                     6
  78 #define ECC_60_BYTE                     7
  79 
  80 /*** Register Mask and bit definitions */
  81 
  82 /* NFC_FLASH_CMD1 Field */
  83 #define CMD_BYTE2_MASK                          0xFF000000
  84 #define CMD_BYTE2_SHIFT                         24
  85 
  86 /* NFC_FLASH_CM2 Field */
  87 #define CMD_BYTE1_MASK                          0xFF000000
  88 #define CMD_BYTE1_SHIFT                         24
  89 #define CMD_CODE_MASK                           0x00FFFF00
  90 #define CMD_CODE_SHIFT                          8
  91 #define BUFNO_MASK                              0x00000006
  92 #define BUFNO_SHIFT                             1
  93 #define START_BIT                               BIT(0)
  94 
  95 /* NFC_COL_ADDR Field */
  96 #define COL_ADDR_MASK                           0x0000FFFF
  97 #define COL_ADDR_SHIFT                          0
  98 #define COL_ADDR(pos, val)                      (((val) & 0xFF) << (8 * (pos)))
  99 
 100 /* NFC_ROW_ADDR Field */
 101 #define ROW_ADDR_MASK                           0x00FFFFFF
 102 #define ROW_ADDR_SHIFT                          0
 103 #define ROW_ADDR(pos, val)                      (((val) & 0xFF) << (8 * (pos)))
 104 
 105 #define ROW_ADDR_CHIP_SEL_RB_MASK               0xF0000000
 106 #define ROW_ADDR_CHIP_SEL_RB_SHIFT              28
 107 #define ROW_ADDR_CHIP_SEL_MASK                  0x0F000000
 108 #define ROW_ADDR_CHIP_SEL_SHIFT                 24
 109 
 110 /* NFC_FLASH_STATUS2 Field */
 111 #define STATUS_BYTE1_MASK                       0x000000FF
 112 
 113 /* NFC_FLASH_CONFIG Field */
 114 #define CONFIG_ECC_SRAM_ADDR_MASK               0x7FC00000
 115 #define CONFIG_ECC_SRAM_ADDR_SHIFT              22
 116 #define CONFIG_ECC_SRAM_REQ_BIT                 BIT(21)
 117 #define CONFIG_DMA_REQ_BIT                      BIT(20)
 118 #define CONFIG_ECC_MODE_MASK                    0x000E0000
 119 #define CONFIG_ECC_MODE_SHIFT                   17
 120 #define CONFIG_FAST_FLASH_BIT                   BIT(16)
 121 #define CONFIG_16BIT                            BIT(7)
 122 #define CONFIG_BOOT_MODE_BIT                    BIT(6)
 123 #define CONFIG_ADDR_AUTO_INCR_BIT               BIT(5)
 124 #define CONFIG_BUFNO_AUTO_INCR_BIT              BIT(4)
 125 #define CONFIG_PAGE_CNT_MASK                    0xF
 126 #define CONFIG_PAGE_CNT_SHIFT                   0
 127 
 128 /* NFC_IRQ_STATUS Field */
 129 #define IDLE_IRQ_BIT                            BIT(29)
 130 #define IDLE_EN_BIT                             BIT(20)
 131 #define CMD_DONE_CLEAR_BIT                      BIT(18)
 132 #define IDLE_CLEAR_BIT                          BIT(17)
 133 
 134 /*
 135  * ECC status - seems to consume 8 bytes (double word). The documented
 136  * status byte is located in the lowest byte of the second word (which is
 137  * the 4th or 7th byte depending on endianness).
 138  * Calculate an offset to store the ECC status at the end of the buffer.
 139  */
 140 #define ECC_SRAM_ADDR           (PAGE_2K + OOB_MAX - 8)
 141 
 142 #define ECC_STATUS              0x4
 143 #define ECC_STATUS_MASK         0x80
 144 #define ECC_STATUS_ERR_COUNT    0x3F
 145 
 146 enum vf610_nfc_variant {
 147         NFC_VFC610 = 1,
 148 };
 149 
 150 struct vf610_nfc {
 151         struct nand_controller base;
 152         struct nand_chip chip;
 153         struct device *dev;
 154         void __iomem *regs;
 155         struct completion cmd_done;
 156         /* Status and ID are in alternate locations. */
 157         enum vf610_nfc_variant variant;
 158         struct clk *clk;
 159         /*
 160          * Indicate that user data is accessed (full page/oob). This is
 161          * useful to indicate the driver whether to swap byte endianness.
 162          * See comments in vf610_nfc_rd_from_sram/vf610_nfc_wr_to_sram.
 163          */
 164         bool data_access;
 165         u32 ecc_mode;
 166 };
 167 
 168 static inline struct vf610_nfc *chip_to_nfc(struct nand_chip *chip)
 169 {
 170         return container_of(chip, struct vf610_nfc, chip);
 171 }
 172 
 173 static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg)
 174 {
 175         return readl(nfc->regs + reg);
 176 }
 177 
 178 static inline void vf610_nfc_write(struct vf610_nfc *nfc, uint reg, u32 val)
 179 {
 180         writel(val, nfc->regs + reg);
 181 }
 182 
 183 static inline void vf610_nfc_set(struct vf610_nfc *nfc, uint reg, u32 bits)
 184 {
 185         vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) | bits);
 186 }
 187 
 188 static inline void vf610_nfc_clear(struct vf610_nfc *nfc, uint reg, u32 bits)
 189 {
 190         vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) & ~bits);
 191 }
 192 
 193 static inline void vf610_nfc_set_field(struct vf610_nfc *nfc, u32 reg,
 194                                        u32 mask, u32 shift, u32 val)
 195 {
 196         vf610_nfc_write(nfc, reg,
 197                         (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift);
 198 }
 199 
 200 static inline bool vf610_nfc_kernel_is_little_endian(void)
 201 {
 202 #ifdef __LITTLE_ENDIAN
 203         return true;
 204 #else
 205         return false;
 206 #endif
 207 }
 208 
 209 /**
 210  * Read accessor for internal SRAM buffer
 211  * @dst: destination address in regular memory
 212  * @src: source address in SRAM buffer
 213  * @len: bytes to copy
 214  * @fix_endian: Fix endianness if required
 215  *
 216  * Use this accessor for the internal SRAM buffers. On the ARM
 217  * Freescale Vybrid SoC it's known that the driver can treat
 218  * the SRAM buffer as if it's memory. Other platform might need
 219  * to treat the buffers differently.
 220  *
 221  * The controller stores bytes from the NAND chip internally in big
 222  * endianness. On little endian platforms such as Vybrid this leads
 223  * to reversed byte order.
 224  * For performance reason (and earlier probably due to unawareness)
 225  * the driver avoids correcting endianness where it has control over
 226  * write and read side (e.g. page wise data access).
 227  */
 228 static inline void vf610_nfc_rd_from_sram(void *dst, const void __iomem *src,
 229                                           size_t len, bool fix_endian)
 230 {
 231         if (vf610_nfc_kernel_is_little_endian() && fix_endian) {
 232                 unsigned int i;
 233 
 234                 for (i = 0; i < len; i += 4) {
 235                         u32 val = swab32(__raw_readl(src + i));
 236 
 237                         memcpy(dst + i, &val, min(sizeof(val), len - i));
 238                 }
 239         } else {
 240                 memcpy_fromio(dst, src, len);
 241         }
 242 }
 243 
 244 /**
 245  * Write accessor for internal SRAM buffer
 246  * @dst: destination address in SRAM buffer
 247  * @src: source address in regular memory
 248  * @len: bytes to copy
 249  * @fix_endian: Fix endianness if required
 250  *
 251  * Use this accessor for the internal SRAM buffers. On the ARM
 252  * Freescale Vybrid SoC it's known that the driver can treat
 253  * the SRAM buffer as if it's memory. Other platform might need
 254  * to treat the buffers differently.
 255  *
 256  * The controller stores bytes from the NAND chip internally in big
 257  * endianness. On little endian platforms such as Vybrid this leads
 258  * to reversed byte order.
 259  * For performance reason (and earlier probably due to unawareness)
 260  * the driver avoids correcting endianness where it has control over
 261  * write and read side (e.g. page wise data access).
 262  */
 263 static inline void vf610_nfc_wr_to_sram(void __iomem *dst, const void *src,
 264                                         size_t len, bool fix_endian)
 265 {
 266         if (vf610_nfc_kernel_is_little_endian() && fix_endian) {
 267                 unsigned int i;
 268 
 269                 for (i = 0; i < len; i += 4) {
 270                         u32 val;
 271 
 272                         memcpy(&val, src + i, min(sizeof(val), len - i));
 273                         __raw_writel(swab32(val), dst + i);
 274                 }
 275         } else {
 276                 memcpy_toio(dst, src, len);
 277         }
 278 }
 279 
 280 /* Clear flags for upcoming command */
 281 static inline void vf610_nfc_clear_status(struct vf610_nfc *nfc)
 282 {
 283         u32 tmp = vf610_nfc_read(nfc, NFC_IRQ_STATUS);
 284 
 285         tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
 286         vf610_nfc_write(nfc, NFC_IRQ_STATUS, tmp);
 287 }
 288 
 289 static void vf610_nfc_done(struct vf610_nfc *nfc)
 290 {
 291         unsigned long timeout = msecs_to_jiffies(100);
 292 
 293         /*
 294          * Barrier is needed after this write. This write need
 295          * to be done before reading the next register the first
 296          * time.
 297          * vf610_nfc_set implicates such a barrier by using writel
 298          * to write to the register.
 299          */
 300         vf610_nfc_set(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT);
 301         vf610_nfc_set(nfc, NFC_FLASH_CMD2, START_BIT);
 302 
 303         if (!wait_for_completion_timeout(&nfc->cmd_done, timeout))
 304                 dev_warn(nfc->dev, "Timeout while waiting for BUSY.\n");
 305 
 306         vf610_nfc_clear_status(nfc);
 307 }
 308 
 309 static irqreturn_t vf610_nfc_irq(int irq, void *data)
 310 {
 311         struct vf610_nfc *nfc = data;
 312 
 313         vf610_nfc_clear(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT);
 314         complete(&nfc->cmd_done);
 315 
 316         return IRQ_HANDLED;
 317 }
 318 
 319 static inline void vf610_nfc_ecc_mode(struct vf610_nfc *nfc, int ecc_mode)
 320 {
 321         vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG,
 322                             CONFIG_ECC_MODE_MASK,
 323                             CONFIG_ECC_MODE_SHIFT, ecc_mode);
 324 }
 325 
 326 static inline void vf610_nfc_transfer_size(struct vf610_nfc *nfc, int size)
 327 {
 328         vf610_nfc_write(nfc, NFC_SECTOR_SIZE, size);
 329 }
 330 
 331 static inline void vf610_nfc_run(struct vf610_nfc *nfc, u32 col, u32 row,
 332                                  u32 cmd1, u32 cmd2, u32 trfr_sz)
 333 {
 334         vf610_nfc_set_field(nfc, NFC_COL_ADDR, COL_ADDR_MASK,
 335                             COL_ADDR_SHIFT, col);
 336 
 337         vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK,
 338                             ROW_ADDR_SHIFT, row);
 339 
 340         vf610_nfc_write(nfc, NFC_SECTOR_SIZE, trfr_sz);
 341         vf610_nfc_write(nfc, NFC_FLASH_CMD1, cmd1);
 342         vf610_nfc_write(nfc, NFC_FLASH_CMD2, cmd2);
 343 
 344         dev_dbg(nfc->dev,
 345                 "col 0x%04x, row 0x%08x, cmd1 0x%08x, cmd2 0x%08x, len %d\n",
 346                 col, row, cmd1, cmd2, trfr_sz);
 347 
 348         vf610_nfc_done(nfc);
 349 }
 350 
 351 static inline const struct nand_op_instr *
 352 vf610_get_next_instr(const struct nand_subop *subop, int *op_id)
 353 {
 354         if (*op_id + 1 >= subop->ninstrs)
 355                 return NULL;
 356 
 357         (*op_id)++;
 358 
 359         return &subop->instrs[*op_id];
 360 }
 361 
 362 static int vf610_nfc_cmd(struct nand_chip *chip,
 363                          const struct nand_subop *subop)
 364 {
 365         const struct nand_op_instr *instr;
 366         struct vf610_nfc *nfc = chip_to_nfc(chip);
 367         int op_id = -1, trfr_sz = 0, offset = 0;
 368         u32 col = 0, row = 0, cmd1 = 0, cmd2 = 0, code = 0;
 369         bool force8bit = false;
 370 
 371         /*
 372          * Some ops are optional, but the hardware requires the operations
 373          * to be in this exact order.
 374          * The op parser enforces the order and makes sure that there isn't
 375          * a read and write element in a single operation.
 376          */
 377         instr = vf610_get_next_instr(subop, &op_id);
 378         if (!instr)
 379                 return -EINVAL;
 380 
 381         if (instr && instr->type == NAND_OP_CMD_INSTR) {
 382                 cmd2 |= instr->ctx.cmd.opcode << CMD_BYTE1_SHIFT;
 383                 code |= COMMAND_CMD_BYTE1;
 384 
 385                 instr = vf610_get_next_instr(subop, &op_id);
 386         }
 387 
 388         if (instr && instr->type == NAND_OP_ADDR_INSTR) {
 389                 int naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
 390                 int i = nand_subop_get_addr_start_off(subop, op_id);
 391 
 392                 for (; i < naddrs; i++) {
 393                         u8 val = instr->ctx.addr.addrs[i];
 394 
 395                         if (i < 2)
 396                                 col |= COL_ADDR(i, val);
 397                         else
 398                                 row |= ROW_ADDR(i - 2, val);
 399                 }
 400                 code |= COMMAND_NADDR_BYTES(naddrs);
 401 
 402                 instr = vf610_get_next_instr(subop, &op_id);
 403         }
 404 
 405         if (instr && instr->type == NAND_OP_DATA_OUT_INSTR) {
 406                 trfr_sz = nand_subop_get_data_len(subop, op_id);
 407                 offset = nand_subop_get_data_start_off(subop, op_id);
 408                 force8bit = instr->ctx.data.force_8bit;
 409 
 410                 /*
 411                  * Don't fix endianness on page access for historical reasons.
 412                  * See comment in vf610_nfc_wr_to_sram
 413                  */
 414                 vf610_nfc_wr_to_sram(nfc->regs + NFC_MAIN_AREA(0) + offset,
 415                                      instr->ctx.data.buf.out + offset,
 416                                      trfr_sz, !nfc->data_access);
 417                 code |= COMMAND_WRITE_DATA;
 418 
 419                 instr = vf610_get_next_instr(subop, &op_id);
 420         }
 421 
 422         if (instr && instr->type == NAND_OP_CMD_INSTR) {
 423                 cmd1 |= instr->ctx.cmd.opcode << CMD_BYTE2_SHIFT;
 424                 code |= COMMAND_CMD_BYTE2;
 425 
 426                 instr = vf610_get_next_instr(subop, &op_id);
 427         }
 428 
 429         if (instr && instr->type == NAND_OP_WAITRDY_INSTR) {
 430                 code |= COMMAND_RB_HANDSHAKE;
 431 
 432                 instr = vf610_get_next_instr(subop, &op_id);
 433         }
 434 
 435         if (instr && instr->type == NAND_OP_DATA_IN_INSTR) {
 436                 trfr_sz = nand_subop_get_data_len(subop, op_id);
 437                 offset = nand_subop_get_data_start_off(subop, op_id);
 438                 force8bit = instr->ctx.data.force_8bit;
 439 
 440                 code |= COMMAND_READ_DATA;
 441         }
 442 
 443         if (force8bit && (chip->options & NAND_BUSWIDTH_16))
 444                 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
 445 
 446         cmd2 |= code << CMD_CODE_SHIFT;
 447 
 448         vf610_nfc_run(nfc, col, row, cmd1, cmd2, trfr_sz);
 449 
 450         if (instr && instr->type == NAND_OP_DATA_IN_INSTR) {
 451                 /*
 452                  * Don't fix endianness on page access for historical reasons.
 453                  * See comment in vf610_nfc_rd_from_sram
 454                  */
 455                 vf610_nfc_rd_from_sram(instr->ctx.data.buf.in + offset,
 456                                        nfc->regs + NFC_MAIN_AREA(0) + offset,
 457                                        trfr_sz, !nfc->data_access);
 458         }
 459 
 460         if (force8bit && (chip->options & NAND_BUSWIDTH_16))
 461                 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
 462 
 463         return 0;
 464 }
 465 
 466 static const struct nand_op_parser vf610_nfc_op_parser = NAND_OP_PARSER(
 467         NAND_OP_PARSER_PATTERN(vf610_nfc_cmd,
 468                 NAND_OP_PARSER_PAT_CMD_ELEM(true),
 469                 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5),
 470                 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, PAGE_2K + OOB_MAX),
 471                 NAND_OP_PARSER_PAT_CMD_ELEM(true),
 472                 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
 473         NAND_OP_PARSER_PATTERN(vf610_nfc_cmd,
 474                 NAND_OP_PARSER_PAT_CMD_ELEM(true),
 475                 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5),
 476                 NAND_OP_PARSER_PAT_CMD_ELEM(true),
 477                 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
 478                 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, PAGE_2K + OOB_MAX)),
 479         );
 480 
 481 /*
 482  * This function supports Vybrid only (MPC5125 would have full RB and four CS)
 483  */
 484 static void vf610_nfc_select_target(struct nand_chip *chip, unsigned int cs)
 485 {
 486         struct vf610_nfc *nfc = chip_to_nfc(chip);
 487         u32 tmp;
 488 
 489         /* Vybrid only (MPC5125 would have full RB and four CS) */
 490         if (nfc->variant != NFC_VFC610)
 491                 return;
 492 
 493         tmp = vf610_nfc_read(nfc, NFC_ROW_ADDR);
 494         tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
 495         tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
 496         tmp |= BIT(cs) << ROW_ADDR_CHIP_SEL_SHIFT;
 497 
 498         vf610_nfc_write(nfc, NFC_ROW_ADDR, tmp);
 499 }
 500 
 501 static int vf610_nfc_exec_op(struct nand_chip *chip,
 502                              const struct nand_operation *op,
 503                              bool check_only)
 504 {
 505         vf610_nfc_select_target(chip, op->cs);
 506         return nand_op_parser_exec_op(chip, &vf610_nfc_op_parser, op,
 507                                       check_only);
 508 }
 509 
 510 static inline int vf610_nfc_correct_data(struct nand_chip *chip, uint8_t *dat,
 511                                          uint8_t *oob, int page)
 512 {
 513         struct vf610_nfc *nfc = chip_to_nfc(chip);
 514         struct mtd_info *mtd = nand_to_mtd(chip);
 515         u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS;
 516         u8 ecc_status;
 517         u8 ecc_count;
 518         int flips_threshold = nfc->chip.ecc.strength / 2;
 519 
 520         ecc_status = vf610_nfc_read(nfc, ecc_status_off) & 0xff;
 521         ecc_count = ecc_status & ECC_STATUS_ERR_COUNT;
 522 
 523         if (!(ecc_status & ECC_STATUS_MASK))
 524                 return ecc_count;
 525 
 526         nfc->data_access = true;
 527         nand_read_oob_op(&nfc->chip, page, 0, oob, mtd->oobsize);
 528         nfc->data_access = false;
 529 
 530         /*
 531          * On an erased page, bit count (including OOB) should be zero or
 532          * at least less then half of the ECC strength.
 533          */
 534         return nand_check_erased_ecc_chunk(dat, nfc->chip.ecc.size, oob,
 535                                            mtd->oobsize, NULL, 0,
 536                                            flips_threshold);
 537 }
 538 
 539 static void vf610_nfc_fill_row(struct nand_chip *chip, int page, u32 *code,
 540                                u32 *row)
 541 {
 542         *row = ROW_ADDR(0, page & 0xff) | ROW_ADDR(1, page >> 8);
 543         *code |= COMMAND_RAR_BYTE1 | COMMAND_RAR_BYTE2;
 544 
 545         if (chip->options & NAND_ROW_ADDR_3) {
 546                 *row |= ROW_ADDR(2, page >> 16);
 547                 *code |= COMMAND_RAR_BYTE3;
 548         }
 549 }
 550 
 551 static int vf610_nfc_read_page(struct nand_chip *chip, uint8_t *buf,
 552                                int oob_required, int page)
 553 {
 554         struct vf610_nfc *nfc = chip_to_nfc(chip);
 555         struct mtd_info *mtd = nand_to_mtd(chip);
 556         int trfr_sz = mtd->writesize + mtd->oobsize;
 557         u32 row = 0, cmd1 = 0, cmd2 = 0, code = 0;
 558         int stat;
 559 
 560         vf610_nfc_select_target(chip, chip->cur_cs);
 561 
 562         cmd2 |= NAND_CMD_READ0 << CMD_BYTE1_SHIFT;
 563         code |= COMMAND_CMD_BYTE1 | COMMAND_CAR_BYTE1 | COMMAND_CAR_BYTE2;
 564 
 565         vf610_nfc_fill_row(chip, page, &code, &row);
 566 
 567         cmd1 |= NAND_CMD_READSTART << CMD_BYTE2_SHIFT;
 568         code |= COMMAND_CMD_BYTE2 | COMMAND_RB_HANDSHAKE | COMMAND_READ_DATA;
 569 
 570         cmd2 |= code << CMD_CODE_SHIFT;
 571 
 572         vf610_nfc_ecc_mode(nfc, nfc->ecc_mode);
 573         vf610_nfc_run(nfc, 0, row, cmd1, cmd2, trfr_sz);
 574         vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
 575 
 576         /*
 577          * Don't fix endianness on page access for historical reasons.
 578          * See comment in vf610_nfc_rd_from_sram
 579          */
 580         vf610_nfc_rd_from_sram(buf, nfc->regs + NFC_MAIN_AREA(0),
 581                                mtd->writesize, false);
 582         if (oob_required)
 583                 vf610_nfc_rd_from_sram(chip->oob_poi,
 584                                        nfc->regs + NFC_MAIN_AREA(0) +
 585                                                    mtd->writesize,
 586                                        mtd->oobsize, false);
 587 
 588         stat = vf610_nfc_correct_data(chip, buf, chip->oob_poi, page);
 589 
 590         if (stat < 0) {
 591                 mtd->ecc_stats.failed++;
 592                 return 0;
 593         } else {
 594                 mtd->ecc_stats.corrected += stat;
 595                 return stat;
 596         }
 597 }
 598 
 599 static int vf610_nfc_write_page(struct nand_chip *chip, const uint8_t *buf,
 600                                 int oob_required, int page)
 601 {
 602         struct vf610_nfc *nfc = chip_to_nfc(chip);
 603         struct mtd_info *mtd = nand_to_mtd(chip);
 604         int trfr_sz = mtd->writesize + mtd->oobsize;
 605         u32 row = 0, cmd1 = 0, cmd2 = 0, code = 0;
 606         u8 status;
 607         int ret;
 608 
 609         vf610_nfc_select_target(chip, chip->cur_cs);
 610 
 611         cmd2 |= NAND_CMD_SEQIN << CMD_BYTE1_SHIFT;
 612         code |= COMMAND_CMD_BYTE1 | COMMAND_CAR_BYTE1 | COMMAND_CAR_BYTE2;
 613 
 614         vf610_nfc_fill_row(chip, page, &code, &row);
 615 
 616         cmd1 |= NAND_CMD_PAGEPROG << CMD_BYTE2_SHIFT;
 617         code |= COMMAND_CMD_BYTE2 | COMMAND_WRITE_DATA;
 618 
 619         /*
 620          * Don't fix endianness on page access for historical reasons.
 621          * See comment in vf610_nfc_wr_to_sram
 622          */
 623         vf610_nfc_wr_to_sram(nfc->regs + NFC_MAIN_AREA(0), buf,
 624                              mtd->writesize, false);
 625 
 626         code |= COMMAND_RB_HANDSHAKE;
 627         cmd2 |= code << CMD_CODE_SHIFT;
 628 
 629         vf610_nfc_ecc_mode(nfc, nfc->ecc_mode);
 630         vf610_nfc_run(nfc, 0, row, cmd1, cmd2, trfr_sz);
 631         vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
 632 
 633         ret = nand_status_op(chip, &status);
 634         if (ret)
 635                 return ret;
 636 
 637         if (status & NAND_STATUS_FAIL)
 638                 return -EIO;
 639 
 640         return 0;
 641 }
 642 
 643 static int vf610_nfc_read_page_raw(struct nand_chip *chip, u8 *buf,
 644                                    int oob_required, int page)
 645 {
 646         struct vf610_nfc *nfc = chip_to_nfc(chip);
 647         int ret;
 648 
 649         nfc->data_access = true;
 650         ret = nand_read_page_raw(chip, buf, oob_required, page);
 651         nfc->data_access = false;
 652 
 653         return ret;
 654 }
 655 
 656 static int vf610_nfc_write_page_raw(struct nand_chip *chip, const u8 *buf,
 657                                     int oob_required, int page)
 658 {
 659         struct vf610_nfc *nfc = chip_to_nfc(chip);
 660         struct mtd_info *mtd = nand_to_mtd(chip);
 661         int ret;
 662 
 663         nfc->data_access = true;
 664         ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
 665         if (!ret && oob_required)
 666                 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
 667                                          false);
 668         nfc->data_access = false;
 669 
 670         if (ret)
 671                 return ret;
 672 
 673         return nand_prog_page_end_op(chip);
 674 }
 675 
 676 static int vf610_nfc_read_oob(struct nand_chip *chip, int page)
 677 {
 678         struct vf610_nfc *nfc = chip_to_nfc(chip);
 679         int ret;
 680 
 681         nfc->data_access = true;
 682         ret = nand_read_oob_std(chip, page);
 683         nfc->data_access = false;
 684 
 685         return ret;
 686 }
 687 
 688 static int vf610_nfc_write_oob(struct nand_chip *chip, int page)
 689 {
 690         struct mtd_info *mtd = nand_to_mtd(chip);
 691         struct vf610_nfc *nfc = chip_to_nfc(chip);
 692         int ret;
 693 
 694         nfc->data_access = true;
 695         ret = nand_prog_page_begin_op(chip, page, mtd->writesize,
 696                                       chip->oob_poi, mtd->oobsize);
 697         nfc->data_access = false;
 698 
 699         if (ret)
 700                 return ret;
 701 
 702         return nand_prog_page_end_op(chip);
 703 }
 704 
 705 static const struct of_device_id vf610_nfc_dt_ids[] = {
 706         { .compatible = "fsl,vf610-nfc", .data = (void *)NFC_VFC610 },
 707         { /* sentinel */ }
 708 };
 709 MODULE_DEVICE_TABLE(of, vf610_nfc_dt_ids);
 710 
 711 static void vf610_nfc_preinit_controller(struct vf610_nfc *nfc)
 712 {
 713         vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
 714         vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
 715         vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
 716         vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
 717         vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
 718         vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
 719         vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
 720 
 721         /* Disable virtual pages, only one elementary transfer unit */
 722         vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
 723                             CONFIG_PAGE_CNT_SHIFT, 1);
 724 }
 725 
 726 static void vf610_nfc_init_controller(struct vf610_nfc *nfc)
 727 {
 728         if (nfc->chip.options & NAND_BUSWIDTH_16)
 729                 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
 730         else
 731                 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
 732 
 733         if (nfc->chip.ecc.mode == NAND_ECC_HW) {
 734                 /* Set ECC status offset in SRAM */
 735                 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG,
 736                                     CONFIG_ECC_SRAM_ADDR_MASK,
 737                                     CONFIG_ECC_SRAM_ADDR_SHIFT,
 738                                     ECC_SRAM_ADDR >> 3);
 739 
 740                 /* Enable ECC status in SRAM */
 741                 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
 742         }
 743 }
 744 
 745 static int vf610_nfc_attach_chip(struct nand_chip *chip)
 746 {
 747         struct mtd_info *mtd = nand_to_mtd(chip);
 748         struct vf610_nfc *nfc = chip_to_nfc(chip);
 749 
 750         vf610_nfc_init_controller(nfc);
 751 
 752         /* Bad block options. */
 753         if (chip->bbt_options & NAND_BBT_USE_FLASH)
 754                 chip->bbt_options |= NAND_BBT_NO_OOB;
 755 
 756         /* Single buffer only, max 256 OOB minus ECC status */
 757         if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
 758                 dev_err(nfc->dev, "Unsupported flash page size\n");
 759                 return -ENXIO;
 760         }
 761 
 762         if (chip->ecc.mode != NAND_ECC_HW)
 763                 return 0;
 764 
 765         if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
 766                 dev_err(nfc->dev, "Unsupported flash with hwecc\n");
 767                 return -ENXIO;
 768         }
 769 
 770         if (chip->ecc.size != mtd->writesize) {
 771                 dev_err(nfc->dev, "Step size needs to be page size\n");
 772                 return -ENXIO;
 773         }
 774 
 775         /* Only 64 byte ECC layouts known */
 776         if (mtd->oobsize > 64)
 777                 mtd->oobsize = 64;
 778 
 779         /* Use default large page ECC layout defined in NAND core */
 780         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
 781         if (chip->ecc.strength == 32) {
 782                 nfc->ecc_mode = ECC_60_BYTE;
 783                 chip->ecc.bytes = 60;
 784         } else if (chip->ecc.strength == 24) {
 785                 nfc->ecc_mode = ECC_45_BYTE;
 786                 chip->ecc.bytes = 45;
 787         } else {
 788                 dev_err(nfc->dev, "Unsupported ECC strength\n");
 789                 return -ENXIO;
 790         }
 791 
 792         chip->ecc.read_page = vf610_nfc_read_page;
 793         chip->ecc.write_page = vf610_nfc_write_page;
 794         chip->ecc.read_page_raw = vf610_nfc_read_page_raw;
 795         chip->ecc.write_page_raw = vf610_nfc_write_page_raw;
 796         chip->ecc.read_oob = vf610_nfc_read_oob;
 797         chip->ecc.write_oob = vf610_nfc_write_oob;
 798 
 799         chip->ecc.size = PAGE_2K;
 800 
 801         return 0;
 802 }
 803 
 804 static const struct nand_controller_ops vf610_nfc_controller_ops = {
 805         .attach_chip = vf610_nfc_attach_chip,
 806         .exec_op = vf610_nfc_exec_op,
 807 
 808 };
 809 
 810 static int vf610_nfc_probe(struct platform_device *pdev)
 811 {
 812         struct vf610_nfc *nfc;
 813         struct resource *res;
 814         struct mtd_info *mtd;
 815         struct nand_chip *chip;
 816         struct device_node *child;
 817         const struct of_device_id *of_id;
 818         int err;
 819         int irq;
 820 
 821         nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
 822         if (!nfc)
 823                 return -ENOMEM;
 824 
 825         nfc->dev = &pdev->dev;
 826         chip = &nfc->chip;
 827         mtd = nand_to_mtd(chip);
 828 
 829         mtd->owner = THIS_MODULE;
 830         mtd->dev.parent = nfc->dev;
 831         mtd->name = DRV_NAME;
 832 
 833         irq = platform_get_irq(pdev, 0);
 834         if (irq <= 0)
 835                 return -EINVAL;
 836 
 837         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 838         nfc->regs = devm_ioremap_resource(nfc->dev, res);
 839         if (IS_ERR(nfc->regs))
 840                 return PTR_ERR(nfc->regs);
 841 
 842         nfc->clk = devm_clk_get(&pdev->dev, NULL);
 843         if (IS_ERR(nfc->clk))
 844                 return PTR_ERR(nfc->clk);
 845 
 846         err = clk_prepare_enable(nfc->clk);
 847         if (err) {
 848                 dev_err(nfc->dev, "Unable to enable clock!\n");
 849                 return err;
 850         }
 851 
 852         of_id = of_match_device(vf610_nfc_dt_ids, &pdev->dev);
 853         if (!of_id)
 854                 return -ENODEV;
 855 
 856         nfc->variant = (enum vf610_nfc_variant)of_id->data;
 857 
 858         for_each_available_child_of_node(nfc->dev->of_node, child) {
 859                 if (of_device_is_compatible(child, "fsl,vf610-nfc-nandcs")) {
 860 
 861                         if (nand_get_flash_node(chip)) {
 862                                 dev_err(nfc->dev,
 863                                         "Only one NAND chip supported!\n");
 864                                 err = -EINVAL;
 865                                 of_node_put(child);
 866                                 goto err_disable_clk;
 867                         }
 868 
 869                         nand_set_flash_node(chip, child);
 870                 }
 871         }
 872 
 873         if (!nand_get_flash_node(chip)) {
 874                 dev_err(nfc->dev, "NAND chip sub-node missing!\n");
 875                 err = -ENODEV;
 876                 goto err_disable_clk;
 877         }
 878 
 879         chip->options |= NAND_NO_SUBPAGE_WRITE;
 880 
 881         init_completion(&nfc->cmd_done);
 882 
 883         err = devm_request_irq(nfc->dev, irq, vf610_nfc_irq, 0, DRV_NAME, nfc);
 884         if (err) {
 885                 dev_err(nfc->dev, "Error requesting IRQ!\n");
 886                 goto err_disable_clk;
 887         }
 888 
 889         vf610_nfc_preinit_controller(nfc);
 890 
 891         nand_controller_init(&nfc->base);
 892         nfc->base.ops = &vf610_nfc_controller_ops;
 893         chip->controller = &nfc->base;
 894 
 895         /* Scan the NAND chip */
 896         err = nand_scan(chip, 1);
 897         if (err)
 898                 goto err_disable_clk;
 899 
 900         platform_set_drvdata(pdev, nfc);
 901 
 902         /* Register device in MTD */
 903         err = mtd_device_register(mtd, NULL, 0);
 904         if (err)
 905                 goto err_cleanup_nand;
 906         return 0;
 907 
 908 err_cleanup_nand:
 909         nand_cleanup(chip);
 910 err_disable_clk:
 911         clk_disable_unprepare(nfc->clk);
 912         return err;
 913 }
 914 
 915 static int vf610_nfc_remove(struct platform_device *pdev)
 916 {
 917         struct vf610_nfc *nfc = platform_get_drvdata(pdev);
 918 
 919         nand_release(&nfc->chip);
 920         clk_disable_unprepare(nfc->clk);
 921         return 0;
 922 }
 923 
 924 #ifdef CONFIG_PM_SLEEP
 925 static int vf610_nfc_suspend(struct device *dev)
 926 {
 927         struct vf610_nfc *nfc = dev_get_drvdata(dev);
 928 
 929         clk_disable_unprepare(nfc->clk);
 930         return 0;
 931 }
 932 
 933 static int vf610_nfc_resume(struct device *dev)
 934 {
 935         struct vf610_nfc *nfc = dev_get_drvdata(dev);
 936         int err;
 937 
 938         err = clk_prepare_enable(nfc->clk);
 939         if (err)
 940                 return err;
 941 
 942         vf610_nfc_preinit_controller(nfc);
 943         vf610_nfc_init_controller(nfc);
 944         return 0;
 945 }
 946 #endif
 947 
 948 static SIMPLE_DEV_PM_OPS(vf610_nfc_pm_ops, vf610_nfc_suspend, vf610_nfc_resume);
 949 
 950 static struct platform_driver vf610_nfc_driver = {
 951         .driver         = {
 952                 .name   = DRV_NAME,
 953                 .of_match_table = vf610_nfc_dt_ids,
 954                 .pm     = &vf610_nfc_pm_ops,
 955         },
 956         .probe          = vf610_nfc_probe,
 957         .remove         = vf610_nfc_remove,
 958 };
 959 
 960 module_platform_driver(vf610_nfc_driver);
 961 
 962 MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>");
 963 MODULE_DESCRIPTION("Freescale VF610/MPC5125 NFC MTD NAND driver");
 964 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/mtd/nand/raw/vf610_nfc.c

DEFINITIONS
