root/drivers/mtd/nand/raw/sharpsl.c

DEFINITIONS

1. mtd_to_sharpsl
2. sharpsl_nand_hwcontrol
3. sharpsl_nand_dev_ready
4. sharpsl_nand_enable_hwecc
5. sharpsl_nand_calculate_ecc
6. sharpsl_nand_probe
7. sharpsl_nand_remove

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Copyright (C) 2004 Richard Purdie
   4  *  Copyright (C) 2008 Dmitry Baryshkov
   5  *
   6  *  Based on Sharp's NAND driver sharp_sl.c
   7  */
   8 
   9 #include <linux/genhd.h>
  10 #include <linux/slab.h>
  11 #include <linux/module.h>
  12 #include <linux/delay.h>
  13 #include <linux/mtd/mtd.h>
  14 #include <linux/mtd/rawnand.h>
  15 #include <linux/mtd/nand_ecc.h>
  16 #include <linux/mtd/partitions.h>
  17 #include <linux/mtd/sharpsl.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/io.h>
  21 
  22 struct sharpsl_nand {
  23         struct nand_chip        chip;
  24 
  25         void __iomem            *io;
  26 };
  27 
  28 static inline struct sharpsl_nand *mtd_to_sharpsl(struct mtd_info *mtd)
  29 {
  30         return container_of(mtd_to_nand(mtd), struct sharpsl_nand, chip);
  31 }
  32 
  33 /* register offset */
  34 #define ECCLPLB         0x00    /* line parity 7 - 0 bit */
  35 #define ECCLPUB         0x04    /* line parity 15 - 8 bit */
  36 #define ECCCP           0x08    /* column parity 5 - 0 bit */
  37 #define ECCCNTR         0x0C    /* ECC byte counter */
  38 #define ECCCLRR         0x10    /* cleare ECC */
  39 #define FLASHIO         0x14    /* Flash I/O */
  40 #define FLASHCTL        0x18    /* Flash Control */
  41 
  42 /* Flash control bit */
  43 #define FLRYBY          (1 << 5)
  44 #define FLCE1           (1 << 4)
  45 #define FLWP            (1 << 3)
  46 #define FLALE           (1 << 2)
  47 #define FLCLE           (1 << 1)
  48 #define FLCE0           (1 << 0)
  49 
  50 /*
  51  *      hardware specific access to control-lines
  52  *      ctrl:
  53  *      NAND_CNE: bit 0 -> ! bit 0 & 4
  54  *      NAND_CLE: bit 1 -> bit 1
  55  *      NAND_ALE: bit 2 -> bit 2
  56  *
  57  */
  58 static void sharpsl_nand_hwcontrol(struct nand_chip *chip, int cmd,
  59                                    unsigned int ctrl)
  60 {
  61         struct sharpsl_nand *sharpsl = mtd_to_sharpsl(nand_to_mtd(chip));
  62 
  63         if (ctrl & NAND_CTRL_CHANGE) {
  64                 unsigned char bits = ctrl & 0x07;
  65 
  66                 bits |= (ctrl & 0x01) << 4;
  67 
  68                 bits ^= 0x11;
  69 
  70                 writeb((readb(sharpsl->io + FLASHCTL) & ~0x17) | bits, sharpsl->io + FLASHCTL);
  71         }
  72 
  73         if (cmd != NAND_CMD_NONE)
  74                 writeb(cmd, chip->legacy.IO_ADDR_W);
  75 }
  76 
  77 static int sharpsl_nand_dev_ready(struct nand_chip *chip)
  78 {
  79         struct sharpsl_nand *sharpsl = mtd_to_sharpsl(nand_to_mtd(chip));
  80         return !((readb(sharpsl->io + FLASHCTL) & FLRYBY) == 0);
  81 }
  82 
  83 static void sharpsl_nand_enable_hwecc(struct nand_chip *chip, int mode)
  84 {
  85         struct sharpsl_nand *sharpsl = mtd_to_sharpsl(nand_to_mtd(chip));
  86         writeb(0, sharpsl->io + ECCCLRR);
  87 }
  88 
  89 static int sharpsl_nand_calculate_ecc(struct nand_chip *chip,
  90                                       const u_char * dat, u_char * ecc_code)
  91 {
  92         struct sharpsl_nand *sharpsl = mtd_to_sharpsl(nand_to_mtd(chip));
  93         ecc_code[0] = ~readb(sharpsl->io + ECCLPUB);
  94         ecc_code[1] = ~readb(sharpsl->io + ECCLPLB);
  95         ecc_code[2] = (~readb(sharpsl->io + ECCCP) << 2) | 0x03;
  96         return readb(sharpsl->io + ECCCNTR) != 0;
  97 }
  98 
  99 /*
 100  * Main initialization routine
 101  */
 102 static int sharpsl_nand_probe(struct platform_device *pdev)
 103 {
 104         struct nand_chip *this;
 105         struct mtd_info *mtd;
 106         struct resource *r;
 107         int err = 0;
 108         struct sharpsl_nand *sharpsl;
 109         struct sharpsl_nand_platform_data *data = dev_get_platdata(&pdev->dev);
 110 
 111         if (!data) {
 112                 dev_err(&pdev->dev, "no platform data!\n");
 113                 return -EINVAL;
 114         }
 115 
 116         /* Allocate memory for MTD device structure and private data */
 117         sharpsl = kzalloc(sizeof(struct sharpsl_nand), GFP_KERNEL);
 118         if (!sharpsl)
 119                 return -ENOMEM;
 120 
 121         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 122         if (!r) {
 123                 dev_err(&pdev->dev, "no io memory resource defined!\n");
 124                 err = -ENODEV;
 125                 goto err_get_res;
 126         }
 127 
 128         /* map physical address */
 129         sharpsl->io = ioremap(r->start, resource_size(r));
 130         if (!sharpsl->io) {
 131                 dev_err(&pdev->dev, "ioremap to access Sharp SL NAND chip failed\n");
 132                 err = -EIO;
 133                 goto err_ioremap;
 134         }
 135 
 136         /* Get pointer to private data */
 137         this = (struct nand_chip *)(&sharpsl->chip);
 138 
 139         /* Link the private data with the MTD structure */
 140         mtd = nand_to_mtd(this);
 141         mtd->dev.parent = &pdev->dev;
 142         mtd_set_ooblayout(mtd, data->ecc_layout);
 143 
 144         platform_set_drvdata(pdev, sharpsl);
 145 
 146         /*
 147          * PXA initialize
 148          */
 149         writeb(readb(sharpsl->io + FLASHCTL) | FLWP, sharpsl->io + FLASHCTL);
 150 
 151         /* Set address of NAND IO lines */
 152         this->legacy.IO_ADDR_R = sharpsl->io + FLASHIO;
 153         this->legacy.IO_ADDR_W = sharpsl->io + FLASHIO;
 154         /* Set address of hardware control function */
 155         this->legacy.cmd_ctrl = sharpsl_nand_hwcontrol;
 156         this->legacy.dev_ready = sharpsl_nand_dev_ready;
 157         /* 15 us command delay time */
 158         this->legacy.chip_delay = 15;
 159         /* set eccmode using hardware ECC */
 160         this->ecc.mode = NAND_ECC_HW;
 161         this->ecc.size = 256;
 162         this->ecc.bytes = 3;
 163         this->ecc.strength = 1;
 164         this->badblock_pattern = data->badblock_pattern;
 165         this->ecc.hwctl = sharpsl_nand_enable_hwecc;
 166         this->ecc.calculate = sharpsl_nand_calculate_ecc;
 167         this->ecc.correct = nand_correct_data;
 168 
 169         /* Scan to find existence of the device */
 170         err = nand_scan(this, 1);
 171         if (err)
 172                 goto err_scan;
 173 
 174         /* Register the partitions */
 175         mtd->name = "sharpsl-nand";
 176 
 177         err = mtd_device_parse_register(mtd, data->part_parsers, NULL,
 178                                         data->partitions, data->nr_partitions);
 179         if (err)
 180                 goto err_add;
 181 
 182         /* Return happy */
 183         return 0;
 184 
 185 err_add:
 186         nand_release(this);
 187 
 188 err_scan:
 189         iounmap(sharpsl->io);
 190 err_ioremap:
 191 err_get_res:
 192         kfree(sharpsl);
 193         return err;
 194 }
 195 
 196 /*
 197  * Clean up routine
 198  */
 199 static int sharpsl_nand_remove(struct platform_device *pdev)
 200 {
 201         struct sharpsl_nand *sharpsl = platform_get_drvdata(pdev);
 202 
 203         /* Release resources, unregister device */
 204         nand_release(&sharpsl->chip);
 205 
 206         iounmap(sharpsl->io);
 207 
 208         /* Free the MTD device structure */
 209         kfree(sharpsl);
 210 
 211         return 0;
 212 }
 213 
 214 static struct platform_driver sharpsl_nand_driver = {
 215         .driver = {
 216                 .name   = "sharpsl-nand",
 217         },
 218         .probe          = sharpsl_nand_probe,
 219         .remove         = sharpsl_nand_remove,
 220 };
 221 
 222 module_platform_driver(sharpsl_nand_driver);
 223 
 224 MODULE_LICENSE("GPL");
 225 MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
 226 MODULE_DESCRIPTION("Device specific logic for NAND flash on Sharp SL-C7xx Series");