root/drivers/mtd/nand/raw/nand_base.c

DEFINITIONS

1. nand_ooblayout_ecc_sp
2. nand_ooblayout_free_sp
3. nand_ooblayout_ecc_lp
4. nand_ooblayout_free_lp
5. nand_ooblayout_ecc_lp_hamming
6. nand_ooblayout_free_lp_hamming
7. check_offs_len
8. nand_select_target
9. nand_deselect_target
10. nand_release_device
11. nand_bbm_get_next_page
12. nand_block_bad
13. nand_isbad_bbm
14. nand_get_device
15. nand_check_wp
16. nand_fill_oob
17. nand_do_write_oob
18. nand_default_block_markbad
19. nand_markbad_bbm
20. nand_block_markbad_lowlevel
21. nand_block_isreserved
22. nand_block_checkbad
23. nand_soft_waitrdy
24. nand_gpio_waitrdy
25. panic_nand_wait
26. nand_supports_get_features
27. nand_supports_set_features
28. nand_reset_data_interface
29. nand_setup_data_interface
30. nand_init_data_interface
31. nand_fill_column_cycles
32. nand_sp_exec_read_page_op
33. nand_lp_exec_read_page_op
34. nand_read_page_op
35. nand_read_param_page_op
36. nand_change_read_column_op
37. nand_read_oob_op
38. nand_exec_prog_page_op
39. nand_prog_page_begin_op
40. nand_prog_page_end_op
41. nand_prog_page_op
42. nand_change_write_column_op
43. nand_readid_op
44. nand_status_op
45. nand_exit_status_op
46. nand_erase_op
47. nand_set_features_op
48. nand_get_features_op
49. nand_wait_rdy_op
50. nand_reset_op
51. nand_read_data_op
52. nand_write_data_op
53. nand_op_parser_must_split_instr
54. nand_op_parser_match_pat
55. nand_op_parser_trace
56. nand_op_parser_trace
57. nand_op_parser_cmp_ctx
58. nand_op_parser_exec_op
59. nand_instr_is_data
60. nand_subop_instr_is_valid
61. nand_subop_get_start_off
62. nand_subop_get_addr_start_off
63. nand_subop_get_num_addr_cyc
64. nand_subop_get_data_start_off
65. nand_subop_get_data_len
66. nand_reset
67. nand_get_features
68. nand_set_features
69. nand_check_erased_buf
70. nand_check_erased_ecc_chunk
71. nand_read_page_raw_notsupp
72. nand_read_page_raw
73. nand_read_page_raw_syndrome
74. nand_read_page_swecc
75. nand_read_subpage
76. nand_read_page_hwecc
77. nand_read_page_hwecc_oob_first
78. nand_read_page_syndrome
79. nand_transfer_oob
80. nand_setup_read_retry
81. nand_wait_readrdy
82. nand_do_read_ops
83. nand_read_oob_std
84. nand_read_oob_syndrome
85. nand_write_oob_std
86. nand_write_oob_syndrome
87. nand_do_read_oob
88. nand_read_oob
89. nand_write_page_raw_notsupp
90. nand_write_page_raw
91. nand_write_page_raw_syndrome
92. nand_write_page_swecc
93. nand_write_page_hwecc
94. nand_write_subpage_hwecc
95. nand_write_page_syndrome
96. nand_write_page
97. nand_do_write_ops
98. panic_nand_write
99. nand_write_oob
100. nand_erase
101. nand_erase_nand
102. nand_sync
103. nand_block_isbad
104. nand_block_markbad
105. nand_suspend
106. nand_resume
107. nand_shutdown
108. nand_set_defaults
109. sanitize_string
110. nand_id_has_period
111. nand_id_len
112. nand_get_bits_per_cell
113. nand_decode_ext_id
114. nand_decode_id
115. nand_decode_bbm_options
116. is_full_id_nand
117. find_full_id_nand
118. nand_manufacturer_detect
119. nand_manufacturer_init
120. nand_manufacturer_cleanup
121. nand_manufacturer_name
122. nand_detect
123. of_get_nand_ecc_mode
124. of_get_nand_ecc_algo
125. of_get_nand_ecc_step_size
126. of_get_nand_ecc_strength
127. of_get_nand_bus_width
128. of_get_nand_on_flash_bbt
129. nand_dt_init
130. nand_scan_ident
131. nand_scan_ident_cleanup
132. nand_set_ecc_soft_ops
133. nand_check_ecc_caps
134. nand_match_ecc_req
135. nand_maximize_ecc
136. nand_ecc_choose_conf
137. nand_ecc_strength_good
138. rawnand_erase
139. rawnand_markbad
140. rawnand_isbad
141. nand_scan_tail
142. nand_attach
143. nand_detach
144. nand_scan_with_ids
145. nand_cleanup
146. nand_release

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Overview:
   4  *   This is the generic MTD driver for NAND flash devices. It should be
   5  *   capable of working with almost all NAND chips currently available.
   6  *
   7  *      Additional technical information is available on
   8  *      http://www.linux-mtd.infradead.org/doc/nand.html
   9  *
  10  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  11  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  12  *
  13  *  Credits:
  14  *      David Woodhouse for adding multichip support
  15  *
  16  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  17  *      rework for 2K page size chips
  18  *
  19  *  TODO:
  20  *      Enable cached programming for 2k page size chips
  21  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  22  *      if we have HW ECC support.
  23  *      BBT table is not serialized, has to be fixed
  24  */
  25 
  26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  27 
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/errno.h>
  31 #include <linux/err.h>
  32 #include <linux/sched.h>
  33 #include <linux/slab.h>
  34 #include <linux/mm.h>
  35 #include <linux/types.h>
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/nand_ecc.h>
  38 #include <linux/mtd/nand_bch.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/bitops.h>
  41 #include <linux/io.h>
  42 #include <linux/mtd/partitions.h>
  43 #include <linux/of.h>
  44 #include <linux/gpio/consumer.h>
  45 
  46 #include "internals.h"
  47 
  48 /* Define default oob placement schemes for large and small page devices */
  49 static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
  50                                  struct mtd_oob_region *oobregion)
  51 {
  52         struct nand_chip *chip = mtd_to_nand(mtd);
  53         struct nand_ecc_ctrl *ecc = &chip->ecc;
  54 
  55         if (section > 1)
  56                 return -ERANGE;
  57 
  58         if (!section) {
  59                 oobregion->offset = 0;
  60                 if (mtd->oobsize == 16)
  61                         oobregion->length = 4;
  62                 else
  63                         oobregion->length = 3;
  64         } else {
  65                 if (mtd->oobsize == 8)
  66                         return -ERANGE;
  67 
  68                 oobregion->offset = 6;
  69                 oobregion->length = ecc->total - 4;
  70         }
  71 
  72         return 0;
  73 }
  74 
  75 static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section,
  76                                   struct mtd_oob_region *oobregion)
  77 {
  78         if (section > 1)
  79                 return -ERANGE;
  80 
  81         if (mtd->oobsize == 16) {
  82                 if (section)
  83                         return -ERANGE;
  84 
  85                 oobregion->length = 8;
  86                 oobregion->offset = 8;
  87         } else {
  88                 oobregion->length = 2;
  89                 if (!section)
  90                         oobregion->offset = 3;
  91                 else
  92                         oobregion->offset = 6;
  93         }
  94 
  95         return 0;
  96 }
  97 
  98 const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = {
  99         .ecc = nand_ooblayout_ecc_sp,
 100         .free = nand_ooblayout_free_sp,
 101 };
 102 EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops);
 103 
 104 static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
 105                                  struct mtd_oob_region *oobregion)
 106 {
 107         struct nand_chip *chip = mtd_to_nand(mtd);
 108         struct nand_ecc_ctrl *ecc = &chip->ecc;
 109 
 110         if (section || !ecc->total)
 111                 return -ERANGE;
 112 
 113         oobregion->length = ecc->total;
 114         oobregion->offset = mtd->oobsize - oobregion->length;
 115 
 116         return 0;
 117 }
 118 
 119 static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
 120                                   struct mtd_oob_region *oobregion)
 121 {
 122         struct nand_chip *chip = mtd_to_nand(mtd);
 123         struct nand_ecc_ctrl *ecc = &chip->ecc;
 124 
 125         if (section)
 126                 return -ERANGE;
 127 
 128         oobregion->length = mtd->oobsize - ecc->total - 2;
 129         oobregion->offset = 2;
 130 
 131         return 0;
 132 }
 133 
 134 const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
 135         .ecc = nand_ooblayout_ecc_lp,
 136         .free = nand_ooblayout_free_lp,
 137 };
 138 EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops);
 139 
 140 /*
 141  * Support the old "large page" layout used for 1-bit Hamming ECC where ECC
 142  * are placed at a fixed offset.
 143  */
 144 static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section,
 145                                          struct mtd_oob_region *oobregion)
 146 {
 147         struct nand_chip *chip = mtd_to_nand(mtd);
 148         struct nand_ecc_ctrl *ecc = &chip->ecc;
 149 
 150         if (section)
 151                 return -ERANGE;
 152 
 153         switch (mtd->oobsize) {
 154         case 64:
 155                 oobregion->offset = 40;
 156                 break;
 157         case 128:
 158                 oobregion->offset = 80;
 159                 break;
 160         default:
 161                 return -EINVAL;
 162         }
 163 
 164         oobregion->length = ecc->total;
 165         if (oobregion->offset + oobregion->length > mtd->oobsize)
 166                 return -ERANGE;
 167 
 168         return 0;
 169 }
 170 
 171 static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section,
 172                                           struct mtd_oob_region *oobregion)
 173 {
 174         struct nand_chip *chip = mtd_to_nand(mtd);
 175         struct nand_ecc_ctrl *ecc = &chip->ecc;
 176         int ecc_offset = 0;
 177 
 178         if (section < 0 || section > 1)
 179                 return -ERANGE;
 180 
 181         switch (mtd->oobsize) {
 182         case 64:
 183                 ecc_offset = 40;
 184                 break;
 185         case 128:
 186                 ecc_offset = 80;
 187                 break;
 188         default:
 189                 return -EINVAL;
 190         }
 191 
 192         if (section == 0) {
 193                 oobregion->offset = 2;
 194                 oobregion->length = ecc_offset - 2;
 195         } else {
 196                 oobregion->offset = ecc_offset + ecc->total;
 197                 oobregion->length = mtd->oobsize - oobregion->offset;
 198         }
 199 
 200         return 0;
 201 }
 202 
 203 static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = {
 204         .ecc = nand_ooblayout_ecc_lp_hamming,
 205         .free = nand_ooblayout_free_lp_hamming,
 206 };
 207 
 208 static int check_offs_len(struct nand_chip *chip, loff_t ofs, uint64_t len)
 209 {
 210         int ret = 0;
 211 
 212         /* Start address must align on block boundary */
 213         if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
 214                 pr_debug("%s: unaligned address\n", __func__);
 215                 ret = -EINVAL;
 216         }
 217 
 218         /* Length must align on block boundary */
 219         if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
 220                 pr_debug("%s: length not block aligned\n", __func__);
 221                 ret = -EINVAL;
 222         }
 223 
 224         return ret;
 225 }
 226 
 227 /**
 228  * nand_select_target() - Select a NAND target (A.K.A. die)
 229  * @chip: NAND chip object
 230  * @cs: the CS line to select. Note that this CS id is always from the chip
 231  *      PoV, not the controller one
 232  *
 233  * Select a NAND target so that further operations executed on @chip go to the
 234  * selected NAND target.
 235  */
 236 void nand_select_target(struct nand_chip *chip, unsigned int cs)
 237 {
 238         /*
 239          * cs should always lie between 0 and nanddev_ntargets(), when that's
 240          * not the case it's a bug and the caller should be fixed.
 241          */
 242         if (WARN_ON(cs > nanddev_ntargets(&chip->base)))
 243                 return;
 244 
 245         chip->cur_cs = cs;
 246 
 247         if (chip->legacy.select_chip)
 248                 chip->legacy.select_chip(chip, cs);
 249 }
 250 EXPORT_SYMBOL_GPL(nand_select_target);
 251 
 252 /**
 253  * nand_deselect_target() - Deselect the currently selected target
 254  * @chip: NAND chip object
 255  *
 256  * Deselect the currently selected NAND target. The result of operations
 257  * executed on @chip after the target has been deselected is undefined.
 258  */
 259 void nand_deselect_target(struct nand_chip *chip)
 260 {
 261         if (chip->legacy.select_chip)
 262                 chip->legacy.select_chip(chip, -1);
 263 
 264         chip->cur_cs = -1;
 265 }
 266 EXPORT_SYMBOL_GPL(nand_deselect_target);
 267 
 268 /**
 269  * nand_release_device - [GENERIC] release chip
 270  * @chip: NAND chip object
 271  *
 272  * Release chip lock and wake up anyone waiting on the device.
 273  */
 274 static void nand_release_device(struct nand_chip *chip)
 275 {
 276         /* Release the controller and the chip */
 277         mutex_unlock(&chip->controller->lock);
 278         mutex_unlock(&chip->lock);
 279 }
 280 
 281 /**
 282  * nand_bbm_get_next_page - Get the next page for bad block markers
 283  * @chip: NAND chip object
 284  * @page: First page to start checking for bad block marker usage
 285  *
 286  * Returns an integer that corresponds to the page offset within a block, for
 287  * a page that is used to store bad block markers. If no more pages are
 288  * available, -EINVAL is returned.
 289  */
 290 int nand_bbm_get_next_page(struct nand_chip *chip, int page)
 291 {
 292         struct mtd_info *mtd = nand_to_mtd(chip);
 293         int last_page = ((mtd->erasesize - mtd->writesize) >>
 294                          chip->page_shift) & chip->pagemask;
 295         unsigned int bbm_flags = NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE
 296                 | NAND_BBM_LASTPAGE;
 297 
 298         if (page == 0 && !(chip->options & bbm_flags))
 299                 return 0;
 300         if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE)
 301                 return 0;
 302         if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE)
 303                 return 1;
 304         if (page <= last_page && chip->options & NAND_BBM_LASTPAGE)
 305                 return last_page;
 306 
 307         return -EINVAL;
 308 }
 309 
 310 /**
 311  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 312  * @chip: NAND chip object
 313  * @ofs: offset from device start
 314  *
 315  * Check, if the block is bad.
 316  */
 317 static int nand_block_bad(struct nand_chip *chip, loff_t ofs)
 318 {
 319         int first_page, page_offset;
 320         int res;
 321         u8 bad;
 322 
 323         first_page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 324         page_offset = nand_bbm_get_next_page(chip, 0);
 325 
 326         while (page_offset >= 0) {
 327                 res = chip->ecc.read_oob(chip, first_page + page_offset);
 328                 if (res < 0)
 329                         return res;
 330 
 331                 bad = chip->oob_poi[chip->badblockpos];
 332 
 333                 if (likely(chip->badblockbits == 8))
 334                         res = bad != 0xFF;
 335                 else
 336                         res = hweight8(bad) < chip->badblockbits;
 337                 if (res)
 338                         return res;
 339 
 340                 page_offset = nand_bbm_get_next_page(chip, page_offset + 1);
 341         }
 342 
 343         return 0;
 344 }
 345 
 346 static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs)
 347 {
 348         if (chip->legacy.block_bad)
 349                 return chip->legacy.block_bad(chip, ofs);
 350 
 351         return nand_block_bad(chip, ofs);
 352 }
 353 
 354 /**
 355  * nand_get_device - [GENERIC] Get chip for selected access
 356  * @chip: NAND chip structure
 357  *
 358  * Lock the device and its controller for exclusive access
 359  *
 360  * Return: -EBUSY if the chip has been suspended, 0 otherwise
 361  */
 362 static int nand_get_device(struct nand_chip *chip)
 363 {
 364         mutex_lock(&chip->lock);
 365         if (chip->suspended) {
 366                 mutex_unlock(&chip->lock);
 367                 return -EBUSY;
 368         }
 369         mutex_lock(&chip->controller->lock);
 370 
 371         return 0;
 372 }
 373 
 374 /**
 375  * nand_check_wp - [GENERIC] check if the chip is write protected
 376  * @chip: NAND chip object
 377  *
 378  * Check, if the device is write protected. The function expects, that the
 379  * device is already selected.
 380  */
 381 static int nand_check_wp(struct nand_chip *chip)
 382 {
 383         u8 status;
 384         int ret;
 385 
 386         /* Broken xD cards report WP despite being writable */
 387         if (chip->options & NAND_BROKEN_XD)
 388                 return 0;
 389 
 390         /* Check the WP bit */
 391         ret = nand_status_op(chip, &status);
 392         if (ret)
 393                 return ret;
 394 
 395         return status & NAND_STATUS_WP ? 0 : 1;
 396 }
 397 
 398 /**
 399  * nand_fill_oob - [INTERN] Transfer client buffer to oob
 400  * @chip: NAND chip object
 401  * @oob: oob data buffer
 402  * @len: oob data write length
 403  * @ops: oob ops structure
 404  */
 405 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
 406                               struct mtd_oob_ops *ops)
 407 {
 408         struct mtd_info *mtd = nand_to_mtd(chip);
 409         int ret;
 410 
 411         /*
 412          * Initialise to all 0xFF, to avoid the possibility of left over OOB
 413          * data from a previous OOB read.
 414          */
 415         memset(chip->oob_poi, 0xff, mtd->oobsize);
 416 
 417         switch (ops->mode) {
 418 
 419         case MTD_OPS_PLACE_OOB:
 420         case MTD_OPS_RAW:
 421                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
 422                 return oob + len;
 423 
 424         case MTD_OPS_AUTO_OOB:
 425                 ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi,
 426                                                   ops->ooboffs, len);
 427                 BUG_ON(ret);
 428                 return oob + len;
 429 
 430         default:
 431                 BUG();
 432         }
 433         return NULL;
 434 }
 435 
 436 /**
 437  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
 438  * @chip: NAND chip object
 439  * @to: offset to write to
 440  * @ops: oob operation description structure
 441  *
 442  * NAND write out-of-band.
 443  */
 444 static int nand_do_write_oob(struct nand_chip *chip, loff_t to,
 445                              struct mtd_oob_ops *ops)
 446 {
 447         struct mtd_info *mtd = nand_to_mtd(chip);
 448         int chipnr, page, status, len, ret;
 449 
 450         pr_debug("%s: to = 0x%08x, len = %i\n",
 451                          __func__, (unsigned int)to, (int)ops->ooblen);
 452 
 453         len = mtd_oobavail(mtd, ops);
 454 
 455         /* Do not allow write past end of page */
 456         if ((ops->ooboffs + ops->ooblen) > len) {
 457                 pr_debug("%s: attempt to write past end of page\n",
 458                                 __func__);
 459                 return -EINVAL;
 460         }
 461 
 462         chipnr = (int)(to >> chip->chip_shift);
 463 
 464         /*
 465          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
 466          * of my DiskOnChip 2000 test units) will clear the whole data page too
 467          * if we don't do this. I have no clue why, but I seem to have 'fixed'
 468          * it in the doc2000 driver in August 1999.  dwmw2.
 469          */
 470         ret = nand_reset(chip, chipnr);
 471         if (ret)
 472                 return ret;
 473 
 474         nand_select_target(chip, chipnr);
 475 
 476         /* Shift to get page */
 477         page = (int)(to >> chip->page_shift);
 478 
 479         /* Check, if it is write protected */
 480         if (nand_check_wp(chip)) {
 481                 nand_deselect_target(chip);
 482                 return -EROFS;
 483         }
 484 
 485         /* Invalidate the page cache, if we write to the cached page */
 486         if (page == chip->pagecache.page)
 487                 chip->pagecache.page = -1;
 488 
 489         nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
 490 
 491         if (ops->mode == MTD_OPS_RAW)
 492                 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask);
 493         else
 494                 status = chip->ecc.write_oob(chip, page & chip->pagemask);
 495 
 496         nand_deselect_target(chip);
 497 
 498         if (status)
 499                 return status;
 500 
 501         ops->oobretlen = ops->ooblen;
 502 
 503         return 0;
 504 }
 505 
 506 /**
 507  * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
 508  * @chip: NAND chip object
 509  * @ofs: offset from device start
 510  *
 511  * This is the default implementation, which can be overridden by a hardware
 512  * specific driver. It provides the details for writing a bad block marker to a
 513  * block.
 514  */
 515 static int nand_default_block_markbad(struct nand_chip *chip, loff_t ofs)
 516 {
 517         struct mtd_info *mtd = nand_to_mtd(chip);
 518         struct mtd_oob_ops ops;
 519         uint8_t buf[2] = { 0, 0 };
 520         int ret = 0, res, page_offset;
 521 
 522         memset(&ops, 0, sizeof(ops));
 523         ops.oobbuf = buf;
 524         ops.ooboffs = chip->badblockpos;
 525         if (chip->options & NAND_BUSWIDTH_16) {
 526                 ops.ooboffs &= ~0x01;
 527                 ops.len = ops.ooblen = 2;
 528         } else {
 529                 ops.len = ops.ooblen = 1;
 530         }
 531         ops.mode = MTD_OPS_PLACE_OOB;
 532 
 533         page_offset = nand_bbm_get_next_page(chip, 0);
 534 
 535         while (page_offset >= 0) {
 536                 res = nand_do_write_oob(chip,
 537                                         ofs + (page_offset * mtd->writesize),
 538                                         &ops);
 539 
 540                 if (!ret)
 541                         ret = res;
 542 
 543                 page_offset = nand_bbm_get_next_page(chip, page_offset + 1);
 544         }
 545 
 546         return ret;
 547 }
 548 
 549 /**
 550  * nand_markbad_bbm - mark a block by updating the BBM
 551  * @chip: NAND chip object
 552  * @ofs: offset of the block to mark bad
 553  */
 554 int nand_markbad_bbm(struct nand_chip *chip, loff_t ofs)
 555 {
 556         if (chip->legacy.block_markbad)
 557                 return chip->legacy.block_markbad(chip, ofs);
 558 
 559         return nand_default_block_markbad(chip, ofs);
 560 }
 561 
 562 /**
 563  * nand_block_markbad_lowlevel - mark a block bad
 564  * @chip: NAND chip object
 565  * @ofs: offset from device start
 566  *
 567  * This function performs the generic NAND bad block marking steps (i.e., bad
 568  * block table(s) and/or marker(s)). We only allow the hardware driver to
 569  * specify how to write bad block markers to OOB (chip->legacy.block_markbad).
 570  *
 571  * We try operations in the following order:
 572  *
 573  *  (1) erase the affected block, to allow OOB marker to be written cleanly
 574  *  (2) write bad block marker to OOB area of affected block (unless flag
 575  *      NAND_BBT_NO_OOB_BBM is present)
 576  *  (3) update the BBT
 577  *
 578  * Note that we retain the first error encountered in (2) or (3), finish the
 579  * procedures, and dump the error in the end.
 580 */
 581 static int nand_block_markbad_lowlevel(struct nand_chip *chip, loff_t ofs)
 582 {
 583         struct mtd_info *mtd = nand_to_mtd(chip);
 584         int res, ret = 0;
 585 
 586         if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
 587                 struct erase_info einfo;
 588 
 589                 /* Attempt erase before marking OOB */
 590                 memset(&einfo, 0, sizeof(einfo));
 591                 einfo.addr = ofs;
 592                 einfo.len = 1ULL << chip->phys_erase_shift;
 593                 nand_erase_nand(chip, &einfo, 0);
 594 
 595                 /* Write bad block marker to OOB */
 596                 ret = nand_get_device(chip);
 597                 if (ret)
 598                         return ret;
 599 
 600                 ret = nand_markbad_bbm(chip, ofs);
 601                 nand_release_device(chip);
 602         }
 603 
 604         /* Mark block bad in BBT */
 605         if (chip->bbt) {
 606                 res = nand_markbad_bbt(chip, ofs);
 607                 if (!ret)
 608                         ret = res;
 609         }
 610 
 611         if (!ret)
 612                 mtd->ecc_stats.badblocks++;
 613 
 614         return ret;
 615 }
 616 
 617 /**
 618  * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
 619  * @mtd: MTD device structure
 620  * @ofs: offset from device start
 621  *
 622  * Check if the block is marked as reserved.
 623  */
 624 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
 625 {
 626         struct nand_chip *chip = mtd_to_nand(mtd);
 627 
 628         if (!chip->bbt)
 629                 return 0;
 630         /* Return info from the table */
 631         return nand_isreserved_bbt(chip, ofs);
 632 }
 633 
 634 /**
 635  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 636  * @chip: NAND chip object
 637  * @ofs: offset from device start
 638  * @allowbbt: 1, if its allowed to access the bbt area
 639  *
 640  * Check, if the block is bad. Either by reading the bad block table or
 641  * calling of the scan function.
 642  */
 643 static int nand_block_checkbad(struct nand_chip *chip, loff_t ofs, int allowbbt)
 644 {
 645         /* Return info from the table */
 646         if (chip->bbt)
 647                 return nand_isbad_bbt(chip, ofs, allowbbt);
 648 
 649         return nand_isbad_bbm(chip, ofs);
 650 }
 651 
 652 /**
 653  * nand_soft_waitrdy - Poll STATUS reg until RDY bit is set to 1
 654  * @chip: NAND chip structure
 655  * @timeout_ms: Timeout in ms
 656  *
 657  * Poll the STATUS register using ->exec_op() until the RDY bit becomes 1.
 658  * If that does not happen whitin the specified timeout, -ETIMEDOUT is
 659  * returned.
 660  *
 661  * This helper is intended to be used when the controller does not have access
 662  * to the NAND R/B pin.
 663  *
 664  * Be aware that calling this helper from an ->exec_op() implementation means
 665  * ->exec_op() must be re-entrant.
 666  *
 667  * Return 0 if the NAND chip is ready, a negative error otherwise.
 668  */
 669 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms)
 670 {
 671         const struct nand_sdr_timings *timings;
 672         u8 status = 0;
 673         int ret;
 674 
 675         if (!nand_has_exec_op(chip))
 676                 return -ENOTSUPP;
 677 
 678         /* Wait tWB before polling the STATUS reg. */
 679         timings = nand_get_sdr_timings(&chip->data_interface);
 680         ndelay(PSEC_TO_NSEC(timings->tWB_max));
 681 
 682         ret = nand_status_op(chip, NULL);
 683         if (ret)
 684                 return ret;
 685 
 686         timeout_ms = jiffies + msecs_to_jiffies(timeout_ms);
 687         do {
 688                 ret = nand_read_data_op(chip, &status, sizeof(status), true);
 689                 if (ret)
 690                         break;
 691 
 692                 if (status & NAND_STATUS_READY)
 693                         break;
 694 
 695                 /*
 696                  * Typical lowest execution time for a tR on most NANDs is 10us,
 697                  * use this as polling delay before doing something smarter (ie.
 698                  * deriving a delay from the timeout value, timeout_ms/ratio).
 699                  */
 700                 udelay(10);
 701         } while (time_before(jiffies, timeout_ms));
 702 
 703         /*
 704          * We have to exit READ_STATUS mode in order to read real data on the
 705          * bus in case the WAITRDY instruction is preceding a DATA_IN
 706          * instruction.
 707          */
 708         nand_exit_status_op(chip);
 709 
 710         if (ret)
 711                 return ret;
 712 
 713         return status & NAND_STATUS_READY ? 0 : -ETIMEDOUT;
 714 };
 715 EXPORT_SYMBOL_GPL(nand_soft_waitrdy);
 716 
 717 /**
 718  * nand_gpio_waitrdy - Poll R/B GPIO pin until ready
 719  * @chip: NAND chip structure
 720  * @gpiod: GPIO descriptor of R/B pin
 721  * @timeout_ms: Timeout in ms
 722  *
 723  * Poll the R/B GPIO pin until it becomes ready. If that does not happen
 724  * whitin the specified timeout, -ETIMEDOUT is returned.
 725  *
 726  * This helper is intended to be used when the controller has access to the
 727  * NAND R/B pin over GPIO.
 728  *
 729  * Return 0 if the R/B pin indicates chip is ready, a negative error otherwise.
 730  */
 731 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
 732                       unsigned long timeout_ms)
 733 {
 734         /* Wait until R/B pin indicates chip is ready or timeout occurs */
 735         timeout_ms = jiffies + msecs_to_jiffies(timeout_ms);
 736         do {
 737                 if (gpiod_get_value_cansleep(gpiod))
 738                         return 0;
 739 
 740                 cond_resched();
 741         } while (time_before(jiffies, timeout_ms));
 742 
 743         return gpiod_get_value_cansleep(gpiod) ? 0 : -ETIMEDOUT;
 744 };
 745 EXPORT_SYMBOL_GPL(nand_gpio_waitrdy);
 746 
 747 /**
 748  * panic_nand_wait - [GENERIC] wait until the command is done
 749  * @chip: NAND chip structure
 750  * @timeo: timeout
 751  *
 752  * Wait for command done. This is a helper function for nand_wait used when
 753  * we are in interrupt context. May happen when in panic and trying to write
 754  * an oops through mtdoops.
 755  */
 756 void panic_nand_wait(struct nand_chip *chip, unsigned long timeo)
 757 {
 758         int i;
 759         for (i = 0; i < timeo; i++) {
 760                 if (chip->legacy.dev_ready) {
 761                         if (chip->legacy.dev_ready(chip))
 762                                 break;
 763                 } else {
 764                         int ret;
 765                         u8 status;
 766 
 767                         ret = nand_read_data_op(chip, &status, sizeof(status),
 768                                                 true);
 769                         if (ret)
 770                                 return;
 771 
 772                         if (status & NAND_STATUS_READY)
 773                                 break;
 774                 }
 775                 mdelay(1);
 776         }
 777 }
 778 
 779 static bool nand_supports_get_features(struct nand_chip *chip, int addr)
 780 {
 781         return (chip->parameters.supports_set_get_features &&
 782                 test_bit(addr, chip->parameters.get_feature_list));
 783 }
 784 
 785 static bool nand_supports_set_features(struct nand_chip *chip, int addr)
 786 {
 787         return (chip->parameters.supports_set_get_features &&
 788                 test_bit(addr, chip->parameters.set_feature_list));
 789 }
 790 
 791 /**
 792  * nand_reset_data_interface - Reset data interface and timings
 793  * @chip: The NAND chip
 794  * @chipnr: Internal die id
 795  *
 796  * Reset the Data interface and timings to ONFI mode 0.
 797  *
 798  * Returns 0 for success or negative error code otherwise.
 799  */
 800 static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
 801 {
 802         int ret;
 803 
 804         if (!nand_has_setup_data_iface(chip))
 805                 return 0;
 806 
 807         /*
 808          * The ONFI specification says:
 809          * "
 810          * To transition from NV-DDR or NV-DDR2 to the SDR data
 811          * interface, the host shall use the Reset (FFh) command
 812          * using SDR timing mode 0. A device in any timing mode is
 813          * required to recognize Reset (FFh) command issued in SDR
 814          * timing mode 0.
 815          * "
 816          *
 817          * Configure the data interface in SDR mode and set the
 818          * timings to timing mode 0.
 819          */
 820 
 821         onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0);
 822         ret = chip->controller->ops->setup_data_interface(chip, chipnr,
 823                                                         &chip->data_interface);
 824         if (ret)
 825                 pr_err("Failed to configure data interface to SDR timing mode 0\n");
 826 
 827         return ret;
 828 }
 829 
 830 /**
 831  * nand_setup_data_interface - Setup the best data interface and timings
 832  * @chip: The NAND chip
 833  * @chipnr: Internal die id
 834  *
 835  * Find and configure the best data interface and NAND timings supported by
 836  * the chip and the driver.
 837  * First tries to retrieve supported timing modes from ONFI information,
 838  * and if the NAND chip does not support ONFI, relies on the
 839  * ->onfi_timing_mode_default specified in the nand_ids table.
 840  *
 841  * Returns 0 for success or negative error code otherwise.
 842  */
 843 static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
 844 {
 845         u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
 846                 chip->onfi_timing_mode_default,
 847         };
 848         int ret;
 849 
 850         if (!nand_has_setup_data_iface(chip))
 851                 return 0;
 852 
 853         /* Change the mode on the chip side (if supported by the NAND chip) */
 854         if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) {
 855                 nand_select_target(chip, chipnr);
 856                 ret = nand_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,
 857                                         tmode_param);
 858                 nand_deselect_target(chip);
 859                 if (ret)
 860                         return ret;
 861         }
 862 
 863         /* Change the mode on the controller side */
 864         ret = chip->controller->ops->setup_data_interface(chip, chipnr,
 865                                                         &chip->data_interface);
 866         if (ret)
 867                 return ret;
 868 
 869         /* Check the mode has been accepted by the chip, if supported */
 870         if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE))
 871                 return 0;
 872 
 873         memset(tmode_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
 874         nand_select_target(chip, chipnr);
 875         ret = nand_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,
 876                                 tmode_param);
 877         nand_deselect_target(chip);
 878         if (ret)
 879                 goto err_reset_chip;
 880 
 881         if (tmode_param[0] != chip->onfi_timing_mode_default) {
 882                 pr_warn("timing mode %d not acknowledged by the NAND chip\n",
 883                         chip->onfi_timing_mode_default);
 884                 goto err_reset_chip;
 885         }
 886 
 887         return 0;
 888 
 889 err_reset_chip:
 890         /*
 891          * Fallback to mode 0 if the chip explicitly did not ack the chosen
 892          * timing mode.
 893          */
 894         nand_reset_data_interface(chip, chipnr);
 895         nand_select_target(chip, chipnr);
 896         nand_reset_op(chip);
 897         nand_deselect_target(chip);
 898 
 899         return ret;
 900 }
 901 
 902 /**
 903  * nand_init_data_interface - find the best data interface and timings
 904  * @chip: The NAND chip
 905  *
 906  * Find the best data interface and NAND timings supported by the chip
 907  * and the driver.
 908  * First tries to retrieve supported timing modes from ONFI information,
 909  * and if the NAND chip does not support ONFI, relies on the
 910  * ->onfi_timing_mode_default specified in the nand_ids table. After this
 911  * function nand_chip->data_interface is initialized with the best timing mode
 912  * available.
 913  *
 914  * Returns 0 for success or negative error code otherwise.
 915  */
 916 static int nand_init_data_interface(struct nand_chip *chip)
 917 {
 918         int modes, mode, ret;
 919 
 920         if (!nand_has_setup_data_iface(chip))
 921                 return 0;
 922 
 923         /*
 924          * First try to identify the best timings from ONFI parameters and
 925          * if the NAND does not support ONFI, fallback to the default ONFI
 926          * timing mode.
 927          */
 928         if (chip->parameters.onfi) {
 929                 modes = chip->parameters.onfi->async_timing_mode;
 930         } else {
 931                 if (!chip->onfi_timing_mode_default)
 932                         return 0;
 933 
 934                 modes = GENMASK(chip->onfi_timing_mode_default, 0);
 935         }
 936 
 937         for (mode = fls(modes) - 1; mode >= 0; mode--) {
 938                 ret = onfi_fill_data_interface(chip, NAND_SDR_IFACE, mode);
 939                 if (ret)
 940                         continue;
 941 
 942                 /*
 943                  * Pass NAND_DATA_IFACE_CHECK_ONLY to only check if the
 944                  * controller supports the requested timings.
 945                  */
 946                 ret = chip->controller->ops->setup_data_interface(chip,
 947                                                  NAND_DATA_IFACE_CHECK_ONLY,
 948                                                  &chip->data_interface);
 949                 if (!ret) {
 950                         chip->onfi_timing_mode_default = mode;
 951                         break;
 952                 }
 953         }
 954 
 955         return 0;
 956 }
 957 
 958 /**
 959  * nand_fill_column_cycles - fill the column cycles of an address
 960  * @chip: The NAND chip
 961  * @addrs: Array of address cycles to fill
 962  * @offset_in_page: The offset in the page
 963  *
 964  * Fills the first or the first two bytes of the @addrs field depending
 965  * on the NAND bus width and the page size.
 966  *
 967  * Returns the number of cycles needed to encode the column, or a negative
 968  * error code in case one of the arguments is invalid.
 969  */
 970 static int nand_fill_column_cycles(struct nand_chip *chip, u8 *addrs,
 971                                    unsigned int offset_in_page)
 972 {
 973         struct mtd_info *mtd = nand_to_mtd(chip);
 974 
 975         /* Make sure the offset is less than the actual page size. */
 976         if (offset_in_page > mtd->writesize + mtd->oobsize)
 977                 return -EINVAL;
 978 
 979         /*
 980          * On small page NANDs, there's a dedicated command to access the OOB
 981          * area, and the column address is relative to the start of the OOB
 982          * area, not the start of the page. Asjust the address accordingly.
 983          */
 984         if (mtd->writesize <= 512 && offset_in_page >= mtd->writesize)
 985                 offset_in_page -= mtd->writesize;
 986 
 987         /*
 988          * The offset in page is expressed in bytes, if the NAND bus is 16-bit
 989          * wide, then it must be divided by 2.
 990          */
 991         if (chip->options & NAND_BUSWIDTH_16) {
 992                 if (WARN_ON(offset_in_page % 2))
 993                         return -EINVAL;
 994 
 995                 offset_in_page /= 2;
 996         }
 997 
 998         addrs[0] = offset_in_page;
 999 
1000         /*
1001          * Small page NANDs use 1 cycle for the columns, while large page NANDs
1002          * need 2
1003          */
1004         if (mtd->writesize <= 512)
1005                 return 1;
1006 
1007         addrs[1] = offset_in_page >> 8;
1008 
1009         return 2;
1010 }
1011 
1012 static int nand_sp_exec_read_page_op(struct nand_chip *chip, unsigned int page,
1013                                      unsigned int offset_in_page, void *buf,
1014                                      unsigned int len)
1015 {
1016         struct mtd_info *mtd = nand_to_mtd(chip);
1017         const struct nand_sdr_timings *sdr =
1018                 nand_get_sdr_timings(&chip->data_interface);
1019         u8 addrs[4];
1020         struct nand_op_instr instrs[] = {
1021                 NAND_OP_CMD(NAND_CMD_READ0, 0),
1022                 NAND_OP_ADDR(3, addrs, PSEC_TO_NSEC(sdr->tWB_max)),
1023                 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max),
1024                                  PSEC_TO_NSEC(sdr->tRR_min)),
1025                 NAND_OP_DATA_IN(len, buf, 0),
1026         };
1027         struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1028         int ret;
1029 
1030         /* Drop the DATA_IN instruction if len is set to 0. */
1031         if (!len)
1032                 op.ninstrs--;
1033 
1034         if (offset_in_page >= mtd->writesize)
1035                 instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB;
1036         else if (offset_in_page >= 256 &&
1037                  !(chip->options & NAND_BUSWIDTH_16))
1038                 instrs[0].ctx.cmd.opcode = NAND_CMD_READ1;
1039 
1040         ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1041         if (ret < 0)
1042                 return ret;
1043 
1044         addrs[1] = page;
1045         addrs[2] = page >> 8;
1046 
1047         if (chip->options & NAND_ROW_ADDR_3) {
1048                 addrs[3] = page >> 16;
1049                 instrs[1].ctx.addr.naddrs++;
1050         }
1051 
1052         return nand_exec_op(chip, &op);
1053 }
1054 
1055 static int nand_lp_exec_read_page_op(struct nand_chip *chip, unsigned int page,
1056                                      unsigned int offset_in_page, void *buf,
1057                                      unsigned int len)
1058 {
1059         const struct nand_sdr_timings *sdr =
1060                 nand_get_sdr_timings(&chip->data_interface);
1061         u8 addrs[5];
1062         struct nand_op_instr instrs[] = {
1063                 NAND_OP_CMD(NAND_CMD_READ0, 0),
1064                 NAND_OP_ADDR(4, addrs, 0),
1065                 NAND_OP_CMD(NAND_CMD_READSTART, PSEC_TO_NSEC(sdr->tWB_max)),
1066                 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max),
1067                                  PSEC_TO_NSEC(sdr->tRR_min)),
1068                 NAND_OP_DATA_IN(len, buf, 0),
1069         };
1070         struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1071         int ret;
1072 
1073         /* Drop the DATA_IN instruction if len is set to 0. */
1074         if (!len)
1075                 op.ninstrs--;
1076 
1077         ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1078         if (ret < 0)
1079                 return ret;
1080 
1081         addrs[2] = page;
1082         addrs[3] = page >> 8;
1083 
1084         if (chip->options & NAND_ROW_ADDR_3) {
1085                 addrs[4] = page >> 16;
1086                 instrs[1].ctx.addr.naddrs++;
1087         }
1088 
1089         return nand_exec_op(chip, &op);
1090 }
1091 
1092 /**
1093  * nand_read_page_op - Do a READ PAGE operation
1094  * @chip: The NAND chip
1095  * @page: page to read
1096  * @offset_in_page: offset within the page
1097  * @buf: buffer used to store the data
1098  * @len: length of the buffer
1099  *
1100  * This function issues a READ PAGE operation.
1101  * This function does not select/unselect the CS line.
1102  *
1103  * Returns 0 on success, a negative error code otherwise.
1104  */
1105 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1106                       unsigned int offset_in_page, void *buf, unsigned int len)
1107 {
1108         struct mtd_info *mtd = nand_to_mtd(chip);
1109 
1110         if (len && !buf)
1111                 return -EINVAL;
1112 
1113         if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1114                 return -EINVAL;
1115 
1116         if (nand_has_exec_op(chip)) {
1117                 if (mtd->writesize > 512)
1118                         return nand_lp_exec_read_page_op(chip, page,
1119                                                          offset_in_page, buf,
1120                                                          len);
1121 
1122                 return nand_sp_exec_read_page_op(chip, page, offset_in_page,
1123                                                  buf, len);
1124         }
1125 
1126         chip->legacy.cmdfunc(chip, NAND_CMD_READ0, offset_in_page, page);
1127         if (len)
1128                 chip->legacy.read_buf(chip, buf, len);
1129 
1130         return 0;
1131 }
1132 EXPORT_SYMBOL_GPL(nand_read_page_op);
1133 
1134 /**
1135  * nand_read_param_page_op - Do a READ PARAMETER PAGE operation
1136  * @chip: The NAND chip
1137  * @page: parameter page to read
1138  * @buf: buffer used to store the data
1139  * @len: length of the buffer
1140  *
1141  * This function issues a READ PARAMETER PAGE operation.
1142  * This function does not select/unselect the CS line.
1143  *
1144  * Returns 0 on success, a negative error code otherwise.
1145  */
1146 int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
1147                             unsigned int len)
1148 {
1149         unsigned int i;
1150         u8 *p = buf;
1151 
1152         if (len && !buf)
1153                 return -EINVAL;
1154 
1155         if (nand_has_exec_op(chip)) {
1156                 const struct nand_sdr_timings *sdr =
1157                         nand_get_sdr_timings(&chip->data_interface);
1158                 struct nand_op_instr instrs[] = {
1159                         NAND_OP_CMD(NAND_CMD_PARAM, 0),
1160                         NAND_OP_ADDR(1, &page, PSEC_TO_NSEC(sdr->tWB_max)),
1161                         NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max),
1162                                          PSEC_TO_NSEC(sdr->tRR_min)),
1163                         NAND_OP_8BIT_DATA_IN(len, buf, 0),
1164                 };
1165                 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1166 
1167                 /* Drop the DATA_IN instruction if len is set to 0. */
1168                 if (!len)
1169                         op.ninstrs--;
1170 
1171                 return nand_exec_op(chip, &op);
1172         }
1173 
1174         chip->legacy.cmdfunc(chip, NAND_CMD_PARAM, page, -1);
1175         for (i = 0; i < len; i++)
1176                 p[i] = chip->legacy.read_byte(chip);
1177 
1178         return 0;
1179 }
1180 
1181 /**
1182  * nand_change_read_column_op - Do a CHANGE READ COLUMN operation
1183  * @chip: The NAND chip
1184  * @offset_in_page: offset within the page
1185  * @buf: buffer used to store the data
1186  * @len: length of the buffer
1187  * @force_8bit: force 8-bit bus access
1188  *
1189  * This function issues a CHANGE READ COLUMN operation.
1190  * This function does not select/unselect the CS line.
1191  *
1192  * Returns 0 on success, a negative error code otherwise.
1193  */
1194 int nand_change_read_column_op(struct nand_chip *chip,
1195                                unsigned int offset_in_page, void *buf,
1196                                unsigned int len, bool force_8bit)
1197 {
1198         struct mtd_info *mtd = nand_to_mtd(chip);
1199 
1200         if (len && !buf)
1201                 return -EINVAL;
1202 
1203         if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1204                 return -EINVAL;
1205 
1206         /* Small page NANDs do not support column change. */
1207         if (mtd->writesize <= 512)
1208                 return -ENOTSUPP;
1209 
1210         if (nand_has_exec_op(chip)) {
1211                 const struct nand_sdr_timings *sdr =
1212                         nand_get_sdr_timings(&chip->data_interface);
1213                 u8 addrs[2] = {};
1214                 struct nand_op_instr instrs[] = {
1215                         NAND_OP_CMD(NAND_CMD_RNDOUT, 0),
1216                         NAND_OP_ADDR(2, addrs, 0),
1217                         NAND_OP_CMD(NAND_CMD_RNDOUTSTART,
1218                                     PSEC_TO_NSEC(sdr->tCCS_min)),
1219                         NAND_OP_DATA_IN(len, buf, 0),
1220                 };
1221                 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1222                 int ret;
1223 
1224                 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1225                 if (ret < 0)
1226                         return ret;
1227 
1228                 /* Drop the DATA_IN instruction if len is set to 0. */
1229                 if (!len)
1230                         op.ninstrs--;
1231 
1232                 instrs[3].ctx.data.force_8bit = force_8bit;
1233 
1234                 return nand_exec_op(chip, &op);
1235         }
1236 
1237         chip->legacy.cmdfunc(chip, NAND_CMD_RNDOUT, offset_in_page, -1);
1238         if (len)
1239                 chip->legacy.read_buf(chip, buf, len);
1240 
1241         return 0;
1242 }
1243 EXPORT_SYMBOL_GPL(nand_change_read_column_op);
1244 
1245 /**
1246  * nand_read_oob_op - Do a READ OOB operation
1247  * @chip: The NAND chip
1248  * @page: page to read
1249  * @offset_in_oob: offset within the OOB area
1250  * @buf: buffer used to store the data
1251  * @len: length of the buffer
1252  *
1253  * This function issues a READ OOB operation.
1254  * This function does not select/unselect the CS line.
1255  *
1256  * Returns 0 on success, a negative error code otherwise.
1257  */
1258 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1259                      unsigned int offset_in_oob, void *buf, unsigned int len)
1260 {
1261         struct mtd_info *mtd = nand_to_mtd(chip);
1262 
1263         if (len && !buf)
1264                 return -EINVAL;
1265 
1266         if (offset_in_oob + len > mtd->oobsize)
1267                 return -EINVAL;
1268 
1269         if (nand_has_exec_op(chip))
1270                 return nand_read_page_op(chip, page,
1271                                          mtd->writesize + offset_in_oob,
1272                                          buf, len);
1273 
1274         chip->legacy.cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page);
1275         if (len)
1276                 chip->legacy.read_buf(chip, buf, len);
1277 
1278         return 0;
1279 }
1280 EXPORT_SYMBOL_GPL(nand_read_oob_op);
1281 
1282 static int nand_exec_prog_page_op(struct nand_chip *chip, unsigned int page,
1283                                   unsigned int offset_in_page, const void *buf,
1284                                   unsigned int len, bool prog)
1285 {
1286         struct mtd_info *mtd = nand_to_mtd(chip);
1287         const struct nand_sdr_timings *sdr =
1288                 nand_get_sdr_timings(&chip->data_interface);
1289         u8 addrs[5] = {};
1290         struct nand_op_instr instrs[] = {
1291                 /*
1292                  * The first instruction will be dropped if we're dealing
1293                  * with a large page NAND and adjusted if we're dealing
1294                  * with a small page NAND and the page offset is > 255.
1295                  */
1296                 NAND_OP_CMD(NAND_CMD_READ0, 0),
1297                 NAND_OP_CMD(NAND_CMD_SEQIN, 0),
1298                 NAND_OP_ADDR(0, addrs, PSEC_TO_NSEC(sdr->tADL_min)),
1299                 NAND_OP_DATA_OUT(len, buf, 0),
1300                 NAND_OP_CMD(NAND_CMD_PAGEPROG, PSEC_TO_NSEC(sdr->tWB_max)),
1301                 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tPROG_max), 0),
1302         };
1303         struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1304         int naddrs = nand_fill_column_cycles(chip, addrs, offset_in_page);
1305         int ret;
1306         u8 status;
1307 
1308         if (naddrs < 0)
1309                 return naddrs;
1310 
1311         addrs[naddrs++] = page;
1312         addrs[naddrs++] = page >> 8;
1313         if (chip->options & NAND_ROW_ADDR_3)
1314                 addrs[naddrs++] = page >> 16;
1315 
1316         instrs[2].ctx.addr.naddrs = naddrs;
1317 
1318         /* Drop the last two instructions if we're not programming the page. */
1319         if (!prog) {
1320                 op.ninstrs -= 2;
1321                 /* Also drop the DATA_OUT instruction if empty. */
1322                 if (!len)
1323                         op.ninstrs--;
1324         }
1325 
1326         if (mtd->writesize <= 512) {
1327                 /*
1328                  * Small pages need some more tweaking: we have to adjust the
1329                  * first instruction depending on the page offset we're trying
1330                  * to access.
1331                  */
1332                 if (offset_in_page >= mtd->writesize)
1333                         instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB;
1334                 else if (offset_in_page >= 256 &&
1335                          !(chip->options & NAND_BUSWIDTH_16))
1336                         instrs[0].ctx.cmd.opcode = NAND_CMD_READ1;
1337         } else {
1338                 /*
1339                  * Drop the first command if we're dealing with a large page
1340                  * NAND.
1341                  */
1342                 op.instrs++;
1343                 op.ninstrs--;
1344         }
1345 
1346         ret = nand_exec_op(chip, &op);
1347         if (!prog || ret)
1348                 return ret;
1349 
1350         ret = nand_status_op(chip, &status);
1351         if (ret)
1352                 return ret;
1353 
1354         return status;
1355 }
1356 
1357 /**
1358  * nand_prog_page_begin_op - starts a PROG PAGE operation
1359  * @chip: The NAND chip
1360  * @page: page to write
1361  * @offset_in_page: offset within the page
1362  * @buf: buffer containing the data to write to the page
1363  * @len: length of the buffer
1364  *
1365  * This function issues the first half of a PROG PAGE operation.
1366  * This function does not select/unselect the CS line.
1367  *
1368  * Returns 0 on success, a negative error code otherwise.
1369  */
1370 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1371                             unsigned int offset_in_page, const void *buf,
1372                             unsigned int len)
1373 {
1374         struct mtd_info *mtd = nand_to_mtd(chip);
1375 
1376         if (len && !buf)
1377                 return -EINVAL;
1378 
1379         if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1380                 return -EINVAL;
1381 
1382         if (nand_has_exec_op(chip))
1383                 return nand_exec_prog_page_op(chip, page, offset_in_page, buf,
1384                                               len, false);
1385 
1386         chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, page);
1387 
1388         if (buf)
1389                 chip->legacy.write_buf(chip, buf, len);
1390 
1391         return 0;
1392 }
1393 EXPORT_SYMBOL_GPL(nand_prog_page_begin_op);
1394 
1395 /**
1396  * nand_prog_page_end_op - ends a PROG PAGE operation
1397  * @chip: The NAND chip
1398  *
1399  * This function issues the second half of a PROG PAGE operation.
1400  * This function does not select/unselect the CS line.
1401  *
1402  * Returns 0 on success, a negative error code otherwise.
1403  */
1404 int nand_prog_page_end_op(struct nand_chip *chip)
1405 {
1406         int ret;
1407         u8 status;
1408 
1409         if (nand_has_exec_op(chip)) {
1410                 const struct nand_sdr_timings *sdr =
1411                         nand_get_sdr_timings(&chip->data_interface);
1412                 struct nand_op_instr instrs[] = {
1413                         NAND_OP_CMD(NAND_CMD_PAGEPROG,
1414                                     PSEC_TO_NSEC(sdr->tWB_max)),
1415                         NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tPROG_max), 0),
1416                 };
1417                 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1418 
1419                 ret = nand_exec_op(chip, &op);
1420                 if (ret)
1421                         return ret;
1422 
1423                 ret = nand_status_op(chip, &status);
1424                 if (ret)
1425                         return ret;
1426         } else {
1427                 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
1428                 ret = chip->legacy.waitfunc(chip);
1429                 if (ret < 0)
1430                         return ret;
1431 
1432                 status = ret;
1433         }
1434 
1435         if (status & NAND_STATUS_FAIL)
1436                 return -EIO;
1437 
1438         return 0;
1439 }
1440 EXPORT_SYMBOL_GPL(nand_prog_page_end_op);
1441 
1442 /**
1443  * nand_prog_page_op - Do a full PROG PAGE operation
1444  * @chip: The NAND chip
1445  * @page: page to write
1446  * @offset_in_page: offset within the page
1447  * @buf: buffer containing the data to write to the page
1448  * @len: length of the buffer
1449  *
1450  * This function issues a full PROG PAGE operation.
1451  * This function does not select/unselect the CS line.
1452  *
1453  * Returns 0 on success, a negative error code otherwise.
1454  */
1455 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1456                       unsigned int offset_in_page, const void *buf,
1457                       unsigned int len)
1458 {
1459         struct mtd_info *mtd = nand_to_mtd(chip);
1460         int status;
1461 
1462         if (!len || !buf)
1463                 return -EINVAL;
1464 
1465         if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1466                 return -EINVAL;
1467 
1468         if (nand_has_exec_op(chip)) {
1469                 status = nand_exec_prog_page_op(chip, page, offset_in_page, buf,
1470                                                 len, true);
1471         } else {
1472                 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page,
1473                                      page);
1474                 chip->legacy.write_buf(chip, buf, len);
1475                 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
1476                 status = chip->legacy.waitfunc(chip);
1477         }
1478 
1479         if (status & NAND_STATUS_FAIL)
1480                 return -EIO;
1481 
1482         return 0;
1483 }
1484 EXPORT_SYMBOL_GPL(nand_prog_page_op);
1485 
1486 /**
1487  * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation
1488  * @chip: The NAND chip
1489  * @offset_in_page: offset within the page
1490  * @buf: buffer containing the data to send to the NAND
1491  * @len: length of the buffer
1492  * @force_8bit: force 8-bit bus access
1493  *
1494  * This function issues a CHANGE WRITE COLUMN operation.
1495  * This function does not select/unselect the CS line.
1496  *
1497  * Returns 0 on success, a negative error code otherwise.
1498  */
1499 int nand_change_write_column_op(struct nand_chip *chip,
1500                                 unsigned int offset_in_page,
1501                                 const void *buf, unsigned int len,
1502                                 bool force_8bit)
1503 {
1504         struct mtd_info *mtd = nand_to_mtd(chip);
1505 
1506         if (len && !buf)
1507                 return -EINVAL;
1508 
1509         if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1510                 return -EINVAL;
1511 
1512         /* Small page NANDs do not support column change. */
1513         if (mtd->writesize <= 512)
1514                 return -ENOTSUPP;
1515 
1516         if (nand_has_exec_op(chip)) {
1517                 const struct nand_sdr_timings *sdr =
1518                         nand_get_sdr_timings(&chip->data_interface);
1519                 u8 addrs[2];
1520                 struct nand_op_instr instrs[] = {
1521                         NAND_OP_CMD(NAND_CMD_RNDIN, 0),
1522                         NAND_OP_ADDR(2, addrs, PSEC_TO_NSEC(sdr->tCCS_min)),
1523                         NAND_OP_DATA_OUT(len, buf, 0),
1524                 };
1525                 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1526                 int ret;
1527 
1528                 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1529                 if (ret < 0)
1530                         return ret;
1531 
1532                 instrs[2].ctx.data.force_8bit = force_8bit;
1533 
1534                 /* Drop the DATA_OUT instruction if len is set to 0. */
1535                 if (!len)
1536                         op.ninstrs--;
1537 
1538                 return nand_exec_op(chip, &op);
1539         }
1540 
1541         chip->legacy.cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1);
1542         if (len)
1543                 chip->legacy.write_buf(chip, buf, len);
1544 
1545         return 0;
1546 }
1547 EXPORT_SYMBOL_GPL(nand_change_write_column_op);
1548 
1549 /**
1550  * nand_readid_op - Do a READID operation
1551  * @chip: The NAND chip
1552  * @addr: address cycle to pass after the READID command
1553  * @buf: buffer used to store the ID
1554  * @len: length of the buffer
1555  *
1556  * This function sends a READID command and reads back the ID returned by the
1557  * NAND.
1558  * This function does not select/unselect the CS line.
1559  *
1560  * Returns 0 on success, a negative error code otherwise.
1561  */
1562 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1563                    unsigned int len)
1564 {
1565         unsigned int i;
1566         u8 *id = buf;
1567 
1568         if (len && !buf)
1569                 return -EINVAL;
1570 
1571         if (nand_has_exec_op(chip)) {
1572                 const struct nand_sdr_timings *sdr =
1573                         nand_get_sdr_timings(&chip->data_interface);
1574                 struct nand_op_instr instrs[] = {
1575                         NAND_OP_CMD(NAND_CMD_READID, 0),
1576                         NAND_OP_ADDR(1, &addr, PSEC_TO_NSEC(sdr->tADL_min)),
1577                         NAND_OP_8BIT_DATA_IN(len, buf, 0),
1578                 };
1579                 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1580 
1581                 /* Drop the DATA_IN instruction if len is set to 0. */
1582                 if (!len)
1583                         op.ninstrs--;
1584 
1585                 return nand_exec_op(chip, &op);
1586         }
1587 
1588         chip->legacy.cmdfunc(chip, NAND_CMD_READID, addr, -1);
1589 
1590         for (i = 0; i < len; i++)
1591                 id[i] = chip->legacy.read_byte(chip);
1592 
1593         return 0;
1594 }
1595 EXPORT_SYMBOL_GPL(nand_readid_op);
1596 
1597 /**
1598  * nand_status_op - Do a STATUS operation
1599  * @chip: The NAND chip
1600  * @status: out variable to store the NAND status
1601  *
1602  * This function sends a STATUS command and reads back the status returned by
1603  * the NAND.
1604  * This function does not select/unselect the CS line.
1605  *
1606  * Returns 0 on success, a negative error code otherwise.
1607  */
1608 int nand_status_op(struct nand_chip *chip, u8 *status)
1609 {
1610         if (nand_has_exec_op(chip)) {
1611                 const struct nand_sdr_timings *sdr =
1612                         nand_get_sdr_timings(&chip->data_interface);
1613                 struct nand_op_instr instrs[] = {
1614                         NAND_OP_CMD(NAND_CMD_STATUS,
1615                                     PSEC_TO_NSEC(sdr->tADL_min)),
1616                         NAND_OP_8BIT_DATA_IN(1, status, 0),
1617                 };
1618                 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1619 
1620                 if (!status)
1621                         op.ninstrs--;
1622 
1623                 return nand_exec_op(chip, &op);
1624         }
1625 
1626         chip->legacy.cmdfunc(chip, NAND_CMD_STATUS, -1, -1);
1627         if (status)
1628                 *status = chip->legacy.read_byte(chip);
1629 
1630         return 0;
1631 }
1632 EXPORT_SYMBOL_GPL(nand_status_op);
1633 
1634 /**
1635  * nand_exit_status_op - Exit a STATUS operation
1636  * @chip: The NAND chip
1637  *
1638  * This function sends a READ0 command to cancel the effect of the STATUS
1639  * command to avoid reading only the status until a new read command is sent.
1640  *
1641  * This function does not select/unselect the CS line.
1642  *
1643  * Returns 0 on success, a negative error code otherwise.
1644  */
1645 int nand_exit_status_op(struct nand_chip *chip)
1646 {
1647         if (nand_has_exec_op(chip)) {
1648                 struct nand_op_instr instrs[] = {
1649                         NAND_OP_CMD(NAND_CMD_READ0, 0),
1650                 };
1651                 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1652 
1653                 return nand_exec_op(chip, &op);
1654         }
1655 
1656         chip->legacy.cmdfunc(chip, NAND_CMD_READ0, -1, -1);
1657 
1658         return 0;
1659 }
1660 
1661 /**
1662  * nand_erase_op - Do an erase operation
1663  * @chip: The NAND chip
1664  * @eraseblock: block to erase
1665  *
1666  * This function sends an ERASE command and waits for the NAND to be ready
1667  * before returning.
1668  * This function does not select/unselect the CS line.
1669  *
1670  * Returns 0 on success, a negative error code otherwise.
1671  */
1672 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
1673 {
1674         unsigned int page = eraseblock <<
1675                             (chip->phys_erase_shift - chip->page_shift);
1676         int ret;
1677         u8 status;
1678 
1679         if (nand_has_exec_op(chip)) {
1680                 const struct nand_sdr_timings *sdr =
1681                         nand_get_sdr_timings(&chip->data_interface);
1682                 u8 addrs[3] = { page, page >> 8, page >> 16 };
1683                 struct nand_op_instr instrs[] = {
1684                         NAND_OP_CMD(NAND_CMD_ERASE1, 0),
1685                         NAND_OP_ADDR(2, addrs, 0),
1686                         NAND_OP_CMD(NAND_CMD_ERASE2,
1687                                     PSEC_TO_MSEC(sdr->tWB_max)),
1688                         NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tBERS_max), 0),
1689                 };
1690                 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1691 
1692                 if (chip->options & NAND_ROW_ADDR_3)
1693                         instrs[1].ctx.addr.naddrs++;
1694 
1695                 ret = nand_exec_op(chip, &op);
1696                 if (ret)
1697                         return ret;
1698 
1699                 ret = nand_status_op(chip, &status);
1700                 if (ret)
1701                         return ret;
1702         } else {
1703                 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE1, -1, page);
1704                 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE2, -1, -1);
1705 
1706                 ret = chip->legacy.waitfunc(chip);
1707                 if (ret < 0)
1708                         return ret;
1709 
1710                 status = ret;
1711         }
1712 
1713         if (status & NAND_STATUS_FAIL)
1714                 return -EIO;
1715 
1716         return 0;
1717 }
1718 EXPORT_SYMBOL_GPL(nand_erase_op);
1719 
1720 /**
1721  * nand_set_features_op - Do a SET FEATURES operation
1722  * @chip: The NAND chip
1723  * @feature: feature id
1724  * @data: 4 bytes of data
1725  *
1726  * This function sends a SET FEATURES command and waits for the NAND to be
1727  * ready before returning.
1728  * This function does not select/unselect the CS line.
1729  *
1730  * Returns 0 on success, a negative error code otherwise.
1731  */
1732 static int nand_set_features_op(struct nand_chip *chip, u8 feature,
1733                                 const void *data)
1734 {
1735         const u8 *params = data;
1736         int i, ret;
1737 
1738         if (nand_has_exec_op(chip)) {
1739                 const struct nand_sdr_timings *sdr =
1740                         nand_get_sdr_timings(&chip->data_interface);
1741                 struct nand_op_instr instrs[] = {
1742                         NAND_OP_CMD(NAND_CMD_SET_FEATURES, 0),
1743                         NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tADL_min)),
1744                         NAND_OP_8BIT_DATA_OUT(ONFI_SUBFEATURE_PARAM_LEN, data,
1745                                               PSEC_TO_NSEC(sdr->tWB_max)),
1746                         NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tFEAT_max), 0),
1747                 };
1748                 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1749 
1750                 return nand_exec_op(chip, &op);
1751         }
1752 
1753         chip->legacy.cmdfunc(chip, NAND_CMD_SET_FEATURES, feature, -1);
1754         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1755                 chip->legacy.write_byte(chip, params[i]);
1756 
1757         ret = chip->legacy.waitfunc(chip);
1758         if (ret < 0)
1759                 return ret;
1760 
1761         if (ret & NAND_STATUS_FAIL)
1762                 return -EIO;
1763 
1764         return 0;
1765 }
1766 
1767 /**
1768  * nand_get_features_op - Do a GET FEATURES operation
1769  * @chip: The NAND chip
1770  * @feature: feature id
1771  * @data: 4 bytes of data
1772  *
1773  * This function sends a GET FEATURES command and waits for the NAND to be
1774  * ready before returning.
1775  * This function does not select/unselect the CS line.
1776  *
1777  * Returns 0 on success, a negative error code otherwise.
1778  */
1779 static int nand_get_features_op(struct nand_chip *chip, u8 feature,
1780                                 void *data)
1781 {
1782         u8 *params = data;
1783         int i;
1784 
1785         if (nand_has_exec_op(chip)) {
1786                 const struct nand_sdr_timings *sdr =
1787                         nand_get_sdr_timings(&chip->data_interface);
1788                 struct nand_op_instr instrs[] = {
1789                         NAND_OP_CMD(NAND_CMD_GET_FEATURES, 0),
1790                         NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tWB_max)),
1791                         NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tFEAT_max),
1792                                          PSEC_TO_NSEC(sdr->tRR_min)),
1793                         NAND_OP_8BIT_DATA_IN(ONFI_SUBFEATURE_PARAM_LEN,
1794                                              data, 0),
1795                 };
1796                 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1797 
1798                 return nand_exec_op(chip, &op);
1799         }
1800 
1801         chip->legacy.cmdfunc(chip, NAND_CMD_GET_FEATURES, feature, -1);
1802         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1803                 params[i] = chip->legacy.read_byte(chip);
1804 
1805         return 0;
1806 }
1807 
1808 static int nand_wait_rdy_op(struct nand_chip *chip, unsigned int timeout_ms,
1809                             unsigned int delay_ns)
1810 {
1811         if (nand_has_exec_op(chip)) {
1812                 struct nand_op_instr instrs[] = {
1813                         NAND_OP_WAIT_RDY(PSEC_TO_MSEC(timeout_ms),
1814                                          PSEC_TO_NSEC(delay_ns)),
1815                 };
1816                 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1817 
1818                 return nand_exec_op(chip, &op);
1819         }
1820 
1821         /* Apply delay or wait for ready/busy pin */
1822         if (!chip->legacy.dev_ready)
1823                 udelay(chip->legacy.chip_delay);
1824         else
1825                 nand_wait_ready(chip);
1826 
1827         return 0;
1828 }
1829 
1830 /**
1831  * nand_reset_op - Do a reset operation
1832  * @chip: The NAND chip
1833  *
1834  * This function sends a RESET command and waits for the NAND to be ready
1835  * before returning.
1836  * This function does not select/unselect the CS line.
1837  *
1838  * Returns 0 on success, a negative error code otherwise.
1839  */
1840 int nand_reset_op(struct nand_chip *chip)
1841 {
1842         if (nand_has_exec_op(chip)) {
1843                 const struct nand_sdr_timings *sdr =
1844                         nand_get_sdr_timings(&chip->data_interface);
1845                 struct nand_op_instr instrs[] = {
1846                         NAND_OP_CMD(NAND_CMD_RESET, PSEC_TO_NSEC(sdr->tWB_max)),
1847                         NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tRST_max), 0),
1848                 };
1849                 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1850 
1851                 return nand_exec_op(chip, &op);
1852         }
1853 
1854         chip->legacy.cmdfunc(chip, NAND_CMD_RESET, -1, -1);
1855 
1856         return 0;
1857 }
1858 EXPORT_SYMBOL_GPL(nand_reset_op);
1859 
1860 /**
1861  * nand_read_data_op - Read data from the NAND
1862  * @chip: The NAND chip
1863  * @buf: buffer used to store the data
1864  * @len: length of the buffer
1865  * @force_8bit: force 8-bit bus access
1866  *
1867  * This function does a raw data read on the bus. Usually used after launching
1868  * another NAND operation like nand_read_page_op().
1869  * This function does not select/unselect the CS line.
1870  *
1871  * Returns 0 on success, a negative error code otherwise.
1872  */
1873 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1874                       bool force_8bit)
1875 {
1876         if (!len || !buf)
1877                 return -EINVAL;
1878 
1879         if (nand_has_exec_op(chip)) {
1880                 struct nand_op_instr instrs[] = {
1881                         NAND_OP_DATA_IN(len, buf, 0),
1882                 };
1883                 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1884 
1885                 instrs[0].ctx.data.force_8bit = force_8bit;
1886 
1887                 return nand_exec_op(chip, &op);
1888         }
1889 
1890         if (force_8bit) {
1891                 u8 *p = buf;
1892                 unsigned int i;
1893 
1894                 for (i = 0; i < len; i++)
1895                         p[i] = chip->legacy.read_byte(chip);
1896         } else {
1897                 chip->legacy.read_buf(chip, buf, len);
1898         }
1899 
1900         return 0;
1901 }
1902 EXPORT_SYMBOL_GPL(nand_read_data_op);
1903 
1904 /**
1905  * nand_write_data_op - Write data from the NAND
1906  * @chip: The NAND chip
1907  * @buf: buffer containing the data to send on the bus
1908  * @len: length of the buffer
1909  * @force_8bit: force 8-bit bus access
1910  *
1911  * This function does a raw data write on the bus. Usually used after launching
1912  * another NAND operation like nand_write_page_begin_op().
1913  * This function does not select/unselect the CS line.
1914  *
1915  * Returns 0 on success, a negative error code otherwise.
1916  */
1917 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1918                        unsigned int len, bool force_8bit)
1919 {
1920         if (!len || !buf)
1921                 return -EINVAL;
1922 
1923         if (nand_has_exec_op(chip)) {
1924                 struct nand_op_instr instrs[] = {
1925                         NAND_OP_DATA_OUT(len, buf, 0),
1926                 };
1927                 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1928 
1929                 instrs[0].ctx.data.force_8bit = force_8bit;
1930 
1931                 return nand_exec_op(chip, &op);
1932         }
1933 
1934         if (force_8bit) {
1935                 const u8 *p = buf;
1936                 unsigned int i;
1937 
1938                 for (i = 0; i < len; i++)
1939                         chip->legacy.write_byte(chip, p[i]);
1940         } else {
1941                 chip->legacy.write_buf(chip, buf, len);
1942         }
1943 
1944         return 0;
1945 }
1946 EXPORT_SYMBOL_GPL(nand_write_data_op);
1947 
1948 /**
1949  * struct nand_op_parser_ctx - Context used by the parser
1950  * @instrs: array of all the instructions that must be addressed
1951  * @ninstrs: length of the @instrs array
1952  * @subop: Sub-operation to be passed to the NAND controller
1953  *
1954  * This structure is used by the core to split NAND operations into
1955  * sub-operations that can be handled by the NAND controller.
1956  */
1957 struct nand_op_parser_ctx {
1958         const struct nand_op_instr *instrs;
1959         unsigned int ninstrs;
1960         struct nand_subop subop;
1961 };
1962 
1963 /**
1964  * nand_op_parser_must_split_instr - Checks if an instruction must be split
1965  * @pat: the parser pattern element that matches @instr
1966  * @instr: pointer to the instruction to check
1967  * @start_offset: this is an in/out parameter. If @instr has already been
1968  *                split, then @start_offset is the offset from which to start
1969  *                (either an address cycle or an offset in the data buffer).
1970  *                Conversely, if the function returns true (ie. instr must be
1971  *                split), this parameter is updated to point to the first
1972  *                data/address cycle that has not been taken care of.
1973  *
1974  * Some NAND controllers are limited and cannot send X address cycles with a
1975  * unique operation, or cannot read/write more than Y bytes at the same time.
1976  * In this case, split the instruction that does not fit in a single
1977  * controller-operation into two or more chunks.
1978  *
1979  * Returns true if the instruction must be split, false otherwise.
1980  * The @start_offset parameter is also updated to the offset at which the next
1981  * bundle of instruction must start (if an address or a data instruction).
1982  */
1983 static bool
1984 nand_op_parser_must_split_instr(const struct nand_op_parser_pattern_elem *pat,
1985                                 const struct nand_op_instr *instr,
1986                                 unsigned int *start_offset)
1987 {
1988         switch (pat->type) {
1989         case NAND_OP_ADDR_INSTR:
1990                 if (!pat->ctx.addr.maxcycles)
1991                         break;
1992 
1993                 if (instr->ctx.addr.naddrs - *start_offset >
1994                     pat->ctx.addr.maxcycles) {
1995                         *start_offset += pat->ctx.addr.maxcycles;
1996                         return true;
1997                 }
1998                 break;
1999 
2000         case NAND_OP_DATA_IN_INSTR:
2001         case NAND_OP_DATA_OUT_INSTR:
2002                 if (!pat->ctx.data.maxlen)
2003                         break;
2004 
2005                 if (instr->ctx.data.len - *start_offset >
2006                     pat->ctx.data.maxlen) {
2007                         *start_offset += pat->ctx.data.maxlen;
2008                         return true;
2009                 }
2010                 break;
2011 
2012         default:
2013                 break;
2014         }
2015 
2016         return false;
2017 }
2018 
2019 /**
2020  * nand_op_parser_match_pat - Checks if a pattern matches the instructions
2021  *                            remaining in the parser context
2022  * @pat: the pattern to test
2023  * @ctx: the parser context structure to match with the pattern @pat
2024  *
2025  * Check if @pat matches the set or a sub-set of instructions remaining in @ctx.
2026  * Returns true if this is the case, false ortherwise. When true is returned,
2027  * @ctx->subop is updated with the set of instructions to be passed to the
2028  * controller driver.
2029  */
2030 static bool
2031 nand_op_parser_match_pat(const struct nand_op_parser_pattern *pat,
2032                          struct nand_op_parser_ctx *ctx)
2033 {
2034         unsigned int instr_offset = ctx->subop.first_instr_start_off;
2035         const struct nand_op_instr *end = ctx->instrs + ctx->ninstrs;
2036         const struct nand_op_instr *instr = ctx->subop.instrs;
2037         unsigned int i, ninstrs;
2038 
2039         for (i = 0, ninstrs = 0; i < pat->nelems && instr < end; i++) {
2040                 /*
2041                  * The pattern instruction does not match the operation
2042                  * instruction. If the instruction is marked optional in the
2043                  * pattern definition, we skip the pattern element and continue
2044                  * to the next one. If the element is mandatory, there's no
2045                  * match and we can return false directly.
2046                  */
2047                 if (instr->type != pat->elems[i].type) {
2048                         if (!pat->elems[i].optional)
2049                                 return false;
2050 
2051                         continue;
2052                 }
2053 
2054                 /*
2055                  * Now check the pattern element constraints. If the pattern is
2056                  * not able to handle the whole instruction in a single step,
2057                  * we have to split it.
2058                  * The last_instr_end_off value comes back updated to point to
2059                  * the position where we have to split the instruction (the
2060                  * start of the next subop chunk).
2061                  */
2062                 if (nand_op_parser_must_split_instr(&pat->elems[i], instr,
2063                                                     &instr_offset)) {
2064                         ninstrs++;
2065                         i++;
2066                         break;
2067                 }
2068 
2069                 instr++;
2070                 ninstrs++;
2071                 instr_offset = 0;
2072         }
2073 
2074         /*
2075          * This can happen if all instructions of a pattern are optional.
2076          * Still, if there's not at least one instruction handled by this
2077          * pattern, this is not a match, and we should try the next one (if
2078          * any).
2079          */
2080         if (!ninstrs)
2081                 return false;
2082 
2083         /*
2084          * We had a match on the pattern head, but the pattern may be longer
2085          * than the instructions we're asked to execute. We need to make sure
2086          * there's no mandatory elements in the pattern tail.
2087          */
2088         for (; i < pat->nelems; i++) {
2089                 if (!pat->elems[i].optional)
2090                         return false;
2091         }
2092 
2093         /*
2094          * We have a match: update the subop structure accordingly and return
2095          * true.
2096          */
2097         ctx->subop.ninstrs = ninstrs;
2098         ctx->subop.last_instr_end_off = instr_offset;
2099 
2100         return true;
2101 }
2102 
2103 #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)
2104 static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx)
2105 {
2106         const struct nand_op_instr *instr;
2107         char *prefix = "      ";
2108         unsigned int i;
2109 
2110         pr_debug("executing subop:\n");
2111 
2112         for (i = 0; i < ctx->ninstrs; i++) {
2113                 instr = &ctx->instrs[i];
2114 
2115                 if (instr == &ctx->subop.instrs[0])
2116                         prefix = "    ->";
2117 
2118                 nand_op_trace(prefix, instr);
2119 
2120                 if (instr == &ctx->subop.instrs[ctx->subop.ninstrs - 1])
2121                         prefix = "      ";
2122         }
2123 }
2124 #else
2125 static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx)
2126 {
2127         /* NOP */
2128 }
2129 #endif
2130 
2131 static int nand_op_parser_cmp_ctx(const struct nand_op_parser_ctx *a,
2132                                   const struct nand_op_parser_ctx *b)
2133 {
2134         if (a->subop.ninstrs < b->subop.ninstrs)
2135                 return -1;
2136         else if (a->subop.ninstrs > b->subop.ninstrs)
2137                 return 1;
2138 
2139         if (a->subop.last_instr_end_off < b->subop.last_instr_end_off)
2140                 return -1;
2141         else if (a->subop.last_instr_end_off > b->subop.last_instr_end_off)
2142                 return 1;
2143 
2144         return 0;
2145 }
2146 
2147 /**
2148  * nand_op_parser_exec_op - exec_op parser
2149  * @chip: the NAND chip
2150  * @parser: patterns description provided by the controller driver
2151  * @op: the NAND operation to address
2152  * @check_only: when true, the function only checks if @op can be handled but
2153  *              does not execute the operation
2154  *
2155  * Helper function designed to ease integration of NAND controller drivers that
2156  * only support a limited set of instruction sequences. The supported sequences
2157  * are described in @parser, and the framework takes care of splitting @op into
2158  * multiple sub-operations (if required) and pass them back to the ->exec()
2159  * callback of the matching pattern if @check_only is set to false.
2160  *
2161  * NAND controller drivers should call this function from their own ->exec_op()
2162  * implementation.
2163  *
2164  * Returns 0 on success, a negative error code otherwise. A failure can be
2165  * caused by an unsupported operation (none of the supported patterns is able
2166  * to handle the requested operation), or an error returned by one of the
2167  * matching pattern->exec() hook.
2168  */
2169 int nand_op_parser_exec_op(struct nand_chip *chip,
2170                            const struct nand_op_parser *parser,
2171                            const struct nand_operation *op, bool check_only)
2172 {
2173         struct nand_op_parser_ctx ctx = {
2174                 .subop.instrs = op->instrs,
2175                 .instrs = op->instrs,
2176                 .ninstrs = op->ninstrs,
2177         };
2178         unsigned int i;
2179 
2180         while (ctx.subop.instrs < op->instrs + op->ninstrs) {
2181                 const struct nand_op_parser_pattern *pattern;
2182                 struct nand_op_parser_ctx best_ctx;
2183                 int ret, best_pattern = -1;
2184 
2185                 for (i = 0; i < parser->npatterns; i++) {
2186                         struct nand_op_parser_ctx test_ctx = ctx;
2187 
2188                         pattern = &parser->patterns[i];
2189                         if (!nand_op_parser_match_pat(pattern, &test_ctx))
2190                                 continue;
2191 
2192                         if (best_pattern >= 0 &&
2193                             nand_op_parser_cmp_ctx(&test_ctx, &best_ctx) <= 0)
2194                                 continue;
2195 
2196                         best_pattern = i;
2197                         best_ctx = test_ctx;
2198                 }
2199 
2200                 if (best_pattern < 0) {
2201                         pr_debug("->exec_op() parser: pattern not found!\n");
2202                         return -ENOTSUPP;
2203                 }
2204 
2205                 ctx = best_ctx;
2206                 nand_op_parser_trace(&ctx);
2207 
2208                 if (!check_only) {
2209                         pattern = &parser->patterns[best_pattern];
2210                         ret = pattern->exec(chip, &ctx.subop);
2211                         if (ret)
2212                                 return ret;
2213                 }
2214 
2215                 /*
2216                  * Update the context structure by pointing to the start of the
2217                  * next subop.
2218                  */
2219                 ctx.subop.instrs = ctx.subop.instrs + ctx.subop.ninstrs;
2220                 if (ctx.subop.last_instr_end_off)
2221                         ctx.subop.instrs -= 1;
2222 
2223                 ctx.subop.first_instr_start_off = ctx.subop.last_instr_end_off;
2224         }
2225 
2226         return 0;
2227 }
2228 EXPORT_SYMBOL_GPL(nand_op_parser_exec_op);
2229 
2230 static bool nand_instr_is_data(const struct nand_op_instr *instr)
2231 {
2232         return instr && (instr->type == NAND_OP_DATA_IN_INSTR ||
2233                          instr->type == NAND_OP_DATA_OUT_INSTR);
2234 }
2235 
2236 static bool nand_subop_instr_is_valid(const struct nand_subop *subop,
2237                                       unsigned int instr_idx)
2238 {
2239         return subop && instr_idx < subop->ninstrs;
2240 }
2241 
2242 static unsigned int nand_subop_get_start_off(const struct nand_subop *subop,
2243                                              unsigned int instr_idx)
2244 {
2245         if (instr_idx)
2246                 return 0;
2247 
2248         return subop->first_instr_start_off;
2249 }
2250 
2251 /**
2252  * nand_subop_get_addr_start_off - Get the start offset in an address array
2253  * @subop: The entire sub-operation
2254  * @instr_idx: Index of the instruction inside the sub-operation
2255  *
2256  * During driver development, one could be tempted to directly use the
2257  * ->addr.addrs field of address instructions. This is wrong as address
2258  * instructions might be split.
2259  *
2260  * Given an address instruction, returns the offset of the first cycle to issue.
2261  */
2262 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
2263                                            unsigned int instr_idx)
2264 {
2265         if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2266                     subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR))
2267                 return 0;
2268 
2269         return nand_subop_get_start_off(subop, instr_idx);
2270 }
2271 EXPORT_SYMBOL_GPL(nand_subop_get_addr_start_off);
2272 
2273 /**
2274  * nand_subop_get_num_addr_cyc - Get the remaining address cycles to assert
2275  * @subop: The entire sub-operation
2276  * @instr_idx: Index of the instruction inside the sub-operation
2277  *
2278  * During driver development, one could be tempted to directly use the
2279  * ->addr->naddrs field of a data instruction. This is wrong as instructions
2280  * might be split.
2281  *
2282  * Given an address instruction, returns the number of address cycle to issue.
2283  */
2284 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
2285                                          unsigned int instr_idx)
2286 {
2287         int start_off, end_off;
2288 
2289         if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2290                     subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR))
2291                 return 0;
2292 
2293         start_off = nand_subop_get_addr_start_off(subop, instr_idx);
2294 
2295         if (instr_idx == subop->ninstrs - 1 &&
2296             subop->last_instr_end_off)
2297                 end_off = subop->last_instr_end_off;
2298         else
2299                 end_off = subop->instrs[instr_idx].ctx.addr.naddrs;
2300 
2301         return end_off - start_off;
2302 }
2303 EXPORT_SYMBOL_GPL(nand_subop_get_num_addr_cyc);
2304 
2305 /**
2306  * nand_subop_get_data_start_off - Get the start offset in a data array
2307  * @subop: The entire sub-operation
2308  * @instr_idx: Index of the instruction inside the sub-operation
2309  *
2310  * During driver development, one could be tempted to directly use the
2311  * ->data->buf.{in,out} field of data instructions. This is wrong as data
2312  * instructions might be split.
2313  *
2314  * Given a data instruction, returns the offset to start from.
2315  */
2316 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
2317                                            unsigned int instr_idx)
2318 {
2319         if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2320                     !nand_instr_is_data(&subop->instrs[instr_idx])))
2321                 return 0;
2322 
2323         return nand_subop_get_start_off(subop, instr_idx);
2324 }
2325 EXPORT_SYMBOL_GPL(nand_subop_get_data_start_off);
2326 
2327 /**
2328  * nand_subop_get_data_len - Get the number of bytes to retrieve
2329  * @subop: The entire sub-operation
2330  * @instr_idx: Index of the instruction inside the sub-operation
2331  *
2332  * During driver development, one could be tempted to directly use the
2333  * ->data->len field of a data instruction. This is wrong as data instructions
2334  * might be split.
2335  *
2336  * Returns the length of the chunk of data to send/receive.
2337  */
2338 unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
2339                                      unsigned int instr_idx)
2340 {
2341         int start_off = 0, end_off;
2342 
2343         if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2344                     !nand_instr_is_data(&subop->instrs[instr_idx])))
2345                 return 0;
2346 
2347         start_off = nand_subop_get_data_start_off(subop, instr_idx);
2348 
2349         if (instr_idx == subop->ninstrs - 1 &&
2350             subop->last_instr_end_off)
2351                 end_off = subop->last_instr_end_off;
2352         else
2353                 end_off = subop->instrs[instr_idx].ctx.data.len;
2354 
2355         return end_off - start_off;
2356 }
2357 EXPORT_SYMBOL_GPL(nand_subop_get_data_len);
2358 
2359 /**
2360  * nand_reset - Reset and initialize a NAND device
2361  * @chip: The NAND chip
2362  * @chipnr: Internal die id
2363  *
2364  * Save the timings data structure, then apply SDR timings mode 0 (see
2365  * nand_reset_data_interface for details), do the reset operation, and
2366  * apply back the previous timings.
2367  *
2368  * Returns 0 on success, a negative error code otherwise.
2369  */
2370 int nand_reset(struct nand_chip *chip, int chipnr)
2371 {
2372         struct nand_data_interface saved_data_intf = chip->data_interface;
2373         int ret;
2374 
2375         ret = nand_reset_data_interface(chip, chipnr);
2376         if (ret)
2377                 return ret;
2378 
2379         /*
2380          * The CS line has to be released before we can apply the new NAND
2381          * interface settings, hence this weird nand_select_target()
2382          * nand_deselect_target() dance.
2383          */
2384         nand_select_target(chip, chipnr);
2385         ret = nand_reset_op(chip);
2386         nand_deselect_target(chip);
2387         if (ret)
2388                 return ret;
2389 
2390         /*
2391          * A nand_reset_data_interface() put both the NAND chip and the NAND
2392          * controller in timings mode 0. If the default mode for this chip is
2393          * also 0, no need to proceed to the change again. Plus, at probe time,
2394          * nand_setup_data_interface() uses ->set/get_features() which would
2395          * fail anyway as the parameter page is not available yet.
2396          */
2397         if (!chip->onfi_timing_mode_default)
2398                 return 0;
2399 
2400         chip->data_interface = saved_data_intf;
2401         ret = nand_setup_data_interface(chip, chipnr);
2402         if (ret)
2403                 return ret;
2404 
2405         return 0;
2406 }
2407 EXPORT_SYMBOL_GPL(nand_reset);
2408 
2409 /**
2410  * nand_get_features - wrapper to perform a GET_FEATURE
2411  * @chip: NAND chip info structure
2412  * @addr: feature address
2413  * @subfeature_param: the subfeature parameters, a four bytes array
2414  *
2415  * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
2416  * operation cannot be handled.
2417  */
2418 int nand_get_features(struct nand_chip *chip, int addr,
2419                       u8 *subfeature_param)
2420 {
2421         if (!nand_supports_get_features(chip, addr))
2422                 return -ENOTSUPP;
2423 
2424         if (chip->legacy.get_features)
2425                 return chip->legacy.get_features(chip, addr, subfeature_param);
2426 
2427         return nand_get_features_op(chip, addr, subfeature_param);
2428 }
2429 
2430 /**
2431  * nand_set_features - wrapper to perform a SET_FEATURE
2432  * @chip: NAND chip info structure
2433  * @addr: feature address
2434  * @subfeature_param: the subfeature parameters, a four bytes array
2435  *
2436  * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
2437  * operation cannot be handled.
2438  */
2439 int nand_set_features(struct nand_chip *chip, int addr,
2440                       u8 *subfeature_param)
2441 {
2442         if (!nand_supports_set_features(chip, addr))
2443                 return -ENOTSUPP;
2444 
2445         if (chip->legacy.set_features)
2446                 return chip->legacy.set_features(chip, addr, subfeature_param);
2447 
2448         return nand_set_features_op(chip, addr, subfeature_param);
2449 }
2450 
2451 /**
2452  * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
2453  * @buf: buffer to test
2454  * @len: buffer length
2455  * @bitflips_threshold: maximum number of bitflips
2456  *
2457  * Check if a buffer contains only 0xff, which means the underlying region
2458  * has been erased and is ready to be programmed.
2459  * The bitflips_threshold specify the maximum number of bitflips before
2460  * considering the region is not erased.
2461  * Note: The logic of this function has been extracted from the memweight
2462  * implementation, except that nand_check_erased_buf function exit before
2463  * testing the whole buffer if the number of bitflips exceed the
2464  * bitflips_threshold value.
2465  *
2466  * Returns a positive number of bitflips less than or equal to
2467  * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
2468  * threshold.
2469  */
2470 static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
2471 {
2472         const unsigned char *bitmap = buf;
2473         int bitflips = 0;
2474         int weight;
2475 
2476         for (; len && ((uintptr_t)bitmap) % sizeof(long);
2477              len--, bitmap++) {
2478                 weight = hweight8(*bitmap);
2479                 bitflips += BITS_PER_BYTE - weight;
2480                 if (unlikely(bitflips > bitflips_threshold))
2481                         return -EBADMSG;
2482         }
2483 
2484         for (; len >= sizeof(long);
2485              len -= sizeof(long), bitmap += sizeof(long)) {
2486                 unsigned long d = *((unsigned long *)bitmap);
2487                 if (d == ~0UL)
2488                         continue;
2489                 weight = hweight_long(d);
2490                 bitflips += BITS_PER_LONG - weight;
2491                 if (unlikely(bitflips > bitflips_threshold))
2492                         return -EBADMSG;
2493         }
2494 
2495         for (; len > 0; len--, bitmap++) {
2496                 weight = hweight8(*bitmap);
2497                 bitflips += BITS_PER_BYTE - weight;
2498                 if (unlikely(bitflips > bitflips_threshold))
2499                         return -EBADMSG;
2500         }
2501 
2502         return bitflips;
2503 }
2504 
2505 /**
2506  * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
2507  *                               0xff data
2508  * @data: data buffer to test
2509  * @datalen: data length
2510  * @ecc: ECC buffer
2511  * @ecclen: ECC length
2512  * @extraoob: extra OOB buffer
2513  * @extraooblen: extra OOB length
2514  * @bitflips_threshold: maximum number of bitflips
2515  *
2516  * Check if a data buffer and its associated ECC and OOB data contains only
2517  * 0xff pattern, which means the underlying region has been erased and is
2518  * ready to be programmed.
2519  * The bitflips_threshold specify the maximum number of bitflips before
2520  * considering the region as not erased.
2521  *
2522  * Note:
2523  * 1/ ECC algorithms are working on pre-defined block sizes which are usually
2524  *    different from the NAND page size. When fixing bitflips, ECC engines will
2525  *    report the number of errors per chunk, and the NAND core infrastructure
2526  *    expect you to return the maximum number of bitflips for the whole page.
2527  *    This is why you should always use this function on a single chunk and
2528  *    not on the whole page. After checking each chunk you should update your
2529  *    max_bitflips value accordingly.
2530  * 2/ When checking for bitflips in erased pages you should not only check
2531  *    the payload data but also their associated ECC data, because a user might
2532  *    have programmed almost all bits to 1 but a few. In this case, we
2533  *    shouldn't consider the chunk as erased, and checking ECC bytes prevent
2534  *    this case.
2535  * 3/ The extraoob argument is optional, and should be used if some of your OOB
2536  *    data are protected by the ECC engine.
2537  *    It could also be used if you support subpages and want to attach some
2538  *    extra OOB data to an ECC chunk.
2539  *
2540  * Returns a positive number of bitflips less than or equal to
2541  * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
2542  * threshold. In case of success, the passed buffers are filled with 0xff.
2543  */
2544 int nand_check_erased_ecc_chunk(void *data, int datalen,
2545                                 void *ecc, int ecclen,
2546                                 void *extraoob, int extraooblen,
2547                                 int bitflips_threshold)
2548 {
2549         int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
2550 
2551         data_bitflips = nand_check_erased_buf(data, datalen,
2552                                               bitflips_threshold);
2553         if (data_bitflips < 0)
2554                 return data_bitflips;
2555 
2556         bitflips_threshold -= data_bitflips;
2557 
2558         ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
2559         if (ecc_bitflips < 0)
2560                 return ecc_bitflips;
2561 
2562         bitflips_threshold -= ecc_bitflips;
2563 
2564         extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
2565                                                   bitflips_threshold);
2566         if (extraoob_bitflips < 0)
2567                 return extraoob_bitflips;
2568 
2569         if (data_bitflips)
2570                 memset(data, 0xff, datalen);
2571 
2572         if (ecc_bitflips)
2573                 memset(ecc, 0xff, ecclen);
2574 
2575         if (extraoob_bitflips)
2576                 memset(extraoob, 0xff, extraooblen);
2577 
2578         return data_bitflips + ecc_bitflips + extraoob_bitflips;
2579 }
2580 EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
2581 
2582 /**
2583  * nand_read_page_raw_notsupp - dummy read raw page function
2584  * @chip: nand chip info structure
2585  * @buf: buffer to store read data
2586  * @oob_required: caller requires OOB data read to chip->oob_poi
2587  * @page: page number to read
2588  *
2589  * Returns -ENOTSUPP unconditionally.
2590  */
2591 int nand_read_page_raw_notsupp(struct nand_chip *chip, u8 *buf,
2592                                int oob_required, int page)
2593 {
2594         return -ENOTSUPP;
2595 }
2596 
2597 /**
2598  * nand_read_page_raw - [INTERN] read raw page data without ecc
2599  * @chip: nand chip info structure
2600  * @buf: buffer to store read data
2601  * @oob_required: caller requires OOB data read to chip->oob_poi
2602  * @page: page number to read
2603  *
2604  * Not for syndrome calculating ECC controllers, which use a special oob layout.
2605  */
2606 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
2607                        int page)
2608 {
2609         struct mtd_info *mtd = nand_to_mtd(chip);
2610         int ret;
2611 
2612         ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize);
2613         if (ret)
2614                 return ret;
2615 
2616         if (oob_required) {
2617                 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
2618                                         false);
2619                 if (ret)
2620                         return ret;
2621         }
2622 
2623         return 0;
2624 }
2625 EXPORT_SYMBOL(nand_read_page_raw);
2626 
2627 /**
2628  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
2629  * @chip: nand chip info structure
2630  * @buf: buffer to store read data
2631  * @oob_required: caller requires OOB data read to chip->oob_poi
2632  * @page: page number to read
2633  *
2634  * We need a special oob layout and handling even when OOB isn't used.
2635  */
2636 static int nand_read_page_raw_syndrome(struct nand_chip *chip, uint8_t *buf,
2637                                        int oob_required, int page)
2638 {
2639         struct mtd_info *mtd = nand_to_mtd(chip);
2640         int eccsize = chip->ecc.size;
2641         int eccbytes = chip->ecc.bytes;
2642         uint8_t *oob = chip->oob_poi;
2643         int steps, size, ret;
2644 
2645         ret = nand_read_page_op(chip, page, 0, NULL, 0);
2646         if (ret)
2647                 return ret;
2648 
2649         for (steps = chip->ecc.steps; steps > 0; steps--) {
2650                 ret = nand_read_data_op(chip, buf, eccsize, false);
2651                 if (ret)
2652                         return ret;
2653 
2654                 buf += eccsize;
2655 
2656                 if (chip->ecc.prepad) {
2657                         ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
2658                                                 false);
2659                         if (ret)
2660                                 return ret;
2661 
2662                         oob += chip->ecc.prepad;
2663                 }
2664 
2665                 ret = nand_read_data_op(chip, oob, eccbytes, false);
2666                 if (ret)
2667                         return ret;
2668 
2669                 oob += eccbytes;
2670 
2671                 if (chip->ecc.postpad) {
2672                         ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
2673                                                 false);
2674                         if (ret)
2675                                 return ret;
2676 
2677                         oob += chip->ecc.postpad;
2678                 }
2679         }
2680 
2681         size = mtd->oobsize - (oob - chip->oob_poi);
2682         if (size) {
2683                 ret = nand_read_data_op(chip, oob, size, false);
2684                 if (ret)
2685                         return ret;
2686         }
2687 
2688         return 0;
2689 }
2690 
2691 /**
2692  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
2693  * @chip: nand chip info structure
2694  * @buf: buffer to store read data
2695  * @oob_required: caller requires OOB data read to chip->oob_poi
2696  * @page: page number to read
2697  */
2698 static int nand_read_page_swecc(struct nand_chip *chip, uint8_t *buf,
2699                                 int oob_required, int page)
2700 {
2701         struct mtd_info *mtd = nand_to_mtd(chip);
2702         int i, eccsize = chip->ecc.size, ret;
2703         int eccbytes = chip->ecc.bytes;
2704         int eccsteps = chip->ecc.steps;
2705         uint8_t *p = buf;
2706         uint8_t *ecc_calc = chip->ecc.calc_buf;
2707         uint8_t *ecc_code = chip->ecc.code_buf;
2708         unsigned int max_bitflips = 0;
2709 
2710         chip->ecc.read_page_raw(chip, buf, 1, page);
2711 
2712         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2713                 chip->ecc.calculate(chip, p, &ecc_calc[i]);
2714 
2715         ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
2716                                          chip->ecc.total);
2717         if (ret)
2718                 return ret;
2719 
2720         eccsteps = chip->ecc.steps;
2721         p = buf;
2722 
2723         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2724                 int stat;
2725 
2726                 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
2727                 if (stat < 0) {
2728                         mtd->ecc_stats.failed++;
2729                 } else {
2730                         mtd->ecc_stats.corrected += stat;
2731                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
2732                 }
2733         }
2734         return max_bitflips;
2735 }
2736 
2737 /**
2738  * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
2739  * @chip: nand chip info structure
2740  * @data_offs: offset of requested data within the page
2741  * @readlen: data length
2742  * @bufpoi: buffer to store read data
2743  * @page: page number to read
2744  */
2745 static int nand_read_subpage(struct nand_chip *chip, uint32_t data_offs,
2746                              uint32_t readlen, uint8_t *bufpoi, int page)
2747 {
2748         struct mtd_info *mtd = nand_to_mtd(chip);
2749         int start_step, end_step, num_steps, ret;
2750         uint8_t *p;
2751         int data_col_addr, i, gaps = 0;
2752         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
2753         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
2754         int index, section = 0;
2755         unsigned int max_bitflips = 0;
2756         struct mtd_oob_region oobregion = { };
2757 
2758         /* Column address within the page aligned to ECC size (256bytes) */
2759         start_step = data_offs / chip->ecc.size;
2760         end_step = (data_offs + readlen - 1) / chip->ecc.size;
2761         num_steps = end_step - start_step + 1;
2762         index = start_step * chip->ecc.bytes;
2763 
2764         /* Data size aligned to ECC ecc.size */
2765         datafrag_len = num_steps * chip->ecc.size;
2766         eccfrag_len = num_steps * chip->ecc.bytes;
2767 
2768         data_col_addr = start_step * chip->ecc.size;
2769         /* If we read not a page aligned data */
2770         p = bufpoi + data_col_addr;
2771         ret = nand_read_page_op(chip, page, data_col_addr, p, datafrag_len);
2772         if (ret)
2773                 return ret;
2774 
2775         /* Calculate ECC */
2776         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
2777                 chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]);
2778 
2779         /*
2780          * The performance is faster if we position offsets according to
2781          * ecc.pos. Let's make sure that there are no gaps in ECC positions.
2782          */
2783         ret = mtd_ooblayout_find_eccregion(mtd, index, &section, &oobregion);
2784         if (ret)
2785                 return ret;
2786 
2787         if (oobregion.length < eccfrag_len)
2788                 gaps = 1;
2789 
2790         if (gaps) {
2791                 ret = nand_change_read_column_op(chip, mtd->writesize,
2792                                                  chip->oob_poi, mtd->oobsize,
2793                                                  false);
2794                 if (ret)
2795                         return ret;
2796         } else {
2797                 /*
2798                  * Send the command to read the particular ECC bytes take care
2799                  * about buswidth alignment in read_buf.
2800                  */
2801                 aligned_pos = oobregion.offset & ~(busw - 1);
2802                 aligned_len = eccfrag_len;
2803                 if (oobregion.offset & (busw - 1))
2804                         aligned_len++;
2805                 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) &
2806                     (busw - 1))
2807                         aligned_len++;
2808 
2809                 ret = nand_change_read_column_op(chip,
2810                                                  mtd->writesize + aligned_pos,
2811                                                  &chip->oob_poi[aligned_pos],
2812                                                  aligned_len, false);
2813                 if (ret)
2814                         return ret;
2815         }
2816 
2817         ret = mtd_ooblayout_get_eccbytes(mtd, chip->ecc.code_buf,
2818                                          chip->oob_poi, index, eccfrag_len);
2819         if (ret)
2820                 return ret;
2821 
2822         p = bufpoi + data_col_addr;
2823         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
2824                 int stat;
2825 
2826                 stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i],
2827                                          &chip->ecc.calc_buf[i]);
2828                 if (stat == -EBADMSG &&
2829                     (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
2830                         /* check for empty pages with bitflips */
2831                         stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
2832                                                 &chip->ecc.code_buf[i],
2833                                                 chip->ecc.bytes,
2834                                                 NULL, 0,
2835                                                 chip->ecc.strength);
2836                 }
2837 
2838                 if (stat < 0) {
2839                         mtd->ecc_stats.failed++;
2840                 } else {
2841                         mtd->ecc_stats.corrected += stat;
2842                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
2843                 }
2844         }
2845         return max_bitflips;
2846 }
2847 
2848 /**
2849  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
2850  * @chip: nand chip info structure
2851  * @buf: buffer to store read data
2852  * @oob_required: caller requires OOB data read to chip->oob_poi
2853  * @page: page number to read
2854  *
2855  * Not for syndrome calculating ECC controllers which need a special oob layout.
2856  */
2857 static int nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,
2858                                 int oob_required, int page)
2859 {
2860         struct mtd_info *mtd = nand_to_mtd(chip);
2861         int i, eccsize = chip->ecc.size, ret;
2862         int eccbytes = chip->ecc.bytes;
2863         int eccsteps = chip->ecc.steps;
2864         uint8_t *p = buf;
2865         uint8_t *ecc_calc = chip->ecc.calc_buf;
2866         uint8_t *ecc_code = chip->ecc.code_buf;
2867         unsigned int max_bitflips = 0;
2868 
2869         ret = nand_read_page_op(chip, page, 0, NULL, 0);
2870         if (ret)
2871                 return ret;
2872 
2873         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2874                 chip->ecc.hwctl(chip, NAND_ECC_READ);
2875 
2876                 ret = nand_read_data_op(chip, p, eccsize, false);
2877                 if (ret)
2878                         return ret;
2879 
2880                 chip->ecc.calculate(chip, p, &ecc_calc[i]);
2881         }
2882 
2883         ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false);
2884         if (ret)
2885                 return ret;
2886 
2887         ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
2888                                          chip->ecc.total);
2889         if (ret)
2890                 return ret;
2891 
2892         eccsteps = chip->ecc.steps;
2893         p = buf;
2894 
2895         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2896                 int stat;
2897 
2898                 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
2899                 if (stat == -EBADMSG &&
2900                     (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
2901                         /* check for empty pages with bitflips */
2902                         stat = nand_check_erased_ecc_chunk(p, eccsize,
2903                                                 &ecc_code[i], eccbytes,
2904                                                 NULL, 0,
2905                                                 chip->ecc.strength);
2906                 }
2907 
2908                 if (stat < 0) {
2909                         mtd->ecc_stats.failed++;
2910                 } else {
2911                         mtd->ecc_stats.corrected += stat;
2912                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
2913                 }
2914         }
2915         return max_bitflips;
2916 }
2917 
2918 /**
2919  * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
2920  * @chip: nand chip info structure
2921  * @buf: buffer to store read data
2922  * @oob_required: caller requires OOB data read to chip->oob_poi
2923  * @page: page number to read
2924  *
2925  * Hardware ECC for large page chips, require OOB to be read first. For this
2926  * ECC mode, the write_page method is re-used from ECC_HW. These methods
2927  * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
2928  * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
2929  * the data area, by overwriting the NAND manufacturer bad block markings.
2930  */
2931 static int nand_read_page_hwecc_oob_first(struct nand_chip *chip, uint8_t *buf,
2932                                           int oob_required, int page)
2933 {
2934         struct mtd_info *mtd = nand_to_mtd(chip);
2935         int i, eccsize = chip->ecc.size, ret;
2936         int eccbytes = chip->ecc.bytes;
2937         int eccsteps = chip->ecc.steps;
2938         uint8_t *p = buf;
2939         uint8_t *ecc_code = chip->ecc.code_buf;
2940         uint8_t *ecc_calc = chip->ecc.calc_buf;
2941         unsigned int max_bitflips = 0;
2942 
2943         /* Read the OOB area first */
2944         ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
2945         if (ret)
2946                 return ret;
2947 
2948         ret = nand_read_page_op(chip, page, 0, NULL, 0);
2949         if (ret)
2950                 return ret;
2951 
2952         ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
2953                                          chip->ecc.total);
2954         if (ret)
2955                 return ret;
2956 
2957         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2958                 int stat;
2959 
2960                 chip->ecc.hwctl(chip, NAND_ECC_READ);
2961 
2962                 ret = nand_read_data_op(chip, p, eccsize, false);
2963                 if (ret)
2964                         return ret;
2965 
2966                 chip->ecc.calculate(chip, p, &ecc_calc[i]);
2967 
2968                 stat = chip->ecc.correct(chip, p, &ecc_code[i], NULL);
2969                 if (stat == -EBADMSG &&
2970                     (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
2971                         /* check for empty pages with bitflips */
2972                         stat = nand_check_erased_ecc_chunk(p, eccsize,
2973                                                 &ecc_code[i], eccbytes,
2974                                                 NULL, 0,
2975                                                 chip->ecc.strength);
2976                 }
2977 
2978                 if (stat < 0) {
2979                         mtd->ecc_stats.failed++;
2980                 } else {
2981                         mtd->ecc_stats.corrected += stat;
2982                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
2983                 }
2984         }
2985         return max_bitflips;
2986 }
2987 
2988 /**
2989  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
2990  * @chip: nand chip info structure
2991  * @buf: buffer to store read data
2992  * @oob_required: caller requires OOB data read to chip->oob_poi
2993  * @page: page number to read
2994  *
2995  * The hw generator calculates the error syndrome automatically. Therefore we
2996  * need a special oob layout and handling.
2997  */
2998 static int nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf,
2999                                    int oob_required, int page)
3000 {
3001         struct mtd_info *mtd = nand_to_mtd(chip);
3002         int ret, i, eccsize = chip->ecc.size;
3003         int eccbytes = chip->ecc.bytes;
3004         int eccsteps = chip->ecc.steps;
3005         int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
3006         uint8_t *p = buf;
3007         uint8_t *oob = chip->oob_poi;
3008         unsigned int max_bitflips = 0;
3009 
3010         ret = nand_read_page_op(chip, page, 0, NULL, 0);
3011         if (ret)
3012                 return ret;
3013 
3014         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3015                 int stat;
3016 
3017                 chip->ecc.hwctl(chip, NAND_ECC_READ);
3018 
3019                 ret = nand_read_data_op(chip, p, eccsize, false);
3020                 if (ret)
3021                         return ret;
3022 
3023                 if (chip->ecc.prepad) {
3024                         ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
3025                                                 false);
3026                         if (ret)
3027                                 return ret;
3028 
3029                         oob += chip->ecc.prepad;
3030                 }
3031 
3032                 chip->ecc.hwctl(chip, NAND_ECC_READSYN);
3033 
3034                 ret = nand_read_data_op(chip, oob, eccbytes, false);
3035                 if (ret)
3036                         return ret;
3037 
3038                 stat = chip->ecc.correct(chip, p, oob, NULL);
3039 
3040                 oob += eccbytes;
3041 
3042                 if (chip->ecc.postpad) {
3043                         ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
3044                                                 false);
3045                         if (ret)
3046                                 return ret;
3047 
3048                         oob += chip->ecc.postpad;
3049                 }
3050 
3051                 if (stat == -EBADMSG &&
3052                     (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3053                         /* check for empty pages with bitflips */
3054                         stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
3055                                                            oob - eccpadbytes,
3056                                                            eccpadbytes,
3057                                                            NULL, 0,
3058                                                            chip->ecc.strength);
3059                 }
3060 
3061                 if (stat < 0) {
3062                         mtd->ecc_stats.failed++;
3063                 } else {
3064                         mtd->ecc_stats.corrected += stat;
3065                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
3066                 }
3067         }
3068 
3069         /* Calculate remaining oob bytes */
3070         i = mtd->oobsize - (oob - chip->oob_poi);
3071         if (i) {
3072                 ret = nand_read_data_op(chip, oob, i, false);
3073                 if (ret)
3074                         return ret;
3075         }
3076 
3077         return max_bitflips;
3078 }
3079 
3080 /**
3081  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
3082  * @chip: NAND chip object
3083  * @oob: oob destination address
3084  * @ops: oob ops structure
3085  * @len: size of oob to transfer
3086  */
3087 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
3088                                   struct mtd_oob_ops *ops, size_t len)
3089 {
3090         struct mtd_info *mtd = nand_to_mtd(chip);
3091         int ret;
3092 
3093         switch (ops->mode) {
3094 
3095         case MTD_OPS_PLACE_OOB:
3096         case MTD_OPS_RAW:
3097                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
3098                 return oob + len;
3099 
3100         case MTD_OPS_AUTO_OOB:
3101                 ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi,
3102                                                   ops->ooboffs, len);
3103                 BUG_ON(ret);
3104                 return oob + len;
3105 
3106         default:
3107                 BUG();
3108         }
3109         return NULL;
3110 }
3111 
3112 /**
3113  * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
3114  * @chip: NAND chip object
3115  * @retry_mode: the retry mode to use
3116  *
3117  * Some vendors supply a special command to shift the Vt threshold, to be used
3118  * when there are too many bitflips in a page (i.e., ECC error). After setting
3119  * a new threshold, the host should retry reading the page.
3120  */
3121 static int nand_setup_read_retry(struct nand_chip *chip, int retry_mode)
3122 {
3123         pr_debug("setting READ RETRY mode %d\n", retry_mode);
3124 
3125         if (retry_mode >= chip->read_retries)
3126                 return -EINVAL;
3127 
3128         if (!chip->setup_read_retry)
3129                 return -EOPNOTSUPP;
3130 
3131         return chip->setup_read_retry(chip, retry_mode);
3132 }
3133 
3134 static void nand_wait_readrdy(struct nand_chip *chip)
3135 {
3136         const struct nand_sdr_timings *sdr;
3137 
3138         if (!(chip->options & NAND_NEED_READRDY))
3139                 return;
3140 
3141         sdr = nand_get_sdr_timings(&chip->data_interface);
3142         WARN_ON(nand_wait_rdy_op(chip, PSEC_TO_MSEC(sdr->tR_max), 0));
3143 }
3144 
3145 /**
3146  * nand_do_read_ops - [INTERN] Read data with ECC
3147  * @chip: NAND chip object
3148  * @from: offset to read from
3149  * @ops: oob ops structure
3150  *
3151  * Internal function. Called with chip held.
3152  */
3153 static int nand_do_read_ops(struct nand_chip *chip, loff_t from,
3154                             struct mtd_oob_ops *ops)
3155 {
3156         int chipnr, page, realpage, col, bytes, aligned, oob_required;
3157         struct mtd_info *mtd = nand_to_mtd(chip);
3158         int ret = 0;
3159         uint32_t readlen = ops->len;
3160         uint32_t oobreadlen = ops->ooblen;
3161         uint32_t max_oobsize = mtd_oobavail(mtd, ops);
3162 
3163         uint8_t *bufpoi, *oob, *buf;
3164         int use_bufpoi;
3165         unsigned int max_bitflips = 0;
3166         int retry_mode = 0;
3167         bool ecc_fail = false;
3168 
3169         chipnr = (int)(from >> chip->chip_shift);
3170         nand_select_target(chip, chipnr);
3171 
3172         realpage = (int)(from >> chip->page_shift);
3173         page = realpage & chip->pagemask;
3174 
3175         col = (int)(from & (mtd->writesize - 1));
3176 
3177         buf = ops->datbuf;
3178         oob = ops->oobbuf;
3179         oob_required = oob ? 1 : 0;
3180 
3181         while (1) {
3182                 unsigned int ecc_failures = mtd->ecc_stats.failed;
3183 
3184                 bytes = min(mtd->writesize - col, readlen);
3185                 aligned = (bytes == mtd->writesize);
3186 
3187                 if (!aligned)
3188                         use_bufpoi = 1;
3189                 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
3190                         use_bufpoi = !virt_addr_valid(buf) ||
3191                                      !IS_ALIGNED((unsigned long)buf,
3192                                                  chip->buf_align);
3193                 else
3194                         use_bufpoi = 0;
3195 
3196                 /* Is the current page in the buffer? */
3197                 if (realpage != chip->pagecache.page || oob) {
3198                         bufpoi = use_bufpoi ? chip->data_buf : buf;
3199 
3200                         if (use_bufpoi && aligned)
3201                                 pr_debug("%s: using read bounce buffer for buf@%p\n",
3202                                                  __func__, buf);
3203 
3204 read_retry:
3205                         /*
3206                          * Now read the page into the buffer.  Absent an error,
3207                          * the read methods return max bitflips per ecc step.
3208                          */
3209                         if (unlikely(ops->mode == MTD_OPS_RAW))
3210                                 ret = chip->ecc.read_page_raw(chip, bufpoi,
3211                                                               oob_required,
3212                                                               page);
3213                         else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
3214                                  !oob)
3215                                 ret = chip->ecc.read_subpage(chip, col, bytes,
3216                                                              bufpoi, page);
3217                         else
3218                                 ret = chip->ecc.read_page(chip, bufpoi,
3219                                                           oob_required, page);
3220                         if (ret < 0) {
3221                                 if (use_bufpoi)
3222                                         /* Invalidate page cache */
3223                                         chip->pagecache.page = -1;
3224                                 break;
3225                         }
3226 
3227                         /* Transfer not aligned data */
3228                         if (use_bufpoi) {
3229                                 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
3230                                     !(mtd->ecc_stats.failed - ecc_failures) &&
3231                                     (ops->mode != MTD_OPS_RAW)) {
3232                                         chip->pagecache.page = realpage;
3233                                         chip->pagecache.bitflips = ret;
3234                                 } else {
3235                                         /* Invalidate page cache */
3236                                         chip->pagecache.page = -1;
3237                                 }
3238                                 memcpy(buf, chip->data_buf + col, bytes);
3239                         }
3240 
3241                         if (unlikely(oob)) {
3242                                 int toread = min(oobreadlen, max_oobsize);
3243 
3244                                 if (toread) {
3245                                         oob = nand_transfer_oob(chip, oob, ops,
3246                                                                 toread);
3247                                         oobreadlen -= toread;
3248                                 }
3249                         }
3250 
3251                         nand_wait_readrdy(chip);
3252 
3253                         if (mtd->ecc_stats.failed - ecc_failures) {
3254                                 if (retry_mode + 1 < chip->read_retries) {
3255                                         retry_mode++;
3256                                         ret = nand_setup_read_retry(chip,
3257                                                         retry_mode);
3258                                         if (ret < 0)
3259                                                 break;
3260 
3261                                         /* Reset failures; retry */
3262                                         mtd->ecc_stats.failed = ecc_failures;
3263                                         goto read_retry;
3264                                 } else {
3265                                         /* No more retry modes; real failure */
3266                                         ecc_fail = true;
3267                                 }
3268                         }
3269 
3270                         buf += bytes;
3271                         max_bitflips = max_t(unsigned int, max_bitflips, ret);
3272                 } else {
3273                         memcpy(buf, chip->data_buf + col, bytes);
3274                         buf += bytes;
3275                         max_bitflips = max_t(unsigned int, max_bitflips,
3276                                              chip->pagecache.bitflips);
3277                 }
3278 
3279                 readlen -= bytes;
3280 
3281                 /* Reset to retry mode 0 */
3282                 if (retry_mode) {
3283                         ret = nand_setup_read_retry(chip, 0);
3284                         if (ret < 0)
3285                                 break;
3286                         retry_mode = 0;
3287                 }
3288 
3289                 if (!readlen)
3290                         break;
3291 
3292                 /* For subsequent reads align to page boundary */
3293                 col = 0;
3294                 /* Increment page address */
3295                 realpage++;
3296 
3297                 page = realpage & chip->pagemask;
3298                 /* Check, if we cross a chip boundary */
3299                 if (!page) {
3300                         chipnr++;
3301                         nand_deselect_target(chip);
3302                         nand_select_target(chip, chipnr);
3303                 }
3304         }
3305         nand_deselect_target(chip);
3306 
3307         ops->retlen = ops->len - (size_t) readlen;
3308         if (oob)
3309                 ops->oobretlen = ops->ooblen - oobreadlen;
3310 
3311         if (ret < 0)
3312                 return ret;
3313 
3314         if (ecc_fail)
3315                 return -EBADMSG;
3316 
3317         return max_bitflips;
3318 }
3319 
3320 /**
3321  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
3322  * @chip: nand chip info structure
3323  * @page: page number to read
3324  */
3325 int nand_read_oob_std(struct nand_chip *chip, int page)
3326 {
3327         struct mtd_info *mtd = nand_to_mtd(chip);
3328 
3329         return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
3330 }
3331 EXPORT_SYMBOL(nand_read_oob_std);
3332 
3333 /**
3334  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
3335  *                          with syndromes
3336  * @chip: nand chip info structure
3337  * @page: page number to read
3338  */
3339 static int nand_read_oob_syndrome(struct nand_chip *chip, int page)
3340 {
3341         struct mtd_info *mtd = nand_to_mtd(chip);
3342         int length = mtd->oobsize;
3343         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
3344         int eccsize = chip->ecc.size;
3345         uint8_t *bufpoi = chip->oob_poi;
3346         int i, toread, sndrnd = 0, pos, ret;
3347 
3348         ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0);
3349         if (ret)
3350                 return ret;
3351 
3352         for (i = 0; i < chip->ecc.steps; i++) {
3353                 if (sndrnd) {
3354                         int ret;
3355 
3356                         pos = eccsize + i * (eccsize + chunk);
3357                         if (mtd->writesize > 512)
3358                                 ret = nand_change_read_column_op(chip, pos,
3359                                                                  NULL, 0,
3360                                                                  false);
3361                         else
3362                                 ret = nand_read_page_op(chip, page, pos, NULL,
3363                                                         0);
3364 
3365                         if (ret)
3366                                 return ret;
3367                 } else
3368                         sndrnd = 1;
3369                 toread = min_t(int, length, chunk);
3370 
3371                 ret = nand_read_data_op(chip, bufpoi, toread, false);
3372                 if (ret)
3373                         return ret;
3374 
3375                 bufpoi += toread;
3376                 length -= toread;
3377         }
3378         if (length > 0) {
3379                 ret = nand_read_data_op(chip, bufpoi, length, false);
3380                 if (ret)
3381                         return ret;
3382         }
3383 
3384         return 0;
3385 }
3386 
3387 /**
3388  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
3389  * @chip: nand chip info structure
3390  * @page: page number to write
3391  */
3392 int nand_write_oob_std(struct nand_chip *chip, int page)
3393 {
3394         struct mtd_info *mtd = nand_to_mtd(chip);
3395 
3396         return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
3397                                  mtd->oobsize);
3398 }
3399 EXPORT_SYMBOL(nand_write_oob_std);
3400 
3401 /**
3402  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
3403  *                           with syndrome - only for large page flash
3404  * @chip: nand chip info structure
3405  * @page: page number to write
3406  */
3407 static int nand_write_oob_syndrome(struct nand_chip *chip, int page)
3408 {
3409         struct mtd_info *mtd = nand_to_mtd(chip);
3410         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
3411         int eccsize = chip->ecc.size, length = mtd->oobsize;
3412         int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;
3413         const uint8_t *bufpoi = chip->oob_poi;
3414 
3415         /*
3416          * data-ecc-data-ecc ... ecc-oob
3417          * or
3418          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
3419          */
3420         if (!chip->ecc.prepad && !chip->ecc.postpad) {
3421                 pos = steps * (eccsize + chunk);
3422                 steps = 0;
3423         } else
3424                 pos = eccsize;
3425 
3426         ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0);
3427         if (ret)
3428                 return ret;
3429 
3430         for (i = 0; i < steps; i++) {
3431                 if (sndcmd) {
3432                         if (mtd->writesize <= 512) {
3433                                 uint32_t fill = 0xFFFFFFFF;
3434 
3435                                 len = eccsize;
3436                                 while (len > 0) {
3437                                         int num = min_t(int, len, 4);
3438 
3439                                         ret = nand_write_data_op(chip, &fill,
3440                                                                  num, false);
3441                                         if (ret)
3442                                                 return ret;
3443 
3444                                         len -= num;
3445                                 }
3446                         } else {
3447                                 pos = eccsize + i * (eccsize + chunk);
3448                                 ret = nand_change_write_column_op(chip, pos,
3449                                                                   NULL, 0,
3450                                                                   false);
3451                                 if (ret)
3452                                         return ret;
3453                         }
3454                 } else
3455                         sndcmd = 1;
3456                 len = min_t(int, length, chunk);
3457 
3458                 ret = nand_write_data_op(chip, bufpoi, len, false);
3459                 if (ret)
3460                         return ret;
3461 
3462                 bufpoi += len;
3463                 length -= len;
3464         }
3465         if (length > 0) {
3466                 ret = nand_write_data_op(chip, bufpoi, length, false);
3467                 if (ret)
3468                         return ret;
3469         }
3470 
3471         return nand_prog_page_end_op(chip);
3472 }
3473 
3474 /**
3475  * nand_do_read_oob - [INTERN] NAND read out-of-band
3476  * @chip: NAND chip object
3477  * @from: offset to read from
3478  * @ops: oob operations description structure
3479  *
3480  * NAND read out-of-band data from the spare area.
3481  */
3482 static int nand_do_read_oob(struct nand_chip *chip, loff_t from,
3483                             struct mtd_oob_ops *ops)
3484 {
3485         struct mtd_info *mtd = nand_to_mtd(chip);
3486         unsigned int max_bitflips = 0;
3487         int page, realpage, chipnr;
3488         struct mtd_ecc_stats stats;
3489         int readlen = ops->ooblen;
3490         int len;
3491         uint8_t *buf = ops->oobbuf;
3492         int ret = 0;
3493 
3494         pr_debug("%s: from = 0x%08Lx, len = %i\n",
3495                         __func__, (unsigned long long)from, readlen);
3496 
3497         stats = mtd->ecc_stats;
3498 
3499         len = mtd_oobavail(mtd, ops);
3500 
3501         chipnr = (int)(from >> chip->chip_shift);
3502         nand_select_target(chip, chipnr);
3503 
3504         /* Shift to get page */
3505         realpage = (int)(from >> chip->page_shift);
3506         page = realpage & chip->pagemask;
3507 
3508         while (1) {
3509                 if (ops->mode == MTD_OPS_RAW)
3510                         ret = chip->ecc.read_oob_raw(chip, page);
3511                 else
3512                         ret = chip->ecc.read_oob(chip, page);
3513 
3514                 if (ret < 0)
3515                         break;
3516 
3517                 len = min(len, readlen);
3518                 buf = nand_transfer_oob(chip, buf, ops, len);
3519 
3520                 nand_wait_readrdy(chip);
3521 
3522                 max_bitflips = max_t(unsigned int, max_bitflips, ret);
3523 
3524                 readlen -= len;
3525                 if (!readlen)
3526                         break;
3527 
3528                 /* Increment page address */
3529                 realpage++;
3530 
3531                 page = realpage & chip->pagemask;
3532                 /* Check, if we cross a chip boundary */
3533                 if (!page) {
3534                         chipnr++;
3535                         nand_deselect_target(chip);
3536                         nand_select_target(chip, chipnr);
3537                 }
3538         }
3539         nand_deselect_target(chip);
3540 
3541         ops->oobretlen = ops->ooblen - readlen;
3542 
3543         if (ret < 0)
3544                 return ret;
3545 
3546         if (mtd->ecc_stats.failed - stats.failed)
3547                 return -EBADMSG;
3548 
3549         return max_bitflips;
3550 }
3551 
3552 /**
3553  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
3554  * @mtd: MTD device structure
3555  * @from: offset to read from
3556  * @ops: oob operation description structure
3557  *
3558  * NAND read data and/or out-of-band data.
3559  */
3560 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
3561                          struct mtd_oob_ops *ops)
3562 {
3563         struct nand_chip *chip = mtd_to_nand(mtd);
3564         int ret;
3565 
3566         ops->retlen = 0;
3567 
3568         if (ops->mode != MTD_OPS_PLACE_OOB &&
3569             ops->mode != MTD_OPS_AUTO_OOB &&
3570             ops->mode != MTD_OPS_RAW)
3571                 return -ENOTSUPP;
3572 
3573         ret = nand_get_device(chip);
3574         if (ret)
3575                 return ret;
3576 
3577         if (!ops->datbuf)
3578                 ret = nand_do_read_oob(chip, from, ops);
3579         else
3580                 ret = nand_do_read_ops(chip, from, ops);
3581 
3582         nand_release_device(chip);
3583         return ret;
3584 }
3585 
3586 /**
3587  * nand_write_page_raw_notsupp - dummy raw page write function
3588  * @chip: nand chip info structure
3589  * @buf: data buffer
3590  * @oob_required: must write chip->oob_poi to OOB
3591  * @page: page number to write
3592  *
3593  * Returns -ENOTSUPP unconditionally.
3594  */
3595 int nand_write_page_raw_notsupp(struct nand_chip *chip, const u8 *buf,
3596                                 int oob_required, int page)
3597 {
3598         return -ENOTSUPP;
3599 }
3600 
3601 /**
3602  * nand_write_page_raw - [INTERN] raw page write function
3603  * @chip: nand chip info structure
3604  * @buf: data buffer
3605  * @oob_required: must write chip->oob_poi to OOB
3606  * @page: page number to write
3607  *
3608  * Not for syndrome calculating ECC controllers, which use a special oob layout.
3609  */
3610 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
3611                         int oob_required, int page)
3612 {
3613         struct mtd_info *mtd = nand_to_mtd(chip);
3614         int ret;
3615 
3616         ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
3617         if (ret)
3618                 return ret;
3619 
3620         if (oob_required) {
3621                 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
3622                                          false);
3623                 if (ret)
3624                         return ret;
3625         }
3626 
3627         return nand_prog_page_end_op(chip);
3628 }
3629 EXPORT_SYMBOL(nand_write_page_raw);
3630 
3631 /**
3632  * nand_write_page_raw_syndrome - [INTERN] raw page write function
3633  * @chip: nand chip info structure
3634  * @buf: data buffer
3635  * @oob_required: must write chip->oob_poi to OOB
3636  * @page: page number to write
3637  *
3638  * We need a special oob layout and handling even when ECC isn't checked.
3639  */
3640 static int nand_write_page_raw_syndrome(struct nand_chip *chip,
3641                                         const uint8_t *buf, int oob_required,
3642                                         int page)
3643 {
3644         struct mtd_info *mtd = nand_to_mtd(chip);
3645         int eccsize = chip->ecc.size;
3646         int eccbytes = chip->ecc.bytes;
3647         uint8_t *oob = chip->oob_poi;
3648         int steps, size, ret;
3649 
3650         ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
3651         if (ret)
3652                 return ret;
3653 
3654         for (steps = chip->ecc.steps; steps > 0; steps--) {
3655                 ret = nand_write_data_op(chip, buf, eccsize, false);
3656                 if (ret)
3657                         return ret;
3658 
3659                 buf += eccsize;
3660 
3661                 if (chip->ecc.prepad) {
3662                         ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
3663                                                  false);
3664                         if (ret)
3665                                 return ret;
3666 
3667                         oob += chip->ecc.prepad;
3668                 }
3669 
3670                 ret = nand_write_data_op(chip, oob, eccbytes, false);
3671                 if (ret)
3672                         return ret;
3673 
3674                 oob += eccbytes;
3675 
3676                 if (chip->ecc.postpad) {
3677                         ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
3678                                                  false);
3679                         if (ret)
3680                                 return ret;
3681 
3682                         oob += chip->ecc.postpad;
3683                 }
3684         }
3685 
3686         size = mtd->oobsize - (oob - chip->oob_poi);
3687         if (size) {
3688                 ret = nand_write_data_op(chip, oob, size, false);
3689                 if (ret)
3690                         return ret;
3691         }
3692 
3693         return nand_prog_page_end_op(chip);
3694 }
3695 /**
3696  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
3697  * @chip: nand chip info structure
3698  * @buf: data buffer
3699  * @oob_required: must write chip->oob_poi to OOB
3700  * @page: page number to write
3701  */
3702 static int nand_write_page_swecc(struct nand_chip *chip, const uint8_t *buf,
3703                                  int oob_required, int page)
3704 {
3705         struct mtd_info *mtd = nand_to_mtd(chip);
3706         int i, eccsize = chip->ecc.size, ret;
3707         int eccbytes = chip->ecc.bytes;
3708         int eccsteps = chip->ecc.steps;
3709         uint8_t *ecc_calc = chip->ecc.calc_buf;
3710         const uint8_t *p = buf;
3711 
3712         /* Software ECC calculation */
3713         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
3714                 chip->ecc.calculate(chip, p, &ecc_calc[i]);
3715 
3716         ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
3717                                          chip->ecc.total);
3718         if (ret)
3719                 return ret;
3720 
3721         return chip->ecc.write_page_raw(chip, buf, 1, page);
3722 }
3723 
3724 /**
3725  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
3726  * @chip: nand chip info structure
3727  * @buf: data buffer
3728  * @oob_required: must write chip->oob_poi to OOB
3729  * @page: page number to write
3730  */
3731 static int nand_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf,
3732                                  int oob_required, int page)
3733 {
3734         struct mtd_info *mtd = nand_to_mtd(chip);
3735         int i, eccsize = chip->ecc.size, ret;
3736         int eccbytes = chip->ecc.bytes;
3737         int eccsteps = chip->ecc.steps;
3738         uint8_t *ecc_calc = chip->ecc.calc_buf;
3739         const uint8_t *p = buf;
3740 
3741         ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
3742         if (ret)
3743                 return ret;
3744 
3745         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3746                 chip->ecc.hwctl(chip, NAND_ECC_WRITE);
3747 
3748                 ret = nand_write_data_op(chip, p, eccsize, false);
3749                 if (ret)
3750                         return ret;
3751 
3752                 chip->ecc.calculate(chip, p, &ecc_calc[i]);
3753         }
3754 
3755         ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
3756                                          chip->ecc.total);
3757         if (ret)
3758                 return ret;
3759 
3760         ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
3761         if (ret)
3762                 return ret;
3763 
3764         return nand_prog_page_end_op(chip);
3765 }
3766 
3767 
3768 /**
3769  * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
3770  * @chip:       nand chip info structure
3771  * @offset:     column address of subpage within the page
3772  * @data_len:   data length
3773  * @buf:        data buffer
3774  * @oob_required: must write chip->oob_poi to OOB
3775  * @page: page number to write
3776  */
3777 static int nand_write_subpage_hwecc(struct nand_chip *chip, uint32_t offset,
3778                                     uint32_t data_len, const uint8_t *buf,
3779                                     int oob_required, int page)
3780 {
3781         struct mtd_info *mtd = nand_to_mtd(chip);
3782         uint8_t *oob_buf  = chip->oob_poi;
3783         uint8_t *ecc_calc = chip->ecc.calc_buf;
3784         int ecc_size      = chip->ecc.size;
3785         int ecc_bytes     = chip->ecc.bytes;
3786         int ecc_steps     = chip->ecc.steps;
3787         uint32_t start_step = offset / ecc_size;
3788         uint32_t end_step   = (offset + data_len - 1) / ecc_size;
3789         int oob_bytes       = mtd->oobsize / ecc_steps;
3790         int step, ret;
3791 
3792         ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
3793         if (ret)
3794                 return ret;
3795 
3796         for (step = 0; step < ecc_steps; step++) {
3797                 /* configure controller for WRITE access */
3798                 chip->ecc.hwctl(chip, NAND_ECC_WRITE);
3799 
3800                 /* write data (untouched subpages already masked by 0xFF) */
3801                 ret = nand_write_data_op(chip, buf, ecc_size, false);
3802                 if (ret)
3803                         return ret;
3804 
3805                 /* mask ECC of un-touched subpages by padding 0xFF */
3806                 if ((step < start_step) || (step > end_step))
3807                         memset(ecc_calc, 0xff, ecc_bytes);
3808                 else
3809                         chip->ecc.calculate(chip, buf, ecc_calc);
3810 
3811                 /* mask OOB of un-touched subpages by padding 0xFF */
3812                 /* if oob_required, preserve OOB metadata of written subpage */
3813                 if (!oob_required || (step < start_step) || (step > end_step))
3814                         memset(oob_buf, 0xff, oob_bytes);
3815 
3816                 buf += ecc_size;
3817                 ecc_calc += ecc_bytes;
3818                 oob_buf  += oob_bytes;
3819         }
3820 
3821         /* copy calculated ECC for whole page to chip->buffer->oob */
3822         /* this include masked-value(0xFF) for unwritten subpages */
3823         ecc_calc = chip->ecc.calc_buf;
3824         ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
3825                                          chip->ecc.total);
3826         if (ret)
3827                 return ret;
3828 
3829         /* write OOB buffer to NAND device */
3830         ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
3831         if (ret)
3832                 return ret;
3833 
3834         return nand_prog_page_end_op(chip);
3835 }
3836 
3837 
3838 /**
3839  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
3840  * @chip: nand chip info structure
3841  * @buf: data buffer
3842  * @oob_required: must write chip->oob_poi to OOB
3843  * @page: page number to write
3844  *
3845  * The hw generator calculates the error syndrome automatically. Therefore we
3846  * need a special oob layout and handling.
3847  */
3848 static int nand_write_page_syndrome(struct nand_chip *chip, const uint8_t *buf,
3849                                     int oob_required, int page)
3850 {
3851         struct mtd_info *mtd = nand_to_mtd(chip);
3852         int i, eccsize = chip->ecc.size;
3853         int eccbytes = chip->ecc.bytes;
3854         int eccsteps = chip->ecc.steps;
3855         const uint8_t *p = buf;
3856         uint8_t *oob = chip->oob_poi;
3857         int ret;
3858 
3859         ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
3860         if (ret)
3861                 return ret;
3862 
3863         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3864                 chip->ecc.hwctl(chip, NAND_ECC_WRITE);
3865 
3866                 ret = nand_write_data_op(chip, p, eccsize, false);
3867                 if (ret)
3868                         return ret;
3869 
3870                 if (chip->ecc.prepad) {
3871                         ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
3872                                                  false);
3873                         if (ret)
3874                                 return ret;
3875 
3876                         oob += chip->ecc.prepad;
3877                 }
3878 
3879                 chip->ecc.calculate(chip, p, oob);
3880 
3881                 ret = nand_write_data_op(chip, oob, eccbytes, false);
3882                 if (ret)
3883                         return ret;
3884 
3885                 oob += eccbytes;
3886 
3887                 if (chip->ecc.postpad) {
3888                         ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
3889                                                  false);
3890                         if (ret)
3891                                 return ret;
3892 
3893                         oob += chip->ecc.postpad;
3894                 }
3895         }
3896 
3897         /* Calculate remaining oob bytes */
3898         i = mtd->oobsize - (oob - chip->oob_poi);
3899         if (i) {
3900                 ret = nand_write_data_op(chip, oob, i, false);
3901                 if (ret)
3902                         return ret;
3903         }
3904 
3905         return nand_prog_page_end_op(chip);
3906 }
3907 
3908 /**
3909  * nand_write_page - write one page
3910  * @chip: NAND chip descriptor
3911  * @offset: address offset within the page
3912  * @data_len: length of actual data to be written
3913  * @buf: the data to write
3914  * @oob_required: must write chip->oob_poi to OOB
3915  * @page: page number to write
3916  * @raw: use _raw version of write_page
3917  */
3918 static int nand_write_page(struct nand_chip *chip, uint32_t offset,
3919                            int data_len, const uint8_t *buf, int oob_required,
3920                            int page, int raw)
3921 {
3922         struct mtd_info *mtd = nand_to_mtd(chip);
3923         int status, subpage;
3924 
3925         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3926                 chip->ecc.write_subpage)
3927                 subpage = offset || (data_len < mtd->writesize);
3928         else
3929                 subpage = 0;
3930 
3931         if (unlikely(raw))
3932                 status = chip->ecc.write_page_raw(chip, buf, oob_required,
3933                                                   page);
3934         else if (subpage)
3935                 status = chip->ecc.write_subpage(chip, offset, data_len, buf,
3936                                                  oob_required, page);
3937         else
3938                 status = chip->ecc.write_page(chip, buf, oob_required, page);
3939 
3940         if (status < 0)
3941                 return status;
3942 
3943         return 0;
3944 }
3945 
3946 #define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)
3947 
3948 /**
3949  * nand_do_write_ops - [INTERN] NAND write with ECC
3950  * @chip: NAND chip object
3951  * @to: offset to write to
3952  * @ops: oob operations description structure
3953  *
3954  * NAND write with ECC.
3955  */
3956 static int nand_do_write_ops(struct nand_chip *chip, loff_t to,
3957                              struct mtd_oob_ops *ops)
3958 {
3959         struct mtd_info *mtd = nand_to_mtd(chip);
3960         int chipnr, realpage, page, column;
3961         uint32_t writelen = ops->len;
3962 
3963         uint32_t oobwritelen = ops->ooblen;
3964         uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
3965 
3966         uint8_t *oob = ops->oobbuf;
3967         uint8_t *buf = ops->datbuf;
3968         int ret;
3969         int oob_required = oob ? 1 : 0;
3970 
3971         ops->retlen = 0;
3972         if (!writelen)
3973                 return 0;
3974 
3975         /* Reject writes, which are not page aligned */
3976         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
3977                 pr_notice("%s: attempt to write non page aligned data\n",
3978                            __func__);
3979                 return -EINVAL;
3980         }
3981 
3982         column = to & (mtd->writesize - 1);
3983 
3984         chipnr = (int)(to >> chip->chip_shift);
3985         nand_select_target(chip, chipnr);
3986 
3987         /* Check, if it is write protected */
3988         if (nand_check_wp(chip)) {
3989                 ret = -EIO;
3990                 goto err_out;
3991         }
3992 
3993         realpage = (int)(to >> chip->page_shift);
3994         page = realpage & chip->pagemask;
3995 
3996         /* Invalidate the page cache, when we write to the cached page */
3997         if (to <= ((loff_t)chip->pagecache.page << chip->page_shift) &&
3998             ((loff_t)chip->pagecache.page << chip->page_shift) < (to + ops->len))
3999                 chip->pagecache.page = -1;
4000 
4001         /* Don't allow multipage oob writes with offset */
4002         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
4003                 ret = -EINVAL;
4004                 goto err_out;
4005         }
4006 
4007         while (1) {
4008                 int bytes = mtd->writesize;
4009                 uint8_t *wbuf = buf;
4010                 int use_bufpoi;
4011                 int part_pagewr = (column || writelen < mtd->writesize);
4012 
4013                 if (part_pagewr)
4014                         use_bufpoi = 1;
4015                 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
4016                         use_bufpoi = !virt_addr_valid(buf) ||
4017                                      !IS_ALIGNED((unsigned long)buf,
4018                                                  chip->buf_align);
4019                 else
4020                         use_bufpoi = 0;
4021 
4022                 /* Partial page write?, or need to use bounce buffer */
4023                 if (use_bufpoi) {
4024                         pr_debug("%s: using write bounce buffer for buf@%p\n",
4025                                          __func__, buf);
4026                         if (part_pagewr)
4027                                 bytes = min_t(int, bytes - column, writelen);
4028                         wbuf = nand_get_data_buf(chip);
4029                         memset(wbuf, 0xff, mtd->writesize);
4030                         memcpy(&wbuf[column], buf, bytes);
4031                 }
4032 
4033                 if (unlikely(oob)) {
4034                         size_t len = min(oobwritelen, oobmaxlen);
4035                         oob = nand_fill_oob(chip, oob, len, ops);
4036                         oobwritelen -= len;
4037                 } else {
4038                         /* We still need to erase leftover OOB data */
4039                         memset(chip->oob_poi, 0xff, mtd->oobsize);
4040                 }
4041 
4042                 ret = nand_write_page(chip, column, bytes, wbuf,
4043                                       oob_required, page,
4044                                       (ops->mode == MTD_OPS_RAW));
4045                 if (ret)
4046                         break;
4047 
4048                 writelen -= bytes;
4049                 if (!writelen)
4050                         break;
4051 
4052                 column = 0;
4053                 buf += bytes;
4054                 realpage++;
4055 
4056                 page = realpage & chip->pagemask;
4057                 /* Check, if we cross a chip boundary */
4058                 if (!page) {
4059                         chipnr++;
4060                         nand_deselect_target(chip);
4061                         nand_select_target(chip, chipnr);
4062                 }
4063         }
4064 
4065         ops->retlen = ops->len - writelen;
4066         if (unlikely(oob))
4067                 ops->oobretlen = ops->ooblen;
4068 
4069 err_out:
4070         nand_deselect_target(chip);
4071         return ret;
4072 }
4073 
4074 /**
4075  * panic_nand_write - [MTD Interface] NAND write with ECC
4076  * @mtd: MTD device structure
4077  * @to: offset to write to
4078  * @len: number of bytes to write
4079  * @retlen: pointer to variable to store the number of written bytes
4080  * @buf: the data to write
4081  *
4082  * NAND write with ECC. Used when performing writes in interrupt context, this
4083  * may for example be called by mtdoops when writing an oops while in panic.
4084  */
4085 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
4086                             size_t *retlen, const uint8_t *buf)
4087 {
4088         struct nand_chip *chip = mtd_to_nand(mtd);
4089         int chipnr = (int)(to >> chip->chip_shift);
4090         struct mtd_oob_ops ops;
4091         int ret;
4092 
4093         nand_select_target(chip, chipnr);
4094 
4095         /* Wait for the device to get ready */
4096         panic_nand_wait(chip, 400);
4097 
4098         memset(&ops, 0, sizeof(ops));
4099         ops.len = len;
4100         ops.datbuf = (uint8_t *)buf;
4101         ops.mode = MTD_OPS_PLACE_OOB;
4102 
4103         ret = nand_do_write_ops(chip, to, &ops);
4104 
4105         *retlen = ops.retlen;
4106         return ret;
4107 }
4108 
4109 /**
4110  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
4111  * @mtd: MTD device structure
4112  * @to: offset to write to
4113  * @ops: oob operation description structure
4114  */
4115 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
4116                           struct mtd_oob_ops *ops)
4117 {
4118         struct nand_chip *chip = mtd_to_nand(mtd);
4119         int ret;
4120 
4121         ops->retlen = 0;
4122 
4123         ret = nand_get_device(chip);
4124         if (ret)
4125                 return ret;
4126 
4127         switch (ops->mode) {
4128         case MTD_OPS_PLACE_OOB:
4129         case MTD_OPS_AUTO_OOB:
4130         case MTD_OPS_RAW:
4131                 break;
4132 
4133         default:
4134                 goto out;
4135         }
4136 
4137         if (!ops->datbuf)
4138                 ret = nand_do_write_oob(chip, to, ops);
4139         else
4140                 ret = nand_do_write_ops(chip, to, ops);
4141 
4142 out:
4143         nand_release_device(chip);
4144         return ret;
4145 }
4146 
4147 /**
4148  * nand_erase - [MTD Interface] erase block(s)
4149  * @mtd: MTD device structure
4150  * @instr: erase instruction
4151  *
4152  * Erase one ore more blocks.
4153  */
4154 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
4155 {
4156         return nand_erase_nand(mtd_to_nand(mtd), instr, 0);
4157 }
4158 
4159 /**
4160  * nand_erase_nand - [INTERN] erase block(s)
4161  * @chip: NAND chip object
4162  * @instr: erase instruction
4163  * @allowbbt: allow erasing the bbt area
4164  *
4165  * Erase one ore more blocks.
4166  */
4167 int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
4168                     int allowbbt)
4169 {
4170         int page, pages_per_block, ret, chipnr;
4171         loff_t len;
4172 
4173         pr_debug("%s: start = 0x%012llx, len = %llu\n",
4174                         __func__, (unsigned long long)instr->addr,
4175                         (unsigned long long)instr->len);
4176 
4177         if (check_offs_len(chip, instr->addr, instr->len))
4178                 return -EINVAL;
4179 
4180         /* Grab the lock and see if the device is available */
4181         ret = nand_get_device(chip);
4182         if (ret)
4183                 return ret;
4184 
4185         /* Shift to get first page */
4186         page = (int)(instr->addr >> chip->page_shift);
4187         chipnr = (int)(instr->addr >> chip->chip_shift);
4188 
4189         /* Calculate pages in each block */
4190         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
4191 
4192         /* Select the NAND device */
4193         nand_select_target(chip, chipnr);
4194 
4195         /* Check, if it is write protected */
4196         if (nand_check_wp(chip)) {
4197                 pr_debug("%s: device is write protected!\n",
4198                                 __func__);
4199                 ret = -EIO;
4200                 goto erase_exit;
4201         }
4202 
4203         /* Loop through the pages */
4204         len = instr->len;
4205 
4206         while (len) {
4207                 /* Check if we have a bad block, we do not erase bad blocks! */
4208                 if (nand_block_checkbad(chip, ((loff_t) page) <<
4209                                         chip->page_shift, allowbbt)) {
4210                         pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
4211                                     __func__, page);
4212                         ret = -EIO;
4213                         goto erase_exit;
4214                 }
4215 
4216                 /*
4217                  * Invalidate the page cache, if we erase the block which
4218                  * contains the current cached page.
4219                  */
4220                 if (page <= chip->pagecache.page && chip->pagecache.page <
4221                     (page + pages_per_block))
4222                         chip->pagecache.page = -1;
4223 
4224                 ret = nand_erase_op(chip, (page & chip->pagemask) >>
4225                                     (chip->phys_erase_shift - chip->page_shift));
4226                 if (ret) {
4227                         pr_debug("%s: failed erase, page 0x%08x\n",
4228                                         __func__, page);
4229                         instr->fail_addr =
4230                                 ((loff_t)page << chip->page_shift);
4231                         goto erase_exit;
4232                 }
4233 
4234                 /* Increment page address and decrement length */
4235                 len -= (1ULL << chip->phys_erase_shift);
4236                 page += pages_per_block;
4237 
4238                 /* Check, if we cross a chip boundary */
4239                 if (len && !(page & chip->pagemask)) {
4240                         chipnr++;
4241                         nand_deselect_target(chip);
4242                         nand_select_target(chip, chipnr);
4243                 }
4244         }
4245 
4246         ret = 0;
4247 erase_exit:
4248 
4249         /* Deselect and wake up anyone waiting on the device */
4250         nand_deselect_target(chip);
4251         nand_release_device(chip);
4252 
4253         /* Return more or less happy */
4254         return ret;
4255 }
4256 
4257 /**
4258  * nand_sync - [MTD Interface] sync
4259  * @mtd: MTD device structure
4260  *
4261  * Sync is actually a wait for chip ready function.
4262  */
4263 static void nand_sync(struct mtd_info *mtd)
4264 {
4265         struct nand_chip *chip = mtd_to_nand(mtd);
4266 
4267         pr_debug("%s: called\n", __func__);
4268 
4269         /* Grab the lock and see if the device is available */
4270         WARN_ON(nand_get_device(chip));
4271         /* Release it and go back */
4272         nand_release_device(chip);
4273 }
4274 
4275 /**
4276  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
4277  * @mtd: MTD device structure
4278  * @offs: offset relative to mtd start
4279  */
4280 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
4281 {
4282         struct nand_chip *chip = mtd_to_nand(mtd);
4283         int chipnr = (int)(offs >> chip->chip_shift);
4284         int ret;
4285 
4286         /* Select the NAND device */
4287         ret = nand_get_device(chip);
4288         if (ret)
4289                 return ret;
4290 
4291         nand_select_target(chip, chipnr);
4292 
4293         ret = nand_block_checkbad(chip, offs, 0);
4294 
4295         nand_deselect_target(chip);
4296         nand_release_device(chip);
4297 
4298         return ret;
4299 }
4300 
4301 /**
4302  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
4303  * @mtd: MTD device structure
4304  * @ofs: offset relative to mtd start
4305  */
4306 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
4307 {
4308         int ret;
4309 
4310         ret = nand_block_isbad(mtd, ofs);
4311         if (ret) {
4312                 /* If it was bad already, return success and do nothing */
4313                 if (ret > 0)
4314                         return 0;
4315                 return ret;
4316         }
4317 
4318         return nand_block_markbad_lowlevel(mtd_to_nand(mtd), ofs);
4319 }
4320 
4321 /**
4322  * nand_suspend - [MTD Interface] Suspend the NAND flash
4323  * @mtd: MTD device structure
4324  */
4325 static int nand_suspend(struct mtd_info *mtd)
4326 {
4327         struct nand_chip *chip = mtd_to_nand(mtd);
4328 
4329         mutex_lock(&chip->lock);
4330         chip->suspended = 1;
4331         mutex_unlock(&chip->lock);
4332 
4333         return 0;
4334 }
4335 
4336 /**
4337  * nand_resume - [MTD Interface] Resume the NAND flash
4338  * @mtd: MTD device structure
4339  */
4340 static void nand_resume(struct mtd_info *mtd)
4341 {
4342         struct nand_chip *chip = mtd_to_nand(mtd);
4343 
4344         mutex_lock(&chip->lock);
4345         if (chip->suspended)
4346                 chip->suspended = 0;
4347         else
4348                 pr_err("%s called for a chip which is not in suspended state\n",
4349                         __func__);
4350         mutex_unlock(&chip->lock);
4351 }
4352 
4353 /**
4354  * nand_shutdown - [MTD Interface] Finish the current NAND operation and
4355  *                 prevent further operations
4356  * @mtd: MTD device structure
4357  */
4358 static void nand_shutdown(struct mtd_info *mtd)
4359 {
4360         nand_suspend(mtd);
4361 }
4362 
4363 /* Set default functions */
4364 static void nand_set_defaults(struct nand_chip *chip)
4365 {
4366         /* If no controller is provided, use the dummy, legacy one. */
4367         if (!chip->controller) {
4368                 chip->controller = &chip->legacy.dummy_controller;
4369                 nand_controller_init(chip->controller);
4370         }
4371 
4372         nand_legacy_set_defaults(chip);
4373 
4374         if (!chip->buf_align)
4375                 chip->buf_align = 1;
4376 }
4377 
4378 /* Sanitize ONFI strings so we can safely print them */
4379 void sanitize_string(uint8_t *s, size_t len)
4380 {
4381         ssize_t i;
4382 
4383         /* Null terminate */
4384         s[len - 1] = 0;
4385 
4386         /* Remove non printable chars */
4387         for (i = 0; i < len - 1; i++) {
4388                 if (s[i] < ' ' || s[i] > 127)
4389                         s[i] = '?';
4390         }
4391 
4392         /* Remove trailing spaces */
4393         strim(s);
4394 }
4395 
4396 /*
4397  * nand_id_has_period - Check if an ID string has a given wraparound period
4398  * @id_data: the ID string
4399  * @arrlen: the length of the @id_data array
4400  * @period: the period of repitition
4401  *
4402  * Check if an ID string is repeated within a given sequence of bytes at
4403  * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
4404  * period of 3). This is a helper function for nand_id_len(). Returns non-zero
4405  * if the repetition has a period of @period; otherwise, returns zero.
4406  */
4407 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
4408 {
4409         int i, j;
4410         for (i = 0; i < period; i++)
4411                 for (j = i + period; j < arrlen; j += period)
4412                         if (id_data[i] != id_data[j])
4413                                 return 0;
4414         return 1;
4415 }
4416 
4417 /*
4418  * nand_id_len - Get the length of an ID string returned by CMD_READID
4419  * @id_data: the ID string
4420  * @arrlen: the length of the @id_data array
4421 
4422  * Returns the length of the ID string, according to known wraparound/trailing
4423  * zero patterns. If no pattern exists, returns the length of the array.
4424  */
4425 static int nand_id_len(u8 *id_data, int arrlen)
4426 {
4427         int last_nonzero, period;
4428 
4429         /* Find last non-zero byte */
4430         for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
4431                 if (id_data[last_nonzero])
4432                         break;
4433 
4434         /* All zeros */
4435         if (last_nonzero < 0)
4436                 return 0;
4437 
4438         /* Calculate wraparound period */
4439         for (period = 1; period < arrlen; period++)
4440                 if (nand_id_has_period(id_data, arrlen, period))
4441                         break;
4442 
4443         /* There's a repeated pattern */
4444         if (period < arrlen)
4445                 return period;
4446 
4447         /* There are trailing zeros */
4448         if (last_nonzero < arrlen - 1)
4449                 return last_nonzero + 1;
4450 
4451         /* No pattern detected */
4452         return arrlen;
4453 }
4454 
4455 /* Extract the bits of per cell from the 3rd byte of the extended ID */
4456 static int nand_get_bits_per_cell(u8 cellinfo)
4457 {
4458         int bits;
4459 
4460         bits = cellinfo & NAND_CI_CELLTYPE_MSK;
4461         bits >>= NAND_CI_CELLTYPE_SHIFT;
4462         return bits + 1;
4463 }
4464 
4465 /*
4466  * Many new NAND share similar device ID codes, which represent the size of the
4467  * chip. The rest of the parameters must be decoded according to generic or
4468  * manufacturer-specific "extended ID" decoding patterns.
4469  */
4470 void nand_decode_ext_id(struct nand_chip *chip)
4471 {
4472         struct nand_memory_organization *memorg;
4473         struct mtd_info *mtd = nand_to_mtd(chip);
4474         int extid;
4475         u8 *id_data = chip->id.data;
4476 
4477         memorg = nanddev_get_memorg(&chip->base);
4478 
4479         /* The 3rd id byte holds MLC / multichip data */
4480         memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
4481         /* The 4th id byte is the important one */
4482         extid = id_data[3];
4483 
4484         /* Calc pagesize */
4485         memorg->pagesize = 1024 << (extid & 0x03);
4486         mtd->writesize = memorg->pagesize;
4487         extid >>= 2;
4488         /* Calc oobsize */
4489         memorg->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
4490         mtd->oobsize = memorg->oobsize;
4491         extid >>= 2;
4492         /* Calc blocksize. Blocksize is multiples of 64KiB */
4493         memorg->pages_per_eraseblock = ((64 * 1024) << (extid & 0x03)) /
4494                                        memorg->pagesize;
4495         mtd->erasesize = (64 * 1024) << (extid & 0x03);
4496         extid >>= 2;
4497         /* Get buswidth information */
4498         if (extid & 0x1)
4499                 chip->options |= NAND_BUSWIDTH_16;
4500 }
4501 EXPORT_SYMBOL_GPL(nand_decode_ext_id);
4502 
4503 /*
4504  * Old devices have chip data hardcoded in the device ID table. nand_decode_id
4505  * decodes a matching ID table entry and assigns the MTD size parameters for
4506  * the chip.
4507  */
4508 static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)
4509 {
4510         struct mtd_info *mtd = nand_to_mtd(chip);
4511         struct nand_memory_organization *memorg;
4512 
4513         memorg = nanddev_get_memorg(&chip->base);
4514 
4515         memorg->pages_per_eraseblock = type->erasesize / type->pagesize;
4516         mtd->erasesize = type->erasesize;
4517         memorg->pagesize = type->pagesize;
4518         mtd->writesize = memorg->pagesize;
4519         memorg->oobsize = memorg->pagesize / 32;
4520         mtd->oobsize = memorg->oobsize;
4521 
4522         /* All legacy ID NAND are small-page, SLC */
4523         memorg->bits_per_cell = 1;
4524 }
4525 
4526 /*
4527  * Set the bad block marker/indicator (BBM/BBI) patterns according to some
4528  * heuristic patterns using various detected parameters (e.g., manufacturer,
4529  * page size, cell-type information).
4530  */
4531 static void nand_decode_bbm_options(struct nand_chip *chip)
4532 {
4533         struct mtd_info *mtd = nand_to_mtd(chip);
4534 
4535         /* Set the bad block position */
4536         if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
4537                 chip->badblockpos = NAND_BBM_POS_LARGE;
4538         else
4539                 chip->badblockpos = NAND_BBM_POS_SMALL;
4540 }
4541 
4542 static inline bool is_full_id_nand(struct nand_flash_dev *type)
4543 {
4544         return type->id_len;
4545 }
4546 
4547 static bool find_full_id_nand(struct nand_chip *chip,
4548                               struct nand_flash_dev *type)
4549 {
4550         struct mtd_info *mtd = nand_to_mtd(chip);
4551         struct nand_memory_organization *memorg;
4552         u8 *id_data = chip->id.data;
4553 
4554         memorg = nanddev_get_memorg(&chip->base);
4555 
4556         if (!strncmp(type->id, id_data, type->id_len)) {
4557                 memorg->pagesize = type->pagesize;
4558                 mtd->writesize = memorg->pagesize;
4559                 memorg->pages_per_eraseblock = type->erasesize /
4560                                                type->pagesize;
4561                 mtd->erasesize = type->erasesize;
4562                 memorg->oobsize = type->oobsize;
4563                 mtd->oobsize = memorg->oobsize;
4564 
4565                 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
4566                 memorg->eraseblocks_per_lun =
4567                         DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
4568                                            memorg->pagesize *
4569                                            memorg->pages_per_eraseblock);
4570                 chip->options |= type->options;
4571                 chip->base.eccreq.strength = NAND_ECC_STRENGTH(type);
4572                 chip->base.eccreq.step_size = NAND_ECC_STEP(type);
4573                 chip->onfi_timing_mode_default =
4574                                         type->onfi_timing_mode_default;
4575 
4576                 chip->parameters.model = kstrdup(type->name, GFP_KERNEL);
4577                 if (!chip->parameters.model)
4578                         return false;
4579 
4580                 return true;
4581         }
4582         return false;
4583 }
4584 
4585 /*
4586  * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC
4587  * compliant and does not have a full-id or legacy-id entry in the nand_ids
4588  * table.
4589  */
4590 static void nand_manufacturer_detect(struct nand_chip *chip)
4591 {
4592         /*
4593          * Try manufacturer detection if available and use
4594          * nand_decode_ext_id() otherwise.
4595          */
4596         if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
4597             chip->manufacturer.desc->ops->detect) {
4598                 struct nand_memory_organization *memorg;
4599 
4600                 memorg = nanddev_get_memorg(&chip->base);
4601 
4602                 /* The 3rd id byte holds MLC / multichip data */
4603                 memorg->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);
4604                 chip->manufacturer.desc->ops->detect(chip);
4605         } else {
4606                 nand_decode_ext_id(chip);
4607         }
4608 }
4609 
4610 /*
4611  * Manufacturer initialization. This function is called for all NANDs including
4612  * ONFI and JEDEC compliant ones.
4613  * Manufacturer drivers should put all their specific initialization code in
4614  * their ->init() hook.
4615  */
4616 static int nand_manufacturer_init(struct nand_chip *chip)
4617 {
4618         if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops ||
4619             !chip->manufacturer.desc->ops->init)
4620                 return 0;
4621 
4622         return chip->manufacturer.desc->ops->init(chip);
4623 }
4624 
4625 /*
4626  * Manufacturer cleanup. This function is called for all NANDs including
4627  * ONFI and JEDEC compliant ones.
4628  * Manufacturer drivers should put all their specific cleanup code in their
4629  * ->cleanup() hook.
4630  */
4631 static void nand_manufacturer_cleanup(struct nand_chip *chip)
4632 {
4633         /* Release manufacturer private data */
4634         if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
4635             chip->manufacturer.desc->ops->cleanup)
4636                 chip->manufacturer.desc->ops->cleanup(chip);
4637 }
4638 
4639 static const char *
4640 nand_manufacturer_name(const struct nand_manufacturer *manufacturer)
4641 {
4642         return manufacturer ? manufacturer->name : "Unknown";
4643 }
4644 
4645 /*
4646  * Get the flash and manufacturer id and lookup if the type is supported.
4647  */
4648 static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
4649 {
4650         const struct nand_manufacturer *manufacturer;
4651         struct mtd_info *mtd = nand_to_mtd(chip);
4652         struct nand_memory_organization *memorg;
4653         int busw, ret;
4654         u8 *id_data = chip->id.data;
4655         u8 maf_id, dev_id;
4656         u64 targetsize;
4657 
4658         /*
4659          * Let's start by initializing memorg fields that might be left
4660          * unassigned by the ID-based detection logic.
4661          */
4662         memorg = nanddev_get_memorg(&chip->base);
4663         memorg->planes_per_lun = 1;
4664         memorg->luns_per_target = 1;
4665 
4666         /*
4667          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
4668          * after power-up.
4669          */
4670         ret = nand_reset(chip, 0);
4671         if (ret)
4672                 return ret;
4673 
4674         /* Select the device */
4675         nand_select_target(chip, 0);
4676 
4677         /* Send the command for reading device ID */
4678         ret = nand_readid_op(chip, 0, id_data, 2);
4679         if (ret)
4680                 return ret;
4681 
4682         /* Read manufacturer and device IDs */
4683         maf_id = id_data[0];
4684         dev_id = id_data[1];
4685 
4686         /*
4687          * Try again to make sure, as some systems the bus-hold or other
4688          * interface concerns can cause random data which looks like a
4689          * possibly credible NAND flash to appear. If the two results do
4690          * not match, ignore the device completely.
4691          */
4692 
4693         /* Read entire ID string */
4694         ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data));
4695         if (ret)
4696                 return ret;
4697 
4698         if (id_data[0] != maf_id || id_data[1] != dev_id) {
4699                 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
4700                         maf_id, dev_id, id_data[0], id_data[1]);
4701                 return -ENODEV;
4702         }
4703 
4704         chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data));
4705 
4706         /* Try to identify manufacturer */
4707         manufacturer = nand_get_manufacturer(maf_id);
4708         chip->manufacturer.desc = manufacturer;
4709 
4710         if (!type)
4711                 type = nand_flash_ids;
4712 
4713         /*
4714          * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic
4715          * override it.
4716          * This is required to make sure initial NAND bus width set by the
4717          * NAND controller driver is coherent with the real NAND bus width
4718          * (extracted by auto-detection code).
4719          */
4720         busw = chip->options & NAND_BUSWIDTH_16;
4721 
4722         /*
4723          * The flag is only set (never cleared), reset it to its default value
4724          * before starting auto-detection.
4725          */
4726         chip->options &= ~NAND_BUSWIDTH_16;
4727 
4728         for (; type->name != NULL; type++) {
4729                 if (is_full_id_nand(type)) {
4730                         if (find_full_id_nand(chip, type))
4731                                 goto ident_done;
4732                 } else if (dev_id == type->dev_id) {
4733                         break;
4734                 }
4735         }
4736 
4737         if (!type->name || !type->pagesize) {
4738                 /* Check if the chip is ONFI compliant */
4739                 ret = nand_onfi_detect(chip);
4740                 if (ret < 0)
4741                         return ret;
4742                 else if (ret)
4743                         goto ident_done;
4744 
4745                 /* Check if the chip is JEDEC compliant */
4746                 ret = nand_jedec_detect(chip);
4747                 if (ret < 0)
4748                         return ret;
4749                 else if (ret)
4750                         goto ident_done;
4751         }
4752 
4753         if (!type->name)
4754                 return -ENODEV;
4755 
4756         chip->parameters.model = kstrdup(type->name, GFP_KERNEL);
4757         if (!chip->parameters.model)
4758                 return -ENOMEM;
4759 
4760         if (!type->pagesize)
4761                 nand_manufacturer_detect(chip);
4762         else
4763                 nand_decode_id(chip, type);
4764 
4765         /* Get chip options */
4766         chip->options |= type->options;
4767 
4768         memorg->eraseblocks_per_lun =
4769                         DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
4770                                            memorg->pagesize *
4771                                            memorg->pages_per_eraseblock);
4772 
4773 ident_done:
4774         if (!mtd->name)
4775                 mtd->name = chip->parameters.model;
4776 
4777         if (chip->options & NAND_BUSWIDTH_AUTO) {
4778                 WARN_ON(busw & NAND_BUSWIDTH_16);
4779                 nand_set_defaults(chip);
4780         } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
4781                 /*
4782                  * Check, if buswidth is correct. Hardware drivers should set
4783                  * chip correct!
4784                  */
4785                 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4786                         maf_id, dev_id);
4787                 pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
4788                         mtd->name);
4789                 pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8,
4790                         (chip->options & NAND_BUSWIDTH_16) ? 16 : 8);
4791                 ret = -EINVAL;
4792 
4793                 goto free_detect_allocation;
4794         }
4795 
4796         nand_decode_bbm_options(chip);
4797 
4798         /* Calculate the address shift from the page size */
4799         chip->page_shift = ffs(mtd->writesize) - 1;
4800         /* Convert chipsize to number of pages per chip -1 */
4801         targetsize = nanddev_target_size(&chip->base);
4802         chip->pagemask = (targetsize >> chip->page_shift) - 1;
4803 
4804         chip->bbt_erase_shift = chip->phys_erase_shift =
4805                 ffs(mtd->erasesize) - 1;
4806         if (targetsize & 0xffffffff)
4807                 chip->chip_shift = ffs((unsigned)targetsize) - 1;
4808         else {
4809                 chip->chip_shift = ffs((unsigned)(targetsize >> 32));
4810                 chip->chip_shift += 32 - 1;
4811         }
4812 
4813         if (chip->chip_shift - chip->page_shift > 16)
4814                 chip->options |= NAND_ROW_ADDR_3;
4815 
4816         chip->badblockbits = 8;
4817 
4818         nand_legacy_adjust_cmdfunc(chip);
4819 
4820         pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4821                 maf_id, dev_id);
4822         pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
4823                 chip->parameters.model);
4824         pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
4825                 (int)(targetsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
4826                 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
4827         return 0;
4828 
4829 free_detect_allocation:
4830         kfree(chip->parameters.model);
4831 
4832         return ret;
4833 }
4834 
4835 static const char * const nand_ecc_modes[] = {
4836         [NAND_ECC_NONE]         = "none",
4837         [NAND_ECC_SOFT]         = "soft",
4838         [NAND_ECC_HW]           = "hw",
4839         [NAND_ECC_HW_SYNDROME]  = "hw_syndrome",
4840         [NAND_ECC_HW_OOB_FIRST] = "hw_oob_first",
4841         [NAND_ECC_ON_DIE]       = "on-die",
4842 };
4843 
4844 static int of_get_nand_ecc_mode(struct device_node *np)
4845 {
4846         const char *pm;
4847         int err, i;
4848 
4849         err = of_property_read_string(np, "nand-ecc-mode", &pm);
4850         if (err < 0)
4851                 return err;
4852 
4853         for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++)
4854                 if (!strcasecmp(pm, nand_ecc_modes[i]))
4855                         return i;
4856 
4857         /*
4858          * For backward compatibility we support few obsoleted values that don't
4859          * have their mappings into nand_ecc_modes_t anymore (they were merged
4860          * with other enums).
4861          */
4862         if (!strcasecmp(pm, "soft_bch"))
4863                 return NAND_ECC_SOFT;
4864 
4865         return -ENODEV;
4866 }
4867 
4868 static const char * const nand_ecc_algos[] = {
4869         [NAND_ECC_HAMMING]      = "hamming",
4870         [NAND_ECC_BCH]          = "bch",
4871         [NAND_ECC_RS]           = "rs",
4872 };
4873 
4874 static int of_get_nand_ecc_algo(struct device_node *np)
4875 {
4876         const char *pm;
4877         int err, i;
4878 
4879         err = of_property_read_string(np, "nand-ecc-algo", &pm);
4880         if (!err) {
4881                 for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++)
4882                         if (!strcasecmp(pm, nand_ecc_algos[i]))
4883                                 return i;
4884                 return -ENODEV;
4885         }
4886 
4887         /*
4888          * For backward compatibility we also read "nand-ecc-mode" checking
4889          * for some obsoleted values that were specifying ECC algorithm.
4890          */
4891         err = of_property_read_string(np, "nand-ecc-mode", &pm);
4892         if (err < 0)
4893                 return err;
4894 
4895         if (!strcasecmp(pm, "soft"))
4896                 return NAND_ECC_HAMMING;
4897         else if (!strcasecmp(pm, "soft_bch"))
4898                 return NAND_ECC_BCH;
4899 
4900         return -ENODEV;
4901 }
4902 
4903 static int of_get_nand_ecc_step_size(struct device_node *np)
4904 {
4905         int ret;
4906         u32 val;
4907 
4908         ret = of_property_read_u32(np, "nand-ecc-step-size", &val);
4909         return ret ? ret : val;
4910 }
4911 
4912 static int of_get_nand_ecc_strength(struct device_node *np)
4913 {
4914         int ret;
4915         u32 val;
4916 
4917         ret = of_property_read_u32(np, "nand-ecc-strength", &val);
4918         return ret ? ret : val;
4919 }
4920 
4921 static int of_get_nand_bus_width(struct device_node *np)
4922 {
4923         u32 val;
4924 
4925         if (of_property_read_u32(np, "nand-bus-width", &val))
4926                 return 8;
4927 
4928         switch (val) {
4929         case 8:
4930         case 16:
4931                 return val;
4932         default:
4933                 return -EIO;
4934         }
4935 }
4936 
4937 static bool of_get_nand_on_flash_bbt(struct device_node *np)
4938 {
4939         return of_property_read_bool(np, "nand-on-flash-bbt");
4940 }
4941 
4942 static int nand_dt_init(struct nand_chip *chip)
4943 {
4944         struct device_node *dn = nand_get_flash_node(chip);
4945         int ecc_mode, ecc_algo, ecc_strength, ecc_step;
4946 
4947         if (!dn)
4948                 return 0;
4949 
4950         if (of_get_nand_bus_width(dn) == 16)
4951                 chip->options |= NAND_BUSWIDTH_16;
4952 
4953         if (of_property_read_bool(dn, "nand-is-boot-medium"))
4954                 chip->options |= NAND_IS_BOOT_MEDIUM;
4955 
4956         if (of_get_nand_on_flash_bbt(dn))
4957                 chip->bbt_options |= NAND_BBT_USE_FLASH;
4958 
4959         ecc_mode = of_get_nand_ecc_mode(dn);
4960         ecc_algo = of_get_nand_ecc_algo(dn);
4961         ecc_strength = of_get_nand_ecc_strength(dn);
4962         ecc_step = of_get_nand_ecc_step_size(dn);
4963 
4964         if (ecc_mode >= 0)
4965                 chip->ecc.mode = ecc_mode;
4966 
4967         if (ecc_algo >= 0)
4968                 chip->ecc.algo = ecc_algo;
4969 
4970         if (ecc_strength >= 0)
4971                 chip->ecc.strength = ecc_strength;
4972 
4973         if (ecc_step > 0)
4974                 chip->ecc.size = ecc_step;
4975 
4976         if (of_property_read_bool(dn, "nand-ecc-maximize"))
4977                 chip->ecc.options |= NAND_ECC_MAXIMIZE;
4978 
4979         return 0;
4980 }
4981 
4982 /**
4983  * nand_scan_ident - Scan for the NAND device
4984  * @chip: NAND chip object
4985  * @maxchips: number of chips to scan for
4986  * @table: alternative NAND ID table
4987  *
4988  * This is the first phase of the normal nand_scan() function. It reads the
4989  * flash ID and sets up MTD fields accordingly.
4990  *
4991  * This helper used to be called directly from controller drivers that needed
4992  * to tweak some ECC-related parameters before nand_scan_tail(). This separation
4993  * prevented dynamic allocations during this phase which was unconvenient and
4994  * as been banned for the benefit of the ->init_ecc()/cleanup_ecc() hooks.
4995  */
4996 static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips,
4997                            struct nand_flash_dev *table)
4998 {
4999         struct mtd_info *mtd = nand_to_mtd(chip);
5000         struct nand_memory_organization *memorg;
5001         int nand_maf_id, nand_dev_id;
5002         unsigned int i;
5003         int ret;
5004 
5005         memorg = nanddev_get_memorg(&chip->base);
5006 
5007         /* Assume all dies are deselected when we enter nand_scan_ident(). */
5008         chip->cur_cs = -1;
5009 
5010         mutex_init(&chip->lock);
5011 
5012         /* Enforce the right timings for reset/detection */
5013         onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0);
5014 
5015         ret = nand_dt_init(chip);
5016         if (ret)
5017                 return ret;
5018 
5019         if (!mtd->name && mtd->dev.parent)
5020                 mtd->name = dev_name(mtd->dev.parent);
5021 
5022         /* Set the default functions */
5023         nand_set_defaults(chip);
5024 
5025         ret = nand_legacy_check_hooks(chip);
5026         if (ret)
5027                 return ret;
5028 
5029         memorg->ntargets = maxchips;
5030 
5031         /* Read the flash type */
5032         ret = nand_detect(chip, table);
5033         if (ret) {
5034                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
5035                         pr_warn("No NAND device found\n");
5036                 nand_deselect_target(chip);
5037                 return ret;
5038         }
5039 
5040         nand_maf_id = chip->id.data[0];
5041         nand_dev_id = chip->id.data[1];
5042 
5043         nand_deselect_target(chip);
5044 
5045         /* Check for a chip array */
5046         for (i = 1; i < maxchips; i++) {
5047                 u8 id[2];
5048 
5049                 /* See comment in nand_get_flash_type for reset */
5050                 ret = nand_reset(chip, i);
5051                 if (ret)
5052                         break;
5053 
5054                 nand_select_target(chip, i);
5055                 /* Send the command for reading device ID */
5056                 ret = nand_readid_op(chip, 0, id, sizeof(id));
5057                 if (ret)
5058                         break;
5059                 /* Read manufacturer and device IDs */
5060                 if (nand_maf_id != id[0] || nand_dev_id != id[1]) {
5061                         nand_deselect_target(chip);
5062                         break;
5063                 }
5064                 nand_deselect_target(chip);
5065         }
5066         if (i > 1)
5067                 pr_info("%d chips detected\n", i);
5068 
5069         /* Store the number of chips and calc total size for mtd */
5070         memorg->ntargets = i;
5071         mtd->size = i * nanddev_target_size(&chip->base);
5072 
5073         return 0;
5074 }
5075 
5076 static void nand_scan_ident_cleanup(struct nand_chip *chip)
5077 {
5078         kfree(chip->parameters.model);
5079         kfree(chip->parameters.onfi);
5080 }
5081 
5082 static int nand_set_ecc_soft_ops(struct nand_chip *chip)
5083 {
5084         struct mtd_info *mtd = nand_to_mtd(chip);
5085         struct nand_ecc_ctrl *ecc = &chip->ecc;
5086 
5087         if (WARN_ON(ecc->mode != NAND_ECC_SOFT))
5088                 return -EINVAL;
5089 
5090         switch (ecc->algo) {
5091         case NAND_ECC_HAMMING:
5092                 ecc->calculate = nand_calculate_ecc;
5093                 ecc->correct = nand_correct_data;
5094                 ecc->read_page = nand_read_page_swecc;
5095                 ecc->read_subpage = nand_read_subpage;
5096                 ecc->write_page = nand_write_page_swecc;
5097                 ecc->read_page_raw = nand_read_page_raw;
5098                 ecc->write_page_raw = nand_write_page_raw;
5099                 ecc->read_oob = nand_read_oob_std;
5100                 ecc->write_oob = nand_write_oob_std;
5101                 if (!ecc->size)
5102                         ecc->size = 256;
5103                 ecc->bytes = 3;
5104                 ecc->strength = 1;
5105 
5106                 if (IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC))
5107                         ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
5108 
5109                 return 0;
5110         case NAND_ECC_BCH:
5111                 if (!mtd_nand_has_bch()) {
5112                         WARN(1, "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n");
5113                         return -EINVAL;
5114                 }
5115                 ecc->calculate = nand_bch_calculate_ecc;
5116                 ecc->correct = nand_bch_correct_data;
5117                 ecc->read_page = nand_read_page_swecc;
5118                 ecc->read_subpage = nand_read_subpage;
5119                 ecc->write_page = nand_write_page_swecc;
5120                 ecc->read_page_raw = nand_read_page_raw;
5121                 ecc->write_page_raw = nand_write_page_raw;
5122                 ecc->read_oob = nand_read_oob_std;
5123                 ecc->write_oob = nand_write_oob_std;
5124 
5125                 /*
5126                 * Board driver should supply ecc.size and ecc.strength
5127                 * values to select how many bits are correctable.
5128                 * Otherwise, default to 4 bits for large page devices.
5129                 */
5130                 if (!ecc->size && (mtd->oobsize >= 64)) {
5131                         ecc->size = 512;
5132                         ecc->strength = 4;
5133                 }
5134 
5135                 /*
5136                  * if no ecc placement scheme was provided pickup the default
5137                  * large page one.
5138                  */
5139                 if (!mtd->ooblayout) {
5140                         /* handle large page devices only */
5141                         if (mtd->oobsize < 64) {
5142                                 WARN(1, "OOB layout is required when using software BCH on small pages\n");
5143                                 return -EINVAL;
5144                         }
5145 
5146                         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
5147 
5148                 }
5149 
5150                 /*
5151                  * We can only maximize ECC config when the default layout is
5152                  * used, otherwise we don't know how many bytes can really be
5153                  * used.
5154                  */
5155                 if (mtd->ooblayout == &nand_ooblayout_lp_ops &&
5156                     ecc->options & NAND_ECC_MAXIMIZE) {
5157                         int steps, bytes;
5158 
5159                         /* Always prefer 1k blocks over 512bytes ones */
5160                         ecc->size = 1024;
5161                         steps = mtd->writesize / ecc->size;
5162 
5163                         /* Reserve 2 bytes for the BBM */
5164                         bytes = (mtd->oobsize - 2) / steps;
5165                         ecc->strength = bytes * 8 / fls(8 * ecc->size);
5166                 }
5167 
5168                 /* See nand_bch_init() for details. */
5169                 ecc->bytes = 0;
5170                 ecc->priv = nand_bch_init(mtd);
5171                 if (!ecc->priv) {
5172                         WARN(1, "BCH ECC initialization failed!\n");
5173                         return -EINVAL;
5174                 }
5175                 return 0;
5176         default:
5177                 WARN(1, "Unsupported ECC algorithm!\n");
5178                 return -EINVAL;
5179         }
5180 }
5181 
5182 /**
5183  * nand_check_ecc_caps - check the sanity of preset ECC settings
5184  * @chip: nand chip info structure
5185  * @caps: ECC caps info structure
5186  * @oobavail: OOB size that the ECC engine can use
5187  *
5188  * When ECC step size and strength are already set, check if they are supported
5189  * by the controller and the calculated ECC bytes fit within the chip's OOB.
5190  * On success, the calculated ECC bytes is set.
5191  */
5192 static int
5193 nand_check_ecc_caps(struct nand_chip *chip,
5194                     const struct nand_ecc_caps *caps, int oobavail)
5195 {
5196         struct mtd_info *mtd = nand_to_mtd(chip);
5197         const struct nand_ecc_step_info *stepinfo;
5198         int preset_step = chip->ecc.size;
5199         int preset_strength = chip->ecc.strength;
5200         int ecc_bytes, nsteps = mtd->writesize / preset_step;
5201         int i, j;
5202 
5203         for (i = 0; i < caps->nstepinfos; i++) {
5204                 stepinfo = &caps->stepinfos[i];
5205 
5206                 if (stepinfo->stepsize != preset_step)
5207                         continue;
5208 
5209                 for (j = 0; j < stepinfo->nstrengths; j++) {
5210                         if (stepinfo->strengths[j] != preset_strength)
5211                                 continue;
5212 
5213                         ecc_bytes = caps->calc_ecc_bytes(preset_step,
5214                                                          preset_strength);
5215                         if (WARN_ON_ONCE(ecc_bytes < 0))
5216                                 return ecc_bytes;
5217 
5218                         if (ecc_bytes * nsteps > oobavail) {
5219                                 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
5220                                        preset_step, preset_strength);
5221                                 return -ENOSPC;
5222                         }
5223 
5224                         chip->ecc.bytes = ecc_bytes;
5225 
5226                         return 0;
5227                 }
5228         }
5229 
5230         pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
5231                preset_step, preset_strength);
5232 
5233         return -ENOTSUPP;
5234 }
5235 
5236 /**
5237  * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
5238  * @chip: nand chip info structure
5239  * @caps: ECC engine caps info structure
5240  * @oobavail: OOB size that the ECC engine can use
5241  *
5242  * If a chip's ECC requirement is provided, try to meet it with the least
5243  * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
5244  * On success, the chosen ECC settings are set.
5245  */
5246 static int
5247 nand_match_ecc_req(struct nand_chip *chip,
5248                    const struct nand_ecc_caps *caps, int oobavail)
5249 {
5250         struct mtd_info *mtd = nand_to_mtd(chip);
5251         const struct nand_ecc_step_info *stepinfo;
5252         int req_step = chip->base.eccreq.step_size;
5253         int req_strength = chip->base.eccreq.strength;
5254         int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
5255         int best_step, best_strength, best_ecc_bytes;
5256         int best_ecc_bytes_total = INT_MAX;
5257         int i, j;
5258 
5259         /* No information provided by the NAND chip */
5260         if (!req_step || !req_strength)
5261                 return -ENOTSUPP;
5262 
5263         /* number of correctable bits the chip requires in a page */
5264         req_corr = mtd->writesize / req_step * req_strength;
5265 
5266         for (i = 0; i < caps->nstepinfos; i++) {
5267                 stepinfo = &caps->stepinfos[i];
5268                 step_size = stepinfo->stepsize;
5269 
5270                 for (j = 0; j < stepinfo->nstrengths; j++) {
5271                         strength = stepinfo->strengths[j];
5272 
5273                         /*
5274                          * If both step size and strength are smaller than the
5275                          * chip's requirement, it is not easy to compare the
5276                          * resulted reliability.
5277                          */
5278                         if (step_size < req_step && strength < req_strength)
5279                                 continue;
5280 
5281                         if (mtd->writesize % step_size)
5282                                 continue;
5283 
5284                         nsteps = mtd->writesize / step_size;
5285 
5286                         ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
5287                         if (WARN_ON_ONCE(ecc_bytes < 0))
5288                                 continue;
5289                         ecc_bytes_total = ecc_bytes * nsteps;
5290 
5291                         if (ecc_bytes_total > oobavail ||
5292                             strength * nsteps < req_corr)
5293                                 continue;
5294 
5295                         /*
5296                          * We assume the best is to meet the chip's requrement
5297                          * with the least number of ECC bytes.
5298                          */
5299                         if (ecc_bytes_total < best_ecc_bytes_total) {
5300                                 best_ecc_bytes_total = ecc_bytes_total;
5301                                 best_step = step_size;
5302                                 best_strength = strength;
5303                                 best_ecc_bytes = ecc_bytes;
5304                         }
5305                 }
5306         }
5307 
5308         if (best_ecc_bytes_total == INT_MAX)
5309                 return -ENOTSUPP;
5310 
5311         chip->ecc.size = best_step;
5312         chip->ecc.strength = best_strength;
5313         chip->ecc.bytes = best_ecc_bytes;
5314 
5315         return 0;
5316 }
5317 
5318 /**
5319  * nand_maximize_ecc - choose the max ECC strength available
5320  * @chip: nand chip info structure
5321  * @caps: ECC engine caps info structure
5322  * @oobavail: OOB size that the ECC engine can use
5323  *
5324  * Choose the max ECC strength that is supported on the controller, and can fit
5325  * within the chip's OOB.  On success, the chosen ECC settings are set.
5326  */
5327 static int
5328 nand_maximize_ecc(struct nand_chip *chip,
5329                   const struct nand_ecc_caps *caps, int oobavail)
5330 {
5331         struct mtd_info *mtd = nand_to_mtd(chip);
5332         const struct nand_ecc_step_info *stepinfo;
5333         int step_size, strength, nsteps, ecc_bytes, corr;
5334         int best_corr = 0;
5335         int best_step = 0;
5336         int best_strength, best_ecc_bytes;
5337         int i, j;
5338 
5339         for (i = 0; i < caps->nstepinfos; i++) {
5340                 stepinfo = &caps->stepinfos[i];
5341                 step_size = stepinfo->stepsize;
5342 
5343                 /* If chip->ecc.size is already set, respect it */
5344                 if (chip->ecc.size && step_size != chip->ecc.size)
5345                         continue;
5346 
5347                 for (j = 0; j < stepinfo->nstrengths; j++) {
5348                         strength = stepinfo->strengths[j];
5349 
5350                         if (mtd->writesize % step_size)
5351                                 continue;
5352 
5353                         nsteps = mtd->writesize / step_size;
5354 
5355                         ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
5356                         if (WARN_ON_ONCE(ecc_bytes < 0))
5357                                 continue;
5358 
5359                         if (ecc_bytes * nsteps > oobavail)
5360                                 continue;
5361 
5362                         corr = strength * nsteps;
5363 
5364                         /*
5365                          * If the number of correctable bits is the same,
5366                          * bigger step_size has more reliability.
5367                          */
5368                         if (corr > best_corr ||
5369                             (corr == best_corr && step_size > best_step)) {
5370                                 best_corr = corr;
5371                                 best_step = step_size;
5372                                 best_strength = strength;
5373                                 best_ecc_bytes = ecc_bytes;
5374                         }
5375                 }
5376         }
5377 
5378         if (!best_corr)
5379                 return -ENOTSUPP;
5380 
5381         chip->ecc.size = best_step;
5382         chip->ecc.strength = best_strength;
5383         chip->ecc.bytes = best_ecc_bytes;
5384 
5385         return 0;
5386 }
5387 
5388 /**
5389  * nand_ecc_choose_conf - Set the ECC strength and ECC step size
5390  * @chip: nand chip info structure
5391  * @caps: ECC engine caps info structure
5392  * @oobavail: OOB size that the ECC engine can use
5393  *
5394  * Choose the ECC configuration according to following logic
5395  *
5396  * 1. If both ECC step size and ECC strength are already set (usually by DT)
5397  *    then check if it is supported by this controller.
5398  * 2. If NAND_ECC_MAXIMIZE is set, then select maximum ECC strength.
5399  * 3. Otherwise, try to match the ECC step size and ECC strength closest
5400  *    to the chip's requirement. If available OOB size can't fit the chip
5401  *    requirement then fallback to the maximum ECC step size and ECC strength.
5402  *
5403  * On success, the chosen ECC settings are set.
5404  */
5405 int nand_ecc_choose_conf(struct nand_chip *chip,
5406                          const struct nand_ecc_caps *caps, int oobavail)
5407 {
5408         struct mtd_info *mtd = nand_to_mtd(chip);
5409 
5410         if (WARN_ON(oobavail < 0 || oobavail > mtd->oobsize))
5411                 return -EINVAL;
5412 
5413         if (chip->ecc.size && chip->ecc.strength)
5414                 return nand_check_ecc_caps(chip, caps, oobavail);
5415 
5416         if (chip->ecc.options & NAND_ECC_MAXIMIZE)
5417                 return nand_maximize_ecc(chip, caps, oobavail);
5418 
5419         if (!nand_match_ecc_req(chip, caps, oobavail))
5420                 return 0;
5421 
5422         return nand_maximize_ecc(chip, caps, oobavail);
5423 }
5424 EXPORT_SYMBOL_GPL(nand_ecc_choose_conf);
5425 
5426 /*
5427  * Check if the chip configuration meet the datasheet requirements.
5428 
5429  * If our configuration corrects A bits per B bytes and the minimum
5430  * required correction level is X bits per Y bytes, then we must ensure
5431  * both of the following are true:
5432  *
5433  * (1) A / B >= X / Y
5434  * (2) A >= X
5435  *
5436  * Requirement (1) ensures we can correct for the required bitflip density.
5437  * Requirement (2) ensures we can correct even when all bitflips are clumped
5438  * in the same sector.
5439  */
5440 static bool nand_ecc_strength_good(struct nand_chip *chip)
5441 {
5442         struct mtd_info *mtd = nand_to_mtd(chip);
5443         struct nand_ecc_ctrl *ecc = &chip->ecc;
5444         int corr, ds_corr;
5445 
5446         if (ecc->size == 0 || chip->base.eccreq.step_size == 0)
5447                 /* Not enough information */
5448                 return true;
5449 
5450         /*
5451          * We get the number of corrected bits per page to compare
5452          * the correction density.
5453          */
5454         corr = (mtd->writesize * ecc->strength) / ecc->size;
5455         ds_corr = (mtd->writesize * chip->base.eccreq.strength) /
5456                   chip->base.eccreq.step_size;
5457 
5458         return corr >= ds_corr && ecc->strength >= chip->base.eccreq.strength;
5459 }
5460 
5461 static int rawnand_erase(struct nand_device *nand, const struct nand_pos *pos)
5462 {
5463         struct nand_chip *chip = container_of(nand, struct nand_chip,
5464                                               base);
5465         unsigned int eb = nanddev_pos_to_row(nand, pos);
5466         int ret;
5467 
5468         eb >>= nand->rowconv.eraseblock_addr_shift;
5469 
5470         nand_select_target(chip, pos->target);
5471         ret = nand_erase_op(chip, eb);
5472         nand_deselect_target(chip);
5473 
5474         return ret;
5475 }
5476 
5477 static int rawnand_markbad(struct nand_device *nand,
5478                            const struct nand_pos *pos)
5479 {
5480         struct nand_chip *chip = container_of(nand, struct nand_chip,
5481                                               base);
5482 
5483         return nand_markbad_bbm(chip, nanddev_pos_to_offs(nand, pos));
5484 }
5485 
5486 static bool rawnand_isbad(struct nand_device *nand, const struct nand_pos *pos)
5487 {
5488         struct nand_chip *chip = container_of(nand, struct nand_chip,
5489                                               base);
5490         int ret;
5491 
5492         nand_select_target(chip, pos->target);
5493         ret = nand_isbad_bbm(chip, nanddev_pos_to_offs(nand, pos));
5494         nand_deselect_target(chip);
5495 
5496         return ret;
5497 }
5498 
5499 static const struct nand_ops rawnand_ops = {
5500         .erase = rawnand_erase,
5501         .markbad = rawnand_markbad,
5502         .isbad = rawnand_isbad,
5503 };
5504 
5505 /**
5506  * nand_scan_tail - Scan for the NAND device
5507  * @chip: NAND chip object
5508  *
5509  * This is the second phase of the normal nand_scan() function. It fills out
5510  * all the uninitialized function pointers with the defaults and scans for a
5511  * bad block table if appropriate.
5512  */
5513 static int nand_scan_tail(struct nand_chip *chip)
5514 {
5515         struct mtd_info *mtd = nand_to_mtd(chip);
5516         struct nand_ecc_ctrl *ecc = &chip->ecc;
5517         int ret, i;
5518 
5519         /* New bad blocks should be marked in OOB, flash-based BBT, or both */
5520         if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
5521                    !(chip->bbt_options & NAND_BBT_USE_FLASH))) {
5522                 return -EINVAL;
5523         }
5524 
5525         chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
5526         if (!chip->data_buf)
5527                 return -ENOMEM;
5528 
5529         /*
5530          * FIXME: some NAND manufacturer drivers expect the first die to be
5531          * selected when manufacturer->init() is called. They should be fixed
5532          * to explictly select the relevant die when interacting with the NAND
5533          * chip.
5534          */
5535         nand_select_target(chip, 0);
5536         ret = nand_manufacturer_init(chip);
5537         nand_deselect_target(chip);
5538         if (ret)
5539                 goto err_free_buf;
5540 
5541         /* Set the internal oob buffer location, just after the page data */
5542         chip->oob_poi = chip->data_buf + mtd->writesize;
5543 
5544         /*
5545          * If no default placement scheme is given, select an appropriate one.
5546          */
5547         if (!mtd->ooblayout &&
5548             !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) {
5549                 switch (mtd->oobsize) {
5550                 case 8:
5551                 case 16:
5552                         mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops);
5553                         break;
5554                 case 64:
5555                 case 128:
5556                         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops);
5557                         break;
5558                 default:
5559                         /*
5560                          * Expose the whole OOB area to users if ECC_NONE
5561                          * is passed. We could do that for all kind of
5562                          * ->oobsize, but we must keep the old large/small
5563                          * page with ECC layout when ->oobsize <= 128 for
5564                          * compatibility reasons.
5565                          */
5566                         if (ecc->mode == NAND_ECC_NONE) {
5567                                 mtd_set_ooblayout(mtd,
5568                                                 &nand_ooblayout_lp_ops);
5569                                 break;
5570                         }
5571 
5572                         WARN(1, "No oob scheme defined for oobsize %d\n",
5573                                 mtd->oobsize);
5574                         ret = -EINVAL;
5575                         goto err_nand_manuf_cleanup;
5576                 }
5577         }
5578 
5579         /*
5580          * Check ECC mode, default to software if 3byte/512byte hardware ECC is
5581          * selected and we have 256 byte pagesize fallback to software ECC
5582          */
5583 
5584         switch (ecc->mode) {
5585         case NAND_ECC_HW_OOB_FIRST:
5586                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
5587                 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
5588                         WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
5589                         ret = -EINVAL;
5590                         goto err_nand_manuf_cleanup;
5591                 }
5592                 if (!ecc->read_page)
5593                         ecc->read_page = nand_read_page_hwecc_oob_first;
5594                 /* fall through */
5595 
5596         case NAND_ECC_HW:
5597                 /* Use standard hwecc read page function? */
5598                 if (!ecc->read_page)
5599                         ecc->read_page = nand_read_page_hwecc;
5600                 if (!ecc->write_page)
5601                         ecc->write_page = nand_write_page_hwecc;
5602                 if (!ecc->read_page_raw)
5603                         ecc->read_page_raw = nand_read_page_raw;
5604                 if (!ecc->write_page_raw)
5605                         ecc->write_page_raw = nand_write_page_raw;
5606                 if (!ecc->read_oob)
5607                         ecc->read_oob = nand_read_oob_std;
5608                 if (!ecc->write_oob)
5609                         ecc->write_oob = nand_write_oob_std;
5610                 if (!ecc->read_subpage)
5611                         ecc->read_subpage = nand_read_subpage;
5612                 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
5613                         ecc->write_subpage = nand_write_subpage_hwecc;
5614                 /* fall through */
5615 
5616         case NAND_ECC_HW_SYNDROME:
5617                 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
5618                     (!ecc->read_page ||
5619                      ecc->read_page == nand_read_page_hwecc ||
5620                      !ecc->write_page ||
5621                      ecc->write_page == nand_write_page_hwecc)) {
5622                         WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
5623                         ret = -EINVAL;
5624                         goto err_nand_manuf_cleanup;
5625                 }
5626                 /* Use standard syndrome read/write page function? */
5627                 if (!ecc->read_page)
5628                         ecc->read_page = nand_read_page_syndrome;
5629                 if (!ecc->write_page)
5630                         ecc->write_page = nand_write_page_syndrome;
5631                 if (!ecc->read_page_raw)
5632                         ecc->read_page_raw = nand_read_page_raw_syndrome;
5633                 if (!ecc->write_page_raw)
5634                         ecc->write_page_raw = nand_write_page_raw_syndrome;
5635                 if (!ecc->read_oob)
5636                         ecc->read_oob = nand_read_oob_syndrome;
5637                 if (!ecc->write_oob)
5638                         ecc->write_oob = nand_write_oob_syndrome;
5639 
5640                 if (mtd->writesize >= ecc->size) {
5641                         if (!ecc->strength) {
5642                                 WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
5643                                 ret = -EINVAL;
5644                                 goto err_nand_manuf_cleanup;
5645                         }
5646                         break;
5647                 }
5648                 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
5649                         ecc->size, mtd->writesize);
5650                 ecc->mode = NAND_ECC_SOFT;
5651                 ecc->algo = NAND_ECC_HAMMING;
5652                 /* fall through */
5653 
5654         case NAND_ECC_SOFT:
5655                 ret = nand_set_ecc_soft_ops(chip);
5656                 if (ret) {
5657                         ret = -EINVAL;
5658                         goto err_nand_manuf_cleanup;
5659                 }
5660                 break;
5661 
5662         case NAND_ECC_ON_DIE:
5663                 if (!ecc->read_page || !ecc->write_page) {
5664                         WARN(1, "No ECC functions supplied; on-die ECC not possible\n");
5665                         ret = -EINVAL;
5666                         goto err_nand_manuf_cleanup;
5667                 }
5668                 if (!ecc->read_oob)
5669                         ecc->read_oob = nand_read_oob_std;
5670                 if (!ecc->write_oob)
5671                         ecc->write_oob = nand_write_oob_std;
5672                 break;
5673 
5674         case NAND_ECC_NONE:
5675                 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
5676                 ecc->read_page = nand_read_page_raw;
5677                 ecc->write_page = nand_write_page_raw;
5678                 ecc->read_oob = nand_read_oob_std;
5679                 ecc->read_page_raw = nand_read_page_raw;
5680                 ecc->write_page_raw = nand_write_page_raw;
5681                 ecc->write_oob = nand_write_oob_std;
5682                 ecc->size = mtd->writesize;
5683                 ecc->bytes = 0;
5684                 ecc->strength = 0;
5685                 break;
5686 
5687         default:
5688                 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode);
5689                 ret = -EINVAL;
5690                 goto err_nand_manuf_cleanup;
5691         }
5692 
5693         if (ecc->correct || ecc->calculate) {
5694                 ecc->calc_buf = kmalloc(mtd->oobsize, GFP_KERNEL);
5695                 ecc->code_buf = kmalloc(mtd->oobsize, GFP_KERNEL);
5696                 if (!ecc->calc_buf || !ecc->code_buf) {
5697                         ret = -ENOMEM;
5698                         goto err_nand_manuf_cleanup;
5699                 }
5700         }
5701 
5702         /* For many systems, the standard OOB write also works for raw */
5703         if (!ecc->read_oob_raw)
5704                 ecc->read_oob_raw = ecc->read_oob;
5705         if (!ecc->write_oob_raw)
5706                 ecc->write_oob_raw = ecc->write_oob;
5707 
5708         /* propagate ecc info to mtd_info */
5709         mtd->ecc_strength = ecc->strength;
5710         mtd->ecc_step_size = ecc->size;
5711 
5712         /*
5713          * Set the number of read / write steps for one page depending on ECC
5714          * mode.
5715          */
5716         ecc->steps = mtd->writesize / ecc->size;
5717         if (ecc->steps * ecc->size != mtd->writesize) {
5718                 WARN(1, "Invalid ECC parameters\n");
5719                 ret = -EINVAL;
5720                 goto err_nand_manuf_cleanup;
5721         }
5722         ecc->total = ecc->steps * ecc->bytes;
5723         if (ecc->total > mtd->oobsize) {
5724                 WARN(1, "Total number of ECC bytes exceeded oobsize\n");
5725                 ret = -EINVAL;
5726                 goto err_nand_manuf_cleanup;
5727         }
5728 
5729         /*
5730          * The number of bytes available for a client to place data into
5731          * the out of band area.
5732          */
5733         ret = mtd_ooblayout_count_freebytes(mtd);
5734         if (ret < 0)
5735                 ret = 0;
5736 
5737         mtd->oobavail = ret;
5738 
5739         /* ECC sanity check: warn if it's too weak */
5740         if (!nand_ecc_strength_good(chip))
5741                 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
5742                         mtd->name);
5743 
5744         /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
5745         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
5746                 switch (ecc->steps) {
5747                 case 2:
5748                         mtd->subpage_sft = 1;
5749                         break;
5750                 case 4:
5751                 case 8:
5752                 case 16:
5753                         mtd->subpage_sft = 2;
5754                         break;
5755                 }
5756         }
5757         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
5758 
5759         /* Invalidate the pagebuffer reference */
5760         chip->pagecache.page = -1;
5761 
5762         /* Large page NAND with SOFT_ECC should support subpage reads */
5763         switch (ecc->mode) {
5764         case NAND_ECC_SOFT:
5765                 if (chip->page_shift > 9)
5766                         chip->options |= NAND_SUBPAGE_READ;
5767                 break;
5768 
5769         default:
5770                 break;
5771         }
5772 
5773         ret = nanddev_init(&chip->base, &rawnand_ops, mtd->owner);
5774         if (ret)
5775                 goto err_nand_manuf_cleanup;
5776 
5777         /* Adjust the MTD_CAP_ flags when NAND_ROM is set. */
5778         if (chip->options & NAND_ROM)
5779                 mtd->flags = MTD_CAP_ROM;
5780 
5781         /* Fill in remaining MTD driver data */
5782         mtd->_erase = nand_erase;
5783         mtd->_point = NULL;
5784         mtd->_unpoint = NULL;
5785         mtd->_panic_write = panic_nand_write;
5786         mtd->_read_oob = nand_read_oob;
5787         mtd->_write_oob = nand_write_oob;
5788         mtd->_sync = nand_sync;
5789         mtd->_lock = NULL;
5790         mtd->_unlock = NULL;
5791         mtd->_suspend = nand_suspend;
5792         mtd->_resume = nand_resume;
5793         mtd->_reboot = nand_shutdown;
5794         mtd->_block_isreserved = nand_block_isreserved;
5795         mtd->_block_isbad = nand_block_isbad;
5796         mtd->_block_markbad = nand_block_markbad;
5797         mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks;
5798 
5799         /*
5800          * Initialize bitflip_threshold to its default prior scan_bbt() call.
5801          * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
5802          * properly set.
5803          */
5804         if (!mtd->bitflip_threshold)
5805                 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
5806 
5807         /* Initialize the ->data_interface field. */
5808         ret = nand_init_data_interface(chip);
5809         if (ret)
5810                 goto err_nanddev_cleanup;
5811 
5812         /* Enter fastest possible mode on all dies. */
5813         for (i = 0; i < nanddev_ntargets(&chip->base); i++) {
5814                 ret = nand_setup_data_interface(chip, i);
5815                 if (ret)
5816                         goto err_nanddev_cleanup;
5817         }
5818 
5819         /* Check, if we should skip the bad block table scan */
5820         if (chip->options & NAND_SKIP_BBTSCAN)
5821                 return 0;
5822 
5823         /* Build bad block table */
5824         ret = nand_create_bbt(chip);
5825         if (ret)
5826                 goto err_nanddev_cleanup;
5827 
5828         return 0;
5829 
5830 
5831 err_nanddev_cleanup:
5832         nanddev_cleanup(&chip->base);
5833 
5834 err_nand_manuf_cleanup:
5835         nand_manufacturer_cleanup(chip);
5836 
5837 err_free_buf:
5838         kfree(chip->data_buf);
5839         kfree(ecc->code_buf);
5840         kfree(ecc->calc_buf);
5841 
5842         return ret;
5843 }
5844 
5845 static int nand_attach(struct nand_chip *chip)
5846 {
5847         if (chip->controller->ops && chip->controller->ops->attach_chip)
5848                 return chip->controller->ops->attach_chip(chip);
5849 
5850         return 0;
5851 }
5852 
5853 static void nand_detach(struct nand_chip *chip)
5854 {
5855         if (chip->controller->ops && chip->controller->ops->detach_chip)
5856                 chip->controller->ops->detach_chip(chip);
5857 }
5858 
5859 /**
5860  * nand_scan_with_ids - [NAND Interface] Scan for the NAND device
5861  * @chip: NAND chip object
5862  * @maxchips: number of chips to scan for.
5863  * @ids: optional flash IDs table
5864  *
5865  * This fills out all the uninitialized function pointers with the defaults.
5866  * The flash ID is read and the mtd/chip structures are filled with the
5867  * appropriate values.
5868  */
5869 int nand_scan_with_ids(struct nand_chip *chip, unsigned int maxchips,
5870                        struct nand_flash_dev *ids)
5871 {
5872         int ret;
5873 
5874         if (!maxchips)
5875                 return -EINVAL;
5876 
5877         ret = nand_scan_ident(chip, maxchips, ids);
5878         if (ret)
5879                 return ret;
5880 
5881         ret = nand_attach(chip);
5882         if (ret)
5883                 goto cleanup_ident;
5884 
5885         ret = nand_scan_tail(chip);
5886         if (ret)
5887                 goto detach_chip;
5888 
5889         return 0;
5890 
5891 detach_chip:
5892         nand_detach(chip);
5893 cleanup_ident:
5894         nand_scan_ident_cleanup(chip);
5895 
5896         return ret;
5897 }
5898 EXPORT_SYMBOL(nand_scan_with_ids);
5899 
5900 /**
5901  * nand_cleanup - [NAND Interface] Free resources held by the NAND device
5902  * @chip: NAND chip object
5903  */
5904 void nand_cleanup(struct nand_chip *chip)
5905 {
5906         if (chip->ecc.mode == NAND_ECC_SOFT &&
5907             chip->ecc.algo == NAND_ECC_BCH)
5908                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
5909 
5910         nanddev_cleanup(&chip->base);
5911 
5912         /* Free bad block table memory */
5913         kfree(chip->bbt);
5914         kfree(chip->data_buf);
5915         kfree(chip->ecc.code_buf);
5916         kfree(chip->ecc.calc_buf);
5917 
5918         /* Free bad block descriptor memory */
5919         if (chip->badblock_pattern && chip->badblock_pattern->options
5920                         & NAND_BBT_DYNAMICSTRUCT)
5921                 kfree(chip->badblock_pattern);
5922 
5923         /* Free manufacturer priv data. */
5924         nand_manufacturer_cleanup(chip);
5925 
5926         /* Free controller specific allocations after chip identification */
5927         nand_detach(chip);
5928 
5929         /* Free identification phase allocations */
5930         nand_scan_ident_cleanup(chip);
5931 }
5932 
5933 EXPORT_SYMBOL_GPL(nand_cleanup);
5934 
5935 /**
5936  * nand_release - [NAND Interface] Unregister the MTD device and free resources
5937  *                held by the NAND device
5938  * @chip: NAND chip object
5939  */
5940 void nand_release(struct nand_chip *chip)
5941 {
5942         mtd_device_unregister(nand_to_mtd(chip));
5943         nand_cleanup(chip);
5944 }
5945 EXPORT_SYMBOL_GPL(nand_release);
5946 
5947 MODULE_LICENSE("GPL");
5948 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
5949 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
5950 MODULE_DESCRIPTION("Generic NAND flash driver code");