1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Freescale GPMI NAND Flash Driver
4 *
5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
6 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
7 */
8 #ifndef __DRIVERS_MTD_NAND_GPMI_NAND_H
9 #define __DRIVERS_MTD_NAND_GPMI_NAND_H
10
11 #include <linux/mtd/rawnand.h>
12 #include <linux/platform_device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmaengine.h>
15
16 #define GPMI_CLK_MAX 5 /* MX6Q needs five clocks */
17 struct resources {
18 void __iomem *gpmi_regs;
19 void __iomem *bch_regs;
20 unsigned int dma_low_channel;
21 unsigned int dma_high_channel;
22 struct clk *clock[GPMI_CLK_MAX];
23 };
24
25 /**
26 * struct bch_geometry - BCH geometry description.
27 * @gf_len: The length of Galois Field. (e.g., 13 or 14)
28 * @ecc_strength: A number that describes the strength of the ECC
29 * algorithm.
30 * @page_size: The size, in bytes, of a physical page, including
31 * both data and OOB.
32 * @metadata_size: The size, in bytes, of the metadata.
33 * @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note
34 * the first chunk in the page includes both data and
35 * metadata, so it's a bit larger than this value.
36 * @ecc_chunk_count: The number of ECC chunks in the page,
37 * @payload_size: The size, in bytes, of the payload buffer.
38 * @auxiliary_size: The size, in bytes, of the auxiliary buffer.
39 * @auxiliary_status_offset: The offset into the auxiliary buffer at which
40 * the ECC status appears.
41 * @block_mark_byte_offset: The byte offset in the ECC-based page view at
42 * which the underlying physical block mark appears.
43 * @block_mark_bit_offset: The bit offset into the ECC-based page view at
44 * which the underlying physical block mark appears.
45 */
46 struct bch_geometry {
47 unsigned int gf_len;
48 unsigned int ecc_strength;
49 unsigned int page_size;
50 unsigned int metadata_size;
51 unsigned int ecc_chunk_size;
52 unsigned int ecc_chunk_count;
53 unsigned int payload_size;
54 unsigned int auxiliary_size;
55 unsigned int auxiliary_status_offset;
56 unsigned int block_mark_byte_offset;
57 unsigned int block_mark_bit_offset;
58 };
59
60 /**
61 * struct boot_rom_geometry - Boot ROM geometry description.
62 * @stride_size_in_pages: The size of a boot block stride, in pages.
63 * @search_area_stride_exponent: The logarithm to base 2 of the size of a
64 * search area in boot block strides.
65 */
66 struct boot_rom_geometry {
67 unsigned int stride_size_in_pages;
68 unsigned int search_area_stride_exponent;
69 };
70
71 enum gpmi_type {
72 IS_MX23,
73 IS_MX28,
74 IS_MX6Q,
75 IS_MX6SX,
76 IS_MX7D,
77 };
78
79 struct gpmi_devdata {
80 enum gpmi_type type;
81 int bch_max_ecc_strength;
82 int max_chain_delay; /* See the async EDO mode */
83 const char * const *clks;
84 const int clks_count;
85 };
86
87 /**
88 * struct gpmi_nfc_hardware_timing - GPMI hardware timing parameters.
89 * @must_apply_timings: Whether controller timings have already been
90 * applied or not (useful only while there is
91 * support for only one chip select)
92 * @clk_rate: The clock rate that must be used to derive the
93 * following parameters
94 * @timing0: HW_GPMI_TIMING0 register
95 * @timing1: HW_GPMI_TIMING1 register
96 * @ctrl1n: HW_GPMI_CTRL1n register
97 */
98 struct gpmi_nfc_hardware_timing {
99 bool must_apply_timings;
100 unsigned long int clk_rate;
101 u32 timing0;
102 u32 timing1;
103 u32 ctrl1n;
104 };
105
106 #define GPMI_MAX_TRANSFERS 8
107
108 struct gpmi_transfer {
109 u8 cmdbuf[8];
110 struct scatterlist sgl;
111 enum dma_data_direction direction;
112 };
113
114 struct gpmi_nand_data {
115 /* Devdata */
116 const struct gpmi_devdata *devdata;
117
118 /* System Interface */
119 struct device *dev;
120 struct platform_device *pdev;
121
122 /* Resources */
123 struct resources resources;
124
125 /* Flash Hardware */
126 struct gpmi_nfc_hardware_timing hw;
127
128 /* BCH */
129 struct bch_geometry bch_geometry;
130 struct completion bch_done;
131
132 /* NAND Boot issue */
133 bool swap_block_mark;
134 struct boot_rom_geometry rom_geometry;
135
136 /* MTD / NAND */
137 struct nand_controller base;
138 struct nand_chip nand;
139
140 struct gpmi_transfer transfers[GPMI_MAX_TRANSFERS];
141 int ntransfers;
142
143 bool bch;
144 uint32_t bch_flashlayout0;
145 uint32_t bch_flashlayout1;
146
147 char *data_buffer_dma;
148
149 void *auxiliary_virt;
150 dma_addr_t auxiliary_phys;
151
152 void *raw_buffer;
153
154 /* DMA channels */
155 #define DMA_CHANS 8
156 struct dma_chan *dma_chans[DMA_CHANS];
157 struct completion dma_done;
158 };
159
160 /* BCH : Status Block Completion Codes */
161 #define STATUS_GOOD 0x00
162 #define STATUS_ERASED 0xff
163 #define STATUS_UNCORRECTABLE 0xfe
164
165 /* Use the devdata to distinguish different Archs. */
166 #define GPMI_IS_MX23(x) ((x)->devdata->type == IS_MX23)
167 #define GPMI_IS_MX28(x) ((x)->devdata->type == IS_MX28)
168 #define GPMI_IS_MX6Q(x) ((x)->devdata->type == IS_MX6Q)
169 #define GPMI_IS_MX6SX(x) ((x)->devdata->type == IS_MX6SX)
170 #define GPMI_IS_MX7D(x) ((x)->devdata->type == IS_MX7D)
171
172 #define GPMI_IS_MX6(x) (GPMI_IS_MX6Q(x) || GPMI_IS_MX6SX(x) || \
173 GPMI_IS_MX7D(x))
174 #define GPMI_IS_MXS(x) (GPMI_IS_MX23(x) || GPMI_IS_MX28(x))
175 #endif