This source file includes following definitions.
- fsmc_ecc1_ooblayout_ecc
- fsmc_ecc1_ooblayout_free
- fsmc_ecc4_ooblayout_ecc
- fsmc_ecc4_ooblayout_free
- nand_to_fsmc
- fsmc_nand_setup
- fsmc_calc_timings
- fsmc_setup_data_interface
- fsmc_enable_hwecc
- fsmc_read_hwecc_ecc4
- fsmc_read_hwecc_ecc1
- count_written_bits
- dma_complete
- dma_xfer
- fsmc_write_buf
- fsmc_read_buf
- fsmc_read_buf_dma
- fsmc_write_buf_dma
- fsmc_exec_op
- fsmc_read_page_hwecc
- fsmc_bch8_correct_data
- filter
- fsmc_nand_probe_config_dt
- fsmc_nand_attach_chip
- fsmc_nand_disable
- fsmc_nand_probe
- fsmc_nand_remove
- fsmc_nand_suspend
- fsmc_nand_resume
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16 #include <linux/clk.h>
17 #include <linux/completion.h>
18 #include <linux/dmaengine.h>
19 #include <linux/dma-direction.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/err.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/resource.h>
25 #include <linux/sched.h>
26 #include <linux/types.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/rawnand.h>
29 #include <linux/mtd/nand_ecc.h>
30 #include <linux/platform_device.h>
31 #include <linux/of.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/io.h>
34 #include <linux/slab.h>
35 #include <linux/amba/bus.h>
36 #include <mtd/mtd-abi.h>
37
38
39 #define CTRL 0x0
40
41 #define BANK_ENABLE BIT(0)
42 #define MUXED BIT(1)
43 #define NOR_DEV (2 << 2)
44 #define WIDTH_16 BIT(4)
45 #define RSTPWRDWN BIT(6)
46 #define WPROT BIT(7)
47 #define WRT_ENABLE BIT(12)
48 #define WAIT_ENB BIT(13)
49
50 #define CTRL_TIM 0x4
51
52
53 #define FSMC_NOR_BANK_SZ 0x8
54 #define FSMC_NOR_REG_SIZE 0x40
55
56 #define FSMC_NOR_REG(base, bank, reg) ((base) + \
57 (FSMC_NOR_BANK_SZ * (bank)) + \
58 (reg))
59
60
61 #define FSMC_PC 0x00
62
63 #define FSMC_RESET BIT(0)
64 #define FSMC_WAITON BIT(1)
65 #define FSMC_ENABLE BIT(2)
66 #define FSMC_DEVTYPE_NAND BIT(3)
67 #define FSMC_DEVWID_16 BIT(4)
68 #define FSMC_ECCEN BIT(6)
69 #define FSMC_ECCPLEN_256 BIT(7)
70 #define FSMC_TCLR_SHIFT (9)
71 #define FSMC_TCLR_MASK (0xF)
72 #define FSMC_TAR_SHIFT (13)
73 #define FSMC_TAR_MASK (0xF)
74 #define STS 0x04
75
76 #define FSMC_CODE_RDY BIT(15)
77 #define COMM 0x08
78
79 #define FSMC_TSET_SHIFT 0
80 #define FSMC_TSET_MASK 0xFF
81 #define FSMC_TWAIT_SHIFT 8
82 #define FSMC_TWAIT_MASK 0xFF
83 #define FSMC_THOLD_SHIFT 16
84 #define FSMC_THOLD_MASK 0xFF
85 #define FSMC_THIZ_SHIFT 24
86 #define FSMC_THIZ_MASK 0xFF
87 #define ATTRIB 0x0C
88 #define IOATA 0x10
89 #define ECC1 0x14
90 #define ECC2 0x18
91 #define ECC3 0x1C
92 #define FSMC_NAND_BANK_SZ 0x20
93
94 #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
95
96 struct fsmc_nand_timings {
97 u8 tclr;
98 u8 tar;
99 u8 thiz;
100 u8 thold;
101 u8 twait;
102 u8 tset;
103 };
104
105 enum access_mode {
106 USE_DMA_ACCESS = 1,
107 USE_WORD_ACCESS,
108 };
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133
134 struct fsmc_nand_data {
135 struct nand_controller base;
136 u32 pid;
137 struct nand_chip nand;
138
139 unsigned int bank;
140 struct device *dev;
141 enum access_mode mode;
142 struct clk *clk;
143
144
145 struct dma_chan *read_dma_chan;
146 struct dma_chan *write_dma_chan;
147 struct completion dma_access_complete;
148
149 struct fsmc_nand_timings *dev_timings;
150
151 dma_addr_t data_pa;
152 void __iomem *data_va;
153 void __iomem *cmd_va;
154 void __iomem *addr_va;
155 void __iomem *regs_va;
156 };
157
158 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
159 struct mtd_oob_region *oobregion)
160 {
161 struct nand_chip *chip = mtd_to_nand(mtd);
162
163 if (section >= chip->ecc.steps)
164 return -ERANGE;
165
166 oobregion->offset = (section * 16) + 2;
167 oobregion->length = 3;
168
169 return 0;
170 }
171
172 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
173 struct mtd_oob_region *oobregion)
174 {
175 struct nand_chip *chip = mtd_to_nand(mtd);
176
177 if (section >= chip->ecc.steps)
178 return -ERANGE;
179
180 oobregion->offset = (section * 16) + 8;
181
182 if (section < chip->ecc.steps - 1)
183 oobregion->length = 8;
184 else
185 oobregion->length = mtd->oobsize - oobregion->offset;
186
187 return 0;
188 }
189
190 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
191 .ecc = fsmc_ecc1_ooblayout_ecc,
192 .free = fsmc_ecc1_ooblayout_free,
193 };
194
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199
200
201 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
202 struct mtd_oob_region *oobregion)
203 {
204 struct nand_chip *chip = mtd_to_nand(mtd);
205
206 if (section >= chip->ecc.steps)
207 return -ERANGE;
208
209 oobregion->length = chip->ecc.bytes;
210
211 if (!section && mtd->writesize <= 512)
212 oobregion->offset = 0;
213 else
214 oobregion->offset = (section * 16) + 2;
215
216 return 0;
217 }
218
219 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
220 struct mtd_oob_region *oobregion)
221 {
222 struct nand_chip *chip = mtd_to_nand(mtd);
223
224 if (section >= chip->ecc.steps)
225 return -ERANGE;
226
227 oobregion->offset = (section * 16) + 15;
228
229 if (section < chip->ecc.steps - 1)
230 oobregion->length = 3;
231 else
232 oobregion->length = mtd->oobsize - oobregion->offset;
233
234 return 0;
235 }
236
237 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
238 .ecc = fsmc_ecc4_ooblayout_ecc,
239 .free = fsmc_ecc4_ooblayout_free,
240 };
241
242 static inline struct fsmc_nand_data *nand_to_fsmc(struct nand_chip *chip)
243 {
244 return container_of(chip, struct fsmc_nand_data, nand);
245 }
246
247
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250
251
252
253 static void fsmc_nand_setup(struct fsmc_nand_data *host,
254 struct fsmc_nand_timings *tims)
255 {
256 u32 value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
257 u32 tclr, tar, thiz, thold, twait, tset;
258
259 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
260 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
261 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
262 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
263 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
264 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
265
266 if (host->nand.options & NAND_BUSWIDTH_16)
267 value |= FSMC_DEVWID_16;
268
269 writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC);
270 writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM);
271 writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB);
272 }
273
274 static int fsmc_calc_timings(struct fsmc_nand_data *host,
275 const struct nand_sdr_timings *sdrt,
276 struct fsmc_nand_timings *tims)
277 {
278 unsigned long hclk = clk_get_rate(host->clk);
279 unsigned long hclkn = NSEC_PER_SEC / hclk;
280 u32 thiz, thold, twait, tset;
281
282 if (sdrt->tRC_min < 30000)
283 return -EOPNOTSUPP;
284
285 tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1;
286 if (tims->tar > FSMC_TAR_MASK)
287 tims->tar = FSMC_TAR_MASK;
288 tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1;
289 if (tims->tclr > FSMC_TCLR_MASK)
290 tims->tclr = FSMC_TCLR_MASK;
291
292 thiz = sdrt->tCS_min - sdrt->tWP_min;
293 tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn);
294
295 thold = sdrt->tDH_min;
296 if (thold < sdrt->tCH_min)
297 thold = sdrt->tCH_min;
298 if (thold < sdrt->tCLH_min)
299 thold = sdrt->tCLH_min;
300 if (thold < sdrt->tWH_min)
301 thold = sdrt->tWH_min;
302 if (thold < sdrt->tALH_min)
303 thold = sdrt->tALH_min;
304 if (thold < sdrt->tREH_min)
305 thold = sdrt->tREH_min;
306 tims->thold = DIV_ROUND_UP(thold / 1000, hclkn);
307 if (tims->thold == 0)
308 tims->thold = 1;
309 else if (tims->thold > FSMC_THOLD_MASK)
310 tims->thold = FSMC_THOLD_MASK;
311
312 twait = max(sdrt->tRP_min, sdrt->tWP_min);
313 tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
314 if (tims->twait == 0)
315 tims->twait = 1;
316 else if (tims->twait > FSMC_TWAIT_MASK)
317 tims->twait = FSMC_TWAIT_MASK;
318
319 tset = max(sdrt->tCS_min - sdrt->tWP_min,
320 sdrt->tCEA_max - sdrt->tREA_max);
321 tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
322 if (tims->tset == 0)
323 tims->tset = 1;
324 else if (tims->tset > FSMC_TSET_MASK)
325 tims->tset = FSMC_TSET_MASK;
326
327 return 0;
328 }
329
330 static int fsmc_setup_data_interface(struct nand_chip *nand, int csline,
331 const struct nand_data_interface *conf)
332 {
333 struct fsmc_nand_data *host = nand_to_fsmc(nand);
334 struct fsmc_nand_timings tims;
335 const struct nand_sdr_timings *sdrt;
336 int ret;
337
338 sdrt = nand_get_sdr_timings(conf);
339 if (IS_ERR(sdrt))
340 return PTR_ERR(sdrt);
341
342 ret = fsmc_calc_timings(host, sdrt, &tims);
343 if (ret)
344 return ret;
345
346 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
347 return 0;
348
349 fsmc_nand_setup(host, &tims);
350
351 return 0;
352 }
353
354
355
356
357 static void fsmc_enable_hwecc(struct nand_chip *chip, int mode)
358 {
359 struct fsmc_nand_data *host = nand_to_fsmc(chip);
360
361 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256,
362 host->regs_va + FSMC_PC);
363 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN,
364 host->regs_va + FSMC_PC);
365 writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN,
366 host->regs_va + FSMC_PC);
367 }
368
369
370
371
372
373
374 static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const u8 *data,
375 u8 *ecc)
376 {
377 struct fsmc_nand_data *host = nand_to_fsmc(chip);
378 u32 ecc_tmp;
379 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
380
381 do {
382 if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY)
383 break;
384
385 cond_resched();
386 } while (!time_after_eq(jiffies, deadline));
387
388 if (time_after_eq(jiffies, deadline)) {
389 dev_err(host->dev, "calculate ecc timed out\n");
390 return -ETIMEDOUT;
391 }
392
393 ecc_tmp = readl_relaxed(host->regs_va + ECC1);
394 ecc[0] = ecc_tmp;
395 ecc[1] = ecc_tmp >> 8;
396 ecc[2] = ecc_tmp >> 16;
397 ecc[3] = ecc_tmp >> 24;
398
399 ecc_tmp = readl_relaxed(host->regs_va + ECC2);
400 ecc[4] = ecc_tmp;
401 ecc[5] = ecc_tmp >> 8;
402 ecc[6] = ecc_tmp >> 16;
403 ecc[7] = ecc_tmp >> 24;
404
405 ecc_tmp = readl_relaxed(host->regs_va + ECC3);
406 ecc[8] = ecc_tmp;
407 ecc[9] = ecc_tmp >> 8;
408 ecc[10] = ecc_tmp >> 16;
409 ecc[11] = ecc_tmp >> 24;
410
411 ecc_tmp = readl_relaxed(host->regs_va + STS);
412 ecc[12] = ecc_tmp >> 16;
413
414 return 0;
415 }
416
417
418
419
420
421
422 static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data,
423 u8 *ecc)
424 {
425 struct fsmc_nand_data *host = nand_to_fsmc(chip);
426 u32 ecc_tmp;
427
428 ecc_tmp = readl_relaxed(host->regs_va + ECC1);
429 ecc[0] = ecc_tmp;
430 ecc[1] = ecc_tmp >> 8;
431 ecc[2] = ecc_tmp >> 16;
432
433 return 0;
434 }
435
436
437 static int count_written_bits(u8 *buff, int size, int max_bits)
438 {
439 int k, written_bits = 0;
440
441 for (k = 0; k < size; k++) {
442 written_bits += hweight8(~buff[k]);
443 if (written_bits > max_bits)
444 break;
445 }
446
447 return written_bits;
448 }
449
450 static void dma_complete(void *param)
451 {
452 struct fsmc_nand_data *host = param;
453
454 complete(&host->dma_access_complete);
455 }
456
457 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
458 enum dma_data_direction direction)
459 {
460 struct dma_chan *chan;
461 struct dma_device *dma_dev;
462 struct dma_async_tx_descriptor *tx;
463 dma_addr_t dma_dst, dma_src, dma_addr;
464 dma_cookie_t cookie;
465 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
466 int ret;
467 unsigned long time_left;
468
469 if (direction == DMA_TO_DEVICE)
470 chan = host->write_dma_chan;
471 else if (direction == DMA_FROM_DEVICE)
472 chan = host->read_dma_chan;
473 else
474 return -EINVAL;
475
476 dma_dev = chan->device;
477 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
478
479 if (direction == DMA_TO_DEVICE) {
480 dma_src = dma_addr;
481 dma_dst = host->data_pa;
482 } else {
483 dma_src = host->data_pa;
484 dma_dst = dma_addr;
485 }
486
487 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
488 len, flags);
489 if (!tx) {
490 dev_err(host->dev, "device_prep_dma_memcpy error\n");
491 ret = -EIO;
492 goto unmap_dma;
493 }
494
495 tx->callback = dma_complete;
496 tx->callback_param = host;
497 cookie = tx->tx_submit(tx);
498
499 ret = dma_submit_error(cookie);
500 if (ret) {
501 dev_err(host->dev, "dma_submit_error %d\n", cookie);
502 goto unmap_dma;
503 }
504
505 dma_async_issue_pending(chan);
506
507 time_left =
508 wait_for_completion_timeout(&host->dma_access_complete,
509 msecs_to_jiffies(3000));
510 if (time_left == 0) {
511 dmaengine_terminate_all(chan);
512 dev_err(host->dev, "wait_for_completion_timeout\n");
513 ret = -ETIMEDOUT;
514 goto unmap_dma;
515 }
516
517 ret = 0;
518
519 unmap_dma:
520 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
521
522 return ret;
523 }
524
525
526
527
528
529
530
531 static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf,
532 int len)
533 {
534 int i;
535
536 if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
537 IS_ALIGNED(len, sizeof(u32))) {
538 u32 *p = (u32 *)buf;
539
540 len = len >> 2;
541 for (i = 0; i < len; i++)
542 writel_relaxed(p[i], host->data_va);
543 } else {
544 for (i = 0; i < len; i++)
545 writeb_relaxed(buf[i], host->data_va);
546 }
547 }
548
549
550
551
552
553
554
555 static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len)
556 {
557 int i;
558
559 if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
560 IS_ALIGNED(len, sizeof(u32))) {
561 u32 *p = (u32 *)buf;
562
563 len = len >> 2;
564 for (i = 0; i < len; i++)
565 p[i] = readl_relaxed(host->data_va);
566 } else {
567 for (i = 0; i < len; i++)
568 buf[i] = readb_relaxed(host->data_va);
569 }
570 }
571
572
573
574
575
576
577
578 static void fsmc_read_buf_dma(struct fsmc_nand_data *host, u8 *buf,
579 int len)
580 {
581 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
582 }
583
584
585
586
587
588
589
590 static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf,
591 int len)
592 {
593 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
594 }
595
596
597
598
599
600
601
602 static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
603 bool check_only)
604 {
605 struct fsmc_nand_data *host = nand_to_fsmc(chip);
606 const struct nand_op_instr *instr = NULL;
607 int ret = 0;
608 unsigned int op_id;
609 int i;
610
611 pr_debug("Executing operation [%d instructions]:\n", op->ninstrs);
612
613 for (op_id = 0; op_id < op->ninstrs; op_id++) {
614 instr = &op->instrs[op_id];
615
616 nand_op_trace(" ", instr);
617
618 switch (instr->type) {
619 case NAND_OP_CMD_INSTR:
620 writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va);
621 break;
622
623 case NAND_OP_ADDR_INSTR:
624 for (i = 0; i < instr->ctx.addr.naddrs; i++)
625 writeb_relaxed(instr->ctx.addr.addrs[i],
626 host->addr_va);
627 break;
628
629 case NAND_OP_DATA_IN_INSTR:
630 if (host->mode == USE_DMA_ACCESS)
631 fsmc_read_buf_dma(host, instr->ctx.data.buf.in,
632 instr->ctx.data.len);
633 else
634 fsmc_read_buf(host, instr->ctx.data.buf.in,
635 instr->ctx.data.len);
636 break;
637
638 case NAND_OP_DATA_OUT_INSTR:
639 if (host->mode == USE_DMA_ACCESS)
640 fsmc_write_buf_dma(host,
641 instr->ctx.data.buf.out,
642 instr->ctx.data.len);
643 else
644 fsmc_write_buf(host, instr->ctx.data.buf.out,
645 instr->ctx.data.len);
646 break;
647
648 case NAND_OP_WAITRDY_INSTR:
649 ret = nand_soft_waitrdy(chip,
650 instr->ctx.waitrdy.timeout_ms);
651 break;
652 }
653 }
654
655 return ret;
656 }
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671 static int fsmc_read_page_hwecc(struct nand_chip *chip, u8 *buf,
672 int oob_required, int page)
673 {
674 struct mtd_info *mtd = nand_to_mtd(chip);
675 int i, j, s, stat, eccsize = chip->ecc.size;
676 int eccbytes = chip->ecc.bytes;
677 int eccsteps = chip->ecc.steps;
678 u8 *p = buf;
679 u8 *ecc_calc = chip->ecc.calc_buf;
680 u8 *ecc_code = chip->ecc.code_buf;
681 int off, len, ret, group = 0;
682
683
684
685
686
687 u16 ecc_oob[7];
688 u8 *oob = (u8 *)&ecc_oob[0];
689 unsigned int max_bitflips = 0;
690
691 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
692 nand_read_page_op(chip, page, s * eccsize, NULL, 0);
693 chip->ecc.hwctl(chip, NAND_ECC_READ);
694 ret = nand_read_data_op(chip, p, eccsize, false);
695 if (ret)
696 return ret;
697
698 for (j = 0; j < eccbytes;) {
699 struct mtd_oob_region oobregion;
700
701 ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
702 if (ret)
703 return ret;
704
705 off = oobregion.offset;
706 len = oobregion.length;
707
708
709
710
711
712
713 if (chip->options & NAND_BUSWIDTH_16)
714 len = roundup(len, 2);
715
716 nand_read_oob_op(chip, page, off, oob + j, len);
717 j += len;
718 }
719
720 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
721 chip->ecc.calculate(chip, p, &ecc_calc[i]);
722
723 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
724 if (stat < 0) {
725 mtd->ecc_stats.failed++;
726 } else {
727 mtd->ecc_stats.corrected += stat;
728 max_bitflips = max_t(unsigned int, max_bitflips, stat);
729 }
730 }
731
732 return max_bitflips;
733 }
734
735
736
737
738
739
740
741
742
743
744
745 static int fsmc_bch8_correct_data(struct nand_chip *chip, u8 *dat,
746 u8 *read_ecc, u8 *calc_ecc)
747 {
748 struct fsmc_nand_data *host = nand_to_fsmc(chip);
749 u32 err_idx[8];
750 u32 num_err, i;
751 u32 ecc1, ecc2, ecc3, ecc4;
752
753 num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF;
754
755
756 if (likely(num_err == 0))
757 return 0;
758
759
760 if (unlikely(num_err > 8)) {
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
776 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
777
778 if ((bits_ecc + bits_data) <= 8) {
779 if (bits_data)
780 memset(dat, 0xff, chip->ecc.size);
781 return bits_data;
782 }
783
784 return -EBADMSG;
785 }
786
787
788
789
790
791
792
793
794
795
796 ecc1 = readl_relaxed(host->regs_va + ECC1);
797 ecc2 = readl_relaxed(host->regs_va + ECC2);
798 ecc3 = readl_relaxed(host->regs_va + ECC3);
799 ecc4 = readl_relaxed(host->regs_va + STS);
800
801 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
802 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
803 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
804 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
805 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
806 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
807 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
808 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
809
810 i = 0;
811 while (num_err--) {
812 change_bit(0, (unsigned long *)&err_idx[i]);
813 change_bit(1, (unsigned long *)&err_idx[i]);
814
815 if (err_idx[i] < chip->ecc.size * 8) {
816 change_bit(err_idx[i], (unsigned long *)dat);
817 i++;
818 }
819 }
820 return i;
821 }
822
823 static bool filter(struct dma_chan *chan, void *slave)
824 {
825 chan->private = slave;
826 return true;
827 }
828
829 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
830 struct fsmc_nand_data *host,
831 struct nand_chip *nand)
832 {
833 struct device_node *np = pdev->dev.of_node;
834 u32 val;
835 int ret;
836
837 nand->options = 0;
838
839 if (!of_property_read_u32(np, "bank-width", &val)) {
840 if (val == 2) {
841 nand->options |= NAND_BUSWIDTH_16;
842 } else if (val != 1) {
843 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
844 return -EINVAL;
845 }
846 }
847
848 if (of_get_property(np, "nand-skip-bbtscan", NULL))
849 nand->options |= NAND_SKIP_BBTSCAN;
850
851 host->dev_timings = devm_kzalloc(&pdev->dev,
852 sizeof(*host->dev_timings),
853 GFP_KERNEL);
854 if (!host->dev_timings)
855 return -ENOMEM;
856
857 ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
858 sizeof(*host->dev_timings));
859 if (ret)
860 host->dev_timings = NULL;
861
862
863 host->bank = 0;
864 if (!of_property_read_u32(np, "bank", &val)) {
865 if (val > 3) {
866 dev_err(&pdev->dev, "invalid bank %u\n", val);
867 return -EINVAL;
868 }
869 host->bank = val;
870 }
871 return 0;
872 }
873
874 static int fsmc_nand_attach_chip(struct nand_chip *nand)
875 {
876 struct mtd_info *mtd = nand_to_mtd(nand);
877 struct fsmc_nand_data *host = nand_to_fsmc(nand);
878
879 if (AMBA_REV_BITS(host->pid) >= 8) {
880 switch (mtd->oobsize) {
881 case 16:
882 case 64:
883 case 128:
884 case 224:
885 case 256:
886 break;
887 default:
888 dev_warn(host->dev,
889 "No oob scheme defined for oobsize %d\n",
890 mtd->oobsize);
891 return -EINVAL;
892 }
893
894 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
895
896 return 0;
897 }
898
899 switch (nand->ecc.mode) {
900 case NAND_ECC_HW:
901 dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
902 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
903 nand->ecc.correct = nand_correct_data;
904 nand->ecc.bytes = 3;
905 nand->ecc.strength = 1;
906 nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
907 break;
908
909 case NAND_ECC_SOFT:
910 if (nand->ecc.algo == NAND_ECC_BCH) {
911 dev_info(host->dev,
912 "Using 4-bit SW BCH ECC scheme\n");
913 break;
914 }
915
916 case NAND_ECC_ON_DIE:
917 break;
918
919 default:
920 dev_err(host->dev, "Unsupported ECC mode!\n");
921 return -ENOTSUPP;
922 }
923
924
925
926
927
928 if (nand->ecc.mode == NAND_ECC_HW) {
929 switch (mtd->oobsize) {
930 case 16:
931 case 64:
932 case 128:
933 mtd_set_ooblayout(mtd,
934 &fsmc_ecc1_ooblayout_ops);
935 break;
936 default:
937 dev_warn(host->dev,
938 "No oob scheme defined for oobsize %d\n",
939 mtd->oobsize);
940 return -EINVAL;
941 }
942 }
943
944 return 0;
945 }
946
947 static const struct nand_controller_ops fsmc_nand_controller_ops = {
948 .attach_chip = fsmc_nand_attach_chip,
949 .exec_op = fsmc_exec_op,
950 .setup_data_interface = fsmc_setup_data_interface,
951 };
952
953
954
955
956
957 static void fsmc_nand_disable(struct fsmc_nand_data *host)
958 {
959 u32 val;
960
961 val = readl(host->regs_va + FSMC_PC);
962 val &= ~FSMC_ENABLE;
963 writel(val, host->regs_va + FSMC_PC);
964 }
965
966
967
968
969
970 static int __init fsmc_nand_probe(struct platform_device *pdev)
971 {
972 struct fsmc_nand_data *host;
973 struct mtd_info *mtd;
974 struct nand_chip *nand;
975 struct resource *res;
976 void __iomem *base;
977 dma_cap_mask_t mask;
978 int ret = 0;
979 u32 pid;
980 int i;
981
982
983 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
984 if (!host)
985 return -ENOMEM;
986
987 nand = &host->nand;
988
989 ret = fsmc_nand_probe_config_dt(pdev, host, nand);
990 if (ret)
991 return ret;
992
993 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
994 host->data_va = devm_ioremap_resource(&pdev->dev, res);
995 if (IS_ERR(host->data_va))
996 return PTR_ERR(host->data_va);
997
998 host->data_pa = (dma_addr_t)res->start;
999
1000 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
1001 host->addr_va = devm_ioremap_resource(&pdev->dev, res);
1002 if (IS_ERR(host->addr_va))
1003 return PTR_ERR(host->addr_va);
1004
1005 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
1006 host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
1007 if (IS_ERR(host->cmd_va))
1008 return PTR_ERR(host->cmd_va);
1009
1010 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
1011 base = devm_ioremap_resource(&pdev->dev, res);
1012 if (IS_ERR(base))
1013 return PTR_ERR(base);
1014
1015 host->regs_va = base + FSMC_NOR_REG_SIZE +
1016 (host->bank * FSMC_NAND_BANK_SZ);
1017
1018 host->clk = devm_clk_get(&pdev->dev, NULL);
1019 if (IS_ERR(host->clk)) {
1020 dev_err(&pdev->dev, "failed to fetch block clock\n");
1021 return PTR_ERR(host->clk);
1022 }
1023
1024 ret = clk_prepare_enable(host->clk);
1025 if (ret)
1026 return ret;
1027
1028
1029
1030
1031
1032 for (pid = 0, i = 0; i < 4; i++)
1033 pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) &
1034 255) << (i * 8);
1035
1036 host->pid = pid;
1037
1038 dev_info(&pdev->dev,
1039 "FSMC device partno %03x, manufacturer %02x, revision %02x, config %02x\n",
1040 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
1041 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
1042
1043 host->dev = &pdev->dev;
1044
1045 if (host->mode == USE_DMA_ACCESS)
1046 init_completion(&host->dma_access_complete);
1047
1048
1049 mtd = nand_to_mtd(&host->nand);
1050 nand_set_flash_node(nand, pdev->dev.of_node);
1051
1052 mtd->dev.parent = &pdev->dev;
1053
1054
1055
1056
1057
1058 nand->ecc.mode = NAND_ECC_HW;
1059 nand->ecc.hwctl = fsmc_enable_hwecc;
1060 nand->ecc.size = 512;
1061 nand->badblockbits = 7;
1062
1063 if (host->mode == USE_DMA_ACCESS) {
1064 dma_cap_zero(mask);
1065 dma_cap_set(DMA_MEMCPY, mask);
1066 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
1067 if (!host->read_dma_chan) {
1068 dev_err(&pdev->dev, "Unable to get read dma channel\n");
1069 goto disable_clk;
1070 }
1071 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
1072 if (!host->write_dma_chan) {
1073 dev_err(&pdev->dev, "Unable to get write dma channel\n");
1074 goto release_dma_read_chan;
1075 }
1076 }
1077
1078 if (host->dev_timings) {
1079 fsmc_nand_setup(host, host->dev_timings);
1080 nand->options |= NAND_KEEP_TIMINGS;
1081 }
1082
1083 if (AMBA_REV_BITS(host->pid) >= 8) {
1084 nand->ecc.read_page = fsmc_read_page_hwecc;
1085 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1086 nand->ecc.correct = fsmc_bch8_correct_data;
1087 nand->ecc.bytes = 13;
1088 nand->ecc.strength = 8;
1089 }
1090
1091 nand_controller_init(&host->base);
1092 host->base.ops = &fsmc_nand_controller_ops;
1093 nand->controller = &host->base;
1094
1095
1096
1097
1098 ret = nand_scan(nand, 1);
1099 if (ret)
1100 goto release_dma_write_chan;
1101
1102 mtd->name = "nand";
1103 ret = mtd_device_register(mtd, NULL, 0);
1104 if (ret)
1105 goto cleanup_nand;
1106
1107 platform_set_drvdata(pdev, host);
1108 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1109
1110 return 0;
1111
1112 cleanup_nand:
1113 nand_cleanup(nand);
1114 release_dma_write_chan:
1115 if (host->mode == USE_DMA_ACCESS)
1116 dma_release_channel(host->write_dma_chan);
1117 release_dma_read_chan:
1118 if (host->mode == USE_DMA_ACCESS)
1119 dma_release_channel(host->read_dma_chan);
1120 disable_clk:
1121 fsmc_nand_disable(host);
1122 clk_disable_unprepare(host->clk);
1123
1124 return ret;
1125 }
1126
1127
1128
1129
1130 static int fsmc_nand_remove(struct platform_device *pdev)
1131 {
1132 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1133
1134 if (host) {
1135 nand_release(&host->nand);
1136 fsmc_nand_disable(host);
1137
1138 if (host->mode == USE_DMA_ACCESS) {
1139 dma_release_channel(host->write_dma_chan);
1140 dma_release_channel(host->read_dma_chan);
1141 }
1142 clk_disable_unprepare(host->clk);
1143 }
1144
1145 return 0;
1146 }
1147
1148 #ifdef CONFIG_PM_SLEEP
1149 static int fsmc_nand_suspend(struct device *dev)
1150 {
1151 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1152
1153 if (host)
1154 clk_disable_unprepare(host->clk);
1155
1156 return 0;
1157 }
1158
1159 static int fsmc_nand_resume(struct device *dev)
1160 {
1161 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1162
1163 if (host) {
1164 clk_prepare_enable(host->clk);
1165 if (host->dev_timings)
1166 fsmc_nand_setup(host, host->dev_timings);
1167 nand_reset(&host->nand, 0);
1168 }
1169
1170 return 0;
1171 }
1172 #endif
1173
1174 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1175
1176 static const struct of_device_id fsmc_nand_id_table[] = {
1177 { .compatible = "st,spear600-fsmc-nand" },
1178 { .compatible = "stericsson,fsmc-nand" },
1179 {}
1180 };
1181 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1182
1183 static struct platform_driver fsmc_nand_driver = {
1184 .remove = fsmc_nand_remove,
1185 .driver = {
1186 .name = "fsmc-nand",
1187 .of_match_table = fsmc_nand_id_table,
1188 .pm = &fsmc_nand_pm_ops,
1189 },
1190 };
1191
1192 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1193
1194 MODULE_LICENSE("GPL v2");
1195 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1196 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");