1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright © 2009 - Maxim Levitsky
4 * driver for Ricoh xD readers
5 */
6
7 #include <linux/pci.h>
8 #include <linux/completion.h>
9 #include <linux/workqueue.h>
10 #include <linux/mtd/rawnand.h>
11 #include <linux/spinlock.h>
12
13
14 /* nand interface + ecc
15 byte write/read does one cycle on nand data lines.
16 dword write/read does 4 cycles
17 if R852_CTL_ECC_ACCESS is set in R852_CTL, then dword read reads
18 results of ecc correction, if DMA read was done before.
19 If write was done two dword reads read generated ecc checksums
20 */
21 #define R852_DATALINE 0x00
22
23 /* control register */
24 #define R852_CTL 0x04
25 #define R852_CTL_COMMAND 0x01 /* send command (#CLE)*/
26 #define R852_CTL_DATA 0x02 /* read/write data (#ALE)*/
27 #define R852_CTL_ON 0x04 /* only seem to controls the hd led, */
28 /* but has to be set on start...*/
29 #define R852_CTL_RESET 0x08 /* unknown, set only on start once*/
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
31 #define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */
32 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
33 #define R852_CTL_WRITE 0x80 /* set when performing writes (#WP) */
34
35 /* card detection status */
36 #define R852_CARD_STA 0x05
37
38 #define R852_CARD_STA_CD 0x01 /* state of #CD line, same as 0x04 */
39 #define R852_CARD_STA_RO 0x02 /* card is readonly */
40 #define R852_CARD_STA_PRESENT 0x04 /* card is present (#CD) */
41 #define R852_CARD_STA_ABSENT 0x08 /* card is absent */
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
43
44 /* card detection irq status & enable*/
45 #define R852_CARD_IRQ_STA 0x06 /* IRQ status */
46 #define R852_CARD_IRQ_ENABLE 0x07 /* IRQ enable */
47
48 #define R852_CARD_IRQ_CD 0x01 /* fire when #CD lights, same as 0x04*/
49 #define R852_CARD_IRQ_REMOVE 0x04 /* detect card removal */
50 #define R852_CARD_IRQ_INSERT 0x08 /* detect card insert */
51 #define R852_CARD_IRQ_UNK1 0x10 /* unknown */
52 #define R852_CARD_IRQ_GENABLE 0x80 /* general enable */
53 #define R852_CARD_IRQ_MASK 0x1D
54
55
56
57 /* hardware enable */
58 #define R852_HW 0x08
59 #define R852_HW_ENABLED 0x01 /* hw enabled */
60 #define R852_HW_UNKNOWN 0x80
61
62
63 /* dma capabilities */
64 #define R852_DMA_CAP 0x09
65 #define R852_SMBIT 0x20 /* if set with bit #6 or bit #7, then */
66 /* hw is smartmedia */
67 #define R852_DMA1 0x40 /* if set w/bit #7, dma is supported */
68 #define R852_DMA2 0x80 /* if set w/bit #6, dma is supported */
69
70
71 /* physical DMA address - 32 bit value*/
72 #define R852_DMA_ADDR 0x0C
73
74
75 /* dma settings */
76 #define R852_DMA_SETTINGS 0x10
77 #define R852_DMA_MEMORY 0x01 /* (memory <-> internal hw buffer) */
78 #define R852_DMA_READ 0x02 /* 0 = write, 1 = read */
79 #define R852_DMA_INTERNAL 0x04 /* (internal hw buffer <-> card) */
80
81 /* dma IRQ status */
82 #define R852_DMA_IRQ_STA 0x14
83
84 /* dma IRQ enable */
85 #define R852_DMA_IRQ_ENABLE 0x18
86
87 #define R852_DMA_IRQ_MEMORY 0x01 /* (memory <-> internal hw buffer) */
88 #define R852_DMA_IRQ_ERROR 0x02 /* error did happen */
89 #define R852_DMA_IRQ_INTERNAL 0x04 /* (internal hw buffer <-> card) */
90 #define R852_DMA_IRQ_MASK 0x07 /* mask of all IRQ bits */
91
92
93 /* ECC syndrome format - read from reg #0 will return two copies of these for
94 each half of the page.
95 first byte is error byte location, and second, bit location + flags */
96 #define R852_ECC_ERR_BIT_MSK 0x07 /* error bit location */
97 #define R852_ECC_CORRECT 0x10 /* no errors - (guessed) */
98 #define R852_ECC_CORRECTABLE 0x20 /* correctable error exist */
99 #define R852_ECC_FAIL 0x40 /* non correctable error detected */
100
101 #define R852_DMA_LEN 512
102
103 #define DMA_INTERNAL 0
104 #define DMA_MEMORY 1
105
106 struct r852_device {
107 void __iomem *mmio; /* mmio */
108 struct nand_chip *chip; /* nand chip backpointer */
109 struct pci_dev *pci_dev; /* pci backpointer */
110
111 /* dma area */
112 dma_addr_t phys_dma_addr; /* bus address of buffer*/
113 struct completion dma_done; /* data transfer done */
114
115 dma_addr_t phys_bounce_buffer; /* bus address of bounce buffer */
116 uint8_t *bounce_buffer; /* virtual address of bounce buffer */
117
118 int dma_dir; /* 1 = read, 0 = write */
119 int dma_stage; /* 0 - idle, 1 - first step,
120 2 - second step */
121
122 int dma_state; /* 0 = internal, 1 = memory */
123 int dma_error; /* dma errors */
124 int dma_usable; /* is it possible to use dma */
125
126 /* card status area */
127 struct delayed_work card_detect_work;
128 struct workqueue_struct *card_workqueue;
129 int card_registered; /* card registered with mtd */
130 int card_detected; /* card detected in slot */
131 int card_unstable; /* whenever the card is inserted,
132 is not known yet */
133 int readonly; /* card is readonly */
134 int sm; /* Is card smartmedia */
135
136 /* interrupt handling */
137 spinlock_t irqlock; /* IRQ protecting lock */
138 int irq; /* irq num */
139 /* misc */
140 void *tmp_buffer; /* temporary buffer */
141 uint8_t ctlreg; /* cached contents of control reg */
142 };
143
144 #define dbg(format, ...) \
145 if (debug) \
146 pr_debug(format "\n", ## __VA_ARGS__)
147
148 #define dbg_verbose(format, ...) \
149 if (debug > 1) \
150 pr_debug(format "\n", ## __VA_ARGS__)
151
152
153 #define message(format, ...) \
154 pr_info(format "\n", ## __VA_ARGS__)