drivers/ata/libahci.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
ahci_enable_ahci
ahci_rpm_get_port
ahci_rpm_put_port
ahci_show_host_caps
ahci_show_host_cap2
ahci_show_host_version
ahci_show_port_cmd
ahci_read_em_buffer
ahci_store_em_buffer
ahci_show_em_supported
ahci_save_initial_config
ahci_restore_initial_config
ahci_scr_offset
ahci_scr_read
ahci_scr_write
ahci_start_engine
ahci_stop_engine
ahci_start_fis_rx
ahci_stop_fis_rx
ahci_power_up
ahci_set_lpm
ahci_power_down
ahci_start_port
ahci_deinit_port
ahci_reset_controller
ahci_sw_activity
ahci_sw_activity_blink
ahci_init_sw_activity
ahci_reset_em
ahci_transmit_led_message
ahci_led_show
ahci_led_store
ahci_activity_store
ahci_activity_show
ahci_port_init
ahci_init_controller
ahci_dev_config
ahci_dev_classify
ahci_fill_cmd_slot
ahci_kick_engine
ahci_exec_polled_cmd
ahci_do_softreset
ahci_check_ready
ahci_softreset
ahci_bad_pmp_check_ready
ahci_pmp_retry_softreset
ahci_do_hardreset
ahci_hardreset
ahci_postreset
ahci_fill_sg
ahci_pmp_qc_defer
ahci_qc_prep
ahci_fbs_dec_intr
ahci_error_intr
ahci_handle_port_interrupt
ahci_port_intr
ahci_multi_irqs_intr_hard
ahci_handle_port_intr
ahci_single_level_irq_intr
ahci_qc_issue
ahci_qc_fill_rtf
ahci_freeze
ahci_thaw
ahci_error_handler
ahci_post_internal_cmd
ahci_set_aggressive_devslp
ahci_enable_fbs
ahci_disable_fbs
ahci_pmp_attach
ahci_pmp_detach
ahci_port_resume
ahci_port_suspend
ahci_port_start
ahci_port_stop
ahci_print_info
ahci_set_em_messages
ahci_host_activate_multi_irqs
ahci_host_activate
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  libahci.c - Common AHCI SATA low-level routines
   4  *
   5  *  Maintained by:  Tejun Heo <tj@kernel.org>
   6  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   7  *                  on emails.
   8  *
   9  *  Copyright 2004-2005 Red Hat, Inc.
  10  *
  11  * libata documentation is available via 'make {ps|pdf}docs',
  12  * as Documentation/driver-api/libata.rst
  13  *
  14  * AHCI hardware documentation:
  15  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  16  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  17  */
  18 
  19 #include <linux/kernel.h>
  20 #include <linux/gfp.h>
  21 #include <linux/module.h>
  22 #include <linux/nospec.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/device.h>
  28 #include <scsi/scsi_host.h>
  29 #include <scsi/scsi_cmnd.h>
  30 #include <linux/libata.h>
  31 #include <linux/pci.h>
  32 #include "ahci.h"
  33 #include "libata.h"
  34 
  35 static int ahci_skip_host_reset;
  36 int ahci_ignore_sss;
  37 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
  38 
  39 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
  40 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
  41 
  42 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
  43 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
  44 
  45 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
  46                         unsigned hints);
  47 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
  48 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
  49                               size_t size);
  50 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
  51                                         ssize_t size);
  52 
  53 
  54 
  55 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
  56 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
  57 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
  58 static int ahci_port_start(struct ata_port *ap);
  59 static void ahci_port_stop(struct ata_port *ap);
  60 static void ahci_qc_prep(struct ata_queued_cmd *qc);
  61 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
  62 static void ahci_freeze(struct ata_port *ap);
  63 static void ahci_thaw(struct ata_port *ap);
  64 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
  65 static void ahci_enable_fbs(struct ata_port *ap);
  66 static void ahci_disable_fbs(struct ata_port *ap);
  67 static void ahci_pmp_attach(struct ata_port *ap);
  68 static void ahci_pmp_detach(struct ata_port *ap);
  69 static int ahci_softreset(struct ata_link *link, unsigned int *class,
  70                           unsigned long deadline);
  71 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
  72                           unsigned long deadline);
  73 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
  74                           unsigned long deadline);
  75 static void ahci_postreset(struct ata_link *link, unsigned int *class);
  76 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
  77 static void ahci_dev_config(struct ata_device *dev);
  78 #ifdef CONFIG_PM
  79 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
  80 #endif
  81 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
  82 static ssize_t ahci_activity_store(struct ata_device *dev,
  83                                    enum sw_activity val);
  84 static void ahci_init_sw_activity(struct ata_link *link);
  85 
  86 static ssize_t ahci_show_host_caps(struct device *dev,
  87                                    struct device_attribute *attr, char *buf);
  88 static ssize_t ahci_show_host_cap2(struct device *dev,
  89                                    struct device_attribute *attr, char *buf);
  90 static ssize_t ahci_show_host_version(struct device *dev,
  91                                       struct device_attribute *attr, char *buf);
  92 static ssize_t ahci_show_port_cmd(struct device *dev,
  93                                   struct device_attribute *attr, char *buf);
  94 static ssize_t ahci_read_em_buffer(struct device *dev,
  95                                    struct device_attribute *attr, char *buf);
  96 static ssize_t ahci_store_em_buffer(struct device *dev,
  97                                     struct device_attribute *attr,
  98                                     const char *buf, size_t size);
  99 static ssize_t ahci_show_em_supported(struct device *dev,
 100                                       struct device_attribute *attr, char *buf);
 101 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
 102 
 103 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
 104 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
 105 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
 106 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
 107 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
 108                    ahci_read_em_buffer, ahci_store_em_buffer);
 109 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
 110 
 111 struct device_attribute *ahci_shost_attrs[] = {
 112         &dev_attr_link_power_management_policy,
 113         &dev_attr_em_message_type,
 114         &dev_attr_em_message,
 115         &dev_attr_ahci_host_caps,
 116         &dev_attr_ahci_host_cap2,
 117         &dev_attr_ahci_host_version,
 118         &dev_attr_ahci_port_cmd,
 119         &dev_attr_em_buffer,
 120         &dev_attr_em_message_supported,
 121         NULL
 122 };
 123 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
 124 
 125 struct device_attribute *ahci_sdev_attrs[] = {
 126         &dev_attr_sw_activity,
 127         &dev_attr_unload_heads,
 128         &dev_attr_ncq_prio_enable,
 129         NULL
 130 };
 131 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
 132 
 133 struct ata_port_operations ahci_ops = {
 134         .inherits               = &sata_pmp_port_ops,
 135 
 136         .qc_defer               = ahci_pmp_qc_defer,
 137         .qc_prep                = ahci_qc_prep,
 138         .qc_issue               = ahci_qc_issue,
 139         .qc_fill_rtf            = ahci_qc_fill_rtf,
 140 
 141         .freeze                 = ahci_freeze,
 142         .thaw                   = ahci_thaw,
 143         .softreset              = ahci_softreset,
 144         .hardreset              = ahci_hardreset,
 145         .postreset              = ahci_postreset,
 146         .pmp_softreset          = ahci_softreset,
 147         .error_handler          = ahci_error_handler,
 148         .post_internal_cmd      = ahci_post_internal_cmd,
 149         .dev_config             = ahci_dev_config,
 150 
 151         .scr_read               = ahci_scr_read,
 152         .scr_write              = ahci_scr_write,
 153         .pmp_attach             = ahci_pmp_attach,
 154         .pmp_detach             = ahci_pmp_detach,
 155 
 156         .set_lpm                = ahci_set_lpm,
 157         .em_show                = ahci_led_show,
 158         .em_store               = ahci_led_store,
 159         .sw_activity_show       = ahci_activity_show,
 160         .sw_activity_store      = ahci_activity_store,
 161         .transmit_led_message   = ahci_transmit_led_message,
 162 #ifdef CONFIG_PM
 163         .port_suspend           = ahci_port_suspend,
 164         .port_resume            = ahci_port_resume,
 165 #endif
 166         .port_start             = ahci_port_start,
 167         .port_stop              = ahci_port_stop,
 168 };
 169 EXPORT_SYMBOL_GPL(ahci_ops);
 170 
 171 struct ata_port_operations ahci_pmp_retry_srst_ops = {
 172         .inherits               = &ahci_ops,
 173         .softreset              = ahci_pmp_retry_softreset,
 174 };
 175 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
 176 
 177 static bool ahci_em_messages __read_mostly = true;
 178 module_param(ahci_em_messages, bool, 0444);
 179 /* add other LED protocol types when they become supported */
 180 MODULE_PARM_DESC(ahci_em_messages,
 181         "AHCI Enclosure Management Message control (0 = off, 1 = on)");
 182 
 183 /* device sleep idle timeout in ms */
 184 static int devslp_idle_timeout __read_mostly = 1000;
 185 module_param(devslp_idle_timeout, int, 0644);
 186 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
 187 
 188 static void ahci_enable_ahci(void __iomem *mmio)
 189 {
 190         int i;
 191         u32 tmp;
 192 
 193         /* turn on AHCI_EN */
 194         tmp = readl(mmio + HOST_CTL);
 195         if (tmp & HOST_AHCI_EN)
 196                 return;
 197 
 198         /* Some controllers need AHCI_EN to be written multiple times.
 199          * Try a few times before giving up.
 200          */
 201         for (i = 0; i < 5; i++) {
 202                 tmp |= HOST_AHCI_EN;
 203                 writel(tmp, mmio + HOST_CTL);
 204                 tmp = readl(mmio + HOST_CTL);   /* flush && sanity check */
 205                 if (tmp & HOST_AHCI_EN)
 206                         return;
 207                 msleep(10);
 208         }
 209 
 210         WARN_ON(1);
 211 }
 212 
 213 /**
 214  *      ahci_rpm_get_port - Make sure the port is powered on
 215  *      @ap: Port to power on
 216  *
 217  *      Whenever there is need to access the AHCI host registers outside of
 218  *      normal execution paths, call this function to make sure the host is
 219  *      actually powered on.
 220  */
 221 static int ahci_rpm_get_port(struct ata_port *ap)
 222 {
 223         return pm_runtime_get_sync(ap->dev);
 224 }
 225 
 226 /**
 227  *      ahci_rpm_put_port - Undoes ahci_rpm_get_port()
 228  *      @ap: Port to power down
 229  *
 230  *      Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
 231  *      if it has no more active users.
 232  */
 233 static void ahci_rpm_put_port(struct ata_port *ap)
 234 {
 235         pm_runtime_put(ap->dev);
 236 }
 237 
 238 static ssize_t ahci_show_host_caps(struct device *dev,
 239                                    struct device_attribute *attr, char *buf)
 240 {
 241         struct Scsi_Host *shost = class_to_shost(dev);
 242         struct ata_port *ap = ata_shost_to_port(shost);
 243         struct ahci_host_priv *hpriv = ap->host->private_data;
 244 
 245         return sprintf(buf, "%x\n", hpriv->cap);
 246 }
 247 
 248 static ssize_t ahci_show_host_cap2(struct device *dev,
 249                                    struct device_attribute *attr, char *buf)
 250 {
 251         struct Scsi_Host *shost = class_to_shost(dev);
 252         struct ata_port *ap = ata_shost_to_port(shost);
 253         struct ahci_host_priv *hpriv = ap->host->private_data;
 254 
 255         return sprintf(buf, "%x\n", hpriv->cap2);
 256 }
 257 
 258 static ssize_t ahci_show_host_version(struct device *dev,
 259                                    struct device_attribute *attr, char *buf)
 260 {
 261         struct Scsi_Host *shost = class_to_shost(dev);
 262         struct ata_port *ap = ata_shost_to_port(shost);
 263         struct ahci_host_priv *hpriv = ap->host->private_data;
 264 
 265         return sprintf(buf, "%x\n", hpriv->version);
 266 }
 267 
 268 static ssize_t ahci_show_port_cmd(struct device *dev,
 269                                   struct device_attribute *attr, char *buf)
 270 {
 271         struct Scsi_Host *shost = class_to_shost(dev);
 272         struct ata_port *ap = ata_shost_to_port(shost);
 273         void __iomem *port_mmio = ahci_port_base(ap);
 274         ssize_t ret;
 275 
 276         ahci_rpm_get_port(ap);
 277         ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
 278         ahci_rpm_put_port(ap);
 279 
 280         return ret;
 281 }
 282 
 283 static ssize_t ahci_read_em_buffer(struct device *dev,
 284                                    struct device_attribute *attr, char *buf)
 285 {
 286         struct Scsi_Host *shost = class_to_shost(dev);
 287         struct ata_port *ap = ata_shost_to_port(shost);
 288         struct ahci_host_priv *hpriv = ap->host->private_data;
 289         void __iomem *mmio = hpriv->mmio;
 290         void __iomem *em_mmio = mmio + hpriv->em_loc;
 291         u32 em_ctl, msg;
 292         unsigned long flags;
 293         size_t count;
 294         int i;
 295 
 296         ahci_rpm_get_port(ap);
 297         spin_lock_irqsave(ap->lock, flags);
 298 
 299         em_ctl = readl(mmio + HOST_EM_CTL);
 300         if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
 301             !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
 302                 spin_unlock_irqrestore(ap->lock, flags);
 303                 ahci_rpm_put_port(ap);
 304                 return -EINVAL;
 305         }
 306 
 307         if (!(em_ctl & EM_CTL_MR)) {
 308                 spin_unlock_irqrestore(ap->lock, flags);
 309                 ahci_rpm_put_port(ap);
 310                 return -EAGAIN;
 311         }
 312 
 313         if (!(em_ctl & EM_CTL_SMB))
 314                 em_mmio += hpriv->em_buf_sz;
 315 
 316         count = hpriv->em_buf_sz;
 317 
 318         /* the count should not be larger than PAGE_SIZE */
 319         if (count > PAGE_SIZE) {
 320                 if (printk_ratelimit())
 321                         ata_port_warn(ap,
 322                                       "EM read buffer size too large: "
 323                                       "buffer size %u, page size %lu\n",
 324                                       hpriv->em_buf_sz, PAGE_SIZE);
 325                 count = PAGE_SIZE;
 326         }
 327 
 328         for (i = 0; i < count; i += 4) {
 329                 msg = readl(em_mmio + i);
 330                 buf[i] = msg & 0xff;
 331                 buf[i + 1] = (msg >> 8) & 0xff;
 332                 buf[i + 2] = (msg >> 16) & 0xff;
 333                 buf[i + 3] = (msg >> 24) & 0xff;
 334         }
 335 
 336         spin_unlock_irqrestore(ap->lock, flags);
 337         ahci_rpm_put_port(ap);
 338 
 339         return i;
 340 }
 341 
 342 static ssize_t ahci_store_em_buffer(struct device *dev,
 343                                     struct device_attribute *attr,
 344                                     const char *buf, size_t size)
 345 {
 346         struct Scsi_Host *shost = class_to_shost(dev);
 347         struct ata_port *ap = ata_shost_to_port(shost);
 348         struct ahci_host_priv *hpriv = ap->host->private_data;
 349         void __iomem *mmio = hpriv->mmio;
 350         void __iomem *em_mmio = mmio + hpriv->em_loc;
 351         const unsigned char *msg_buf = buf;
 352         u32 em_ctl, msg;
 353         unsigned long flags;
 354         int i;
 355 
 356         /* check size validity */
 357         if (!(ap->flags & ATA_FLAG_EM) ||
 358             !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
 359             size % 4 || size > hpriv->em_buf_sz)
 360                 return -EINVAL;
 361 
 362         ahci_rpm_get_port(ap);
 363         spin_lock_irqsave(ap->lock, flags);
 364 
 365         em_ctl = readl(mmio + HOST_EM_CTL);
 366         if (em_ctl & EM_CTL_TM) {
 367                 spin_unlock_irqrestore(ap->lock, flags);
 368                 ahci_rpm_put_port(ap);
 369                 return -EBUSY;
 370         }
 371 
 372         for (i = 0; i < size; i += 4) {
 373                 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
 374                       msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
 375                 writel(msg, em_mmio + i);
 376         }
 377 
 378         writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
 379 
 380         spin_unlock_irqrestore(ap->lock, flags);
 381         ahci_rpm_put_port(ap);
 382 
 383         return size;
 384 }
 385 
 386 static ssize_t ahci_show_em_supported(struct device *dev,
 387                                       struct device_attribute *attr, char *buf)
 388 {
 389         struct Scsi_Host *shost = class_to_shost(dev);
 390         struct ata_port *ap = ata_shost_to_port(shost);
 391         struct ahci_host_priv *hpriv = ap->host->private_data;
 392         void __iomem *mmio = hpriv->mmio;
 393         u32 em_ctl;
 394 
 395         ahci_rpm_get_port(ap);
 396         em_ctl = readl(mmio + HOST_EM_CTL);
 397         ahci_rpm_put_port(ap);
 398 
 399         return sprintf(buf, "%s%s%s%s\n",
 400                        em_ctl & EM_CTL_LED ? "led " : "",
 401                        em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
 402                        em_ctl & EM_CTL_SES ? "ses-2 " : "",
 403                        em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
 404 }
 405 
 406 /**
 407  *      ahci_save_initial_config - Save and fixup initial config values
 408  *      @dev: target AHCI device
 409  *      @hpriv: host private area to store config values
 410  *
 411  *      Some registers containing configuration info might be setup by
 412  *      BIOS and might be cleared on reset.  This function saves the
 413  *      initial values of those registers into @hpriv such that they
 414  *      can be restored after controller reset.
 415  *
 416  *      If inconsistent, config values are fixed up by this function.
 417  *
 418  *      If it is not set already this function sets hpriv->start_engine to
 419  *      ahci_start_engine.
 420  *
 421  *      LOCKING:
 422  *      None.
 423  */
 424 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
 425 {
 426         void __iomem *mmio = hpriv->mmio;
 427         u32 cap, cap2, vers, port_map;
 428         int i;
 429 
 430         /* make sure AHCI mode is enabled before accessing CAP */
 431         ahci_enable_ahci(mmio);
 432 
 433         /* Values prefixed with saved_ are written back to host after
 434          * reset.  Values without are used for driver operation.
 435          */
 436         hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
 437         hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
 438 
 439         /* CAP2 register is only defined for AHCI 1.2 and later */
 440         vers = readl(mmio + HOST_VERSION);
 441         if ((vers >> 16) > 1 ||
 442            ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
 443                 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
 444         else
 445                 hpriv->saved_cap2 = cap2 = 0;
 446 
 447         /* some chips have errata preventing 64bit use */
 448         if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
 449                 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
 450                 cap &= ~HOST_CAP_64;
 451         }
 452 
 453         if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
 454                 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
 455                 cap &= ~HOST_CAP_NCQ;
 456         }
 457 
 458         if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
 459                 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
 460                 cap |= HOST_CAP_NCQ;
 461         }
 462 
 463         if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
 464                 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
 465                 cap &= ~HOST_CAP_PMP;
 466         }
 467 
 468         if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
 469                 dev_info(dev,
 470                          "controller can't do SNTF, turning off CAP_SNTF\n");
 471                 cap &= ~HOST_CAP_SNTF;
 472         }
 473 
 474         if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
 475                 dev_info(dev,
 476                          "controller can't do DEVSLP, turning off\n");
 477                 cap2 &= ~HOST_CAP2_SDS;
 478                 cap2 &= ~HOST_CAP2_SADM;
 479         }
 480 
 481         if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
 482                 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
 483                 cap |= HOST_CAP_FBS;
 484         }
 485 
 486         if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
 487                 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
 488                 cap &= ~HOST_CAP_FBS;
 489         }
 490 
 491         if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
 492                 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
 493                 cap |= HOST_CAP_ALPM;
 494         }
 495 
 496         if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
 497                 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
 498                          port_map, hpriv->force_port_map);
 499                 port_map = hpriv->force_port_map;
 500                 hpriv->saved_port_map = port_map;
 501         }
 502 
 503         if (hpriv->mask_port_map) {
 504                 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
 505                         port_map,
 506                         port_map & hpriv->mask_port_map);
 507                 port_map &= hpriv->mask_port_map;
 508         }
 509 
 510         /* cross check port_map and cap.n_ports */
 511         if (port_map) {
 512                 int map_ports = 0;
 513 
 514                 for (i = 0; i < AHCI_MAX_PORTS; i++)
 515                         if (port_map & (1 << i))
 516                                 map_ports++;
 517 
 518                 /* If PI has more ports than n_ports, whine, clear
 519                  * port_map and let it be generated from n_ports.
 520                  */
 521                 if (map_ports > ahci_nr_ports(cap)) {
 522                         dev_warn(dev,
 523                                  "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
 524                                  port_map, ahci_nr_ports(cap));
 525                         port_map = 0;
 526                 }
 527         }
 528 
 529         /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
 530         if (!port_map && vers < 0x10300) {
 531                 port_map = (1 << ahci_nr_ports(cap)) - 1;
 532                 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
 533 
 534                 /* write the fixed up value to the PI register */
 535                 hpriv->saved_port_map = port_map;
 536         }
 537 
 538         /* record values to use during operation */
 539         hpriv->cap = cap;
 540         hpriv->cap2 = cap2;
 541         hpriv->version = readl(mmio + HOST_VERSION);
 542         hpriv->port_map = port_map;
 543 
 544         if (!hpriv->start_engine)
 545                 hpriv->start_engine = ahci_start_engine;
 546 
 547         if (!hpriv->stop_engine)
 548                 hpriv->stop_engine = ahci_stop_engine;
 549 
 550         if (!hpriv->irq_handler)
 551                 hpriv->irq_handler = ahci_single_level_irq_intr;
 552 }
 553 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
 554 
 555 /**
 556  *      ahci_restore_initial_config - Restore initial config
 557  *      @host: target ATA host
 558  *
 559  *      Restore initial config stored by ahci_save_initial_config().
 560  *
 561  *      LOCKING:
 562  *      None.
 563  */
 564 static void ahci_restore_initial_config(struct ata_host *host)
 565 {
 566         struct ahci_host_priv *hpriv = host->private_data;
 567         void __iomem *mmio = hpriv->mmio;
 568 
 569         writel(hpriv->saved_cap, mmio + HOST_CAP);
 570         if (hpriv->saved_cap2)
 571                 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
 572         writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
 573         (void) readl(mmio + HOST_PORTS_IMPL);   /* flush */
 574 }
 575 
 576 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
 577 {
 578         static const int offset[] = {
 579                 [SCR_STATUS]            = PORT_SCR_STAT,
 580                 [SCR_CONTROL]           = PORT_SCR_CTL,
 581                 [SCR_ERROR]             = PORT_SCR_ERR,
 582                 [SCR_ACTIVE]            = PORT_SCR_ACT,
 583                 [SCR_NOTIFICATION]      = PORT_SCR_NTF,
 584         };
 585         struct ahci_host_priv *hpriv = ap->host->private_data;
 586 
 587         if (sc_reg < ARRAY_SIZE(offset) &&
 588             (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
 589                 return offset[sc_reg];
 590         return 0;
 591 }
 592 
 593 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
 594 {
 595         void __iomem *port_mmio = ahci_port_base(link->ap);
 596         int offset = ahci_scr_offset(link->ap, sc_reg);
 597 
 598         if (offset) {
 599                 *val = readl(port_mmio + offset);
 600                 return 0;
 601         }
 602         return -EINVAL;
 603 }
 604 
 605 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
 606 {
 607         void __iomem *port_mmio = ahci_port_base(link->ap);
 608         int offset = ahci_scr_offset(link->ap, sc_reg);
 609 
 610         if (offset) {
 611                 writel(val, port_mmio + offset);
 612                 return 0;
 613         }
 614         return -EINVAL;
 615 }
 616 
 617 void ahci_start_engine(struct ata_port *ap)
 618 {
 619         void __iomem *port_mmio = ahci_port_base(ap);
 620         u32 tmp;
 621 
 622         /* start DMA */
 623         tmp = readl(port_mmio + PORT_CMD);
 624         tmp |= PORT_CMD_START;
 625         writel(tmp, port_mmio + PORT_CMD);
 626         readl(port_mmio + PORT_CMD); /* flush */
 627 }
 628 EXPORT_SYMBOL_GPL(ahci_start_engine);
 629 
 630 int ahci_stop_engine(struct ata_port *ap)
 631 {
 632         void __iomem *port_mmio = ahci_port_base(ap);
 633         struct ahci_host_priv *hpriv = ap->host->private_data;
 634         u32 tmp;
 635 
 636         /*
 637          * On some controllers, stopping a port's DMA engine while the port
 638          * is in ALPM state (partial or slumber) results in failures on
 639          * subsequent DMA engine starts.  For those controllers, put the
 640          * port back in active state before stopping its DMA engine.
 641          */
 642         if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
 643             (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
 644             ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
 645                 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
 646                 return -EIO;
 647         }
 648 
 649         tmp = readl(port_mmio + PORT_CMD);
 650 
 651         /* check if the HBA is idle */
 652         if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
 653                 return 0;
 654 
 655         /*
 656          * Don't try to issue commands but return with ENODEV if the
 657          * AHCI controller not available anymore (e.g. due to PCIe hot
 658          * unplugging). Otherwise a 500ms delay for each port is added.
 659          */
 660         if (tmp == 0xffffffff) {
 661                 dev_err(ap->host->dev, "AHCI controller unavailable!\n");
 662                 return -ENODEV;
 663         }
 664 
 665         /* setting HBA to idle */
 666         tmp &= ~PORT_CMD_START;
 667         writel(tmp, port_mmio + PORT_CMD);
 668 
 669         /* wait for engine to stop. This could be as long as 500 msec */
 670         tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
 671                                 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
 672         if (tmp & PORT_CMD_LIST_ON)
 673                 return -EIO;
 674 
 675         return 0;
 676 }
 677 EXPORT_SYMBOL_GPL(ahci_stop_engine);
 678 
 679 void ahci_start_fis_rx(struct ata_port *ap)
 680 {
 681         void __iomem *port_mmio = ahci_port_base(ap);
 682         struct ahci_host_priv *hpriv = ap->host->private_data;
 683         struct ahci_port_priv *pp = ap->private_data;
 684         u32 tmp;
 685 
 686         /* set FIS registers */
 687         if (hpriv->cap & HOST_CAP_64)
 688                 writel((pp->cmd_slot_dma >> 16) >> 16,
 689                        port_mmio + PORT_LST_ADDR_HI);
 690         writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
 691 
 692         if (hpriv->cap & HOST_CAP_64)
 693                 writel((pp->rx_fis_dma >> 16) >> 16,
 694                        port_mmio + PORT_FIS_ADDR_HI);
 695         writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
 696 
 697         /* enable FIS reception */
 698         tmp = readl(port_mmio + PORT_CMD);
 699         tmp |= PORT_CMD_FIS_RX;
 700         writel(tmp, port_mmio + PORT_CMD);
 701 
 702         /* flush */
 703         readl(port_mmio + PORT_CMD);
 704 }
 705 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
 706 
 707 static int ahci_stop_fis_rx(struct ata_port *ap)
 708 {
 709         void __iomem *port_mmio = ahci_port_base(ap);
 710         u32 tmp;
 711 
 712         /* disable FIS reception */
 713         tmp = readl(port_mmio + PORT_CMD);
 714         tmp &= ~PORT_CMD_FIS_RX;
 715         writel(tmp, port_mmio + PORT_CMD);
 716 
 717         /* wait for completion, spec says 500ms, give it 1000 */
 718         tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
 719                                 PORT_CMD_FIS_ON, 10, 1000);
 720         if (tmp & PORT_CMD_FIS_ON)
 721                 return -EBUSY;
 722 
 723         return 0;
 724 }
 725 
 726 static void ahci_power_up(struct ata_port *ap)
 727 {
 728         struct ahci_host_priv *hpriv = ap->host->private_data;
 729         void __iomem *port_mmio = ahci_port_base(ap);
 730         u32 cmd;
 731 
 732         cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
 733 
 734         /* spin up device */
 735         if (hpriv->cap & HOST_CAP_SSS) {
 736                 cmd |= PORT_CMD_SPIN_UP;
 737                 writel(cmd, port_mmio + PORT_CMD);
 738         }
 739 
 740         /* wake up link */
 741         writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
 742 }
 743 
 744 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
 745                         unsigned int hints)
 746 {
 747         struct ata_port *ap = link->ap;
 748         struct ahci_host_priv *hpriv = ap->host->private_data;
 749         struct ahci_port_priv *pp = ap->private_data;
 750         void __iomem *port_mmio = ahci_port_base(ap);
 751 
 752         if (policy != ATA_LPM_MAX_POWER) {
 753                 /* wakeup flag only applies to the max power policy */
 754                 hints &= ~ATA_LPM_WAKE_ONLY;
 755 
 756                 /*
 757                  * Disable interrupts on Phy Ready. This keeps us from
 758                  * getting woken up due to spurious phy ready
 759                  * interrupts.
 760                  */
 761                 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
 762                 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
 763 
 764                 sata_link_scr_lpm(link, policy, false);
 765         }
 766 
 767         if (hpriv->cap & HOST_CAP_ALPM) {
 768                 u32 cmd = readl(port_mmio + PORT_CMD);
 769 
 770                 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
 771                         if (!(hints & ATA_LPM_WAKE_ONLY))
 772                                 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
 773                         cmd |= PORT_CMD_ICC_ACTIVE;
 774 
 775                         writel(cmd, port_mmio + PORT_CMD);
 776                         readl(port_mmio + PORT_CMD);
 777 
 778                         /* wait 10ms to be sure we've come out of LPM state */
 779                         ata_msleep(ap, 10);
 780 
 781                         if (hints & ATA_LPM_WAKE_ONLY)
 782                                 return 0;
 783                 } else {
 784                         cmd |= PORT_CMD_ALPE;
 785                         if (policy == ATA_LPM_MIN_POWER)
 786                                 cmd |= PORT_CMD_ASP;
 787                         else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
 788                                 cmd &= ~PORT_CMD_ASP;
 789 
 790                         /* write out new cmd value */
 791                         writel(cmd, port_mmio + PORT_CMD);
 792                 }
 793         }
 794 
 795         /* set aggressive device sleep */
 796         if ((hpriv->cap2 & HOST_CAP2_SDS) &&
 797             (hpriv->cap2 & HOST_CAP2_SADM) &&
 798             (link->device->flags & ATA_DFLAG_DEVSLP)) {
 799                 if (policy == ATA_LPM_MIN_POWER ||
 800                     policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
 801                         ahci_set_aggressive_devslp(ap, true);
 802                 else
 803                         ahci_set_aggressive_devslp(ap, false);
 804         }
 805 
 806         if (policy == ATA_LPM_MAX_POWER) {
 807                 sata_link_scr_lpm(link, policy, false);
 808 
 809                 /* turn PHYRDY IRQ back on */
 810                 pp->intr_mask |= PORT_IRQ_PHYRDY;
 811                 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
 812         }
 813 
 814         return 0;
 815 }
 816 
 817 #ifdef CONFIG_PM
 818 static void ahci_power_down(struct ata_port *ap)
 819 {
 820         struct ahci_host_priv *hpriv = ap->host->private_data;
 821         void __iomem *port_mmio = ahci_port_base(ap);
 822         u32 cmd, scontrol;
 823 
 824         if (!(hpriv->cap & HOST_CAP_SSS))
 825                 return;
 826 
 827         /* put device into listen mode, first set PxSCTL.DET to 0 */
 828         scontrol = readl(port_mmio + PORT_SCR_CTL);
 829         scontrol &= ~0xf;
 830         writel(scontrol, port_mmio + PORT_SCR_CTL);
 831 
 832         /* then set PxCMD.SUD to 0 */
 833         cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
 834         cmd &= ~PORT_CMD_SPIN_UP;
 835         writel(cmd, port_mmio + PORT_CMD);
 836 }
 837 #endif
 838 
 839 static void ahci_start_port(struct ata_port *ap)
 840 {
 841         struct ahci_host_priv *hpriv = ap->host->private_data;
 842         struct ahci_port_priv *pp = ap->private_data;
 843         struct ata_link *link;
 844         struct ahci_em_priv *emp;
 845         ssize_t rc;
 846         int i;
 847 
 848         /* enable FIS reception */
 849         ahci_start_fis_rx(ap);
 850 
 851         /* enable DMA */
 852         if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
 853                 hpriv->start_engine(ap);
 854 
 855         /* turn on LEDs */
 856         if (ap->flags & ATA_FLAG_EM) {
 857                 ata_for_each_link(link, ap, EDGE) {
 858                         emp = &pp->em_priv[link->pmp];
 859 
 860                         /* EM Transmit bit maybe busy during init */
 861                         for (i = 0; i < EM_MAX_RETRY; i++) {
 862                                 rc = ap->ops->transmit_led_message(ap,
 863                                                                emp->led_state,
 864                                                                4);
 865                                 /*
 866                                  * If busy, give a breather but do not
 867                                  * release EH ownership by using msleep()
 868                                  * instead of ata_msleep().  EM Transmit
 869                                  * bit is busy for the whole host and
 870                                  * releasing ownership will cause other
 871                                  * ports to fail the same way.
 872                                  */
 873                                 if (rc == -EBUSY)
 874                                         msleep(1);
 875                                 else
 876                                         break;
 877                         }
 878                 }
 879         }
 880 
 881         if (ap->flags & ATA_FLAG_SW_ACTIVITY)
 882                 ata_for_each_link(link, ap, EDGE)
 883                         ahci_init_sw_activity(link);
 884 
 885 }
 886 
 887 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
 888 {
 889         int rc;
 890         struct ahci_host_priv *hpriv = ap->host->private_data;
 891 
 892         /* disable DMA */
 893         rc = hpriv->stop_engine(ap);
 894         if (rc) {
 895                 *emsg = "failed to stop engine";
 896                 return rc;
 897         }
 898 
 899         /* disable FIS reception */
 900         rc = ahci_stop_fis_rx(ap);
 901         if (rc) {
 902                 *emsg = "failed stop FIS RX";
 903                 return rc;
 904         }
 905 
 906         return 0;
 907 }
 908 
 909 int ahci_reset_controller(struct ata_host *host)
 910 {
 911         struct ahci_host_priv *hpriv = host->private_data;
 912         void __iomem *mmio = hpriv->mmio;
 913         u32 tmp;
 914 
 915         /* we must be in AHCI mode, before using anything
 916          * AHCI-specific, such as HOST_RESET.
 917          */
 918         ahci_enable_ahci(mmio);
 919 
 920         /* global controller reset */
 921         if (!ahci_skip_host_reset) {
 922                 tmp = readl(mmio + HOST_CTL);
 923                 if ((tmp & HOST_RESET) == 0) {
 924                         writel(tmp | HOST_RESET, mmio + HOST_CTL);
 925                         readl(mmio + HOST_CTL); /* flush */
 926                 }
 927 
 928                 /*
 929                  * to perform host reset, OS should set HOST_RESET
 930                  * and poll until this bit is read to be "0".
 931                  * reset must complete within 1 second, or
 932                  * the hardware should be considered fried.
 933                  */
 934                 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
 935                                         HOST_RESET, 10, 1000);
 936 
 937                 if (tmp & HOST_RESET) {
 938                         dev_err(host->dev, "controller reset failed (0x%x)\n",
 939                                 tmp);
 940                         return -EIO;
 941                 }
 942 
 943                 /* turn on AHCI mode */
 944                 ahci_enable_ahci(mmio);
 945 
 946                 /* Some registers might be cleared on reset.  Restore
 947                  * initial values.
 948                  */
 949                 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
 950                         ahci_restore_initial_config(host);
 951         } else
 952                 dev_info(host->dev, "skipping global host reset\n");
 953 
 954         return 0;
 955 }
 956 EXPORT_SYMBOL_GPL(ahci_reset_controller);
 957 
 958 static void ahci_sw_activity(struct ata_link *link)
 959 {
 960         struct ata_port *ap = link->ap;
 961         struct ahci_port_priv *pp = ap->private_data;
 962         struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
 963 
 964         if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
 965                 return;
 966 
 967         emp->activity++;
 968         if (!timer_pending(&emp->timer))
 969                 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
 970 }
 971 
 972 static void ahci_sw_activity_blink(struct timer_list *t)
 973 {
 974         struct ahci_em_priv *emp = from_timer(emp, t, timer);
 975         struct ata_link *link = emp->link;
 976         struct ata_port *ap = link->ap;
 977 
 978         unsigned long led_message = emp->led_state;
 979         u32 activity_led_state;
 980         unsigned long flags;
 981 
 982         led_message &= EM_MSG_LED_VALUE;
 983         led_message |= ap->port_no | (link->pmp << 8);
 984 
 985         /* check to see if we've had activity.  If so,
 986          * toggle state of LED and reset timer.  If not,
 987          * turn LED to desired idle state.
 988          */
 989         spin_lock_irqsave(ap->lock, flags);
 990         if (emp->saved_activity != emp->activity) {
 991                 emp->saved_activity = emp->activity;
 992                 /* get the current LED state */
 993                 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
 994 
 995                 if (activity_led_state)
 996                         activity_led_state = 0;
 997                 else
 998                         activity_led_state = 1;
 999 
1000                 /* clear old state */
1001                 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1002 
1003                 /* toggle state */
1004                 led_message |= (activity_led_state << 16);
1005                 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1006         } else {
1007                 /* switch to idle */
1008                 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1009                 if (emp->blink_policy == BLINK_OFF)
1010                         led_message |= (1 << 16);
1011         }
1012         spin_unlock_irqrestore(ap->lock, flags);
1013         ap->ops->transmit_led_message(ap, led_message, 4);
1014 }
1015 
1016 static void ahci_init_sw_activity(struct ata_link *link)
1017 {
1018         struct ata_port *ap = link->ap;
1019         struct ahci_port_priv *pp = ap->private_data;
1020         struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1021 
1022         /* init activity stats, setup timer */
1023         emp->saved_activity = emp->activity = 0;
1024         emp->link = link;
1025         timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
1026 
1027         /* check our blink policy and set flag for link if it's enabled */
1028         if (emp->blink_policy)
1029                 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1030 }
1031 
1032 int ahci_reset_em(struct ata_host *host)
1033 {
1034         struct ahci_host_priv *hpriv = host->private_data;
1035         void __iomem *mmio = hpriv->mmio;
1036         u32 em_ctl;
1037 
1038         em_ctl = readl(mmio + HOST_EM_CTL);
1039         if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1040                 return -EINVAL;
1041 
1042         writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1043         return 0;
1044 }
1045 EXPORT_SYMBOL_GPL(ahci_reset_em);
1046 
1047 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1048                                         ssize_t size)
1049 {
1050         struct ahci_host_priv *hpriv = ap->host->private_data;
1051         struct ahci_port_priv *pp = ap->private_data;
1052         void __iomem *mmio = hpriv->mmio;
1053         u32 em_ctl;
1054         u32 message[] = {0, 0};
1055         unsigned long flags;
1056         int pmp;
1057         struct ahci_em_priv *emp;
1058 
1059         /* get the slot number from the message */
1060         pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1061         if (pmp < EM_MAX_SLOTS)
1062                 emp = &pp->em_priv[pmp];
1063         else
1064                 return -EINVAL;
1065 
1066         ahci_rpm_get_port(ap);
1067         spin_lock_irqsave(ap->lock, flags);
1068 
1069         /*
1070          * if we are still busy transmitting a previous message,
1071          * do not allow
1072          */
1073         em_ctl = readl(mmio + HOST_EM_CTL);
1074         if (em_ctl & EM_CTL_TM) {
1075                 spin_unlock_irqrestore(ap->lock, flags);
1076                 ahci_rpm_put_port(ap);
1077                 return -EBUSY;
1078         }
1079 
1080         if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1081                 /*
1082                  * create message header - this is all zero except for
1083                  * the message size, which is 4 bytes.
1084                  */
1085                 message[0] |= (4 << 8);
1086 
1087                 /* ignore 0:4 of byte zero, fill in port info yourself */
1088                 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1089 
1090                 /* write message to EM_LOC */
1091                 writel(message[0], mmio + hpriv->em_loc);
1092                 writel(message[1], mmio + hpriv->em_loc+4);
1093 
1094                 /*
1095                  * tell hardware to transmit the message
1096                  */
1097                 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1098         }
1099 
1100         /* save off new led state for port/slot */
1101         emp->led_state = state;
1102 
1103         spin_unlock_irqrestore(ap->lock, flags);
1104         ahci_rpm_put_port(ap);
1105 
1106         return size;
1107 }
1108 
1109 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1110 {
1111         struct ahci_port_priv *pp = ap->private_data;
1112         struct ata_link *link;
1113         struct ahci_em_priv *emp;
1114         int rc = 0;
1115 
1116         ata_for_each_link(link, ap, EDGE) {
1117                 emp = &pp->em_priv[link->pmp];
1118                 rc += sprintf(buf, "%lx\n", emp->led_state);
1119         }
1120         return rc;
1121 }
1122 
1123 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1124                                 size_t size)
1125 {
1126         unsigned int state;
1127         int pmp;
1128         struct ahci_port_priv *pp = ap->private_data;
1129         struct ahci_em_priv *emp;
1130 
1131         if (kstrtouint(buf, 0, &state) < 0)
1132                 return -EINVAL;
1133 
1134         /* get the slot number from the message */
1135         pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1136         if (pmp < EM_MAX_SLOTS) {
1137                 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1138                 emp = &pp->em_priv[pmp];
1139         } else {
1140                 return -EINVAL;
1141         }
1142 
1143         /* mask off the activity bits if we are in sw_activity
1144          * mode, user should turn off sw_activity before setting
1145          * activity led through em_message
1146          */
1147         if (emp->blink_policy)
1148                 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1149 
1150         return ap->ops->transmit_led_message(ap, state, size);
1151 }
1152 
1153 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1154 {
1155         struct ata_link *link = dev->link;
1156         struct ata_port *ap = link->ap;
1157         struct ahci_port_priv *pp = ap->private_data;
1158         struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1159         u32 port_led_state = emp->led_state;
1160 
1161         /* save the desired Activity LED behavior */
1162         if (val == OFF) {
1163                 /* clear LFLAG */
1164                 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1165 
1166                 /* set the LED to OFF */
1167                 port_led_state &= EM_MSG_LED_VALUE_OFF;
1168                 port_led_state |= (ap->port_no | (link->pmp << 8));
1169                 ap->ops->transmit_led_message(ap, port_led_state, 4);
1170         } else {
1171                 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1172                 if (val == BLINK_OFF) {
1173                         /* set LED to ON for idle */
1174                         port_led_state &= EM_MSG_LED_VALUE_OFF;
1175                         port_led_state |= (ap->port_no | (link->pmp << 8));
1176                         port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1177                         ap->ops->transmit_led_message(ap, port_led_state, 4);
1178                 }
1179         }
1180         emp->blink_policy = val;
1181         return 0;
1182 }
1183 
1184 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1185 {
1186         struct ata_link *link = dev->link;
1187         struct ata_port *ap = link->ap;
1188         struct ahci_port_priv *pp = ap->private_data;
1189         struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1190 
1191         /* display the saved value of activity behavior for this
1192          * disk.
1193          */
1194         return sprintf(buf, "%d\n", emp->blink_policy);
1195 }
1196 
1197 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1198                            int port_no, void __iomem *mmio,
1199                            void __iomem *port_mmio)
1200 {
1201         struct ahci_host_priv *hpriv = ap->host->private_data;
1202         const char *emsg = NULL;
1203         int rc;
1204         u32 tmp;
1205 
1206         /* make sure port is not active */
1207         rc = ahci_deinit_port(ap, &emsg);
1208         if (rc)
1209                 dev_warn(dev, "%s (%d)\n", emsg, rc);
1210 
1211         /* clear SError */
1212         tmp = readl(port_mmio + PORT_SCR_ERR);
1213         VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1214         writel(tmp, port_mmio + PORT_SCR_ERR);
1215 
1216         /* clear port IRQ */
1217         tmp = readl(port_mmio + PORT_IRQ_STAT);
1218         VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1219         if (tmp)
1220                 writel(tmp, port_mmio + PORT_IRQ_STAT);
1221 
1222         writel(1 << port_no, mmio + HOST_IRQ_STAT);
1223 
1224         /* mark esata ports */
1225         tmp = readl(port_mmio + PORT_CMD);
1226         if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1227                 ap->pflags |= ATA_PFLAG_EXTERNAL;
1228 }
1229 
1230 void ahci_init_controller(struct ata_host *host)
1231 {
1232         struct ahci_host_priv *hpriv = host->private_data;
1233         void __iomem *mmio = hpriv->mmio;
1234         int i;
1235         void __iomem *port_mmio;
1236         u32 tmp;
1237 
1238         for (i = 0; i < host->n_ports; i++) {
1239                 struct ata_port *ap = host->ports[i];
1240 
1241                 port_mmio = ahci_port_base(ap);
1242                 if (ata_port_is_dummy(ap))
1243                         continue;
1244 
1245                 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1246         }
1247 
1248         tmp = readl(mmio + HOST_CTL);
1249         VPRINTK("HOST_CTL 0x%x\n", tmp);
1250         writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1251         tmp = readl(mmio + HOST_CTL);
1252         VPRINTK("HOST_CTL 0x%x\n", tmp);
1253 }
1254 EXPORT_SYMBOL_GPL(ahci_init_controller);
1255 
1256 static void ahci_dev_config(struct ata_device *dev)
1257 {
1258         struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1259 
1260         if (hpriv->flags & AHCI_HFLAG_SECT255) {
1261                 dev->max_sectors = 255;
1262                 ata_dev_info(dev,
1263                              "SB600 AHCI: limiting to 255 sectors per cmd\n");
1264         }
1265 }
1266 
1267 unsigned int ahci_dev_classify(struct ata_port *ap)
1268 {
1269         void __iomem *port_mmio = ahci_port_base(ap);
1270         struct ata_taskfile tf;
1271         u32 tmp;
1272 
1273         tmp = readl(port_mmio + PORT_SIG);
1274         tf.lbah         = (tmp >> 24)   & 0xff;
1275         tf.lbam         = (tmp >> 16)   & 0xff;
1276         tf.lbal         = (tmp >> 8)    & 0xff;
1277         tf.nsect        = (tmp)         & 0xff;
1278 
1279         return ata_dev_classify(&tf);
1280 }
1281 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1282 
1283 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1284                         u32 opts)
1285 {
1286         dma_addr_t cmd_tbl_dma;
1287 
1288         cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1289 
1290         pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1291         pp->cmd_slot[tag].status = 0;
1292         pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1293         pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1294 }
1295 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1296 
1297 int ahci_kick_engine(struct ata_port *ap)
1298 {
1299         void __iomem *port_mmio = ahci_port_base(ap);
1300         struct ahci_host_priv *hpriv = ap->host->private_data;
1301         u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1302         u32 tmp;
1303         int busy, rc;
1304 
1305         /* stop engine */
1306         rc = hpriv->stop_engine(ap);
1307         if (rc)
1308                 goto out_restart;
1309 
1310         /* need to do CLO?
1311          * always do CLO if PMP is attached (AHCI-1.3 9.2)
1312          */
1313         busy = status & (ATA_BUSY | ATA_DRQ);
1314         if (!busy && !sata_pmp_attached(ap)) {
1315                 rc = 0;
1316                 goto out_restart;
1317         }
1318 
1319         if (!(hpriv->cap & HOST_CAP_CLO)) {
1320                 rc = -EOPNOTSUPP;
1321                 goto out_restart;
1322         }
1323 
1324         /* perform CLO */
1325         tmp = readl(port_mmio + PORT_CMD);
1326         tmp |= PORT_CMD_CLO;
1327         writel(tmp, port_mmio + PORT_CMD);
1328 
1329         rc = 0;
1330         tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1331                                 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1332         if (tmp & PORT_CMD_CLO)
1333                 rc = -EIO;
1334 
1335         /* restart engine */
1336  out_restart:
1337         hpriv->start_engine(ap);
1338         return rc;
1339 }
1340 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1341 
1342 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1343                                 struct ata_taskfile *tf, int is_cmd, u16 flags,
1344                                 unsigned long timeout_msec)
1345 {
1346         const u32 cmd_fis_len = 5; /* five dwords */
1347         struct ahci_port_priv *pp = ap->private_data;
1348         void __iomem *port_mmio = ahci_port_base(ap);
1349         u8 *fis = pp->cmd_tbl;
1350         u32 tmp;
1351 
1352         /* prep the command */
1353         ata_tf_to_fis(tf, pmp, is_cmd, fis);
1354         ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1355 
1356         /* set port value for softreset of Port Multiplier */
1357         if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1358                 tmp = readl(port_mmio + PORT_FBS);
1359                 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1360                 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1361                 writel(tmp, port_mmio + PORT_FBS);
1362                 pp->fbs_last_dev = pmp;
1363         }
1364 
1365         /* issue & wait */
1366         writel(1, port_mmio + PORT_CMD_ISSUE);
1367 
1368         if (timeout_msec) {
1369                 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1370                                         0x1, 0x1, 1, timeout_msec);
1371                 if (tmp & 0x1) {
1372                         ahci_kick_engine(ap);
1373                         return -EBUSY;
1374                 }
1375         } else
1376                 readl(port_mmio + PORT_CMD_ISSUE);      /* flush */
1377 
1378         return 0;
1379 }
1380 
1381 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1382                       int pmp, unsigned long deadline,
1383                       int (*check_ready)(struct ata_link *link))
1384 {
1385         struct ata_port *ap = link->ap;
1386         struct ahci_host_priv *hpriv = ap->host->private_data;
1387         struct ahci_port_priv *pp = ap->private_data;
1388         const char *reason = NULL;
1389         unsigned long now, msecs;
1390         struct ata_taskfile tf;
1391         bool fbs_disabled = false;
1392         int rc;
1393 
1394         DPRINTK("ENTER\n");
1395 
1396         /* prepare for SRST (AHCI-1.1 10.4.1) */
1397         rc = ahci_kick_engine(ap);
1398         if (rc && rc != -EOPNOTSUPP)
1399                 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1400 
1401         /*
1402          * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1403          * clear PxFBS.EN to '0' prior to issuing software reset to devices
1404          * that is attached to port multiplier.
1405          */
1406         if (!ata_is_host_link(link) && pp->fbs_enabled) {
1407                 ahci_disable_fbs(ap);
1408                 fbs_disabled = true;
1409         }
1410 
1411         ata_tf_init(link->device, &tf);
1412 
1413         /* issue the first H2D Register FIS */
1414         msecs = 0;
1415         now = jiffies;
1416         if (time_after(deadline, now))
1417                 msecs = jiffies_to_msecs(deadline - now);
1418 
1419         tf.ctl |= ATA_SRST;
1420         if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1421                                  AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1422                 rc = -EIO;
1423                 reason = "1st FIS failed";
1424                 goto fail;
1425         }
1426 
1427         /* spec says at least 5us, but be generous and sleep for 1ms */
1428         ata_msleep(ap, 1);
1429 
1430         /* issue the second H2D Register FIS */
1431         tf.ctl &= ~ATA_SRST;
1432         ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1433 
1434         /* wait for link to become ready */
1435         rc = ata_wait_after_reset(link, deadline, check_ready);
1436         if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1437                 /*
1438                  * Workaround for cases where link online status can't
1439                  * be trusted.  Treat device readiness timeout as link
1440                  * offline.
1441                  */
1442                 ata_link_info(link, "device not ready, treating as offline\n");
1443                 *class = ATA_DEV_NONE;
1444         } else if (rc) {
1445                 /* link occupied, -ENODEV too is an error */
1446                 reason = "device not ready";
1447                 goto fail;
1448         } else
1449                 *class = ahci_dev_classify(ap);
1450 
1451         /* re-enable FBS if disabled before */
1452         if (fbs_disabled)
1453                 ahci_enable_fbs(ap);
1454 
1455         DPRINTK("EXIT, class=%u\n", *class);
1456         return 0;
1457 
1458  fail:
1459         ata_link_err(link, "softreset failed (%s)\n", reason);
1460         return rc;
1461 }
1462 
1463 int ahci_check_ready(struct ata_link *link)
1464 {
1465         void __iomem *port_mmio = ahci_port_base(link->ap);
1466         u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1467 
1468         return ata_check_ready(status);
1469 }
1470 EXPORT_SYMBOL_GPL(ahci_check_ready);
1471 
1472 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1473                           unsigned long deadline)
1474 {
1475         int pmp = sata_srst_pmp(link);
1476 
1477         DPRINTK("ENTER\n");
1478 
1479         return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1480 }
1481 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1482 
1483 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1484 {
1485         void __iomem *port_mmio = ahci_port_base(link->ap);
1486         u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1487         u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1488 
1489         /*
1490          * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1491          * which can save timeout delay.
1492          */
1493         if (irq_status & PORT_IRQ_BAD_PMP)
1494                 return -EIO;
1495 
1496         return ata_check_ready(status);
1497 }
1498 
1499 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1500                                     unsigned long deadline)
1501 {
1502         struct ata_port *ap = link->ap;
1503         void __iomem *port_mmio = ahci_port_base(ap);
1504         int pmp = sata_srst_pmp(link);
1505         int rc;
1506         u32 irq_sts;
1507 
1508         DPRINTK("ENTER\n");
1509 
1510         rc = ahci_do_softreset(link, class, pmp, deadline,
1511                                ahci_bad_pmp_check_ready);
1512 
1513         /*
1514          * Soft reset fails with IPMS set when PMP is enabled but
1515          * SATA HDD/ODD is connected to SATA port, do soft reset
1516          * again to port 0.
1517          */
1518         if (rc == -EIO) {
1519                 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1520                 if (irq_sts & PORT_IRQ_BAD_PMP) {
1521                         ata_link_warn(link,
1522                                         "applying PMP SRST workaround "
1523                                         "and retrying\n");
1524                         rc = ahci_do_softreset(link, class, 0, deadline,
1525                                                ahci_check_ready);
1526                 }
1527         }
1528 
1529         return rc;
1530 }
1531 
1532 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1533                       unsigned long deadline, bool *online)
1534 {
1535         const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1536         struct ata_port *ap = link->ap;
1537         struct ahci_port_priv *pp = ap->private_data;
1538         struct ahci_host_priv *hpriv = ap->host->private_data;
1539         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1540         struct ata_taskfile tf;
1541         int rc;
1542 
1543         DPRINTK("ENTER\n");
1544 
1545         hpriv->stop_engine(ap);
1546 
1547         /* clear D2H reception area to properly wait for D2H FIS */
1548         ata_tf_init(link->device, &tf);
1549         tf.command = ATA_BUSY;
1550         ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1551 
1552         rc = sata_link_hardreset(link, timing, deadline, online,
1553                                  ahci_check_ready);
1554 
1555         hpriv->start_engine(ap);
1556 
1557         if (*online)
1558                 *class = ahci_dev_classify(ap);
1559 
1560         DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1561         return rc;
1562 }
1563 EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1564 
1565 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1566                           unsigned long deadline)
1567 {
1568         bool online;
1569 
1570         return ahci_do_hardreset(link, class, deadline, &online);
1571 }
1572 
1573 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1574 {
1575         struct ata_port *ap = link->ap;
1576         void __iomem *port_mmio = ahci_port_base(ap);
1577         u32 new_tmp, tmp;
1578 
1579         ata_std_postreset(link, class);
1580 
1581         /* Make sure port's ATAPI bit is set appropriately */
1582         new_tmp = tmp = readl(port_mmio + PORT_CMD);
1583         if (*class == ATA_DEV_ATAPI)
1584                 new_tmp |= PORT_CMD_ATAPI;
1585         else
1586                 new_tmp &= ~PORT_CMD_ATAPI;
1587         if (new_tmp != tmp) {
1588                 writel(new_tmp, port_mmio + PORT_CMD);
1589                 readl(port_mmio + PORT_CMD); /* flush */
1590         }
1591 }
1592 
1593 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1594 {
1595         struct scatterlist *sg;
1596         struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1597         unsigned int si;
1598 
1599         VPRINTK("ENTER\n");
1600 
1601         /*
1602          * Next, the S/G list.
1603          */
1604         for_each_sg(qc->sg, sg, qc->n_elem, si) {
1605                 dma_addr_t addr = sg_dma_address(sg);
1606                 u32 sg_len = sg_dma_len(sg);
1607 
1608                 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1609                 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1610                 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1611         }
1612 
1613         return si;
1614 }
1615 
1616 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1617 {
1618         struct ata_port *ap = qc->ap;
1619         struct ahci_port_priv *pp = ap->private_data;
1620 
1621         if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1622                 return ata_std_qc_defer(qc);
1623         else
1624                 return sata_pmp_qc_defer_cmd_switch(qc);
1625 }
1626 
1627 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1628 {
1629         struct ata_port *ap = qc->ap;
1630         struct ahci_port_priv *pp = ap->private_data;
1631         int is_atapi = ata_is_atapi(qc->tf.protocol);
1632         void *cmd_tbl;
1633         u32 opts;
1634         const u32 cmd_fis_len = 5; /* five dwords */
1635         unsigned int n_elem;
1636 
1637         /*
1638          * Fill in command table information.  First, the header,
1639          * a SATA Register - Host to Device command FIS.
1640          */
1641         cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
1642 
1643         ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1644         if (is_atapi) {
1645                 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1646                 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1647         }
1648 
1649         n_elem = 0;
1650         if (qc->flags & ATA_QCFLAG_DMAMAP)
1651                 n_elem = ahci_fill_sg(qc, cmd_tbl);
1652 
1653         /*
1654          * Fill in command slot information.
1655          */
1656         opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1657         if (qc->tf.flags & ATA_TFLAG_WRITE)
1658                 opts |= AHCI_CMD_WRITE;
1659         if (is_atapi)
1660                 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1661 
1662         ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
1663 }
1664 
1665 static void ahci_fbs_dec_intr(struct ata_port *ap)
1666 {
1667         struct ahci_port_priv *pp = ap->private_data;
1668         void __iomem *port_mmio = ahci_port_base(ap);
1669         u32 fbs = readl(port_mmio + PORT_FBS);
1670         int retries = 3;
1671 
1672         DPRINTK("ENTER\n");
1673         BUG_ON(!pp->fbs_enabled);
1674 
1675         /* time to wait for DEC is not specified by AHCI spec,
1676          * add a retry loop for safety.
1677          */
1678         writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1679         fbs = readl(port_mmio + PORT_FBS);
1680         while ((fbs & PORT_FBS_DEC) && retries--) {
1681                 udelay(1);
1682                 fbs = readl(port_mmio + PORT_FBS);
1683         }
1684 
1685         if (fbs & PORT_FBS_DEC)
1686                 dev_err(ap->host->dev, "failed to clear device error\n");
1687 }
1688 
1689 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1690 {
1691         struct ahci_host_priv *hpriv = ap->host->private_data;
1692         struct ahci_port_priv *pp = ap->private_data;
1693         struct ata_eh_info *host_ehi = &ap->link.eh_info;
1694         struct ata_link *link = NULL;
1695         struct ata_queued_cmd *active_qc;
1696         struct ata_eh_info *active_ehi;
1697         bool fbs_need_dec = false;
1698         u32 serror;
1699 
1700         /* determine active link with error */
1701         if (pp->fbs_enabled) {
1702                 void __iomem *port_mmio = ahci_port_base(ap);
1703                 u32 fbs = readl(port_mmio + PORT_FBS);
1704                 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1705 
1706                 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1707                         link = &ap->pmp_link[pmp];
1708                         fbs_need_dec = true;
1709                 }
1710 
1711         } else
1712                 ata_for_each_link(link, ap, EDGE)
1713                         if (ata_link_active(link))
1714                                 break;
1715 
1716         if (!link)
1717                 link = &ap->link;
1718 
1719         active_qc = ata_qc_from_tag(ap, link->active_tag);
1720         active_ehi = &link->eh_info;
1721 
1722         /* record irq stat */
1723         ata_ehi_clear_desc(host_ehi);
1724         ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1725 
1726         /* AHCI needs SError cleared; otherwise, it might lock up */
1727         ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1728         ahci_scr_write(&ap->link, SCR_ERROR, serror);
1729         host_ehi->serror |= serror;
1730 
1731         /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1732         if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1733                 irq_stat &= ~PORT_IRQ_IF_ERR;
1734 
1735         if (irq_stat & PORT_IRQ_TF_ERR) {
1736                 /* If qc is active, charge it; otherwise, the active
1737                  * link.  There's no active qc on NCQ errors.  It will
1738                  * be determined by EH by reading log page 10h.
1739                  */
1740                 if (active_qc)
1741                         active_qc->err_mask |= AC_ERR_DEV;
1742                 else
1743                         active_ehi->err_mask |= AC_ERR_DEV;
1744 
1745                 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1746                         host_ehi->serror &= ~SERR_INTERNAL;
1747         }
1748 
1749         if (irq_stat & PORT_IRQ_UNK_FIS) {
1750                 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1751 
1752                 active_ehi->err_mask |= AC_ERR_HSM;
1753                 active_ehi->action |= ATA_EH_RESET;
1754                 ata_ehi_push_desc(active_ehi,
1755                                   "unknown FIS %08x %08x %08x %08x" ,
1756                                   unk[0], unk[1], unk[2], unk[3]);
1757         }
1758 
1759         if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1760                 active_ehi->err_mask |= AC_ERR_HSM;
1761                 active_ehi->action |= ATA_EH_RESET;
1762                 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1763         }
1764 
1765         if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1766                 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1767                 host_ehi->action |= ATA_EH_RESET;
1768                 ata_ehi_push_desc(host_ehi, "host bus error");
1769         }
1770 
1771         if (irq_stat & PORT_IRQ_IF_ERR) {
1772                 if (fbs_need_dec)
1773                         active_ehi->err_mask |= AC_ERR_DEV;
1774                 else {
1775                         host_ehi->err_mask |= AC_ERR_ATA_BUS;
1776                         host_ehi->action |= ATA_EH_RESET;
1777                 }
1778 
1779                 ata_ehi_push_desc(host_ehi, "interface fatal error");
1780         }
1781 
1782         if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1783                 ata_ehi_hotplugged(host_ehi);
1784                 ata_ehi_push_desc(host_ehi, "%s",
1785                         irq_stat & PORT_IRQ_CONNECT ?
1786                         "connection status changed" : "PHY RDY changed");
1787         }
1788 
1789         /* okay, let's hand over to EH */
1790 
1791         if (irq_stat & PORT_IRQ_FREEZE)
1792                 ata_port_freeze(ap);
1793         else if (fbs_need_dec) {
1794                 ata_link_abort(link);
1795                 ahci_fbs_dec_intr(ap);
1796         } else
1797                 ata_port_abort(ap);
1798 }
1799 
1800 static void ahci_handle_port_interrupt(struct ata_port *ap,
1801                                        void __iomem *port_mmio, u32 status)
1802 {
1803         struct ata_eh_info *ehi = &ap->link.eh_info;
1804         struct ahci_port_priv *pp = ap->private_data;
1805         struct ahci_host_priv *hpriv = ap->host->private_data;
1806         int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1807         u32 qc_active = 0;
1808         int rc;
1809 
1810         /* ignore BAD_PMP while resetting */
1811         if (unlikely(resetting))
1812                 status &= ~PORT_IRQ_BAD_PMP;
1813 
1814         if (sata_lpm_ignore_phy_events(&ap->link)) {
1815                 status &= ~PORT_IRQ_PHYRDY;
1816                 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1817         }
1818 
1819         if (unlikely(status & PORT_IRQ_ERROR)) {
1820                 ahci_error_intr(ap, status);
1821                 return;
1822         }
1823 
1824         if (status & PORT_IRQ_SDB_FIS) {
1825                 /* If SNotification is available, leave notification
1826                  * handling to sata_async_notification().  If not,
1827                  * emulate it by snooping SDB FIS RX area.
1828                  *
1829                  * Snooping FIS RX area is probably cheaper than
1830                  * poking SNotification but some constrollers which
1831                  * implement SNotification, ICH9 for example, don't
1832                  * store AN SDB FIS into receive area.
1833                  */
1834                 if (hpriv->cap & HOST_CAP_SNTF)
1835                         sata_async_notification(ap);
1836                 else {
1837                         /* If the 'N' bit in word 0 of the FIS is set,
1838                          * we just received asynchronous notification.
1839                          * Tell libata about it.
1840                          *
1841                          * Lack of SNotification should not appear in
1842                          * ahci 1.2, so the workaround is unnecessary
1843                          * when FBS is enabled.
1844                          */
1845                         if (pp->fbs_enabled)
1846                                 WARN_ON_ONCE(1);
1847                         else {
1848                                 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1849                                 u32 f0 = le32_to_cpu(f[0]);
1850                                 if (f0 & (1 << 15))
1851                                         sata_async_notification(ap);
1852                         }
1853                 }
1854         }
1855 
1856         /* pp->active_link is not reliable once FBS is enabled, both
1857          * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1858          * NCQ and non-NCQ commands may be in flight at the same time.
1859          */
1860         if (pp->fbs_enabled) {
1861                 if (ap->qc_active) {
1862                         qc_active = readl(port_mmio + PORT_SCR_ACT);
1863                         qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1864                 }
1865         } else {
1866                 /* pp->active_link is valid iff any command is in flight */
1867                 if (ap->qc_active && pp->active_link->sactive)
1868                         qc_active = readl(port_mmio + PORT_SCR_ACT);
1869                 else
1870                         qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1871         }
1872 
1873 
1874         rc = ata_qc_complete_multiple(ap, qc_active);
1875 
1876         /* while resetting, invalid completions are expected */
1877         if (unlikely(rc < 0 && !resetting)) {
1878                 ehi->err_mask |= AC_ERR_HSM;
1879                 ehi->action |= ATA_EH_RESET;
1880                 ata_port_freeze(ap);
1881         }
1882 }
1883 
1884 static void ahci_port_intr(struct ata_port *ap)
1885 {
1886         void __iomem *port_mmio = ahci_port_base(ap);
1887         u32 status;
1888 
1889         status = readl(port_mmio + PORT_IRQ_STAT);
1890         writel(status, port_mmio + PORT_IRQ_STAT);
1891 
1892         ahci_handle_port_interrupt(ap, port_mmio, status);
1893 }
1894 
1895 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1896 {
1897         struct ata_port *ap = dev_instance;
1898         void __iomem *port_mmio = ahci_port_base(ap);
1899         u32 status;
1900 
1901         VPRINTK("ENTER\n");
1902 
1903         status = readl(port_mmio + PORT_IRQ_STAT);
1904         writel(status, port_mmio + PORT_IRQ_STAT);
1905 
1906         spin_lock(ap->lock);
1907         ahci_handle_port_interrupt(ap, port_mmio, status);
1908         spin_unlock(ap->lock);
1909 
1910         VPRINTK("EXIT\n");
1911 
1912         return IRQ_HANDLED;
1913 }
1914 
1915 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1916 {
1917         unsigned int i, handled = 0;
1918 
1919         for (i = 0; i < host->n_ports; i++) {
1920                 struct ata_port *ap;
1921 
1922                 if (!(irq_masked & (1 << i)))
1923                         continue;
1924 
1925                 ap = host->ports[i];
1926                 if (ap) {
1927                         ahci_port_intr(ap);
1928                         VPRINTK("port %u\n", i);
1929                 } else {
1930                         VPRINTK("port %u (no irq)\n", i);
1931                         if (ata_ratelimit())
1932                                 dev_warn(host->dev,
1933                                          "interrupt on disabled port %u\n", i);
1934                 }
1935 
1936                 handled = 1;
1937         }
1938 
1939         return handled;
1940 }
1941 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1942 
1943 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1944 {
1945         struct ata_host *host = dev_instance;
1946         struct ahci_host_priv *hpriv;
1947         unsigned int rc = 0;
1948         void __iomem *mmio;
1949         u32 irq_stat, irq_masked;
1950 
1951         VPRINTK("ENTER\n");
1952 
1953         hpriv = host->private_data;
1954         mmio = hpriv->mmio;
1955 
1956         /* sigh.  0xffffffff is a valid return from h/w */
1957         irq_stat = readl(mmio + HOST_IRQ_STAT);
1958         if (!irq_stat)
1959                 return IRQ_NONE;
1960 
1961         irq_masked = irq_stat & hpriv->port_map;
1962 
1963         spin_lock(&host->lock);
1964 
1965         rc = ahci_handle_port_intr(host, irq_masked);
1966 
1967         /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1968          * it should be cleared after all the port events are cleared;
1969          * otherwise, it will raise a spurious interrupt after each
1970          * valid one.  Please read section 10.6.2 of ahci 1.1 for more
1971          * information.
1972          *
1973          * Also, use the unmasked value to clear interrupt as spurious
1974          * pending event on a dummy port might cause screaming IRQ.
1975          */
1976         writel(irq_stat, mmio + HOST_IRQ_STAT);
1977 
1978         spin_unlock(&host->lock);
1979 
1980         VPRINTK("EXIT\n");
1981 
1982         return IRQ_RETVAL(rc);
1983 }
1984 
1985 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1986 {
1987         struct ata_port *ap = qc->ap;
1988         void __iomem *port_mmio = ahci_port_base(ap);
1989         struct ahci_port_priv *pp = ap->private_data;
1990 
1991         /* Keep track of the currently active link.  It will be used
1992          * in completion path to determine whether NCQ phase is in
1993          * progress.
1994          */
1995         pp->active_link = qc->dev->link;
1996 
1997         if (ata_is_ncq(qc->tf.protocol))
1998                 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
1999 
2000         if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2001                 u32 fbs = readl(port_mmio + PORT_FBS);
2002                 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2003                 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2004                 writel(fbs, port_mmio + PORT_FBS);
2005                 pp->fbs_last_dev = qc->dev->link->pmp;
2006         }
2007 
2008         writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
2009 
2010         ahci_sw_activity(qc->dev->link);
2011 
2012         return 0;
2013 }
2014 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2015 
2016 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2017 {
2018         struct ahci_port_priv *pp = qc->ap->private_data;
2019         u8 *rx_fis = pp->rx_fis;
2020 
2021         if (pp->fbs_enabled)
2022                 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2023 
2024         /*
2025          * After a successful execution of an ATA PIO data-in command,
2026          * the device doesn't send D2H Reg FIS to update the TF and
2027          * the host should take TF and E_Status from the preceding PIO
2028          * Setup FIS.
2029          */
2030         if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2031             !(qc->flags & ATA_QCFLAG_FAILED)) {
2032                 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2033                 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2034         } else
2035                 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2036 
2037         return true;
2038 }
2039 
2040 static void ahci_freeze(struct ata_port *ap)
2041 {
2042         void __iomem *port_mmio = ahci_port_base(ap);
2043 
2044         /* turn IRQ off */
2045         writel(0, port_mmio + PORT_IRQ_MASK);
2046 }
2047 
2048 static void ahci_thaw(struct ata_port *ap)
2049 {
2050         struct ahci_host_priv *hpriv = ap->host->private_data;
2051         void __iomem *mmio = hpriv->mmio;
2052         void __iomem *port_mmio = ahci_port_base(ap);
2053         u32 tmp;
2054         struct ahci_port_priv *pp = ap->private_data;
2055 
2056         /* clear IRQ */
2057         tmp = readl(port_mmio + PORT_IRQ_STAT);
2058         writel(tmp, port_mmio + PORT_IRQ_STAT);
2059         writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2060 
2061         /* turn IRQ back on */
2062         writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2063 }
2064 
2065 void ahci_error_handler(struct ata_port *ap)
2066 {
2067         struct ahci_host_priv *hpriv = ap->host->private_data;
2068 
2069         if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2070                 /* restart engine */
2071                 hpriv->stop_engine(ap);
2072                 hpriv->start_engine(ap);
2073         }
2074 
2075         sata_pmp_error_handler(ap);
2076 
2077         if (!ata_dev_enabled(ap->link.device))
2078                 hpriv->stop_engine(ap);
2079 }
2080 EXPORT_SYMBOL_GPL(ahci_error_handler);
2081 
2082 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2083 {
2084         struct ata_port *ap = qc->ap;
2085 
2086         /* make DMA engine forget about the failed command */
2087         if (qc->flags & ATA_QCFLAG_FAILED)
2088                 ahci_kick_engine(ap);
2089 }
2090 
2091 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2092 {
2093         struct ahci_host_priv *hpriv = ap->host->private_data;
2094         void __iomem *port_mmio = ahci_port_base(ap);
2095         struct ata_device *dev = ap->link.device;
2096         u32 devslp, dm, dito, mdat, deto, dito_conf;
2097         int rc;
2098         unsigned int err_mask;
2099 
2100         devslp = readl(port_mmio + PORT_DEVSLP);
2101         if (!(devslp & PORT_DEVSLP_DSP)) {
2102                 dev_info(ap->host->dev, "port does not support device sleep\n");
2103                 return;
2104         }
2105 
2106         /* disable device sleep */
2107         if (!sleep) {
2108                 if (devslp & PORT_DEVSLP_ADSE) {
2109                         writel(devslp & ~PORT_DEVSLP_ADSE,
2110                                port_mmio + PORT_DEVSLP);
2111                         err_mask = ata_dev_set_feature(dev,
2112                                                        SETFEATURES_SATA_DISABLE,
2113                                                        SATA_DEVSLP);
2114                         if (err_mask && err_mask != AC_ERR_DEV)
2115                                 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2116                 }
2117                 return;
2118         }
2119 
2120         dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2121         dito = devslp_idle_timeout / (dm + 1);
2122         if (dito > 0x3ff)
2123                 dito = 0x3ff;
2124 
2125         dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2126 
2127         /* device sleep was already enabled and same dito */
2128         if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
2129                 return;
2130 
2131         /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2132         rc = hpriv->stop_engine(ap);
2133         if (rc)
2134                 return;
2135 
2136         /* Use the nominal value 10 ms if the read MDAT is zero,
2137          * the nominal value of DETO is 20 ms.
2138          */
2139         if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2140             ATA_LOG_DEVSLP_VALID_MASK) {
2141                 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2142                        ATA_LOG_DEVSLP_MDAT_MASK;
2143                 if (!mdat)
2144                         mdat = 10;
2145                 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2146                 if (!deto)
2147                         deto = 20;
2148         } else {
2149                 mdat = 10;
2150                 deto = 20;
2151         }
2152 
2153         /* Make dito, mdat, deto bits to 0s */
2154         devslp &= ~GENMASK_ULL(24, 2);
2155         devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2156                    (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2157                    (deto << PORT_DEVSLP_DETO_OFFSET) |
2158                    PORT_DEVSLP_ADSE);
2159         writel(devslp, port_mmio + PORT_DEVSLP);
2160 
2161         hpriv->start_engine(ap);
2162 
2163         /* enable device sleep feature for the drive */
2164         err_mask = ata_dev_set_feature(dev,
2165                                        SETFEATURES_SATA_ENABLE,
2166                                        SATA_DEVSLP);
2167         if (err_mask && err_mask != AC_ERR_DEV)
2168                 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2169 }
2170 
2171 static void ahci_enable_fbs(struct ata_port *ap)
2172 {
2173         struct ahci_host_priv *hpriv = ap->host->private_data;
2174         struct ahci_port_priv *pp = ap->private_data;
2175         void __iomem *port_mmio = ahci_port_base(ap);
2176         u32 fbs;
2177         int rc;
2178 
2179         if (!pp->fbs_supported)
2180                 return;
2181 
2182         fbs = readl(port_mmio + PORT_FBS);
2183         if (fbs & PORT_FBS_EN) {
2184                 pp->fbs_enabled = true;
2185                 pp->fbs_last_dev = -1; /* initialization */
2186                 return;
2187         }
2188 
2189         rc = hpriv->stop_engine(ap);
2190         if (rc)
2191                 return;
2192 
2193         writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2194         fbs = readl(port_mmio + PORT_FBS);
2195         if (fbs & PORT_FBS_EN) {
2196                 dev_info(ap->host->dev, "FBS is enabled\n");
2197                 pp->fbs_enabled = true;
2198                 pp->fbs_last_dev = -1; /* initialization */
2199         } else
2200                 dev_err(ap->host->dev, "Failed to enable FBS\n");
2201 
2202         hpriv->start_engine(ap);
2203 }
2204 
2205 static void ahci_disable_fbs(struct ata_port *ap)
2206 {
2207         struct ahci_host_priv *hpriv = ap->host->private_data;
2208         struct ahci_port_priv *pp = ap->private_data;
2209         void __iomem *port_mmio = ahci_port_base(ap);
2210         u32 fbs;
2211         int rc;
2212 
2213         if (!pp->fbs_supported)
2214                 return;
2215 
2216         fbs = readl(port_mmio + PORT_FBS);
2217         if ((fbs & PORT_FBS_EN) == 0) {
2218                 pp->fbs_enabled = false;
2219                 return;
2220         }
2221 
2222         rc = hpriv->stop_engine(ap);
2223         if (rc)
2224                 return;
2225 
2226         writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2227         fbs = readl(port_mmio + PORT_FBS);
2228         if (fbs & PORT_FBS_EN)
2229                 dev_err(ap->host->dev, "Failed to disable FBS\n");
2230         else {
2231                 dev_info(ap->host->dev, "FBS is disabled\n");
2232                 pp->fbs_enabled = false;
2233         }
2234 
2235         hpriv->start_engine(ap);
2236 }
2237 
2238 static void ahci_pmp_attach(struct ata_port *ap)
2239 {
2240         void __iomem *port_mmio = ahci_port_base(ap);
2241         struct ahci_port_priv *pp = ap->private_data;
2242         u32 cmd;
2243 
2244         cmd = readl(port_mmio + PORT_CMD);
2245         cmd |= PORT_CMD_PMP;
2246         writel(cmd, port_mmio + PORT_CMD);
2247 
2248         ahci_enable_fbs(ap);
2249 
2250         pp->intr_mask |= PORT_IRQ_BAD_PMP;
2251 
2252         /*
2253          * We must not change the port interrupt mask register if the
2254          * port is marked frozen, the value in pp->intr_mask will be
2255          * restored later when the port is thawed.
2256          *
2257          * Note that during initialization, the port is marked as
2258          * frozen since the irq handler is not yet registered.
2259          */
2260         if (!(ap->pflags & ATA_PFLAG_FROZEN))
2261                 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2262 }
2263 
2264 static void ahci_pmp_detach(struct ata_port *ap)
2265 {
2266         void __iomem *port_mmio = ahci_port_base(ap);
2267         struct ahci_port_priv *pp = ap->private_data;
2268         u32 cmd;
2269 
2270         ahci_disable_fbs(ap);
2271 
2272         cmd = readl(port_mmio + PORT_CMD);
2273         cmd &= ~PORT_CMD_PMP;
2274         writel(cmd, port_mmio + PORT_CMD);
2275 
2276         pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2277 
2278         /* see comment above in ahci_pmp_attach() */
2279         if (!(ap->pflags & ATA_PFLAG_FROZEN))
2280                 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2281 }
2282 
2283 int ahci_port_resume(struct ata_port *ap)
2284 {
2285         ahci_rpm_get_port(ap);
2286 
2287         ahci_power_up(ap);
2288         ahci_start_port(ap);
2289 
2290         if (sata_pmp_attached(ap))
2291                 ahci_pmp_attach(ap);
2292         else
2293                 ahci_pmp_detach(ap);
2294 
2295         return 0;
2296 }
2297 EXPORT_SYMBOL_GPL(ahci_port_resume);
2298 
2299 #ifdef CONFIG_PM
2300 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2301 {
2302         const char *emsg = NULL;
2303         int rc;
2304 
2305         rc = ahci_deinit_port(ap, &emsg);
2306         if (rc == 0)
2307                 ahci_power_down(ap);
2308         else {
2309                 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2310                 ata_port_freeze(ap);
2311         }
2312 
2313         ahci_rpm_put_port(ap);
2314         return rc;
2315 }
2316 #endif
2317 
2318 static int ahci_port_start(struct ata_port *ap)
2319 {
2320         struct ahci_host_priv *hpriv = ap->host->private_data;
2321         struct device *dev = ap->host->dev;
2322         struct ahci_port_priv *pp;
2323         void *mem;
2324         dma_addr_t mem_dma;
2325         size_t dma_sz, rx_fis_sz;
2326 
2327         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2328         if (!pp)
2329                 return -ENOMEM;
2330 
2331         if (ap->host->n_ports > 1) {
2332                 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2333                 if (!pp->irq_desc) {
2334                         devm_kfree(dev, pp);
2335                         return -ENOMEM;
2336                 }
2337                 snprintf(pp->irq_desc, 8,
2338                          "%s%d", dev_driver_string(dev), ap->port_no);
2339         }
2340 
2341         /* check FBS capability */
2342         if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2343                 void __iomem *port_mmio = ahci_port_base(ap);
2344                 u32 cmd = readl(port_mmio + PORT_CMD);
2345                 if (cmd & PORT_CMD_FBSCP)
2346                         pp->fbs_supported = true;
2347                 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2348                         dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2349                                  ap->port_no);
2350                         pp->fbs_supported = true;
2351                 } else
2352                         dev_warn(dev, "port %d is not capable of FBS\n",
2353                                  ap->port_no);
2354         }
2355 
2356         if (pp->fbs_supported) {
2357                 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2358                 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2359         } else {
2360                 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2361                 rx_fis_sz = AHCI_RX_FIS_SZ;
2362         }
2363 
2364         mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2365         if (!mem)
2366                 return -ENOMEM;
2367 
2368         /*
2369          * First item in chunk of DMA memory: 32-slot command table,
2370          * 32 bytes each in size
2371          */
2372         pp->cmd_slot = mem;
2373         pp->cmd_slot_dma = mem_dma;
2374 
2375         mem += AHCI_CMD_SLOT_SZ;
2376         mem_dma += AHCI_CMD_SLOT_SZ;
2377 
2378         /*
2379          * Second item: Received-FIS area
2380          */
2381         pp->rx_fis = mem;
2382         pp->rx_fis_dma = mem_dma;
2383 
2384         mem += rx_fis_sz;
2385         mem_dma += rx_fis_sz;
2386 
2387         /*
2388          * Third item: data area for storing a single command
2389          * and its scatter-gather table
2390          */
2391         pp->cmd_tbl = mem;
2392         pp->cmd_tbl_dma = mem_dma;
2393 
2394         /*
2395          * Save off initial list of interrupts to be enabled.
2396          * This could be changed later
2397          */
2398         pp->intr_mask = DEF_PORT_IRQ;
2399 
2400         /*
2401          * Switch to per-port locking in case each port has its own MSI vector.
2402          */
2403         if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2404                 spin_lock_init(&pp->lock);
2405                 ap->lock = &pp->lock;
2406         }
2407 
2408         ap->private_data = pp;
2409 
2410         /* engage engines, captain */
2411         return ahci_port_resume(ap);
2412 }
2413 
2414 static void ahci_port_stop(struct ata_port *ap)
2415 {
2416         const char *emsg = NULL;
2417         struct ahci_host_priv *hpriv = ap->host->private_data;
2418         void __iomem *host_mmio = hpriv->mmio;
2419         int rc;
2420 
2421         /* de-initialize port */
2422         rc = ahci_deinit_port(ap, &emsg);
2423         if (rc)
2424                 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2425 
2426         /*
2427          * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2428          * re-enabling INTx.
2429          */
2430         writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2431 
2432         ahci_rpm_put_port(ap);
2433 }
2434 
2435 void ahci_print_info(struct ata_host *host, const char *scc_s)
2436 {
2437         struct ahci_host_priv *hpriv = host->private_data;
2438         u32 vers, cap, cap2, impl, speed;
2439         const char *speed_s;
2440 
2441         vers = hpriv->version;
2442         cap = hpriv->cap;
2443         cap2 = hpriv->cap2;
2444         impl = hpriv->port_map;
2445 
2446         speed = (cap >> 20) & 0xf;
2447         if (speed == 1)
2448                 speed_s = "1.5";
2449         else if (speed == 2)
2450                 speed_s = "3";
2451         else if (speed == 3)
2452                 speed_s = "6";
2453         else
2454                 speed_s = "?";
2455 
2456         dev_info(host->dev,
2457                 "AHCI %02x%02x.%02x%02x "
2458                 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2459                 ,
2460 
2461                 (vers >> 24) & 0xff,
2462                 (vers >> 16) & 0xff,
2463                 (vers >> 8) & 0xff,
2464                 vers & 0xff,
2465 
2466                 ((cap >> 8) & 0x1f) + 1,
2467                 (cap & 0x1f) + 1,
2468                 speed_s,
2469                 impl,
2470                 scc_s);
2471 
2472         dev_info(host->dev,
2473                 "flags: "
2474                 "%s%s%s%s%s%s%s"
2475                 "%s%s%s%s%s%s%s"
2476                 "%s%s%s%s%s%s%s"
2477                 "%s%s\n"
2478                 ,
2479 
2480                 cap & HOST_CAP_64 ? "64bit " : "",
2481                 cap & HOST_CAP_NCQ ? "ncq " : "",
2482                 cap & HOST_CAP_SNTF ? "sntf " : "",
2483                 cap & HOST_CAP_MPS ? "ilck " : "",
2484                 cap & HOST_CAP_SSS ? "stag " : "",
2485                 cap & HOST_CAP_ALPM ? "pm " : "",
2486                 cap & HOST_CAP_LED ? "led " : "",
2487                 cap & HOST_CAP_CLO ? "clo " : "",
2488                 cap & HOST_CAP_ONLY ? "only " : "",
2489                 cap & HOST_CAP_PMP ? "pmp " : "",
2490                 cap & HOST_CAP_FBS ? "fbs " : "",
2491                 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2492                 cap & HOST_CAP_SSC ? "slum " : "",
2493                 cap & HOST_CAP_PART ? "part " : "",
2494                 cap & HOST_CAP_CCC ? "ccc " : "",
2495                 cap & HOST_CAP_EMS ? "ems " : "",
2496                 cap & HOST_CAP_SXS ? "sxs " : "",
2497                 cap2 & HOST_CAP2_DESO ? "deso " : "",
2498                 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2499                 cap2 & HOST_CAP2_SDS ? "sds " : "",
2500                 cap2 & HOST_CAP2_APST ? "apst " : "",
2501                 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2502                 cap2 & HOST_CAP2_BOH ? "boh " : ""
2503                 );
2504 }
2505 EXPORT_SYMBOL_GPL(ahci_print_info);
2506 
2507 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2508                           struct ata_port_info *pi)
2509 {
2510         u8 messages;
2511         void __iomem *mmio = hpriv->mmio;
2512         u32 em_loc = readl(mmio + HOST_EM_LOC);
2513         u32 em_ctl = readl(mmio + HOST_EM_CTL);
2514 
2515         if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2516                 return;
2517 
2518         messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2519 
2520         if (messages) {
2521                 /* store em_loc */
2522                 hpriv->em_loc = ((em_loc >> 16) * 4);
2523                 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2524                 hpriv->em_msg_type = messages;
2525                 pi->flags |= ATA_FLAG_EM;
2526                 if (!(em_ctl & EM_CTL_ALHD))
2527                         pi->flags |= ATA_FLAG_SW_ACTIVITY;
2528         }
2529 }
2530 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2531 
2532 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2533                                          struct scsi_host_template *sht)
2534 {
2535         struct ahci_host_priv *hpriv = host->private_data;
2536         int i, rc;
2537 
2538         rc = ata_host_start(host);
2539         if (rc)
2540                 return rc;
2541         /*
2542          * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2543          * allocated. That is one MSI per port, starting from @irq.
2544          */
2545         for (i = 0; i < host->n_ports; i++) {
2546                 struct ahci_port_priv *pp = host->ports[i]->private_data;
2547                 int irq = hpriv->get_irq_vector(host, i);
2548 
2549                 /* Do not receive interrupts sent by dummy ports */
2550                 if (!pp) {
2551                         disable_irq(irq);
2552                         continue;
2553                 }
2554 
2555                 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2556                                 0, pp->irq_desc, host->ports[i]);
2557 
2558                 if (rc)
2559                         return rc;
2560                 ata_port_desc(host->ports[i], "irq %d", irq);
2561         }
2562 
2563         return ata_host_register(host, sht);
2564 }
2565 
2566 /**
2567  *      ahci_host_activate - start AHCI host, request IRQs and register it
2568  *      @host: target ATA host
2569  *      @sht: scsi_host_template to use when registering the host
2570  *
2571  *      LOCKING:
2572  *      Inherited from calling layer (may sleep).
2573  *
2574  *      RETURNS:
2575  *      0 on success, -errno otherwise.
2576  */
2577 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2578 {
2579         struct ahci_host_priv *hpriv = host->private_data;
2580         int irq = hpriv->irq;
2581         int rc;
2582 
2583         if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2584                 if (hpriv->irq_handler &&
2585                     hpriv->irq_handler != ahci_single_level_irq_intr)
2586                         dev_warn(host->dev,
2587                                  "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2588                 if (!hpriv->get_irq_vector) {
2589                         dev_err(host->dev,
2590                                 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2591                         return -EIO;
2592                 }
2593 
2594                 rc = ahci_host_activate_multi_irqs(host, sht);
2595         } else {
2596                 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2597                                        IRQF_SHARED, sht);
2598         }
2599 
2600 
2601         return rc;
2602 }
2603 EXPORT_SYMBOL_GPL(ahci_host_activate);
2604 
2605 MODULE_AUTHOR("Jeff Garzik");
2606 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2607 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/ata/libahci.c

DEFINITIONS
