1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * pata_mpiix.c - Intel MPIIX PATA for new ATA layer
4 * (C) 2005-2006 Red Hat Inc
5 * Alan Cox <alan@lxorguk.ukuu.org.uk>
6 *
7 * The MPIIX is different enough to the PIIX4 and friends that we give it
8 * a separate driver. The old ide/pci code handles this by just not tuning
9 * MPIIX at all.
10 *
11 * The MPIIX also differs in another important way from the majority of PIIX
12 * devices. The chip is a bridge (pardon the pun) between the old world of
13 * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
14 * IDE controller is not decoded in PCI space and the chip does not claim to
15 * be IDE class PCI. This requires slightly non-standard probe logic compared
16 * with PCI IDE and also that we do not disable the device when our driver is
17 * unloaded (as it has many other functions).
18 *
19 * The driver consciously keeps this logic internally to avoid pushing quirky
20 * PATA history into the clean libata layer.
21 *
22 * Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
23 * hard disk present this driver will not detect it. This is not a bug. In this
24 * configuration the secondary port of the MPIIX is disabled and the addresses
25 * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
26 * to operate.
27 */
28
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/blkdev.h>
33 #include <linux/delay.h>
34 #include <scsi/scsi_host.h>
35 #include <linux/libata.h>
36
37 #define DRV_NAME "pata_mpiix"
38 #define DRV_VERSION "0.7.7"
39
40 enum {
41 IDETIM = 0x6C, /* IDE control register */
42 IORDY = (1 << 1),
43 PPE = (1 << 2),
44 FTIM = (1 << 0),
45 ENABLED = (1 << 15),
46 SECONDARY = (1 << 14)
47 };
48
49 static int mpiix_pre_reset(struct ata_link *link, unsigned long deadline)
50 {
51 struct ata_port *ap = link->ap;
52 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
53 static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 };
54
55 if (!pci_test_config_bits(pdev, &mpiix_enable_bits))
56 return -ENOENT;
57
58 return ata_sff_prereset(link, deadline);
59 }
60
61 /**
62 * mpiix_set_piomode - set initial PIO mode data
63 * @ap: ATA interface
64 * @adev: ATA device
65 *
66 * Called to do the PIO mode setup. The MPIIX allows us to program the
67 * IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
68 * prefetching or IORDY are used.
69 *
70 * This would get very ugly because we can only program timing for one
71 * device at a time, the other gets PIO0. Fortunately libata calls
72 * our qc_issue command before a command is issued so we can flip the
73 * timings back and forth to reduce the pain.
74 */
75
76 static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
77 {
78 int control = 0;
79 int pio = adev->pio_mode - XFER_PIO_0;
80 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
81 u16 idetim;
82 static const /* ISP RTC */
83 u8 timings[][2] = { { 0, 0 },
84 { 0, 0 },
85 { 1, 0 },
86 { 2, 1 },
87 { 2, 3 }, };
88
89 pci_read_config_word(pdev, IDETIM, &idetim);
90
91 /* Mask the IORDY/TIME/PPE for this device */
92 if (adev->class == ATA_DEV_ATA)
93 control |= PPE; /* Enable prefetch/posting for disk */
94 if (ata_pio_need_iordy(adev))
95 control |= IORDY;
96 if (pio > 1)
97 control |= FTIM; /* This drive is on the fast timing bank */
98
99 /* Mask out timing and clear both TIME bank selects */
100 idetim &= 0xCCEE;
101 idetim &= ~(0x07 << (4 * adev->devno));
102 idetim |= control << (4 * adev->devno);
103
104 idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
105 pci_write_config_word(pdev, IDETIM, idetim);
106
107 /* We use ap->private_data as a pointer to the device currently
108 loaded for timing */
109 ap->private_data = adev;
110 }
111
112 /**
113 * mpiix_qc_issue - command issue
114 * @qc: command pending
115 *
116 * Called when the libata layer is about to issue a command. We wrap
117 * this interface so that we can load the correct ATA timings if
118 * necessary. Our logic also clears TIME0/TIME1 for the other device so
119 * that, even if we get this wrong, cycles to the other device will
120 * be made PIO0.
121 */
122
123 static unsigned int mpiix_qc_issue(struct ata_queued_cmd *qc)
124 {
125 struct ata_port *ap = qc->ap;
126 struct ata_device *adev = qc->dev;
127
128 /* If modes have been configured and the channel data is not loaded
129 then load it. We have to check if pio_mode is set as the core code
130 does not set adev->pio_mode to XFER_PIO_0 while probing as would be
131 logical */
132
133 if (adev->pio_mode && adev != ap->private_data)
134 mpiix_set_piomode(ap, adev);
135
136 return ata_sff_qc_issue(qc);
137 }
138
139 static struct scsi_host_template mpiix_sht = {
140 ATA_PIO_SHT(DRV_NAME),
141 };
142
143 static struct ata_port_operations mpiix_port_ops = {
144 .inherits = &ata_sff_port_ops,
145 .qc_issue = mpiix_qc_issue,
146 .cable_detect = ata_cable_40wire,
147 .set_piomode = mpiix_set_piomode,
148 .prereset = mpiix_pre_reset,
149 .sff_data_xfer = ata_sff_data_xfer32,
150 };
151
152 static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
153 {
154 /* Single threaded by the PCI probe logic */
155 struct ata_host *host;
156 struct ata_port *ap;
157 void __iomem *cmd_addr, *ctl_addr;
158 u16 idetim;
159 int cmd, ctl, irq;
160
161 ata_print_version_once(&dev->dev, DRV_VERSION);
162
163 host = ata_host_alloc(&dev->dev, 1);
164 if (!host)
165 return -ENOMEM;
166 ap = host->ports[0];
167
168 /* MPIIX has many functions which can be turned on or off according
169 to other devices present. Make sure IDE is enabled before we try
170 and use it */
171
172 pci_read_config_word(dev, IDETIM, &idetim);
173 if (!(idetim & ENABLED))
174 return -ENODEV;
175
176 /* See if it's primary or secondary channel... */
177 if (!(idetim & SECONDARY)) {
178 cmd = 0x1F0;
179 ctl = 0x3F6;
180 irq = 14;
181 } else {
182 cmd = 0x170;
183 ctl = 0x376;
184 irq = 15;
185 }
186
187 cmd_addr = devm_ioport_map(&dev->dev, cmd, 8);
188 ctl_addr = devm_ioport_map(&dev->dev, ctl, 1);
189 if (!cmd_addr || !ctl_addr)
190 return -ENOMEM;
191
192 ata_port_desc(ap, "cmd 0x%x ctl 0x%x", cmd, ctl);
193
194 /* We do our own plumbing to avoid leaking special cases for whacko
195 ancient hardware into the core code. There are two issues to
196 worry about. #1 The chip is a bridge so if in legacy mode and
197 without BARs set fools the setup. #2 If you pci_disable_device
198 the MPIIX your box goes castors up */
199
200 ap->ops = &mpiix_port_ops;
201 ap->pio_mask = ATA_PIO4;
202 ap->flags |= ATA_FLAG_SLAVE_POSS;
203
204 ap->ioaddr.cmd_addr = cmd_addr;
205 ap->ioaddr.ctl_addr = ctl_addr;
206 ap->ioaddr.altstatus_addr = ctl_addr;
207
208 /* Let libata fill in the port details */
209 ata_sff_std_ports(&ap->ioaddr);
210
211 /* activate host */
212 return ata_host_activate(host, irq, ata_sff_interrupt, IRQF_SHARED,
213 &mpiix_sht);
214 }
215
216 static const struct pci_device_id mpiix[] = {
217 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },
218
219 { },
220 };
221
222 static struct pci_driver mpiix_pci_driver = {
223 .name = DRV_NAME,
224 .id_table = mpiix,
225 .probe = mpiix_init_one,
226 .remove = ata_pci_remove_one,
227 #ifdef CONFIG_PM_SLEEP
228 .suspend = ata_pci_device_suspend,
229 .resume = ata_pci_device_resume,
230 #endif
231 };
232
233 module_pci_driver(mpiix_pci_driver);
234
235 MODULE_AUTHOR("Alan Cox");
236 MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
237 MODULE_LICENSE("GPL");
238 MODULE_DEVICE_TABLE(pci, mpiix);
239 MODULE_VERSION(DRV_VERSION);