drivers/ata/sata

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This source file includes following definitions.
fsl_sata_set_irq_coalescing
fsl_sata_intr_coalescing_show
fsl_sata_intr_coalescing_store
fsl_sata_rx_watermark_show
fsl_sata_rx_watermark_store
sata_fsl_tag
sata_fsl_setup_cmd_hdr_entry
sata_fsl_fill_sg
sata_fsl_qc_prep
sata_fsl_qc_issue
sata_fsl_qc_fill_rtf
sata_fsl_scr_write
sata_fsl_scr_read
sata_fsl_freeze
sata_fsl_thaw
sata_fsl_pmp_attach
sata_fsl_pmp_detach
sata_fsl_port_start
sata_fsl_port_stop
sata_fsl_dev_classify
sata_fsl_hardreset
sata_fsl_softreset
sata_fsl_error_handler
sata_fsl_post_internal_cmd
sata_fsl_error_intr
sata_fsl_host_intr
sata_fsl_interrupt
sata_fsl_init_controller
sata_fsl_probe
sata_fsl_remove
sata_fsl_suspend
sata_fsl_resume
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * drivers/ata/sata_fsl.c
   4  *
   5  * Freescale 3.0Gbps SATA device driver
   6  *
   7  * Author: Ashish Kalra <ashish.kalra@freescale.com>
   8  * Li Yang <leoli@freescale.com>
   9  *
  10  * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
  11  */
  12 
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/slab.h>
  17 
  18 #include <scsi/scsi_host.h>
  19 #include <scsi/scsi_cmnd.h>
  20 #include <linux/libata.h>
  21 #include <asm/io.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_platform.h>
  25 
  26 static unsigned int intr_coalescing_count;
  27 module_param(intr_coalescing_count, int, S_IRUGO);
  28 MODULE_PARM_DESC(intr_coalescing_count,
  29                                  "INT coalescing count threshold (1..31)");
  30 
  31 static unsigned int intr_coalescing_ticks;
  32 module_param(intr_coalescing_ticks, int, S_IRUGO);
  33 MODULE_PARM_DESC(intr_coalescing_ticks,
  34                                  "INT coalescing timer threshold in AHB ticks");
  35 /* Controller information */
  36 enum {
  37         SATA_FSL_QUEUE_DEPTH    = 16,
  38         SATA_FSL_MAX_PRD        = 63,
  39         SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
  40         SATA_FSL_MAX_PRD_DIRECT = 16,   /* Direct PRDT entries */
  41 
  42         SATA_FSL_HOST_FLAGS     = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
  43                                    ATA_FLAG_PMP | ATA_FLAG_NCQ |
  44                                    ATA_FLAG_AN | ATA_FLAG_NO_LOG_PAGE),
  45 
  46         SATA_FSL_MAX_CMDS       = SATA_FSL_QUEUE_DEPTH,
  47         SATA_FSL_CMD_HDR_SIZE   = 16,   /* 4 DWORDS */
  48         SATA_FSL_CMD_SLOT_SIZE  = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
  49 
  50         /*
  51          * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
  52          * chained indirect PRDEs up to a max count of 63.
  53          * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
  54          * be setup as an indirect descriptor, pointing to it's next
  55          * (contiguous) PRDE. Though chained indirect PRDE arrays are
  56          * supported,it will be more efficient to use a direct PRDT and
  57          * a single chain/link to indirect PRDE array/PRDT.
  58          */
  59 
  60         SATA_FSL_CMD_DESC_CFIS_SZ       = 32,
  61         SATA_FSL_CMD_DESC_SFIS_SZ       = 32,
  62         SATA_FSL_CMD_DESC_ACMD_SZ       = 16,
  63         SATA_FSL_CMD_DESC_RSRVD         = 16,
  64 
  65         SATA_FSL_CMD_DESC_SIZE  = (SATA_FSL_CMD_DESC_CFIS_SZ +
  66                                  SATA_FSL_CMD_DESC_SFIS_SZ +
  67                                  SATA_FSL_CMD_DESC_ACMD_SZ +
  68                                  SATA_FSL_CMD_DESC_RSRVD +
  69                                  SATA_FSL_MAX_PRD * 16),
  70 
  71         SATA_FSL_CMD_DESC_OFFSET_TO_PRDT        =
  72                                 (SATA_FSL_CMD_DESC_CFIS_SZ +
  73                                  SATA_FSL_CMD_DESC_SFIS_SZ +
  74                                  SATA_FSL_CMD_DESC_ACMD_SZ +
  75                                  SATA_FSL_CMD_DESC_RSRVD),
  76 
  77         SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
  78         SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
  79                                         SATA_FSL_CMD_DESC_AR_SZ),
  80 
  81         /*
  82          * MPC8315 has two SATA controllers, SATA1 & SATA2
  83          * (one port per controller)
  84          * MPC837x has 2/4 controllers, one port per controller
  85          */
  86 
  87         SATA_FSL_MAX_PORTS      = 1,
  88 
  89         SATA_FSL_IRQ_FLAG       = IRQF_SHARED,
  90 };
  91 
  92 /*
  93  * Interrupt Coalescing Control Register bitdefs  */
  94 enum {
  95         ICC_MIN_INT_COUNT_THRESHOLD     = 1,
  96         ICC_MAX_INT_COUNT_THRESHOLD     = ((1 << 5) - 1),
  97         ICC_MIN_INT_TICKS_THRESHOLD     = 0,
  98         ICC_MAX_INT_TICKS_THRESHOLD     = ((1 << 19) - 1),
  99         ICC_SAFE_INT_TICKS              = 1,
 100 };
 101 
 102 /*
 103 * Host Controller command register set - per port
 104 */
 105 enum {
 106         CQ = 0,
 107         CA = 8,
 108         CC = 0x10,
 109         CE = 0x18,
 110         DE = 0x20,
 111         CHBA = 0x24,
 112         HSTATUS = 0x28,
 113         HCONTROL = 0x2C,
 114         CQPMP = 0x30,
 115         SIGNATURE = 0x34,
 116         ICC = 0x38,
 117 
 118         /*
 119          * Host Status Register (HStatus) bitdefs
 120          */
 121         ONLINE = (1 << 31),
 122         GOING_OFFLINE = (1 << 30),
 123         BIST_ERR = (1 << 29),
 124         CLEAR_ERROR = (1 << 27),
 125 
 126         FATAL_ERR_HC_MASTER_ERR = (1 << 18),
 127         FATAL_ERR_PARITY_ERR_TX = (1 << 17),
 128         FATAL_ERR_PARITY_ERR_RX = (1 << 16),
 129         FATAL_ERR_DATA_UNDERRUN = (1 << 13),
 130         FATAL_ERR_DATA_OVERRUN = (1 << 12),
 131         FATAL_ERR_CRC_ERR_TX = (1 << 11),
 132         FATAL_ERR_CRC_ERR_RX = (1 << 10),
 133         FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
 134         FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
 135 
 136         FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
 137             FATAL_ERR_PARITY_ERR_TX |
 138             FATAL_ERR_PARITY_ERR_RX |
 139             FATAL_ERR_DATA_UNDERRUN |
 140             FATAL_ERR_DATA_OVERRUN |
 141             FATAL_ERR_CRC_ERR_TX |
 142             FATAL_ERR_CRC_ERR_RX |
 143             FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
 144 
 145         INT_ON_DATA_LENGTH_MISMATCH = (1 << 12),
 146         INT_ON_FATAL_ERR = (1 << 5),
 147         INT_ON_PHYRDY_CHG = (1 << 4),
 148 
 149         INT_ON_SIGNATURE_UPDATE = (1 << 3),
 150         INT_ON_SNOTIFY_UPDATE = (1 << 2),
 151         INT_ON_SINGL_DEVICE_ERR = (1 << 1),
 152         INT_ON_CMD_COMPLETE = 1,
 153 
 154         INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
 155             INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
 156 
 157         /*
 158          * Host Control Register (HControl) bitdefs
 159          */
 160         HCONTROL_ONLINE_PHY_RST = (1 << 31),
 161         HCONTROL_FORCE_OFFLINE = (1 << 30),
 162         HCONTROL_LEGACY = (1 << 28),
 163         HCONTROL_PARITY_PROT_MOD = (1 << 14),
 164         HCONTROL_DPATH_PARITY = (1 << 12),
 165         HCONTROL_SNOOP_ENABLE = (1 << 10),
 166         HCONTROL_PMP_ATTACHED = (1 << 9),
 167         HCONTROL_COPYOUT_STATFIS = (1 << 8),
 168         IE_ON_FATAL_ERR = (1 << 5),
 169         IE_ON_PHYRDY_CHG = (1 << 4),
 170         IE_ON_SIGNATURE_UPDATE = (1 << 3),
 171         IE_ON_SNOTIFY_UPDATE = (1 << 2),
 172         IE_ON_SINGL_DEVICE_ERR = (1 << 1),
 173         IE_ON_CMD_COMPLETE = 1,
 174 
 175         DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
 176             IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
 177             IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
 178 
 179         EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
 180         DATA_SNOOP_ENABLE_V1 = (1 << 22),
 181         DATA_SNOOP_ENABLE_V2 = (1 << 28),
 182 };
 183 
 184 /*
 185  * SATA Superset Registers
 186  */
 187 enum {
 188         SSTATUS = 0,
 189         SERROR = 4,
 190         SCONTROL = 8,
 191         SNOTIFY = 0xC,
 192 };
 193 
 194 /*
 195  * Control Status Register Set
 196  */
 197 enum {
 198         TRANSCFG = 0,
 199         TRANSSTATUS = 4,
 200         LINKCFG = 8,
 201         LINKCFG1 = 0xC,
 202         LINKCFG2 = 0x10,
 203         LINKSTATUS = 0x14,
 204         LINKSTATUS1 = 0x18,
 205         PHYCTRLCFG = 0x1C,
 206         COMMANDSTAT = 0x20,
 207 };
 208 
 209 /* TRANSCFG (transport-layer) configuration control */
 210 enum {
 211         TRANSCFG_RX_WATER_MARK = (1 << 4),
 212 };
 213 
 214 /* PHY (link-layer) configuration control */
 215 enum {
 216         PHY_BIST_ENABLE = 0x01,
 217 };
 218 
 219 /*
 220  * Command Header Table entry, i.e, command slot
 221  * 4 Dwords per command slot, command header size ==  64 Dwords.
 222  */
 223 struct cmdhdr_tbl_entry {
 224         u32 cda;
 225         u32 prde_fis_len;
 226         u32 ttl;
 227         u32 desc_info;
 228 };
 229 
 230 /*
 231  * Description information bitdefs
 232  */
 233 enum {
 234         CMD_DESC_RES = (1 << 11),
 235         VENDOR_SPECIFIC_BIST = (1 << 10),
 236         CMD_DESC_SNOOP_ENABLE = (1 << 9),
 237         FPDMA_QUEUED_CMD = (1 << 8),
 238         SRST_CMD = (1 << 7),
 239         BIST = (1 << 6),
 240         ATAPI_CMD = (1 << 5),
 241 };
 242 
 243 /*
 244  * Command Descriptor
 245  */
 246 struct command_desc {
 247         u8 cfis[8 * 4];
 248         u8 sfis[8 * 4];
 249         u8 acmd[4 * 4];
 250         u8 fill[4 * 4];
 251         u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
 252         u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
 253 };
 254 
 255 /*
 256  * Physical region table descriptor(PRD)
 257  */
 258 
 259 struct prde {
 260         u32 dba;
 261         u8 fill[2 * 4];
 262         u32 ddc_and_ext;
 263 };
 264 
 265 /*
 266  * ata_port private data
 267  * This is our per-port instance data.
 268  */
 269 struct sata_fsl_port_priv {
 270         struct cmdhdr_tbl_entry *cmdslot;
 271         dma_addr_t cmdslot_paddr;
 272         struct command_desc *cmdentry;
 273         dma_addr_t cmdentry_paddr;
 274 };
 275 
 276 /*
 277  * ata_port->host_set private data
 278  */
 279 struct sata_fsl_host_priv {
 280         void __iomem *hcr_base;
 281         void __iomem *ssr_base;
 282         void __iomem *csr_base;
 283         int irq;
 284         int data_snoop;
 285         struct device_attribute intr_coalescing;
 286         struct device_attribute rx_watermark;
 287 };
 288 
 289 static void fsl_sata_set_irq_coalescing(struct ata_host *host,
 290                 unsigned int count, unsigned int ticks)
 291 {
 292         struct sata_fsl_host_priv *host_priv = host->private_data;
 293         void __iomem *hcr_base = host_priv->hcr_base;
 294         unsigned long flags;
 295 
 296         if (count > ICC_MAX_INT_COUNT_THRESHOLD)
 297                 count = ICC_MAX_INT_COUNT_THRESHOLD;
 298         else if (count < ICC_MIN_INT_COUNT_THRESHOLD)
 299                 count = ICC_MIN_INT_COUNT_THRESHOLD;
 300 
 301         if (ticks > ICC_MAX_INT_TICKS_THRESHOLD)
 302                 ticks = ICC_MAX_INT_TICKS_THRESHOLD;
 303         else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) &&
 304                         (count > ICC_MIN_INT_COUNT_THRESHOLD))
 305                 ticks = ICC_SAFE_INT_TICKS;
 306 
 307         spin_lock_irqsave(&host->lock, flags);
 308         iowrite32((count << 24 | ticks), hcr_base + ICC);
 309 
 310         intr_coalescing_count = count;
 311         intr_coalescing_ticks = ticks;
 312         spin_unlock_irqrestore(&host->lock, flags);
 313 
 314         DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
 315                         intr_coalescing_count, intr_coalescing_ticks);
 316         DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n",
 317                         hcr_base, ioread32(hcr_base + ICC));
 318 }
 319 
 320 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
 321                 struct device_attribute *attr, char *buf)
 322 {
 323         return sprintf(buf, "%d %d\n",
 324                         intr_coalescing_count, intr_coalescing_ticks);
 325 }
 326 
 327 static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
 328                 struct device_attribute *attr,
 329                 const char *buf, size_t count)
 330 {
 331         unsigned int coalescing_count,  coalescing_ticks;
 332 
 333         if (sscanf(buf, "%d%d",
 334                                 &coalescing_count,
 335                                 &coalescing_ticks) != 2) {
 336                 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
 337                 return -EINVAL;
 338         }
 339 
 340         fsl_sata_set_irq_coalescing(dev_get_drvdata(dev),
 341                         coalescing_count, coalescing_ticks);
 342 
 343         return strlen(buf);
 344 }
 345 
 346 static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
 347                 struct device_attribute *attr, char *buf)
 348 {
 349         unsigned int rx_watermark;
 350         unsigned long flags;
 351         struct ata_host *host = dev_get_drvdata(dev);
 352         struct sata_fsl_host_priv *host_priv = host->private_data;
 353         void __iomem *csr_base = host_priv->csr_base;
 354 
 355         spin_lock_irqsave(&host->lock, flags);
 356         rx_watermark = ioread32(csr_base + TRANSCFG);
 357         rx_watermark &= 0x1f;
 358 
 359         spin_unlock_irqrestore(&host->lock, flags);
 360         return sprintf(buf, "%d\n", rx_watermark);
 361 }
 362 
 363 static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
 364                 struct device_attribute *attr,
 365                 const char *buf, size_t count)
 366 {
 367         unsigned int rx_watermark;
 368         unsigned long flags;
 369         struct ata_host *host = dev_get_drvdata(dev);
 370         struct sata_fsl_host_priv *host_priv = host->private_data;
 371         void __iomem *csr_base = host_priv->csr_base;
 372         u32 temp;
 373 
 374         if (sscanf(buf, "%d", &rx_watermark) != 1) {
 375                 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
 376                 return -EINVAL;
 377         }
 378 
 379         spin_lock_irqsave(&host->lock, flags);
 380         temp = ioread32(csr_base + TRANSCFG);
 381         temp &= 0xffffffe0;
 382         iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
 383 
 384         spin_unlock_irqrestore(&host->lock, flags);
 385         return strlen(buf);
 386 }
 387 
 388 static inline unsigned int sata_fsl_tag(unsigned int tag,
 389                                         void __iomem *hcr_base)
 390 {
 391         /* We let libATA core do actual (queue) tag allocation */
 392 
 393         if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
 394                 DPRINTK("tag %d invalid : out of range\n", tag);
 395                 return 0;
 396         }
 397 
 398         if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
 399                 DPRINTK("tag %d invalid : in use!!\n", tag);
 400                 return 0;
 401         }
 402 
 403         return tag;
 404 }
 405 
 406 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
 407                                          unsigned int tag, u32 desc_info,
 408                                          u32 data_xfer_len, u8 num_prde,
 409                                          u8 fis_len)
 410 {
 411         dma_addr_t cmd_descriptor_address;
 412 
 413         cmd_descriptor_address = pp->cmdentry_paddr +
 414             tag * SATA_FSL_CMD_DESC_SIZE;
 415 
 416         /* NOTE: both data_xfer_len & fis_len are Dword counts */
 417 
 418         pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
 419         pp->cmdslot[tag].prde_fis_len =
 420             cpu_to_le32((num_prde << 16) | (fis_len << 2));
 421         pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
 422         pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
 423 
 424         VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
 425                 pp->cmdslot[tag].cda,
 426                 pp->cmdslot[tag].prde_fis_len,
 427                 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
 428 
 429 }
 430 
 431 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
 432                                      u32 *ttl, dma_addr_t cmd_desc_paddr,
 433                                      int data_snoop)
 434 {
 435         struct scatterlist *sg;
 436         unsigned int num_prde = 0;
 437         u32 ttl_dwords = 0;
 438 
 439         /*
 440          * NOTE : direct & indirect prdt's are contiguously allocated
 441          */
 442         struct prde *prd = (struct prde *)&((struct command_desc *)
 443                                             cmd_desc)->prdt;
 444 
 445         struct prde *prd_ptr_to_indirect_ext = NULL;
 446         unsigned indirect_ext_segment_sz = 0;
 447         dma_addr_t indirect_ext_segment_paddr;
 448         unsigned int si;
 449 
 450         VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
 451 
 452         indirect_ext_segment_paddr = cmd_desc_paddr +
 453             SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
 454 
 455         for_each_sg(qc->sg, sg, qc->n_elem, si) {
 456                 dma_addr_t sg_addr = sg_dma_address(sg);
 457                 u32 sg_len = sg_dma_len(sg);
 458 
 459                 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
 460                         (unsigned long long)sg_addr, sg_len);
 461 
 462                 /* warn if each s/g element is not dword aligned */
 463                 if (unlikely(sg_addr & 0x03))
 464                         ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
 465                                      (unsigned long long)sg_addr);
 466                 if (unlikely(sg_len & 0x03))
 467                         ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n",
 468                                      sg_len);
 469 
 470                 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
 471                     sg_next(sg) != NULL) {
 472                         VPRINTK("setting indirect prde\n");
 473                         prd_ptr_to_indirect_ext = prd;
 474                         prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
 475                         indirect_ext_segment_sz = 0;
 476                         ++prd;
 477                         ++num_prde;
 478                 }
 479 
 480                 ttl_dwords += sg_len;
 481                 prd->dba = cpu_to_le32(sg_addr);
 482                 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
 483 
 484                 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
 485                         ttl_dwords, prd->dba, prd->ddc_and_ext);
 486 
 487                 ++num_prde;
 488                 ++prd;
 489                 if (prd_ptr_to_indirect_ext)
 490                         indirect_ext_segment_sz += sg_len;
 491         }
 492 
 493         if (prd_ptr_to_indirect_ext) {
 494                 /* set indirect extension flag along with indirect ext. size */
 495                 prd_ptr_to_indirect_ext->ddc_and_ext =
 496                     cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
 497                                  data_snoop |
 498                                  (indirect_ext_segment_sz & ~0x03)));
 499         }
 500 
 501         *ttl = ttl_dwords;
 502         return num_prde;
 503 }
 504 
 505 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
 506 {
 507         struct ata_port *ap = qc->ap;
 508         struct sata_fsl_port_priv *pp = ap->private_data;
 509         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 510         void __iomem *hcr_base = host_priv->hcr_base;
 511         unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
 512         struct command_desc *cd;
 513         u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
 514         u32 num_prde = 0;
 515         u32 ttl_dwords = 0;
 516         dma_addr_t cd_paddr;
 517 
 518         cd = (struct command_desc *)pp->cmdentry + tag;
 519         cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
 520 
 521         ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
 522 
 523         VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
 524                 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
 525 
 526         if (qc->tf.protocol == ATA_PROT_NCQ) {
 527                 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
 528                         cd->cfis[3], cd->cfis[11]);
 529         }
 530 
 531         /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
 532         if (ata_is_atapi(qc->tf.protocol)) {
 533                 desc_info |= ATAPI_CMD;
 534                 memset((void *)&cd->acmd, 0, 32);
 535                 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
 536         }
 537 
 538         if (qc->flags & ATA_QCFLAG_DMAMAP)
 539                 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
 540                                             &ttl_dwords, cd_paddr,
 541                                             host_priv->data_snoop);
 542 
 543         if (qc->tf.protocol == ATA_PROT_NCQ)
 544                 desc_info |= FPDMA_QUEUED_CMD;
 545 
 546         sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
 547                                      num_prde, 5);
 548 
 549         VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
 550                 desc_info, ttl_dwords, num_prde);
 551 }
 552 
 553 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
 554 {
 555         struct ata_port *ap = qc->ap;
 556         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 557         void __iomem *hcr_base = host_priv->hcr_base;
 558         unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
 559 
 560         VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
 561                 ioread32(CQ + hcr_base),
 562                 ioread32(CA + hcr_base),
 563                 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
 564 
 565         iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
 566 
 567         /* Simply queue command to the controller/device */
 568         iowrite32(1 << tag, CQ + hcr_base);
 569 
 570         VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
 571                 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
 572 
 573         VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
 574                 ioread32(CE + hcr_base),
 575                 ioread32(DE + hcr_base),
 576                 ioread32(CC + hcr_base),
 577                 ioread32(COMMANDSTAT + host_priv->csr_base));
 578 
 579         return 0;
 580 }
 581 
 582 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
 583 {
 584         struct sata_fsl_port_priv *pp = qc->ap->private_data;
 585         struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
 586         void __iomem *hcr_base = host_priv->hcr_base;
 587         unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
 588         struct command_desc *cd;
 589 
 590         cd = pp->cmdentry + tag;
 591 
 592         ata_tf_from_fis(cd->sfis, &qc->result_tf);
 593         return true;
 594 }
 595 
 596 static int sata_fsl_scr_write(struct ata_link *link,
 597                               unsigned int sc_reg_in, u32 val)
 598 {
 599         struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
 600         void __iomem *ssr_base = host_priv->ssr_base;
 601         unsigned int sc_reg;
 602 
 603         switch (sc_reg_in) {
 604         case SCR_STATUS:
 605         case SCR_ERROR:
 606         case SCR_CONTROL:
 607         case SCR_ACTIVE:
 608                 sc_reg = sc_reg_in;
 609                 break;
 610         default:
 611                 return -EINVAL;
 612         }
 613 
 614         VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
 615 
 616         iowrite32(val, ssr_base + (sc_reg * 4));
 617         return 0;
 618 }
 619 
 620 static int sata_fsl_scr_read(struct ata_link *link,
 621                              unsigned int sc_reg_in, u32 *val)
 622 {
 623         struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
 624         void __iomem *ssr_base = host_priv->ssr_base;
 625         unsigned int sc_reg;
 626 
 627         switch (sc_reg_in) {
 628         case SCR_STATUS:
 629         case SCR_ERROR:
 630         case SCR_CONTROL:
 631         case SCR_ACTIVE:
 632                 sc_reg = sc_reg_in;
 633                 break;
 634         default:
 635                 return -EINVAL;
 636         }
 637 
 638         VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
 639 
 640         *val = ioread32(ssr_base + (sc_reg * 4));
 641         return 0;
 642 }
 643 
 644 static void sata_fsl_freeze(struct ata_port *ap)
 645 {
 646         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 647         void __iomem *hcr_base = host_priv->hcr_base;
 648         u32 temp;
 649 
 650         VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
 651                 ioread32(CQ + hcr_base),
 652                 ioread32(CA + hcr_base),
 653                 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
 654         VPRINTK("CmdStat = 0x%x\n",
 655                 ioread32(host_priv->csr_base + COMMANDSTAT));
 656 
 657         /* disable interrupts on the controller/port */
 658         temp = ioread32(hcr_base + HCONTROL);
 659         iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
 660 
 661         VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
 662                 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
 663 }
 664 
 665 static void sata_fsl_thaw(struct ata_port *ap)
 666 {
 667         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 668         void __iomem *hcr_base = host_priv->hcr_base;
 669         u32 temp;
 670 
 671         /* ack. any pending IRQs for this controller/port */
 672         temp = ioread32(hcr_base + HSTATUS);
 673 
 674         VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
 675 
 676         if (temp & 0x3F)
 677                 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
 678 
 679         /* enable interrupts on the controller/port */
 680         temp = ioread32(hcr_base + HCONTROL);
 681         iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
 682 
 683         VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
 684                 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
 685 }
 686 
 687 static void sata_fsl_pmp_attach(struct ata_port *ap)
 688 {
 689         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 690         void __iomem *hcr_base = host_priv->hcr_base;
 691         u32 temp;
 692 
 693         temp = ioread32(hcr_base + HCONTROL);
 694         iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
 695 }
 696 
 697 static void sata_fsl_pmp_detach(struct ata_port *ap)
 698 {
 699         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 700         void __iomem *hcr_base = host_priv->hcr_base;
 701         u32 temp;
 702 
 703         temp = ioread32(hcr_base + HCONTROL);
 704         temp &= ~HCONTROL_PMP_ATTACHED;
 705         iowrite32(temp, hcr_base + HCONTROL);
 706 
 707         /* enable interrupts on the controller/port */
 708         temp = ioread32(hcr_base + HCONTROL);
 709         iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
 710 
 711 }
 712 
 713 static int sata_fsl_port_start(struct ata_port *ap)
 714 {
 715         struct device *dev = ap->host->dev;
 716         struct sata_fsl_port_priv *pp;
 717         void *mem;
 718         dma_addr_t mem_dma;
 719         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 720         void __iomem *hcr_base = host_priv->hcr_base;
 721         u32 temp;
 722 
 723         pp = kzalloc(sizeof(*pp), GFP_KERNEL);
 724         if (!pp)
 725                 return -ENOMEM;
 726 
 727         mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
 728                                  GFP_KERNEL);
 729         if (!mem) {
 730                 kfree(pp);
 731                 return -ENOMEM;
 732         }
 733 
 734         pp->cmdslot = mem;
 735         pp->cmdslot_paddr = mem_dma;
 736 
 737         mem += SATA_FSL_CMD_SLOT_SIZE;
 738         mem_dma += SATA_FSL_CMD_SLOT_SIZE;
 739 
 740         pp->cmdentry = mem;
 741         pp->cmdentry_paddr = mem_dma;
 742 
 743         ap->private_data = pp;
 744 
 745         VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
 746                 pp->cmdslot_paddr, pp->cmdentry_paddr);
 747 
 748         /* Now, update the CHBA register in host controller cmd register set */
 749         iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
 750 
 751         /*
 752          * Now, we can bring the controller on-line & also initiate
 753          * the COMINIT sequence, we simply return here and the boot-probing
 754          * & device discovery process is re-initiated by libATA using a
 755          * Softreset EH (dummy) session. Hence, boot probing and device
 756          * discovey will be part of sata_fsl_softreset() callback.
 757          */
 758 
 759         temp = ioread32(hcr_base + HCONTROL);
 760         iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
 761 
 762         VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
 763         VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
 764         VPRINTK("CHBA  = 0x%x\n", ioread32(hcr_base + CHBA));
 765 
 766         return 0;
 767 }
 768 
 769 static void sata_fsl_port_stop(struct ata_port *ap)
 770 {
 771         struct device *dev = ap->host->dev;
 772         struct sata_fsl_port_priv *pp = ap->private_data;
 773         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 774         void __iomem *hcr_base = host_priv->hcr_base;
 775         u32 temp;
 776 
 777         /*
 778          * Force host controller to go off-line, aborting current operations
 779          */
 780         temp = ioread32(hcr_base + HCONTROL);
 781         temp &= ~HCONTROL_ONLINE_PHY_RST;
 782         temp |= HCONTROL_FORCE_OFFLINE;
 783         iowrite32(temp, hcr_base + HCONTROL);
 784 
 785         /* Poll for controller to go offline - should happen immediately */
 786         ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
 787 
 788         ap->private_data = NULL;
 789         dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
 790                           pp->cmdslot, pp->cmdslot_paddr);
 791 
 792         kfree(pp);
 793 }
 794 
 795 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
 796 {
 797         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 798         void __iomem *hcr_base = host_priv->hcr_base;
 799         struct ata_taskfile tf;
 800         u32 temp;
 801 
 802         temp = ioread32(hcr_base + SIGNATURE);
 803 
 804         VPRINTK("raw sig = 0x%x\n", temp);
 805         VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
 806         VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
 807 
 808         tf.lbah = (temp >> 24) & 0xff;
 809         tf.lbam = (temp >> 16) & 0xff;
 810         tf.lbal = (temp >> 8) & 0xff;
 811         tf.nsect = temp & 0xff;
 812 
 813         return ata_dev_classify(&tf);
 814 }
 815 
 816 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
 817                                         unsigned long deadline)
 818 {
 819         struct ata_port *ap = link->ap;
 820         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 821         void __iomem *hcr_base = host_priv->hcr_base;
 822         u32 temp;
 823         int i = 0;
 824         unsigned long start_jiffies;
 825 
 826         DPRINTK("in xx_hardreset\n");
 827 
 828 try_offline_again:
 829         /*
 830          * Force host controller to go off-line, aborting current operations
 831          */
 832         temp = ioread32(hcr_base + HCONTROL);
 833         temp &= ~HCONTROL_ONLINE_PHY_RST;
 834         iowrite32(temp, hcr_base + HCONTROL);
 835 
 836         /* Poll for controller to go offline */
 837         temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
 838                                  1, 500);
 839 
 840         if (temp & ONLINE) {
 841                 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i);
 842 
 843                 /*
 844                  * Try to offline controller atleast twice
 845                  */
 846                 i++;
 847                 if (i == 2)
 848                         goto err;
 849                 else
 850                         goto try_offline_again;
 851         }
 852 
 853         DPRINTK("hardreset, controller off-lined\n");
 854         VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
 855         VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
 856 
 857         /*
 858          * PHY reset should remain asserted for atleast 1ms
 859          */
 860         ata_msleep(ap, 1);
 861 
 862         sata_set_spd(link);
 863 
 864         /*
 865          * Now, bring the host controller online again, this can take time
 866          * as PHY reset and communication establishment, 1st D2H FIS and
 867          * device signature update is done, on safe side assume 500ms
 868          * NOTE : Host online status may be indicated immediately!!
 869          */
 870 
 871         temp = ioread32(hcr_base + HCONTROL);
 872         temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
 873         temp |= HCONTROL_PMP_ATTACHED;
 874         iowrite32(temp, hcr_base + HCONTROL);
 875 
 876         temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
 877 
 878         if (!(temp & ONLINE)) {
 879                 ata_port_err(ap, "Hardreset failed, not on-lined\n");
 880                 goto err;
 881         }
 882 
 883         DPRINTK("hardreset, controller off-lined & on-lined\n");
 884         VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
 885         VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
 886 
 887         /*
 888          * First, wait for the PHYRDY change to occur before waiting for
 889          * the signature, and also verify if SStatus indicates device
 890          * presence
 891          */
 892 
 893         temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
 894         if ((!(temp & 0x10)) || ata_link_offline(link)) {
 895                 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n",
 896                               ioread32(hcr_base + HSTATUS));
 897                 *class = ATA_DEV_NONE;
 898                 return 0;
 899         }
 900 
 901         /*
 902          * Wait for the first D2H from device,i.e,signature update notification
 903          */
 904         start_jiffies = jiffies;
 905         temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
 906                         500, jiffies_to_msecs(deadline - start_jiffies));
 907 
 908         if ((temp & 0xFF) != 0x18) {
 909                 ata_port_warn(ap, "No Signature Update\n");
 910                 *class = ATA_DEV_NONE;
 911                 goto do_followup_srst;
 912         } else {
 913                 ata_port_info(ap, "Signature Update detected @ %d msecs\n",
 914                               jiffies_to_msecs(jiffies - start_jiffies));
 915                 *class = sata_fsl_dev_classify(ap);
 916                 return 0;
 917         }
 918 
 919 do_followup_srst:
 920         /*
 921          * request libATA to perform follow-up softreset
 922          */
 923         return -EAGAIN;
 924 
 925 err:
 926         return -EIO;
 927 }
 928 
 929 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
 930                                         unsigned long deadline)
 931 {
 932         struct ata_port *ap = link->ap;
 933         struct sata_fsl_port_priv *pp = ap->private_data;
 934         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 935         void __iomem *hcr_base = host_priv->hcr_base;
 936         int pmp = sata_srst_pmp(link);
 937         u32 temp;
 938         struct ata_taskfile tf;
 939         u8 *cfis;
 940         u32 Serror;
 941 
 942         DPRINTK("in xx_softreset\n");
 943 
 944         if (ata_link_offline(link)) {
 945                 DPRINTK("PHY reports no device\n");
 946                 *class = ATA_DEV_NONE;
 947                 return 0;
 948         }
 949 
 950         /*
 951          * Send a device reset (SRST) explicitly on command slot #0
 952          * Check : will the command queue (reg) be cleared during offlining ??
 953          * Also we will be online only if Phy commn. has been established
 954          * and device presence has been detected, therefore if we have
 955          * reached here, we can send a command to the target device
 956          */
 957 
 958         DPRINTK("Sending SRST/device reset\n");
 959 
 960         ata_tf_init(link->device, &tf);
 961         cfis = (u8 *) &pp->cmdentry->cfis;
 962 
 963         /* device reset/SRST is a control register update FIS, uses tag0 */
 964         sata_fsl_setup_cmd_hdr_entry(pp, 0,
 965                 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
 966 
 967         tf.ctl |= ATA_SRST;     /* setup SRST bit in taskfile control reg */
 968         ata_tf_to_fis(&tf, pmp, 0, cfis);
 969 
 970         DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
 971                 cfis[0], cfis[1], cfis[2], cfis[3]);
 972 
 973         /*
 974          * Queue SRST command to the controller/device, ensure that no
 975          * other commands are active on the controller/device
 976          */
 977 
 978         DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
 979                 ioread32(CQ + hcr_base),
 980                 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
 981 
 982         iowrite32(0xFFFF, CC + hcr_base);
 983         if (pmp != SATA_PMP_CTRL_PORT)
 984                 iowrite32(pmp, CQPMP + hcr_base);
 985         iowrite32(1, CQ + hcr_base);
 986 
 987         temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
 988         if (temp & 0x1) {
 989                 ata_port_warn(ap, "ATA_SRST issue failed\n");
 990 
 991                 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
 992                         ioread32(CQ + hcr_base),
 993                         ioread32(CA + hcr_base), ioread32(CC + hcr_base));
 994 
 995                 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
 996 
 997                 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
 998                 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
 999                 DPRINTK("Serror = 0x%x\n", Serror);
1000                 goto err;
1001         }
1002 
1003         ata_msleep(ap, 1);
1004 
1005         /*
1006          * SATA device enters reset state after receiving a Control register
1007          * FIS with SRST bit asserted and it awaits another H2D Control reg.
1008          * FIS with SRST bit cleared, then the device does internal diags &
1009          * initialization, followed by indicating it's initialization status
1010          * using ATA signature D2H register FIS to the host controller.
1011          */
1012 
1013         sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
1014                                       0, 0, 5);
1015 
1016         tf.ctl &= ~ATA_SRST;    /* 2nd H2D Ctl. register FIS */
1017         ata_tf_to_fis(&tf, pmp, 0, cfis);
1018 
1019         if (pmp != SATA_PMP_CTRL_PORT)
1020                 iowrite32(pmp, CQPMP + hcr_base);
1021         iowrite32(1, CQ + hcr_base);
1022         ata_msleep(ap, 150);            /* ?? */
1023 
1024         /*
1025          * The above command would have signalled an interrupt on command
1026          * complete, which needs special handling, by clearing the Nth
1027          * command bit of the CCreg
1028          */
1029         iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
1030 
1031         DPRINTK("SATA FSL : Now checking device signature\n");
1032 
1033         *class = ATA_DEV_NONE;
1034 
1035         /* Verify if SStatus indicates device presence */
1036         if (ata_link_online(link)) {
1037                 /*
1038                  * if we are here, device presence has been detected,
1039                  * 1st D2H FIS would have been received, but sfis in
1040                  * command desc. is not updated, but signature register
1041                  * would have been updated
1042                  */
1043 
1044                 *class = sata_fsl_dev_classify(ap);
1045 
1046                 DPRINTK("class = %d\n", *class);
1047                 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
1048                 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
1049         }
1050 
1051         return 0;
1052 
1053 err:
1054         return -EIO;
1055 }
1056 
1057 static void sata_fsl_error_handler(struct ata_port *ap)
1058 {
1059 
1060         DPRINTK("in xx_error_handler\n");
1061         sata_pmp_error_handler(ap);
1062 
1063 }
1064 
1065 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1066 {
1067         if (qc->flags & ATA_QCFLAG_FAILED)
1068                 qc->err_mask |= AC_ERR_OTHER;
1069 
1070         if (qc->err_mask) {
1071                 /* make DMA engine forget about the failed command */
1072 
1073         }
1074 }
1075 
1076 static void sata_fsl_error_intr(struct ata_port *ap)
1077 {
1078         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1079         void __iomem *hcr_base = host_priv->hcr_base;
1080         u32 hstatus, dereg=0, cereg = 0, SError = 0;
1081         unsigned int err_mask = 0, action = 0;
1082         int freeze = 0, abort=0;
1083         struct ata_link *link = NULL;
1084         struct ata_queued_cmd *qc = NULL;
1085         struct ata_eh_info *ehi;
1086 
1087         hstatus = ioread32(hcr_base + HSTATUS);
1088         cereg = ioread32(hcr_base + CE);
1089 
1090         /* first, analyze and record host port events */
1091         link = &ap->link;
1092         ehi = &link->eh_info;
1093         ata_ehi_clear_desc(ehi);
1094 
1095         /*
1096          * Handle & Clear SError
1097          */
1098 
1099         sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1100         if (unlikely(SError & 0xFFFF0000))
1101                 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
1102 
1103         DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1104                 hstatus, cereg, ioread32(hcr_base + DE), SError);
1105 
1106         /* handle fatal errors */
1107         if (hstatus & FATAL_ERROR_DECODE) {
1108                 ehi->err_mask |= AC_ERR_ATA_BUS;
1109                 ehi->action |= ATA_EH_SOFTRESET;
1110 
1111                 freeze = 1;
1112         }
1113 
1114         /* Handle SDB FIS receive & notify update */
1115         if (hstatus & INT_ON_SNOTIFY_UPDATE)
1116                 sata_async_notification(ap);
1117 
1118         /* Handle PHYRDY change notification */
1119         if (hstatus & INT_ON_PHYRDY_CHG) {
1120                 DPRINTK("SATA FSL: PHYRDY change indication\n");
1121 
1122                 /* Setup a soft-reset EH action */
1123                 ata_ehi_hotplugged(ehi);
1124                 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1125                 freeze = 1;
1126         }
1127 
1128         /* handle single device errors */
1129         if (cereg) {
1130                 /*
1131                  * clear the command error, also clears queue to the device
1132                  * in error, and we can (re)issue commands to this device.
1133                  * When a device is in error all commands queued into the
1134                  * host controller and at the device are considered aborted
1135                  * and the queue for that device is stopped. Now, after
1136                  * clearing the device error, we can issue commands to the
1137                  * device to interrogate it to find the source of the error.
1138                  */
1139                 abort = 1;
1140 
1141                 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1142                         ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1143 
1144                 /* find out the offending link and qc */
1145                 if (ap->nr_pmp_links) {
1146                         unsigned int dev_num;
1147 
1148                         dereg = ioread32(hcr_base + DE);
1149                         iowrite32(dereg, hcr_base + DE);
1150                         iowrite32(cereg, hcr_base + CE);
1151 
1152                         dev_num = ffs(dereg) - 1;
1153                         if (dev_num < ap->nr_pmp_links && dereg != 0) {
1154                                 link = &ap->pmp_link[dev_num];
1155                                 ehi = &link->eh_info;
1156                                 qc = ata_qc_from_tag(ap, link->active_tag);
1157                                 /*
1158                                  * We should consider this as non fatal error,
1159                                  * and TF must be updated as done below.
1160                                  */
1161 
1162                                 err_mask |= AC_ERR_DEV;
1163 
1164                         } else {
1165                                 err_mask |= AC_ERR_HSM;
1166                                 action |= ATA_EH_HARDRESET;
1167                                 freeze = 1;
1168                         }
1169                 } else {
1170                         dereg = ioread32(hcr_base + DE);
1171                         iowrite32(dereg, hcr_base + DE);
1172                         iowrite32(cereg, hcr_base + CE);
1173 
1174                         qc = ata_qc_from_tag(ap, link->active_tag);
1175                         /*
1176                          * We should consider this as non fatal error,
1177                          * and TF must be updated as done below.
1178                         */
1179                         err_mask |= AC_ERR_DEV;
1180                 }
1181         }
1182 
1183         /* record error info */
1184         if (qc)
1185                 qc->err_mask |= err_mask;
1186         else
1187                 ehi->err_mask |= err_mask;
1188 
1189         ehi->action |= action;
1190 
1191         /* freeze or abort */
1192         if (freeze)
1193                 ata_port_freeze(ap);
1194         else if (abort) {
1195                 if (qc)
1196                         ata_link_abort(qc->dev->link);
1197                 else
1198                         ata_port_abort(ap);
1199         }
1200 }
1201 
1202 static void sata_fsl_host_intr(struct ata_port *ap)
1203 {
1204         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1205         void __iomem *hcr_base = host_priv->hcr_base;
1206         u32 hstatus, done_mask = 0;
1207         struct ata_queued_cmd *qc;
1208         u32 SError;
1209         u32 tag;
1210         u32 status_mask = INT_ON_ERROR;
1211 
1212         hstatus = ioread32(hcr_base + HSTATUS);
1213 
1214         sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1215 
1216         /* Read command completed register */
1217         done_mask = ioread32(hcr_base + CC);
1218 
1219         /* Workaround for data length mismatch errata */
1220         if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
1221                 ata_qc_for_each_with_internal(ap, qc, tag) {
1222                         if (qc && ata_is_atapi(qc->tf.protocol)) {
1223                                 u32 hcontrol;
1224                                 /* Set HControl[27] to clear error registers */
1225                                 hcontrol = ioread32(hcr_base + HCONTROL);
1226                                 iowrite32(hcontrol | CLEAR_ERROR,
1227                                                 hcr_base + HCONTROL);
1228 
1229                                 /* Clear HControl[27] */
1230                                 iowrite32(hcontrol & ~CLEAR_ERROR,
1231                                                 hcr_base + HCONTROL);
1232 
1233                                 /* Clear SError[E] bit */
1234                                 sata_fsl_scr_write(&ap->link, SCR_ERROR,
1235                                                 SError);
1236 
1237                                 /* Ignore fatal error and device error */
1238                                 status_mask &= ~(INT_ON_SINGL_DEVICE_ERR
1239                                                 | INT_ON_FATAL_ERR);
1240                                 break;
1241                         }
1242                 }
1243         }
1244 
1245         if (unlikely(SError & 0xFFFF0000)) {
1246                 DPRINTK("serror @host_intr : 0x%x\n", SError);
1247                 sata_fsl_error_intr(ap);
1248         }
1249 
1250         if (unlikely(hstatus & status_mask)) {
1251                 DPRINTK("error interrupt!!\n");
1252                 sata_fsl_error_intr(ap);
1253                 return;
1254         }
1255 
1256         VPRINTK("Status of all queues :\n");
1257         VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n",
1258                 done_mask,
1259                 ioread32(hcr_base + CA),
1260                 ioread32(hcr_base + CE),
1261                 ioread32(hcr_base + CQ),
1262                 ap->qc_active);
1263 
1264         if (done_mask & ap->qc_active) {
1265                 int i;
1266                 /* clear CC bit, this will also complete the interrupt */
1267                 iowrite32(done_mask, hcr_base + CC);
1268 
1269                 DPRINTK("Status of all queues :\n");
1270                 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1271                         done_mask, ioread32(hcr_base + CA),
1272                         ioread32(hcr_base + CE));
1273 
1274                 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1275                         if (done_mask & (1 << i))
1276                                 DPRINTK
1277                                     ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1278                                      i, ioread32(hcr_base + CC),
1279                                      ioread32(hcr_base + CA));
1280                 }
1281                 ata_qc_complete_multiple(ap, ata_qc_get_active(ap) ^ done_mask);
1282                 return;
1283 
1284         } else if ((ap->qc_active & (1ULL << ATA_TAG_INTERNAL))) {
1285                 iowrite32(1, hcr_base + CC);
1286                 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1287 
1288                 DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1289                          ioread32(hcr_base + CC));
1290 
1291                 if (qc) {
1292                         ata_qc_complete(qc);
1293                 }
1294         } else {
1295                 /* Spurious Interrupt!! */
1296                 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1297                         ioread32(hcr_base + CC));
1298                 iowrite32(done_mask, hcr_base + CC);
1299                 return;
1300         }
1301 }
1302 
1303 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1304 {
1305         struct ata_host *host = dev_instance;
1306         struct sata_fsl_host_priv *host_priv = host->private_data;
1307         void __iomem *hcr_base = host_priv->hcr_base;
1308         u32 interrupt_enables;
1309         unsigned handled = 0;
1310         struct ata_port *ap;
1311 
1312         /* ack. any pending IRQs for this controller/port */
1313         interrupt_enables = ioread32(hcr_base + HSTATUS);
1314         interrupt_enables &= 0x3F;
1315 
1316         DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1317 
1318         if (!interrupt_enables)
1319                 return IRQ_NONE;
1320 
1321         spin_lock(&host->lock);
1322 
1323         /* Assuming one port per host controller */
1324 
1325         ap = host->ports[0];
1326         if (ap) {
1327                 sata_fsl_host_intr(ap);
1328         } else {
1329                 dev_warn(host->dev, "interrupt on disabled port 0\n");
1330         }
1331 
1332         iowrite32(interrupt_enables, hcr_base + HSTATUS);
1333         handled = 1;
1334 
1335         spin_unlock(&host->lock);
1336 
1337         return IRQ_RETVAL(handled);
1338 }
1339 
1340 /*
1341  * Multiple ports are represented by multiple SATA controllers with
1342  * one port per controller
1343  */
1344 static int sata_fsl_init_controller(struct ata_host *host)
1345 {
1346         struct sata_fsl_host_priv *host_priv = host->private_data;
1347         void __iomem *hcr_base = host_priv->hcr_base;
1348         u32 temp;
1349 
1350         /*
1351          * NOTE : We cannot bring the controller online before setting
1352          * the CHBA, hence main controller initialization is done as
1353          * part of the port_start() callback
1354          */
1355 
1356         /* sata controller to operate in enterprise mode */
1357         temp = ioread32(hcr_base + HCONTROL);
1358         iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
1359 
1360         /* ack. any pending IRQs for this controller/port */
1361         temp = ioread32(hcr_base + HSTATUS);
1362         if (temp & 0x3F)
1363                 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1364 
1365         /* Keep interrupts disabled on the controller */
1366         temp = ioread32(hcr_base + HCONTROL);
1367         iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1368 
1369         /* Disable interrupt coalescing control(icc), for the moment */
1370         DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1371         iowrite32(0x01000000, hcr_base + ICC);
1372 
1373         /* clear error registers, SError is cleared by libATA  */
1374         iowrite32(0x00000FFFF, hcr_base + CE);
1375         iowrite32(0x00000FFFF, hcr_base + DE);
1376 
1377         /*
1378          * reset the number of command complete bits which will cause the
1379          * interrupt to be signaled
1380          */
1381         fsl_sata_set_irq_coalescing(host, intr_coalescing_count,
1382                         intr_coalescing_ticks);
1383 
1384         /*
1385          * host controller will be brought on-line, during xx_port_start()
1386          * callback, that should also initiate the OOB, COMINIT sequence
1387          */
1388 
1389         DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1390         DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1391 
1392         return 0;
1393 }
1394 
1395 /*
1396  * scsi mid-layer and libata interface structures
1397  */
1398 static struct scsi_host_template sata_fsl_sht = {
1399         ATA_NCQ_SHT("sata_fsl"),
1400         .can_queue = SATA_FSL_QUEUE_DEPTH,
1401         .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1402         .dma_boundary = ATA_DMA_BOUNDARY,
1403 };
1404 
1405 static struct ata_port_operations sata_fsl_ops = {
1406         .inherits               = &sata_pmp_port_ops,
1407 
1408         .qc_defer = ata_std_qc_defer,
1409         .qc_prep = sata_fsl_qc_prep,
1410         .qc_issue = sata_fsl_qc_issue,
1411         .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1412 
1413         .scr_read = sata_fsl_scr_read,
1414         .scr_write = sata_fsl_scr_write,
1415 
1416         .freeze = sata_fsl_freeze,
1417         .thaw = sata_fsl_thaw,
1418         .softreset = sata_fsl_softreset,
1419         .hardreset = sata_fsl_hardreset,
1420         .pmp_softreset = sata_fsl_softreset,
1421         .error_handler = sata_fsl_error_handler,
1422         .post_internal_cmd = sata_fsl_post_internal_cmd,
1423 
1424         .port_start = sata_fsl_port_start,
1425         .port_stop = sata_fsl_port_stop,
1426 
1427         .pmp_attach = sata_fsl_pmp_attach,
1428         .pmp_detach = sata_fsl_pmp_detach,
1429 };
1430 
1431 static const struct ata_port_info sata_fsl_port_info[] = {
1432         {
1433          .flags = SATA_FSL_HOST_FLAGS,
1434          .pio_mask = ATA_PIO4,
1435          .udma_mask = ATA_UDMA6,
1436          .port_ops = &sata_fsl_ops,
1437          },
1438 };
1439 
1440 static int sata_fsl_probe(struct platform_device *ofdev)
1441 {
1442         int retval = -ENXIO;
1443         void __iomem *hcr_base = NULL;
1444         void __iomem *ssr_base = NULL;
1445         void __iomem *csr_base = NULL;
1446         struct sata_fsl_host_priv *host_priv = NULL;
1447         int irq;
1448         struct ata_host *host = NULL;
1449         u32 temp;
1450 
1451         struct ata_port_info pi = sata_fsl_port_info[0];
1452         const struct ata_port_info *ppi[] = { &pi, NULL };
1453 
1454         dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n");
1455 
1456         hcr_base = of_iomap(ofdev->dev.of_node, 0);
1457         if (!hcr_base)
1458                 goto error_exit_with_cleanup;
1459 
1460         ssr_base = hcr_base + 0x100;
1461         csr_base = hcr_base + 0x140;
1462 
1463         if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
1464                 temp = ioread32(csr_base + TRANSCFG);
1465                 temp = temp & 0xffffffe0;
1466                 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
1467         }
1468 
1469         DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1470         DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1471         DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1472 
1473         host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1474         if (!host_priv)
1475                 goto error_exit_with_cleanup;
1476 
1477         host_priv->hcr_base = hcr_base;
1478         host_priv->ssr_base = ssr_base;
1479         host_priv->csr_base = csr_base;
1480 
1481         irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1482         if (!irq) {
1483                 dev_err(&ofdev->dev, "invalid irq from platform\n");
1484                 goto error_exit_with_cleanup;
1485         }
1486         host_priv->irq = irq;
1487 
1488         if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
1489                 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
1490         else
1491                 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
1492 
1493         /* allocate host structure */
1494         host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1495         if (!host) {
1496                 retval = -ENOMEM;
1497                 goto error_exit_with_cleanup;
1498         }
1499 
1500         /* host->iomap is not used currently */
1501         host->private_data = host_priv;
1502 
1503         /* initialize host controller */
1504         sata_fsl_init_controller(host);
1505 
1506         /*
1507          * Now, register with libATA core, this will also initiate the
1508          * device discovery process, invoking our port_start() handler &
1509          * error_handler() to execute a dummy Softreset EH session
1510          */
1511         ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1512                           &sata_fsl_sht);
1513 
1514         host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show;
1515         host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store;
1516         sysfs_attr_init(&host_priv->intr_coalescing.attr);
1517         host_priv->intr_coalescing.attr.name = "intr_coalescing";
1518         host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR;
1519         retval = device_create_file(host->dev, &host_priv->intr_coalescing);
1520         if (retval)
1521                 goto error_exit_with_cleanup;
1522 
1523         host_priv->rx_watermark.show = fsl_sata_rx_watermark_show;
1524         host_priv->rx_watermark.store = fsl_sata_rx_watermark_store;
1525         sysfs_attr_init(&host_priv->rx_watermark.attr);
1526         host_priv->rx_watermark.attr.name = "rx_watermark";
1527         host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR;
1528         retval = device_create_file(host->dev, &host_priv->rx_watermark);
1529         if (retval) {
1530                 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1531                 goto error_exit_with_cleanup;
1532         }
1533 
1534         return 0;
1535 
1536 error_exit_with_cleanup:
1537 
1538         if (host)
1539                 ata_host_detach(host);
1540 
1541         if (hcr_base)
1542                 iounmap(hcr_base);
1543         kfree(host_priv);
1544 
1545         return retval;
1546 }
1547 
1548 static int sata_fsl_remove(struct platform_device *ofdev)
1549 {
1550         struct ata_host *host = platform_get_drvdata(ofdev);
1551         struct sata_fsl_host_priv *host_priv = host->private_data;
1552 
1553         device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1554         device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
1555 
1556         ata_host_detach(host);
1557 
1558         irq_dispose_mapping(host_priv->irq);
1559         iounmap(host_priv->hcr_base);
1560         kfree(host_priv);
1561 
1562         return 0;
1563 }
1564 
1565 #ifdef CONFIG_PM_SLEEP
1566 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
1567 {
1568         struct ata_host *host = platform_get_drvdata(op);
1569         return ata_host_suspend(host, state);
1570 }
1571 
1572 static int sata_fsl_resume(struct platform_device *op)
1573 {
1574         struct ata_host *host = platform_get_drvdata(op);
1575         struct sata_fsl_host_priv *host_priv = host->private_data;
1576         int ret;
1577         void __iomem *hcr_base = host_priv->hcr_base;
1578         struct ata_port *ap = host->ports[0];
1579         struct sata_fsl_port_priv *pp = ap->private_data;
1580 
1581         ret = sata_fsl_init_controller(host);
1582         if (ret) {
1583                 dev_err(&op->dev, "Error initializing hardware\n");
1584                 return ret;
1585         }
1586 
1587         /* Recovery the CHBA register in host controller cmd register set */
1588         iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1589 
1590         iowrite32((ioread32(hcr_base + HCONTROL)
1591                                 | HCONTROL_ONLINE_PHY_RST
1592                                 | HCONTROL_SNOOP_ENABLE
1593                                 | HCONTROL_PMP_ATTACHED),
1594                         hcr_base + HCONTROL);
1595 
1596         ata_host_resume(host);
1597         return 0;
1598 }
1599 #endif
1600 
1601 static const struct of_device_id fsl_sata_match[] = {
1602         {
1603                 .compatible = "fsl,pq-sata",
1604         },
1605         {
1606                 .compatible = "fsl,pq-sata-v2",
1607         },
1608         {},
1609 };
1610 
1611 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1612 
1613 static struct platform_driver fsl_sata_driver = {
1614         .driver = {
1615                 .name = "fsl-sata",
1616                 .of_match_table = fsl_sata_match,
1617         },
1618         .probe          = sata_fsl_probe,
1619         .remove         = sata_fsl_remove,
1620 #ifdef CONFIG_PM_SLEEP
1621         .suspend        = sata_fsl_suspend,
1622         .resume         = sata_fsl_resume,
1623 #endif
1624 };
1625 
1626 module_platform_driver(fsl_sata_driver);
1627 
1628 MODULE_LICENSE("GPL");
1629 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1630 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1631 MODULE_VERSION("1.10");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/ata/sata_fsl.c

DEFINITIONS
