drivers/ata/pata_arasan

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This source file includes following definitions.
cf_dumpregs
cf_ginterrupt_enable
cf_interrupt_enable
cf_card_reset
cf_ctrl_reset
cf_card_detect
cf_init
cf_exit
dma_callback
dma_complete
wait4buf
dma_xfer
sg_xfer
data_xfer
delayed_finish
arasan_cf_interrupt
arasan_cf_freeze
arasan_cf_error_handler
arasan_cf_dma_start
arasan_cf_qc_issue
arasan_cf_set_piomode
arasan_cf_set_dmamode
arasan_cf_probe
arasan_cf_remove
arasan_cf_suspend
arasan_cf_resume
   1 /*
   2  * drivers/ata/pata_arasan_cf.c
   3  *
   4  * Arasan Compact Flash host controller source file
   5  *
   6  * Copyright (C) 2011 ST Microelectronics
   7  * Viresh Kumar <vireshk@kernel.org>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13 
  14 /*
  15  * The Arasan CompactFlash Device Controller IP core has three basic modes of
  16  * operation: PC card ATA using I/O mode, PC card ATA using memory mode, PC card
  17  * ATA using true IDE modes. This driver supports only True IDE mode currently.
  18  *
  19  * Arasan CF Controller shares global irq register with Arasan XD Controller.
  20  *
  21  * Tested on arch/arm/mach-spear13xx
  22  */
  23 
  24 #include <linux/ata.h>
  25 #include <linux/clk.h>
  26 #include <linux/completion.h>
  27 #include <linux/delay.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/io.h>
  30 #include <linux/irq.h>
  31 #include <linux/kernel.h>
  32 #include <linux/libata.h>
  33 #include <linux/module.h>
  34 #include <linux/of.h>
  35 #include <linux/pata_arasan_cf_data.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm.h>
  38 #include <linux/slab.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/types.h>
  41 #include <linux/workqueue.h>
  42 
  43 #define DRIVER_NAME     "arasan_cf"
  44 #define TIMEOUT         msecs_to_jiffies(3000)
  45 
  46 /* Registers */
  47 /* CompactFlash Interface Status */
  48 #define CFI_STS                 0x000
  49         #define STS_CHG                         (1)
  50         #define BIN_AUDIO_OUT                   (1 << 1)
  51         #define CARD_DETECT1                    (1 << 2)
  52         #define CARD_DETECT2                    (1 << 3)
  53         #define INP_ACK                         (1 << 4)
  54         #define CARD_READY                      (1 << 5)
  55         #define IO_READY                        (1 << 6)
  56         #define B16_IO_PORT_SEL                 (1 << 7)
  57 /* IRQ */
  58 #define IRQ_STS                 0x004
  59 /* Interrupt Enable */
  60 #define IRQ_EN                  0x008
  61         #define CARD_DETECT_IRQ                 (1)
  62         #define STATUS_CHNG_IRQ                 (1 << 1)
  63         #define MEM_MODE_IRQ                    (1 << 2)
  64         #define IO_MODE_IRQ                     (1 << 3)
  65         #define TRUE_IDE_MODE_IRQ               (1 << 8)
  66         #define PIO_XFER_ERR_IRQ                (1 << 9)
  67         #define BUF_AVAIL_IRQ                   (1 << 10)
  68         #define XFER_DONE_IRQ                   (1 << 11)
  69         #define IGNORED_IRQS    (STATUS_CHNG_IRQ | MEM_MODE_IRQ | IO_MODE_IRQ |\
  70                                         TRUE_IDE_MODE_IRQ)
  71         #define TRUE_IDE_IRQS   (CARD_DETECT_IRQ | PIO_XFER_ERR_IRQ |\
  72                                         BUF_AVAIL_IRQ | XFER_DONE_IRQ)
  73 /* Operation Mode */
  74 #define OP_MODE                 0x00C
  75         #define CARD_MODE_MASK                  (0x3)
  76         #define MEM_MODE                        (0x0)
  77         #define IO_MODE                         (0x1)
  78         #define TRUE_IDE_MODE                   (0x2)
  79 
  80         #define CARD_TYPE_MASK                  (1 << 2)
  81         #define CF_CARD                         (0)
  82         #define CF_PLUS_CARD                    (1 << 2)
  83 
  84         #define CARD_RESET                      (1 << 3)
  85         #define CFHOST_ENB                      (1 << 4)
  86         #define OUTPUTS_TRISTATE                (1 << 5)
  87         #define ULTRA_DMA_ENB                   (1 << 8)
  88         #define MULTI_WORD_DMA_ENB              (1 << 9)
  89         #define DRQ_BLOCK_SIZE_MASK             (0x3 << 11)
  90         #define DRQ_BLOCK_SIZE_512              (0)
  91         #define DRQ_BLOCK_SIZE_1024             (1 << 11)
  92         #define DRQ_BLOCK_SIZE_2048             (2 << 11)
  93         #define DRQ_BLOCK_SIZE_4096             (3 << 11)
  94 /* CF Interface Clock Configuration */
  95 #define CLK_CFG                 0x010
  96         #define CF_IF_CLK_MASK                  (0XF)
  97 /* CF Timing Mode Configuration */
  98 #define TM_CFG                  0x014
  99         #define MEM_MODE_TIMING_MASK            (0x3)
 100         #define MEM_MODE_TIMING_250NS           (0x0)
 101         #define MEM_MODE_TIMING_120NS           (0x1)
 102         #define MEM_MODE_TIMING_100NS           (0x2)
 103         #define MEM_MODE_TIMING_80NS            (0x3)
 104 
 105         #define IO_MODE_TIMING_MASK             (0x3 << 2)
 106         #define IO_MODE_TIMING_250NS            (0x0 << 2)
 107         #define IO_MODE_TIMING_120NS            (0x1 << 2)
 108         #define IO_MODE_TIMING_100NS            (0x2 << 2)
 109         #define IO_MODE_TIMING_80NS             (0x3 << 2)
 110 
 111         #define TRUEIDE_PIO_TIMING_MASK         (0x7 << 4)
 112         #define TRUEIDE_PIO_TIMING_SHIFT        4
 113 
 114         #define TRUEIDE_MWORD_DMA_TIMING_MASK   (0x7 << 7)
 115         #define TRUEIDE_MWORD_DMA_TIMING_SHIFT  7
 116 
 117         #define ULTRA_DMA_TIMING_MASK           (0x7 << 10)
 118         #define ULTRA_DMA_TIMING_SHIFT          10
 119 /* CF Transfer Address */
 120 #define XFER_ADDR               0x014
 121         #define XFER_ADDR_MASK                  (0x7FF)
 122         #define MAX_XFER_COUNT                  0x20000u
 123 /* Transfer Control */
 124 #define XFER_CTR                0x01C
 125         #define XFER_COUNT_MASK                 (0x3FFFF)
 126         #define ADDR_INC_DISABLE                (1 << 24)
 127         #define XFER_WIDTH_MASK                 (1 << 25)
 128         #define XFER_WIDTH_8B                   (0)
 129         #define XFER_WIDTH_16B                  (1 << 25)
 130 
 131         #define MEM_TYPE_MASK                   (1 << 26)
 132         #define MEM_TYPE_COMMON                 (0)
 133         #define MEM_TYPE_ATTRIBUTE              (1 << 26)
 134 
 135         #define MEM_IO_XFER_MASK                (1 << 27)
 136         #define MEM_XFER                        (0)
 137         #define IO_XFER                         (1 << 27)
 138 
 139         #define DMA_XFER_MODE                   (1 << 28)
 140 
 141         #define AHB_BUS_NORMAL_PIO_OPRTN        (~(1 << 29))
 142         #define XFER_DIR_MASK                   (1 << 30)
 143         #define XFER_READ                       (0)
 144         #define XFER_WRITE                      (1 << 30)
 145 
 146         #define XFER_START                      (1 << 31)
 147 /* Write Data Port */
 148 #define WRITE_PORT              0x024
 149 /* Read Data Port */
 150 #define READ_PORT               0x028
 151 /* ATA Data Port */
 152 #define ATA_DATA_PORT           0x030
 153         #define ATA_DATA_PORT_MASK              (0xFFFF)
 154 /* ATA Error/Features */
 155 #define ATA_ERR_FTR             0x034
 156 /* ATA Sector Count */
 157 #define ATA_SC                  0x038
 158 /* ATA Sector Number */
 159 #define ATA_SN                  0x03C
 160 /* ATA Cylinder Low */
 161 #define ATA_CL                  0x040
 162 /* ATA Cylinder High */
 163 #define ATA_CH                  0x044
 164 /* ATA Select Card/Head */
 165 #define ATA_SH                  0x048
 166 /* ATA Status-Command */
 167 #define ATA_STS_CMD             0x04C
 168 /* ATA Alternate Status/Device Control */
 169 #define ATA_ASTS_DCTR           0x050
 170 /* Extended Write Data Port 0x200-0x3FC */
 171 #define EXT_WRITE_PORT          0x200
 172 /* Extended Read Data Port 0x400-0x5FC */
 173 #define EXT_READ_PORT           0x400
 174         #define FIFO_SIZE       0x200u
 175 /* Global Interrupt Status */
 176 #define GIRQ_STS                0x800
 177 /* Global Interrupt Status enable */
 178 #define GIRQ_STS_EN             0x804
 179 /* Global Interrupt Signal enable */
 180 #define GIRQ_SGN_EN             0x808
 181         #define GIRQ_CF         (1)
 182         #define GIRQ_XD         (1 << 1)
 183 
 184 /* Compact Flash Controller Dev Structure */
 185 struct arasan_cf_dev {
 186         /* pointer to ata_host structure */
 187         struct ata_host *host;
 188         /* clk structure */
 189         struct clk *clk;
 190 
 191         /* physical base address of controller */
 192         dma_addr_t pbase;
 193         /* virtual base address of controller */
 194         void __iomem *vbase;
 195         /* irq number*/
 196         int irq;
 197 
 198         /* status to be updated to framework regarding DMA transfer */
 199         u8 dma_status;
 200         /* Card is present or Not */
 201         u8 card_present;
 202 
 203         /* dma specific */
 204         /* Completion for transfer complete interrupt from controller */
 205         struct completion cf_completion;
 206         /* Completion for DMA transfer complete. */
 207         struct completion dma_completion;
 208         /* Dma channel allocated */
 209         struct dma_chan *dma_chan;
 210         /* Mask for DMA transfers */
 211         dma_cap_mask_t mask;
 212         /* DMA transfer work */
 213         struct work_struct work;
 214         /* DMA delayed finish work */
 215         struct delayed_work dwork;
 216         /* qc to be transferred using DMA */
 217         struct ata_queued_cmd *qc;
 218 };
 219 
 220 static struct scsi_host_template arasan_cf_sht = {
 221         ATA_BASE_SHT(DRIVER_NAME),
 222         .sg_tablesize = SG_NONE,
 223         .dma_boundary = 0xFFFFFFFFUL,
 224 };
 225 
 226 static void cf_dumpregs(struct arasan_cf_dev *acdev)
 227 {
 228         struct device *dev = acdev->host->dev;
 229 
 230         dev_dbg(dev, ": =========== REGISTER DUMP ===========");
 231         dev_dbg(dev, ": CFI_STS: %x", readl(acdev->vbase + CFI_STS));
 232         dev_dbg(dev, ": IRQ_STS: %x", readl(acdev->vbase + IRQ_STS));
 233         dev_dbg(dev, ": IRQ_EN: %x", readl(acdev->vbase + IRQ_EN));
 234         dev_dbg(dev, ": OP_MODE: %x", readl(acdev->vbase + OP_MODE));
 235         dev_dbg(dev, ": CLK_CFG: %x", readl(acdev->vbase + CLK_CFG));
 236         dev_dbg(dev, ": TM_CFG: %x", readl(acdev->vbase + TM_CFG));
 237         dev_dbg(dev, ": XFER_CTR: %x", readl(acdev->vbase + XFER_CTR));
 238         dev_dbg(dev, ": GIRQ_STS: %x", readl(acdev->vbase + GIRQ_STS));
 239         dev_dbg(dev, ": GIRQ_STS_EN: %x", readl(acdev->vbase + GIRQ_STS_EN));
 240         dev_dbg(dev, ": GIRQ_SGN_EN: %x", readl(acdev->vbase + GIRQ_SGN_EN));
 241         dev_dbg(dev, ": =====================================");
 242 }
 243 
 244 /* Enable/Disable global interrupts shared between CF and XD ctrlr. */
 245 static void cf_ginterrupt_enable(struct arasan_cf_dev *acdev, bool enable)
 246 {
 247         /* enable should be 0 or 1 */
 248         writel(enable, acdev->vbase + GIRQ_STS_EN);
 249         writel(enable, acdev->vbase + GIRQ_SGN_EN);
 250 }
 251 
 252 /* Enable/Disable CF interrupts */
 253 static inline void
 254 cf_interrupt_enable(struct arasan_cf_dev *acdev, u32 mask, bool enable)
 255 {
 256         u32 val = readl(acdev->vbase + IRQ_EN);
 257         /* clear & enable/disable irqs */
 258         if (enable) {
 259                 writel(mask, acdev->vbase + IRQ_STS);
 260                 writel(val | mask, acdev->vbase + IRQ_EN);
 261         } else
 262                 writel(val & ~mask, acdev->vbase + IRQ_EN);
 263 }
 264 
 265 static inline void cf_card_reset(struct arasan_cf_dev *acdev)
 266 {
 267         u32 val = readl(acdev->vbase + OP_MODE);
 268 
 269         writel(val | CARD_RESET, acdev->vbase + OP_MODE);
 270         udelay(200);
 271         writel(val & ~CARD_RESET, acdev->vbase + OP_MODE);
 272 }
 273 
 274 static inline void cf_ctrl_reset(struct arasan_cf_dev *acdev)
 275 {
 276         writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
 277                         acdev->vbase + OP_MODE);
 278         writel(readl(acdev->vbase + OP_MODE) | CFHOST_ENB,
 279                         acdev->vbase + OP_MODE);
 280 }
 281 
 282 static void cf_card_detect(struct arasan_cf_dev *acdev, bool hotplugged)
 283 {
 284         struct ata_port *ap = acdev->host->ports[0];
 285         struct ata_eh_info *ehi = &ap->link.eh_info;
 286         u32 val = readl(acdev->vbase + CFI_STS);
 287 
 288         /* Both CD1 & CD2 should be low if card inserted completely */
 289         if (!(val & (CARD_DETECT1 | CARD_DETECT2))) {
 290                 if (acdev->card_present)
 291                         return;
 292                 acdev->card_present = 1;
 293                 cf_card_reset(acdev);
 294         } else {
 295                 if (!acdev->card_present)
 296                         return;
 297                 acdev->card_present = 0;
 298         }
 299 
 300         if (hotplugged) {
 301                 ata_ehi_hotplugged(ehi);
 302                 ata_port_freeze(ap);
 303         }
 304 }
 305 
 306 static int cf_init(struct arasan_cf_dev *acdev)
 307 {
 308         struct arasan_cf_pdata *pdata = dev_get_platdata(acdev->host->dev);
 309         unsigned int if_clk;
 310         unsigned long flags;
 311         int ret = 0;
 312 
 313         ret = clk_prepare_enable(acdev->clk);
 314         if (ret) {
 315                 dev_dbg(acdev->host->dev, "clock enable failed");
 316                 return ret;
 317         }
 318 
 319         ret = clk_set_rate(acdev->clk, 166000000);
 320         if (ret) {
 321                 dev_warn(acdev->host->dev, "clock set rate failed");
 322                 clk_disable_unprepare(acdev->clk);
 323                 return ret;
 324         }
 325 
 326         spin_lock_irqsave(&acdev->host->lock, flags);
 327         /* configure CF interface clock */
 328         /* TODO: read from device tree */
 329         if_clk = CF_IF_CLK_166M;
 330         if (pdata && pdata->cf_if_clk <= CF_IF_CLK_200M)
 331                 if_clk = pdata->cf_if_clk;
 332 
 333         writel(if_clk, acdev->vbase + CLK_CFG);
 334 
 335         writel(TRUE_IDE_MODE | CFHOST_ENB, acdev->vbase + OP_MODE);
 336         cf_interrupt_enable(acdev, CARD_DETECT_IRQ, 1);
 337         cf_ginterrupt_enable(acdev, 1);
 338         spin_unlock_irqrestore(&acdev->host->lock, flags);
 339 
 340         return ret;
 341 }
 342 
 343 static void cf_exit(struct arasan_cf_dev *acdev)
 344 {
 345         unsigned long flags;
 346 
 347         spin_lock_irqsave(&acdev->host->lock, flags);
 348         cf_ginterrupt_enable(acdev, 0);
 349         cf_interrupt_enable(acdev, TRUE_IDE_IRQS, 0);
 350         cf_card_reset(acdev);
 351         writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
 352                         acdev->vbase + OP_MODE);
 353         spin_unlock_irqrestore(&acdev->host->lock, flags);
 354         clk_disable_unprepare(acdev->clk);
 355 }
 356 
 357 static void dma_callback(void *dev)
 358 {
 359         struct arasan_cf_dev *acdev = dev;
 360 
 361         complete(&acdev->dma_completion);
 362 }
 363 
 364 static inline void dma_complete(struct arasan_cf_dev *acdev)
 365 {
 366         struct ata_queued_cmd *qc = acdev->qc;
 367         unsigned long flags;
 368 
 369         acdev->qc = NULL;
 370         ata_sff_interrupt(acdev->irq, acdev->host);
 371 
 372         spin_lock_irqsave(&acdev->host->lock, flags);
 373         if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
 374                 ata_ehi_push_desc(&qc->ap->link.eh_info, "DMA Failed: Timeout");
 375         spin_unlock_irqrestore(&acdev->host->lock, flags);
 376 }
 377 
 378 static inline int wait4buf(struct arasan_cf_dev *acdev)
 379 {
 380         if (!wait_for_completion_timeout(&acdev->cf_completion, TIMEOUT)) {
 381                 u32 rw = acdev->qc->tf.flags & ATA_TFLAG_WRITE;
 382 
 383                 dev_err(acdev->host->dev, "%s TimeOut", rw ? "write" : "read");
 384                 return -ETIMEDOUT;
 385         }
 386 
 387         /* Check if PIO Error interrupt has occurred */
 388         if (acdev->dma_status & ATA_DMA_ERR)
 389                 return -EAGAIN;
 390 
 391         return 0;
 392 }
 393 
 394 static int
 395 dma_xfer(struct arasan_cf_dev *acdev, dma_addr_t src, dma_addr_t dest, u32 len)
 396 {
 397         struct dma_async_tx_descriptor *tx;
 398         struct dma_chan *chan = acdev->dma_chan;
 399         dma_cookie_t cookie;
 400         unsigned long flags = DMA_PREP_INTERRUPT;
 401         int ret = 0;
 402 
 403         tx = chan->device->device_prep_dma_memcpy(chan, dest, src, len, flags);
 404         if (!tx) {
 405                 dev_err(acdev->host->dev, "device_prep_dma_memcpy failed\n");
 406                 return -EAGAIN;
 407         }
 408 
 409         tx->callback = dma_callback;
 410         tx->callback_param = acdev;
 411         cookie = tx->tx_submit(tx);
 412 
 413         ret = dma_submit_error(cookie);
 414         if (ret) {
 415                 dev_err(acdev->host->dev, "dma_submit_error\n");
 416                 return ret;
 417         }
 418 
 419         chan->device->device_issue_pending(chan);
 420 
 421         /* Wait for DMA to complete */
 422         if (!wait_for_completion_timeout(&acdev->dma_completion, TIMEOUT)) {
 423                 dmaengine_terminate_all(chan);
 424                 dev_err(acdev->host->dev, "wait_for_completion_timeout\n");
 425                 return -ETIMEDOUT;
 426         }
 427 
 428         return ret;
 429 }
 430 
 431 static int sg_xfer(struct arasan_cf_dev *acdev, struct scatterlist *sg)
 432 {
 433         dma_addr_t dest = 0, src = 0;
 434         u32 xfer_cnt, sglen, dma_len, xfer_ctr;
 435         u32 write = acdev->qc->tf.flags & ATA_TFLAG_WRITE;
 436         unsigned long flags;
 437         int ret = 0;
 438 
 439         sglen = sg_dma_len(sg);
 440         if (write) {
 441                 src = sg_dma_address(sg);
 442                 dest = acdev->pbase + EXT_WRITE_PORT;
 443         } else {
 444                 dest = sg_dma_address(sg);
 445                 src = acdev->pbase + EXT_READ_PORT;
 446         }
 447 
 448         /*
 449          * For each sg:
 450          * MAX_XFER_COUNT data will be transferred before we get transfer
 451          * complete interrupt. Between after FIFO_SIZE data
 452          * buffer available interrupt will be generated. At this time we will
 453          * fill FIFO again: max FIFO_SIZE data.
 454          */
 455         while (sglen) {
 456                 xfer_cnt = min(sglen, MAX_XFER_COUNT);
 457                 spin_lock_irqsave(&acdev->host->lock, flags);
 458                 xfer_ctr = readl(acdev->vbase + XFER_CTR) &
 459                         ~XFER_COUNT_MASK;
 460                 writel(xfer_ctr | xfer_cnt | XFER_START,
 461                                 acdev->vbase + XFER_CTR);
 462                 spin_unlock_irqrestore(&acdev->host->lock, flags);
 463 
 464                 /* continue dma xfers until current sg is completed */
 465                 while (xfer_cnt) {
 466                         /* wait for read to complete */
 467                         if (!write) {
 468                                 ret = wait4buf(acdev);
 469                                 if (ret)
 470                                         goto fail;
 471                         }
 472 
 473                         /* read/write FIFO in chunk of FIFO_SIZE */
 474                         dma_len = min(xfer_cnt, FIFO_SIZE);
 475                         ret = dma_xfer(acdev, src, dest, dma_len);
 476                         if (ret) {
 477                                 dev_err(acdev->host->dev, "dma failed");
 478                                 goto fail;
 479                         }
 480 
 481                         if (write)
 482                                 src += dma_len;
 483                         else
 484                                 dest += dma_len;
 485 
 486                         sglen -= dma_len;
 487                         xfer_cnt -= dma_len;
 488 
 489                         /* wait for write to complete */
 490                         if (write) {
 491                                 ret = wait4buf(acdev);
 492                                 if (ret)
 493                                         goto fail;
 494                         }
 495                 }
 496         }
 497 
 498 fail:
 499         spin_lock_irqsave(&acdev->host->lock, flags);
 500         writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
 501                         acdev->vbase + XFER_CTR);
 502         spin_unlock_irqrestore(&acdev->host->lock, flags);
 503 
 504         return ret;
 505 }
 506 
 507 /*
 508  * This routine uses External DMA controller to read/write data to FIFO of CF
 509  * controller. There are two xfer related interrupt supported by CF controller:
 510  * - buf_avail: This interrupt is generated as soon as we have buffer of 512
 511  *      bytes available for reading or empty buffer available for writing.
 512  * - xfer_done: This interrupt is generated on transfer of "xfer_size" amount of
 513  *      data to/from FIFO. xfer_size is programmed in XFER_CTR register.
 514  *
 515  * Max buffer size = FIFO_SIZE = 512 Bytes.
 516  * Max xfer_size = MAX_XFER_COUNT = 256 KB.
 517  */
 518 static void data_xfer(struct work_struct *work)
 519 {
 520         struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev,
 521                         work);
 522         struct ata_queued_cmd *qc = acdev->qc;
 523         struct scatterlist *sg;
 524         unsigned long flags;
 525         u32 temp;
 526         int ret = 0;
 527 
 528         /* request dma channels */
 529         /* dma_request_channel may sleep, so calling from process context */
 530         acdev->dma_chan = dma_request_slave_channel(acdev->host->dev, "data");
 531         if (!acdev->dma_chan) {
 532                 dev_err(acdev->host->dev, "Unable to get dma_chan\n");
 533                 goto chan_request_fail;
 534         }
 535 
 536         for_each_sg(qc->sg, sg, qc->n_elem, temp) {
 537                 ret = sg_xfer(acdev, sg);
 538                 if (ret)
 539                         break;
 540         }
 541 
 542         dma_release_channel(acdev->dma_chan);
 543 
 544         /* data xferred successfully */
 545         if (!ret) {
 546                 u32 status;
 547 
 548                 spin_lock_irqsave(&acdev->host->lock, flags);
 549                 status = ioread8(qc->ap->ioaddr.altstatus_addr);
 550                 spin_unlock_irqrestore(&acdev->host->lock, flags);
 551                 if (status & (ATA_BUSY | ATA_DRQ)) {
 552                         ata_sff_queue_delayed_work(&acdev->dwork, 1);
 553                         return;
 554                 }
 555 
 556                 goto sff_intr;
 557         }
 558 
 559         cf_dumpregs(acdev);
 560 
 561 chan_request_fail:
 562         spin_lock_irqsave(&acdev->host->lock, flags);
 563         /* error when transferring data to/from memory */
 564         qc->err_mask |= AC_ERR_HOST_BUS;
 565         qc->ap->hsm_task_state = HSM_ST_ERR;
 566 
 567         cf_ctrl_reset(acdev);
 568         spin_unlock_irqrestore(&acdev->host->lock, flags);
 569 sff_intr:
 570         dma_complete(acdev);
 571 }
 572 
 573 static void delayed_finish(struct work_struct *work)
 574 {
 575         struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev,
 576                         dwork.work);
 577         struct ata_queued_cmd *qc = acdev->qc;
 578         unsigned long flags;
 579         u8 status;
 580 
 581         spin_lock_irqsave(&acdev->host->lock, flags);
 582         status = ioread8(qc->ap->ioaddr.altstatus_addr);
 583         spin_unlock_irqrestore(&acdev->host->lock, flags);
 584 
 585         if (status & (ATA_BUSY | ATA_DRQ))
 586                 ata_sff_queue_delayed_work(&acdev->dwork, 1);
 587         else
 588                 dma_complete(acdev);
 589 }
 590 
 591 static irqreturn_t arasan_cf_interrupt(int irq, void *dev)
 592 {
 593         struct arasan_cf_dev *acdev = ((struct ata_host *)dev)->private_data;
 594         unsigned long flags;
 595         u32 irqsts;
 596 
 597         irqsts = readl(acdev->vbase + GIRQ_STS);
 598         if (!(irqsts & GIRQ_CF))
 599                 return IRQ_NONE;
 600 
 601         spin_lock_irqsave(&acdev->host->lock, flags);
 602         irqsts = readl(acdev->vbase + IRQ_STS);
 603         writel(irqsts, acdev->vbase + IRQ_STS);         /* clear irqs */
 604         writel(GIRQ_CF, acdev->vbase + GIRQ_STS);       /* clear girqs */
 605 
 606         /* handle only relevant interrupts */
 607         irqsts &= ~IGNORED_IRQS;
 608 
 609         if (irqsts & CARD_DETECT_IRQ) {
 610                 cf_card_detect(acdev, 1);
 611                 spin_unlock_irqrestore(&acdev->host->lock, flags);
 612                 return IRQ_HANDLED;
 613         }
 614 
 615         if (irqsts & PIO_XFER_ERR_IRQ) {
 616                 acdev->dma_status = ATA_DMA_ERR;
 617                 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
 618                                 acdev->vbase + XFER_CTR);
 619                 spin_unlock_irqrestore(&acdev->host->lock, flags);
 620                 complete(&acdev->cf_completion);
 621                 dev_err(acdev->host->dev, "pio xfer err irq\n");
 622                 return IRQ_HANDLED;
 623         }
 624 
 625         spin_unlock_irqrestore(&acdev->host->lock, flags);
 626 
 627         if (irqsts & BUF_AVAIL_IRQ) {
 628                 complete(&acdev->cf_completion);
 629                 return IRQ_HANDLED;
 630         }
 631 
 632         if (irqsts & XFER_DONE_IRQ) {
 633                 struct ata_queued_cmd *qc = acdev->qc;
 634 
 635                 /* Send Complete only for write */
 636                 if (qc->tf.flags & ATA_TFLAG_WRITE)
 637                         complete(&acdev->cf_completion);
 638         }
 639 
 640         return IRQ_HANDLED;
 641 }
 642 
 643 static void arasan_cf_freeze(struct ata_port *ap)
 644 {
 645         struct arasan_cf_dev *acdev = ap->host->private_data;
 646 
 647         /* stop transfer and reset controller */
 648         writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
 649                         acdev->vbase + XFER_CTR);
 650         cf_ctrl_reset(acdev);
 651         acdev->dma_status = ATA_DMA_ERR;
 652 
 653         ata_sff_dma_pause(ap);
 654         ata_sff_freeze(ap);
 655 }
 656 
 657 static void arasan_cf_error_handler(struct ata_port *ap)
 658 {
 659         struct arasan_cf_dev *acdev = ap->host->private_data;
 660 
 661         /*
 662          * DMA transfers using an external DMA controller may be scheduled.
 663          * Abort them before handling error. Refer data_xfer() for further
 664          * details.
 665          */
 666         cancel_work_sync(&acdev->work);
 667         cancel_delayed_work_sync(&acdev->dwork);
 668         return ata_sff_error_handler(ap);
 669 }
 670 
 671 static void arasan_cf_dma_start(struct arasan_cf_dev *acdev)
 672 {
 673         struct ata_queued_cmd *qc = acdev->qc;
 674         struct ata_port *ap = qc->ap;
 675         struct ata_taskfile *tf = &qc->tf;
 676         u32 xfer_ctr = readl(acdev->vbase + XFER_CTR) & ~XFER_DIR_MASK;
 677         u32 write = tf->flags & ATA_TFLAG_WRITE;
 678 
 679         xfer_ctr |= write ? XFER_WRITE : XFER_READ;
 680         writel(xfer_ctr, acdev->vbase + XFER_CTR);
 681 
 682         ap->ops->sff_exec_command(ap, tf);
 683         ata_sff_queue_work(&acdev->work);
 684 }
 685 
 686 static unsigned int arasan_cf_qc_issue(struct ata_queued_cmd *qc)
 687 {
 688         struct ata_port *ap = qc->ap;
 689         struct arasan_cf_dev *acdev = ap->host->private_data;
 690 
 691         /* defer PIO handling to sff_qc_issue */
 692         if (!ata_is_dma(qc->tf.protocol))
 693                 return ata_sff_qc_issue(qc);
 694 
 695         /* select the device */
 696         ata_wait_idle(ap);
 697         ata_sff_dev_select(ap, qc->dev->devno);
 698         ata_wait_idle(ap);
 699 
 700         /* start the command */
 701         switch (qc->tf.protocol) {
 702         case ATA_PROT_DMA:
 703                 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
 704 
 705                 ap->ops->sff_tf_load(ap, &qc->tf);
 706                 acdev->dma_status = 0;
 707                 acdev->qc = qc;
 708                 arasan_cf_dma_start(acdev);
 709                 ap->hsm_task_state = HSM_ST_LAST;
 710                 break;
 711 
 712         default:
 713                 WARN_ON(1);
 714                 return AC_ERR_SYSTEM;
 715         }
 716 
 717         return 0;
 718 }
 719 
 720 static void arasan_cf_set_piomode(struct ata_port *ap, struct ata_device *adev)
 721 {
 722         struct arasan_cf_dev *acdev = ap->host->private_data;
 723         u8 pio = adev->pio_mode - XFER_PIO_0;
 724         unsigned long flags;
 725         u32 val;
 726 
 727         /* Arasan ctrl supports Mode0 -> Mode6 */
 728         if (pio > 6) {
 729                 dev_err(ap->dev, "Unknown PIO mode\n");
 730                 return;
 731         }
 732 
 733         spin_lock_irqsave(&acdev->host->lock, flags);
 734         val = readl(acdev->vbase + OP_MODE) &
 735                 ~(ULTRA_DMA_ENB | MULTI_WORD_DMA_ENB | DRQ_BLOCK_SIZE_MASK);
 736         writel(val, acdev->vbase + OP_MODE);
 737         val = readl(acdev->vbase + TM_CFG) & ~TRUEIDE_PIO_TIMING_MASK;
 738         val |= pio << TRUEIDE_PIO_TIMING_SHIFT;
 739         writel(val, acdev->vbase + TM_CFG);
 740 
 741         cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 0);
 742         cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 1);
 743         spin_unlock_irqrestore(&acdev->host->lock, flags);
 744 }
 745 
 746 static void arasan_cf_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 747 {
 748         struct arasan_cf_dev *acdev = ap->host->private_data;
 749         u32 opmode, tmcfg, dma_mode = adev->dma_mode;
 750         unsigned long flags;
 751 
 752         spin_lock_irqsave(&acdev->host->lock, flags);
 753         opmode = readl(acdev->vbase + OP_MODE) &
 754                 ~(MULTI_WORD_DMA_ENB | ULTRA_DMA_ENB);
 755         tmcfg = readl(acdev->vbase + TM_CFG);
 756 
 757         if ((dma_mode >= XFER_UDMA_0) && (dma_mode <= XFER_UDMA_6)) {
 758                 opmode |= ULTRA_DMA_ENB;
 759                 tmcfg &= ~ULTRA_DMA_TIMING_MASK;
 760                 tmcfg |= (dma_mode - XFER_UDMA_0) << ULTRA_DMA_TIMING_SHIFT;
 761         } else if ((dma_mode >= XFER_MW_DMA_0) && (dma_mode <= XFER_MW_DMA_4)) {
 762                 opmode |= MULTI_WORD_DMA_ENB;
 763                 tmcfg &= ~TRUEIDE_MWORD_DMA_TIMING_MASK;
 764                 tmcfg |= (dma_mode - XFER_MW_DMA_0) <<
 765                         TRUEIDE_MWORD_DMA_TIMING_SHIFT;
 766         } else {
 767                 dev_err(ap->dev, "Unknown DMA mode\n");
 768                 spin_unlock_irqrestore(&acdev->host->lock, flags);
 769                 return;
 770         }
 771 
 772         writel(opmode, acdev->vbase + OP_MODE);
 773         writel(tmcfg, acdev->vbase + TM_CFG);
 774         writel(DMA_XFER_MODE, acdev->vbase + XFER_CTR);
 775 
 776         cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 0);
 777         cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 1);
 778         spin_unlock_irqrestore(&acdev->host->lock, flags);
 779 }
 780 
 781 static struct ata_port_operations arasan_cf_ops = {
 782         .inherits = &ata_sff_port_ops,
 783         .freeze = arasan_cf_freeze,
 784         .error_handler = arasan_cf_error_handler,
 785         .qc_issue = arasan_cf_qc_issue,
 786         .set_piomode = arasan_cf_set_piomode,
 787         .set_dmamode = arasan_cf_set_dmamode,
 788 };
 789 
 790 static int arasan_cf_probe(struct platform_device *pdev)
 791 {
 792         struct arasan_cf_dev *acdev;
 793         struct arasan_cf_pdata *pdata = dev_get_platdata(&pdev->dev);
 794         struct ata_host *host;
 795         struct ata_port *ap;
 796         struct resource *res;
 797         u32 quirk;
 798         irq_handler_t irq_handler = NULL;
 799         int ret;
 800 
 801         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 802         if (!res)
 803                 return -EINVAL;
 804 
 805         if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
 806                                 DRIVER_NAME)) {
 807                 dev_warn(&pdev->dev, "Failed to get memory region resource\n");
 808                 return -ENOENT;
 809         }
 810 
 811         acdev = devm_kzalloc(&pdev->dev, sizeof(*acdev), GFP_KERNEL);
 812         if (!acdev)
 813                 return -ENOMEM;
 814 
 815         if (pdata)
 816                 quirk = pdata->quirk;
 817         else
 818                 quirk = CF_BROKEN_UDMA; /* as it is on spear1340 */
 819 
 820         /* if irq is 0, support only PIO */
 821         acdev->irq = platform_get_irq(pdev, 0);
 822         if (acdev->irq)
 823                 irq_handler = arasan_cf_interrupt;
 824         else
 825                 quirk |= CF_BROKEN_MWDMA | CF_BROKEN_UDMA;
 826 
 827         acdev->pbase = res->start;
 828         acdev->vbase = devm_ioremap_nocache(&pdev->dev, res->start,
 829                         resource_size(res));
 830         if (!acdev->vbase) {
 831                 dev_warn(&pdev->dev, "ioremap fail\n");
 832                 return -ENOMEM;
 833         }
 834 
 835         acdev->clk = devm_clk_get(&pdev->dev, NULL);
 836         if (IS_ERR(acdev->clk)) {
 837                 dev_warn(&pdev->dev, "Clock not found\n");
 838                 return PTR_ERR(acdev->clk);
 839         }
 840 
 841         /* allocate host */
 842         host = ata_host_alloc(&pdev->dev, 1);
 843         if (!host) {
 844                 dev_warn(&pdev->dev, "alloc host fail\n");
 845                 return -ENOMEM;
 846         }
 847 
 848         ap = host->ports[0];
 849         host->private_data = acdev;
 850         acdev->host = host;
 851         ap->ops = &arasan_cf_ops;
 852         ap->pio_mask = ATA_PIO6;
 853         ap->mwdma_mask = ATA_MWDMA4;
 854         ap->udma_mask = ATA_UDMA6;
 855 
 856         init_completion(&acdev->cf_completion);
 857         init_completion(&acdev->dma_completion);
 858         INIT_WORK(&acdev->work, data_xfer);
 859         INIT_DELAYED_WORK(&acdev->dwork, delayed_finish);
 860         dma_cap_set(DMA_MEMCPY, acdev->mask);
 861 
 862         /* Handle platform specific quirks */
 863         if (quirk) {
 864                 if (quirk & CF_BROKEN_PIO) {
 865                         ap->ops->set_piomode = NULL;
 866                         ap->pio_mask = 0;
 867                 }
 868                 if (quirk & CF_BROKEN_MWDMA)
 869                         ap->mwdma_mask = 0;
 870                 if (quirk & CF_BROKEN_UDMA)
 871                         ap->udma_mask = 0;
 872         }
 873         ap->flags |= ATA_FLAG_PIO_POLLING | ATA_FLAG_NO_ATAPI;
 874 
 875         ap->ioaddr.cmd_addr = acdev->vbase + ATA_DATA_PORT;
 876         ap->ioaddr.data_addr = acdev->vbase + ATA_DATA_PORT;
 877         ap->ioaddr.error_addr = acdev->vbase + ATA_ERR_FTR;
 878         ap->ioaddr.feature_addr = acdev->vbase + ATA_ERR_FTR;
 879         ap->ioaddr.nsect_addr = acdev->vbase + ATA_SC;
 880         ap->ioaddr.lbal_addr = acdev->vbase + ATA_SN;
 881         ap->ioaddr.lbam_addr = acdev->vbase + ATA_CL;
 882         ap->ioaddr.lbah_addr = acdev->vbase + ATA_CH;
 883         ap->ioaddr.device_addr = acdev->vbase + ATA_SH;
 884         ap->ioaddr.status_addr = acdev->vbase + ATA_STS_CMD;
 885         ap->ioaddr.command_addr = acdev->vbase + ATA_STS_CMD;
 886         ap->ioaddr.altstatus_addr = acdev->vbase + ATA_ASTS_DCTR;
 887         ap->ioaddr.ctl_addr = acdev->vbase + ATA_ASTS_DCTR;
 888 
 889         ata_port_desc(ap, "phy_addr %llx virt_addr %p",
 890                       (unsigned long long) res->start, acdev->vbase);
 891 
 892         ret = cf_init(acdev);
 893         if (ret)
 894                 return ret;
 895 
 896         cf_card_detect(acdev, 0);
 897 
 898         ret = ata_host_activate(host, acdev->irq, irq_handler, 0,
 899                                 &arasan_cf_sht);
 900         if (!ret)
 901                 return 0;
 902 
 903         cf_exit(acdev);
 904 
 905         return ret;
 906 }
 907 
 908 static int arasan_cf_remove(struct platform_device *pdev)
 909 {
 910         struct ata_host *host = platform_get_drvdata(pdev);
 911         struct arasan_cf_dev *acdev = host->ports[0]->private_data;
 912 
 913         ata_host_detach(host);
 914         cf_exit(acdev);
 915 
 916         return 0;
 917 }
 918 
 919 #ifdef CONFIG_PM_SLEEP
 920 static int arasan_cf_suspend(struct device *dev)
 921 {
 922         struct ata_host *host = dev_get_drvdata(dev);
 923         struct arasan_cf_dev *acdev = host->ports[0]->private_data;
 924 
 925         if (acdev->dma_chan)
 926                 dmaengine_terminate_all(acdev->dma_chan);
 927 
 928         cf_exit(acdev);
 929         return ata_host_suspend(host, PMSG_SUSPEND);
 930 }
 931 
 932 static int arasan_cf_resume(struct device *dev)
 933 {
 934         struct ata_host *host = dev_get_drvdata(dev);
 935         struct arasan_cf_dev *acdev = host->ports[0]->private_data;
 936 
 937         cf_init(acdev);
 938         ata_host_resume(host);
 939 
 940         return 0;
 941 }
 942 #endif
 943 
 944 static SIMPLE_DEV_PM_OPS(arasan_cf_pm_ops, arasan_cf_suspend, arasan_cf_resume);
 945 
 946 #ifdef CONFIG_OF
 947 static const struct of_device_id arasan_cf_id_table[] = {
 948         { .compatible = "arasan,cf-spear1340" },
 949         {}
 950 };
 951 MODULE_DEVICE_TABLE(of, arasan_cf_id_table);
 952 #endif
 953 
 954 static struct platform_driver arasan_cf_driver = {
 955         .probe          = arasan_cf_probe,
 956         .remove         = arasan_cf_remove,
 957         .driver         = {
 958                 .name   = DRIVER_NAME,
 959                 .pm     = &arasan_cf_pm_ops,
 960                 .of_match_table = of_match_ptr(arasan_cf_id_table),
 961         },
 962 };
 963 
 964 module_platform_driver(arasan_cf_driver);
 965 
 966 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");
 967 MODULE_DESCRIPTION("Arasan ATA Compact Flash driver");
 968 MODULE_LICENSE("GPL");
 969 MODULE_ALIAS("platform:" DRIVER_NAME);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/ata/pata_arasan_cf.c

DEFINITIONS
