drivers/ata/ahci.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
ahci_pci_save_initial_config
ahci_pci_init_controller
ahci_vt8251_hardreset
ahci_p5wdh_hardreset
ahci_avn_hardreset
ahci_pci_disable_interrupts
ahci_pci_device_runtime_suspend
ahci_pci_device_runtime_resume
ahci_pci_device_suspend
ahci_pci_device_resume
ahci_configure_dma_masks
ahci_pci_print_info
ahci_p5wdh_workaround
ahci_mcp89_apple_enable
is_mcp89_apple
ahci_sb600_enable_64bit
ahci_broken_system_poweroff
ahci_broken_suspend
ahci_broken_lpm
ahci_broken_online
ahci_broken_devslp
ahci_gtf_filter_workaround
ahci_gtf_filter_workaround
acer_sa5_271_workaround
ahci_thunderx_irq_handler
ahci_remap_check
ahci_get_irq_vector
ahci_init_msi
ahci_update_initial_lpm_policy
ahci_intel_pcs_quirk
ahci_init_one
ahci_shutdown_one
ahci_remove_one
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  ahci.c - AHCI SATA support
   4  *
   5  *  Maintained by:  Tejun Heo <tj@kernel.org>
   6  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   7  *                  on emails.
   8  *
   9  *  Copyright 2004-2005 Red Hat, Inc.
  10  *
  11  * libata documentation is available via 'make {ps|pdf}docs',
  12  * as Documentation/driver-api/libata.rst
  13  *
  14  * AHCI hardware documentation:
  15  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  16  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  17  */
  18 
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/device.h>
  27 #include <linux/dmi.h>
  28 #include <linux/gfp.h>
  29 #include <linux/msi.h>
  30 #include <scsi/scsi_host.h>
  31 #include <scsi/scsi_cmnd.h>
  32 #include <linux/libata.h>
  33 #include <linux/ahci-remap.h>
  34 #include <linux/io-64-nonatomic-lo-hi.h>
  35 #include "ahci.h"
  36 
  37 #define DRV_NAME        "ahci"
  38 #define DRV_VERSION     "3.0"
  39 
  40 enum {
  41         AHCI_PCI_BAR_STA2X11    = 0,
  42         AHCI_PCI_BAR_CAVIUM     = 0,
  43         AHCI_PCI_BAR_ENMOTUS    = 2,
  44         AHCI_PCI_BAR_CAVIUM_GEN5        = 4,
  45         AHCI_PCI_BAR_STANDARD   = 5,
  46 };
  47 
  48 enum board_ids {
  49         /* board IDs by feature in alphabetical order */
  50         board_ahci,
  51         board_ahci_ign_iferr,
  52         board_ahci_mobile,
  53         board_ahci_nomsi,
  54         board_ahci_noncq,
  55         board_ahci_nosntf,
  56         board_ahci_yes_fbs,
  57 
  58         /* board IDs for specific chipsets in alphabetical order */
  59         board_ahci_avn,
  60         board_ahci_mcp65,
  61         board_ahci_mcp77,
  62         board_ahci_mcp89,
  63         board_ahci_mv,
  64         board_ahci_sb600,
  65         board_ahci_sb700,       /* for SB700 and SB800 */
  66         board_ahci_vt8251,
  67 
  68         /*
  69          * board IDs for Intel chipsets that support more than 6 ports
  70          * *and* end up needing the PCS quirk.
  71          */
  72         board_ahci_pcs7,
  73 
  74         /* aliases */
  75         board_ahci_mcp_linux    = board_ahci_mcp65,
  76         board_ahci_mcp67        = board_ahci_mcp65,
  77         board_ahci_mcp73        = board_ahci_mcp65,
  78         board_ahci_mcp79        = board_ahci_mcp77,
  79 };
  80 
  81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  82 static void ahci_remove_one(struct pci_dev *dev);
  83 static void ahci_shutdown_one(struct pci_dev *dev);
  84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
  85                                  unsigned long deadline);
  86 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
  87                               unsigned long deadline);
  88 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
  89 static bool is_mcp89_apple(struct pci_dev *pdev);
  90 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
  91                                 unsigned long deadline);
  92 #ifdef CONFIG_PM
  93 static int ahci_pci_device_runtime_suspend(struct device *dev);
  94 static int ahci_pci_device_runtime_resume(struct device *dev);
  95 #ifdef CONFIG_PM_SLEEP
  96 static int ahci_pci_device_suspend(struct device *dev);
  97 static int ahci_pci_device_resume(struct device *dev);
  98 #endif
  99 #endif /* CONFIG_PM */
 100 
 101 static struct scsi_host_template ahci_sht = {
 102         AHCI_SHT("ahci"),
 103 };
 104 
 105 static struct ata_port_operations ahci_vt8251_ops = {
 106         .inherits               = &ahci_ops,
 107         .hardreset              = ahci_vt8251_hardreset,
 108 };
 109 
 110 static struct ata_port_operations ahci_p5wdh_ops = {
 111         .inherits               = &ahci_ops,
 112         .hardreset              = ahci_p5wdh_hardreset,
 113 };
 114 
 115 static struct ata_port_operations ahci_avn_ops = {
 116         .inherits               = &ahci_ops,
 117         .hardreset              = ahci_avn_hardreset,
 118 };
 119 
 120 static const struct ata_port_info ahci_port_info[] = {
 121         /* by features */
 122         [board_ahci] = {
 123                 .flags          = AHCI_FLAG_COMMON,
 124                 .pio_mask       = ATA_PIO4,
 125                 .udma_mask      = ATA_UDMA6,
 126                 .port_ops       = &ahci_ops,
 127         },
 128         [board_ahci_ign_iferr] = {
 129                 AHCI_HFLAGS     (AHCI_HFLAG_IGN_IRQ_IF_ERR),
 130                 .flags          = AHCI_FLAG_COMMON,
 131                 .pio_mask       = ATA_PIO4,
 132                 .udma_mask      = ATA_UDMA6,
 133                 .port_ops       = &ahci_ops,
 134         },
 135         [board_ahci_mobile] = {
 136                 AHCI_HFLAGS     (AHCI_HFLAG_IS_MOBILE),
 137                 .flags          = AHCI_FLAG_COMMON,
 138                 .pio_mask       = ATA_PIO4,
 139                 .udma_mask      = ATA_UDMA6,
 140                 .port_ops       = &ahci_ops,
 141         },
 142         [board_ahci_nomsi] = {
 143                 AHCI_HFLAGS     (AHCI_HFLAG_NO_MSI),
 144                 .flags          = AHCI_FLAG_COMMON,
 145                 .pio_mask       = ATA_PIO4,
 146                 .udma_mask      = ATA_UDMA6,
 147                 .port_ops       = &ahci_ops,
 148         },
 149         [board_ahci_noncq] = {
 150                 AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ),
 151                 .flags          = AHCI_FLAG_COMMON,
 152                 .pio_mask       = ATA_PIO4,
 153                 .udma_mask      = ATA_UDMA6,
 154                 .port_ops       = &ahci_ops,
 155         },
 156         [board_ahci_nosntf] = {
 157                 AHCI_HFLAGS     (AHCI_HFLAG_NO_SNTF),
 158                 .flags          = AHCI_FLAG_COMMON,
 159                 .pio_mask       = ATA_PIO4,
 160                 .udma_mask      = ATA_UDMA6,
 161                 .port_ops       = &ahci_ops,
 162         },
 163         [board_ahci_yes_fbs] = {
 164                 AHCI_HFLAGS     (AHCI_HFLAG_YES_FBS),
 165                 .flags          = AHCI_FLAG_COMMON,
 166                 .pio_mask       = ATA_PIO4,
 167                 .udma_mask      = ATA_UDMA6,
 168                 .port_ops       = &ahci_ops,
 169         },
 170         /* by chipsets */
 171         [board_ahci_avn] = {
 172                 .flags          = AHCI_FLAG_COMMON,
 173                 .pio_mask       = ATA_PIO4,
 174                 .udma_mask      = ATA_UDMA6,
 175                 .port_ops       = &ahci_avn_ops,
 176         },
 177         [board_ahci_mcp65] = {
 178                 AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
 179                                  AHCI_HFLAG_YES_NCQ),
 180                 .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
 181                 .pio_mask       = ATA_PIO4,
 182                 .udma_mask      = ATA_UDMA6,
 183                 .port_ops       = &ahci_ops,
 184         },
 185         [board_ahci_mcp77] = {
 186                 AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
 187                 .flags          = AHCI_FLAG_COMMON,
 188                 .pio_mask       = ATA_PIO4,
 189                 .udma_mask      = ATA_UDMA6,
 190                 .port_ops       = &ahci_ops,
 191         },
 192         [board_ahci_mcp89] = {
 193                 AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA),
 194                 .flags          = AHCI_FLAG_COMMON,
 195                 .pio_mask       = ATA_PIO4,
 196                 .udma_mask      = ATA_UDMA6,
 197                 .port_ops       = &ahci_ops,
 198         },
 199         [board_ahci_mv] = {
 200                 AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
 201                                  AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
 202                 .flags          = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
 203                 .pio_mask       = ATA_PIO4,
 204                 .udma_mask      = ATA_UDMA6,
 205                 .port_ops       = &ahci_ops,
 206         },
 207         [board_ahci_sb600] = {
 208                 AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL |
 209                                  AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
 210                                  AHCI_HFLAG_32BIT_ONLY),
 211                 .flags          = AHCI_FLAG_COMMON,
 212                 .pio_mask       = ATA_PIO4,
 213                 .udma_mask      = ATA_UDMA6,
 214                 .port_ops       = &ahci_pmp_retry_srst_ops,
 215         },
 216         [board_ahci_sb700] = {  /* for SB700 and SB800 */
 217                 AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL),
 218                 .flags          = AHCI_FLAG_COMMON,
 219                 .pio_mask       = ATA_PIO4,
 220                 .udma_mask      = ATA_UDMA6,
 221                 .port_ops       = &ahci_pmp_retry_srst_ops,
 222         },
 223         [board_ahci_vt8251] = {
 224                 AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
 225                 .flags          = AHCI_FLAG_COMMON,
 226                 .pio_mask       = ATA_PIO4,
 227                 .udma_mask      = ATA_UDMA6,
 228                 .port_ops       = &ahci_vt8251_ops,
 229         },
 230         [board_ahci_pcs7] = {
 231                 .flags          = AHCI_FLAG_COMMON,
 232                 .pio_mask       = ATA_PIO4,
 233                 .udma_mask      = ATA_UDMA6,
 234                 .port_ops       = &ahci_ops,
 235         },
 236 };
 237 
 238 static const struct pci_device_id ahci_pci_tbl[] = {
 239         /* Intel */
 240         { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
 241         { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
 242         { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
 243         { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
 244         { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
 245         { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
 246         { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
 247         { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
 248         { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
 249         { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
 250         { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
 251         { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
 252         { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
 253         { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
 254         { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
 255         { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
 256         { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
 257         { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
 258         { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
 259         { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
 260         { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
 261         { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
 262         { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
 263         { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
 264         { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
 265         { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
 266         { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
 267         { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
 268         { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
 269         { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
 270         { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
 271         { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
 272         { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
 273         { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
 274         { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
 275         { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
 276         { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
 277         { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
 278         { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
 279         { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
 280         { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
 281         { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
 282         { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
 283         { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
 284         { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
 285         { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
 286         { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
 287         { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
 288         { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
 289         { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
 290         { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
 291         { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
 292         { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
 293         { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
 294         { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
 295         { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
 296         { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
 297         { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
 298         { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
 299         { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
 300         { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
 301         { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
 302         { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
 303         { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
 304         { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
 305         { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
 306         { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
 307         { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
 308         { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
 309         { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
 310         { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
 311         { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
 312         { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
 313         { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
 314         { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
 315         { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
 316         { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
 317         { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
 318         { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
 319         { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
 320         { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
 321         { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
 322         { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
 323         { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
 324         { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
 325         { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
 326         { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
 327         { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
 328         { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
 329         { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
 330         { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
 331         { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
 332         { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
 333         { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
 334         { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
 335         { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
 336         { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
 337         { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
 338         { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
 339         { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
 340         { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
 341         { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
 342         { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
 343         { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
 344         { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
 345         { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
 346         { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
 347         { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
 348         { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
 349         { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
 350         { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
 351         { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
 352         { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
 353         { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
 354         { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
 355         { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
 356         { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
 357         { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
 358         { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
 359         { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
 360         { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
 361         { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
 362         { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
 363         { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
 364         { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
 365         { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
 366         { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
 367         { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
 368         { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
 369         { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
 370         { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
 371         { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
 372         { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
 373         { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
 374         { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
 375         { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
 376         { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
 377         { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
 378         { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
 379         { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
 380         { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
 381         { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
 382         { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
 383         { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
 384         { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
 385         { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
 386         { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
 387         { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
 388         { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
 389         { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
 390         { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
 391         { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
 392         { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
 393         { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
 394         { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
 395         { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
 396         { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
 397         { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
 398         { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
 399         { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
 400         { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
 401         { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
 402 
 403         /* JMicron 360/1/3/5/6, match class to avoid IDE function */
 404         { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 405           PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
 406         /* JMicron 362B and 362C have an AHCI function with IDE class code */
 407         { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
 408         { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
 409         /* May need to update quirk_jmicron_async_suspend() for additions */
 410 
 411         /* ATI */
 412         { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
 413         { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
 414         { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
 415         { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
 416         { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
 417         { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
 418         { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
 419 
 420         /* AMD */
 421         { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
 422         { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
 423         /* AMD is using RAID class only for ahci controllers */
 424         { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 425           PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
 426 
 427         /* VIA */
 428         { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
 429         { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
 430 
 431         /* NVIDIA */
 432         { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },      /* MCP65 */
 433         { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },      /* MCP65 */
 434         { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },      /* MCP65 */
 435         { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },      /* MCP65 */
 436         { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },      /* MCP65 */
 437         { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },      /* MCP65 */
 438         { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },      /* MCP65 */
 439         { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },      /* MCP65 */
 440         { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },      /* MCP67 */
 441         { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },      /* MCP67 */
 442         { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },      /* MCP67 */
 443         { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },      /* MCP67 */
 444         { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },      /* MCP67 */
 445         { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },      /* MCP67 */
 446         { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },      /* MCP67 */
 447         { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },      /* MCP67 */
 448         { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },      /* MCP67 */
 449         { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },      /* MCP67 */
 450         { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },      /* MCP67 */
 451         { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },      /* MCP67 */
 452         { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },  /* Linux ID */
 453         { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },  /* Linux ID */
 454         { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },  /* Linux ID */
 455         { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },  /* Linux ID */
 456         { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },  /* Linux ID */
 457         { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },  /* Linux ID */
 458         { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },  /* Linux ID */
 459         { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },  /* Linux ID */
 460         { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },  /* Linux ID */
 461         { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },  /* Linux ID */
 462         { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },  /* Linux ID */
 463         { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },  /* Linux ID */
 464         { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },  /* Linux ID */
 465         { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },  /* Linux ID */
 466         { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },  /* Linux ID */
 467         { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },  /* Linux ID */
 468         { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },      /* MCP73 */
 469         { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },      /* MCP73 */
 470         { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },      /* MCP73 */
 471         { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },      /* MCP73 */
 472         { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },      /* MCP73 */
 473         { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },      /* MCP73 */
 474         { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },      /* MCP73 */
 475         { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },      /* MCP73 */
 476         { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },      /* MCP73 */
 477         { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },      /* MCP73 */
 478         { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },      /* MCP73 */
 479         { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },      /* MCP73 */
 480         { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },      /* MCP77 */
 481         { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },      /* MCP77 */
 482         { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },      /* MCP77 */
 483         { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },      /* MCP77 */
 484         { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },      /* MCP77 */
 485         { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },      /* MCP77 */
 486         { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },      /* MCP77 */
 487         { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },      /* MCP77 */
 488         { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },      /* MCP77 */
 489         { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },      /* MCP77 */
 490         { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },      /* MCP77 */
 491         { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },      /* MCP77 */
 492         { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },      /* MCP79 */
 493         { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },      /* MCP79 */
 494         { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },      /* MCP79 */
 495         { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },      /* MCP79 */
 496         { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },      /* MCP79 */
 497         { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },      /* MCP79 */
 498         { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },      /* MCP79 */
 499         { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },      /* MCP79 */
 500         { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },      /* MCP79 */
 501         { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },      /* MCP79 */
 502         { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },      /* MCP79 */
 503         { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },      /* MCP79 */
 504         { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },      /* MCP89 */
 505         { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },      /* MCP89 */
 506         { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },      /* MCP89 */
 507         { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },      /* MCP89 */
 508         { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },      /* MCP89 */
 509         { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },      /* MCP89 */
 510         { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },      /* MCP89 */
 511         { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },      /* MCP89 */
 512         { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },      /* MCP89 */
 513         { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },      /* MCP89 */
 514         { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },      /* MCP89 */
 515         { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },      /* MCP89 */
 516 
 517         /* SiS */
 518         { PCI_VDEVICE(SI, 0x1184), board_ahci },                /* SiS 966 */
 519         { PCI_VDEVICE(SI, 0x1185), board_ahci },                /* SiS 968 */
 520         { PCI_VDEVICE(SI, 0x0186), board_ahci },                /* SiS 968 */
 521 
 522         /* ST Microelectronics */
 523         { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },           /* ST ConneXt */
 524 
 525         /* Marvell */
 526         { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },        /* 6145 */
 527         { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },        /* 6121 */
 528         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
 529           .class = PCI_CLASS_STORAGE_SATA_AHCI,
 530           .class_mask = 0xffffff,
 531           .driver_data = board_ahci_yes_fbs },                  /* 88se9128 */
 532         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
 533           .driver_data = board_ahci_yes_fbs },                  /* 88se9125 */
 534         { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
 535                          PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
 536           .driver_data = board_ahci_yes_fbs },                  /* 88se9170 */
 537         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
 538           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
 539         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
 540           .driver_data = board_ahci_yes_fbs },                  /* 88se9182 */
 541         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
 542           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
 543         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
 544           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 on some Gigabyte */
 545         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
 546           .driver_data = board_ahci_yes_fbs },
 547         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2),        /* 88se91a2 */
 548           .driver_data = board_ahci_yes_fbs },
 549         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
 550           .driver_data = board_ahci_yes_fbs },
 551         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
 552           .driver_data = board_ahci_yes_fbs },
 553         { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
 554           .driver_data = board_ahci_yes_fbs },
 555         { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
 556           .driver_data = board_ahci_yes_fbs },
 557 
 558         /* Promise */
 559         { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },   /* PDC42819 */
 560         { PCI_VDEVICE(PROMISE, 0x3781), board_ahci },   /* FastTrak TX8660 ahci-mode */
 561 
 562         /* Asmedia */
 563         { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },   /* ASM1060 */
 564         { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },   /* ASM1060 */
 565         { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },   /* ASM1061 */
 566         { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },   /* ASM1062 */
 567         { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci },   /* ASM1061R */
 568         { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci },   /* ASM1062R */
 569 
 570         /*
 571          * Samsung SSDs found on some macbooks.  NCQ times out if MSI is
 572          * enabled.  https://bugzilla.kernel.org/show_bug.cgi?id=60731
 573          */
 574         { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
 575         { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
 576 
 577         /* Enmotus */
 578         { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
 579 
 580         /* Generic, PCI class code for AHCI */
 581         { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 582           PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
 583 
 584         { }     /* terminate list */
 585 };
 586 
 587 static const struct dev_pm_ops ahci_pci_pm_ops = {
 588         SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
 589         SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
 590                            ahci_pci_device_runtime_resume, NULL)
 591 };
 592 
 593 static struct pci_driver ahci_pci_driver = {
 594         .name                   = DRV_NAME,
 595         .id_table               = ahci_pci_tbl,
 596         .probe                  = ahci_init_one,
 597         .remove                 = ahci_remove_one,
 598         .shutdown               = ahci_shutdown_one,
 599         .driver = {
 600                 .pm             = &ahci_pci_pm_ops,
 601         },
 602 };
 603 
 604 #if IS_ENABLED(CONFIG_PATA_MARVELL)
 605 static int marvell_enable;
 606 #else
 607 static int marvell_enable = 1;
 608 #endif
 609 module_param(marvell_enable, int, 0644);
 610 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
 611 
 612 static int mobile_lpm_policy = -1;
 613 module_param(mobile_lpm_policy, int, 0644);
 614 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
 615 
 616 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
 617                                          struct ahci_host_priv *hpriv)
 618 {
 619         if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
 620                 dev_info(&pdev->dev, "JMB361 has only one port\n");
 621                 hpriv->force_port_map = 1;
 622         }
 623 
 624         /*
 625          * Temporary Marvell 6145 hack: PATA port presence
 626          * is asserted through the standard AHCI port
 627          * presence register, as bit 4 (counting from 0)
 628          */
 629         if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 630                 if (pdev->device == 0x6121)
 631                         hpriv->mask_port_map = 0x3;
 632                 else
 633                         hpriv->mask_port_map = 0xf;
 634                 dev_info(&pdev->dev,
 635                           "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
 636         }
 637 
 638         ahci_save_initial_config(&pdev->dev, hpriv);
 639 }
 640 
 641 static void ahci_pci_init_controller(struct ata_host *host)
 642 {
 643         struct ahci_host_priv *hpriv = host->private_data;
 644         struct pci_dev *pdev = to_pci_dev(host->dev);
 645         void __iomem *port_mmio;
 646         u32 tmp;
 647         int mv;
 648 
 649         if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 650                 if (pdev->device == 0x6121)
 651                         mv = 2;
 652                 else
 653                         mv = 4;
 654                 port_mmio = __ahci_port_base(host, mv);
 655 
 656                 writel(0, port_mmio + PORT_IRQ_MASK);
 657 
 658                 /* clear port IRQ */
 659                 tmp = readl(port_mmio + PORT_IRQ_STAT);
 660                 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
 661                 if (tmp)
 662                         writel(tmp, port_mmio + PORT_IRQ_STAT);
 663         }
 664 
 665         ahci_init_controller(host);
 666 }
 667 
 668 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 669                                  unsigned long deadline)
 670 {
 671         struct ata_port *ap = link->ap;
 672         struct ahci_host_priv *hpriv = ap->host->private_data;
 673         bool online;
 674         int rc;
 675 
 676         DPRINTK("ENTER\n");
 677 
 678         hpriv->stop_engine(ap);
 679 
 680         rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 681                                  deadline, &online, NULL);
 682 
 683         hpriv->start_engine(ap);
 684 
 685         DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 686 
 687         /* vt8251 doesn't clear BSY on signature FIS reception,
 688          * request follow-up softreset.
 689          */
 690         return online ? -EAGAIN : rc;
 691 }
 692 
 693 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 694                                 unsigned long deadline)
 695 {
 696         struct ata_port *ap = link->ap;
 697         struct ahci_port_priv *pp = ap->private_data;
 698         struct ahci_host_priv *hpriv = ap->host->private_data;
 699         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 700         struct ata_taskfile tf;
 701         bool online;
 702         int rc;
 703 
 704         hpriv->stop_engine(ap);
 705 
 706         /* clear D2H reception area to properly wait for D2H FIS */
 707         ata_tf_init(link->device, &tf);
 708         tf.command = ATA_BUSY;
 709         ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 710 
 711         rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 712                                  deadline, &online, NULL);
 713 
 714         hpriv->start_engine(ap);
 715 
 716         /* The pseudo configuration device on SIMG4726 attached to
 717          * ASUS P5W-DH Deluxe doesn't send signature FIS after
 718          * hardreset if no device is attached to the first downstream
 719          * port && the pseudo device locks up on SRST w/ PMP==0.  To
 720          * work around this, wait for !BSY only briefly.  If BSY isn't
 721          * cleared, perform CLO and proceed to IDENTIFY (achieved by
 722          * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
 723          *
 724          * Wait for two seconds.  Devices attached to downstream port
 725          * which can't process the following IDENTIFY after this will
 726          * have to be reset again.  For most cases, this should
 727          * suffice while making probing snappish enough.
 728          */
 729         if (online) {
 730                 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
 731                                           ahci_check_ready);
 732                 if (rc)
 733                         ahci_kick_engine(ap);
 734         }
 735         return rc;
 736 }
 737 
 738 /*
 739  * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
 740  *
 741  * It has been observed with some SSDs that the timing of events in the
 742  * link synchronization phase can leave the port in a state that can not
 743  * be recovered by a SATA-hard-reset alone.  The failing signature is
 744  * SStatus.DET stuck at 1 ("Device presence detected but Phy
 745  * communication not established").  It was found that unloading and
 746  * reloading the driver when this problem occurs allows the drive
 747  * connection to be recovered (DET advanced to 0x3).  The critical
 748  * component of reloading the driver is that the port state machines are
 749  * reset by bouncing "port enable" in the AHCI PCS configuration
 750  * register.  So, reproduce that effect by bouncing a port whenever we
 751  * see DET==1 after a reset.
 752  */
 753 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
 754                               unsigned long deadline)
 755 {
 756         const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
 757         struct ata_port *ap = link->ap;
 758         struct ahci_port_priv *pp = ap->private_data;
 759         struct ahci_host_priv *hpriv = ap->host->private_data;
 760         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 761         unsigned long tmo = deadline - jiffies;
 762         struct ata_taskfile tf;
 763         bool online;
 764         int rc, i;
 765 
 766         DPRINTK("ENTER\n");
 767 
 768         hpriv->stop_engine(ap);
 769 
 770         for (i = 0; i < 2; i++) {
 771                 u16 val;
 772                 u32 sstatus;
 773                 int port = ap->port_no;
 774                 struct ata_host *host = ap->host;
 775                 struct pci_dev *pdev = to_pci_dev(host->dev);
 776 
 777                 /* clear D2H reception area to properly wait for D2H FIS */
 778                 ata_tf_init(link->device, &tf);
 779                 tf.command = ATA_BUSY;
 780                 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 781 
 782                 rc = sata_link_hardreset(link, timing, deadline, &online,
 783                                 ahci_check_ready);
 784 
 785                 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
 786                                 (sstatus & 0xf) != 1)
 787                         break;
 788 
 789                 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
 790                                 port);
 791 
 792                 pci_read_config_word(pdev, 0x92, &val);
 793                 val &= ~(1 << port);
 794                 pci_write_config_word(pdev, 0x92, val);
 795                 ata_msleep(ap, 1000);
 796                 val |= 1 << port;
 797                 pci_write_config_word(pdev, 0x92, val);
 798                 deadline += tmo;
 799         }
 800 
 801         hpriv->start_engine(ap);
 802 
 803         if (online)
 804                 *class = ahci_dev_classify(ap);
 805 
 806         DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 807         return rc;
 808 }
 809 
 810 
 811 #ifdef CONFIG_PM
 812 static void ahci_pci_disable_interrupts(struct ata_host *host)
 813 {
 814         struct ahci_host_priv *hpriv = host->private_data;
 815         void __iomem *mmio = hpriv->mmio;
 816         u32 ctl;
 817 
 818         /* AHCI spec rev1.1 section 8.3.3:
 819          * Software must disable interrupts prior to requesting a
 820          * transition of the HBA to D3 state.
 821          */
 822         ctl = readl(mmio + HOST_CTL);
 823         ctl &= ~HOST_IRQ_EN;
 824         writel(ctl, mmio + HOST_CTL);
 825         readl(mmio + HOST_CTL); /* flush */
 826 }
 827 
 828 static int ahci_pci_device_runtime_suspend(struct device *dev)
 829 {
 830         struct pci_dev *pdev = to_pci_dev(dev);
 831         struct ata_host *host = pci_get_drvdata(pdev);
 832 
 833         ahci_pci_disable_interrupts(host);
 834         return 0;
 835 }
 836 
 837 static int ahci_pci_device_runtime_resume(struct device *dev)
 838 {
 839         struct pci_dev *pdev = to_pci_dev(dev);
 840         struct ata_host *host = pci_get_drvdata(pdev);
 841         int rc;
 842 
 843         rc = ahci_reset_controller(host);
 844         if (rc)
 845                 return rc;
 846         ahci_pci_init_controller(host);
 847         return 0;
 848 }
 849 
 850 #ifdef CONFIG_PM_SLEEP
 851 static int ahci_pci_device_suspend(struct device *dev)
 852 {
 853         struct pci_dev *pdev = to_pci_dev(dev);
 854         struct ata_host *host = pci_get_drvdata(pdev);
 855         struct ahci_host_priv *hpriv = host->private_data;
 856 
 857         if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
 858                 dev_err(&pdev->dev,
 859                         "BIOS update required for suspend/resume\n");
 860                 return -EIO;
 861         }
 862 
 863         ahci_pci_disable_interrupts(host);
 864         return ata_host_suspend(host, PMSG_SUSPEND);
 865 }
 866 
 867 static int ahci_pci_device_resume(struct device *dev)
 868 {
 869         struct pci_dev *pdev = to_pci_dev(dev);
 870         struct ata_host *host = pci_get_drvdata(pdev);
 871         int rc;
 872 
 873         /* Apple BIOS helpfully mangles the registers on resume */
 874         if (is_mcp89_apple(pdev))
 875                 ahci_mcp89_apple_enable(pdev);
 876 
 877         if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
 878                 rc = ahci_reset_controller(host);
 879                 if (rc)
 880                         return rc;
 881 
 882                 ahci_pci_init_controller(host);
 883         }
 884 
 885         ata_host_resume(host);
 886 
 887         return 0;
 888 }
 889 #endif
 890 
 891 #endif /* CONFIG_PM */
 892 
 893 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 894 {
 895         const int dma_bits = using_dac ? 64 : 32;
 896         int rc;
 897 
 898         /*
 899          * If the device fixup already set the dma_mask to some non-standard
 900          * value, don't extend it here. This happens on STA2X11, for example.
 901          *
 902          * XXX: manipulating the DMA mask from platform code is completely
 903          * bogus, platform code should use dev->bus_dma_mask instead..
 904          */
 905         if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
 906                 return 0;
 907 
 908         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
 909         if (rc)
 910                 dev_err(&pdev->dev, "DMA enable failed\n");
 911         return rc;
 912 }
 913 
 914 static void ahci_pci_print_info(struct ata_host *host)
 915 {
 916         struct pci_dev *pdev = to_pci_dev(host->dev);
 917         u16 cc;
 918         const char *scc_s;
 919 
 920         pci_read_config_word(pdev, 0x0a, &cc);
 921         if (cc == PCI_CLASS_STORAGE_IDE)
 922                 scc_s = "IDE";
 923         else if (cc == PCI_CLASS_STORAGE_SATA)
 924                 scc_s = "SATA";
 925         else if (cc == PCI_CLASS_STORAGE_RAID)
 926                 scc_s = "RAID";
 927         else
 928                 scc_s = "unknown";
 929 
 930         ahci_print_info(host, scc_s);
 931 }
 932 
 933 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
 934  * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
 935  * support PMP and the 4726 either directly exports the device
 936  * attached to the first downstream port or acts as a hardware storage
 937  * controller and emulate a single ATA device (can be RAID 0/1 or some
 938  * other configuration).
 939  *
 940  * When there's no device attached to the first downstream port of the
 941  * 4726, "Config Disk" appears, which is a pseudo ATA device to
 942  * configure the 4726.  However, ATA emulation of the device is very
 943  * lame.  It doesn't send signature D2H Reg FIS after the initial
 944  * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
 945  *
 946  * The following function works around the problem by always using
 947  * hardreset on the port and not depending on receiving signature FIS
 948  * afterward.  If signature FIS isn't received soon, ATA class is
 949  * assumed without follow-up softreset.
 950  */
 951 static void ahci_p5wdh_workaround(struct ata_host *host)
 952 {
 953         static const struct dmi_system_id sysids[] = {
 954                 {
 955                         .ident = "P5W DH Deluxe",
 956                         .matches = {
 957                                 DMI_MATCH(DMI_SYS_VENDOR,
 958                                           "ASUSTEK COMPUTER INC"),
 959                                 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
 960                         },
 961                 },
 962                 { }
 963         };
 964         struct pci_dev *pdev = to_pci_dev(host->dev);
 965 
 966         if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
 967             dmi_check_system(sysids)) {
 968                 struct ata_port *ap = host->ports[1];
 969 
 970                 dev_info(&pdev->dev,
 971                          "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
 972 
 973                 ap->ops = &ahci_p5wdh_ops;
 974                 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
 975         }
 976 }
 977 
 978 /*
 979  * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
 980  * booting in BIOS compatibility mode.  We restore the registers but not ID.
 981  */
 982 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
 983 {
 984         u32 val;
 985 
 986         printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
 987 
 988         pci_read_config_dword(pdev, 0xf8, &val);
 989         val |= 1 << 0x1b;
 990         /* the following changes the device ID, but appears not to affect function */
 991         /* val = (val & ~0xf0000000) | 0x80000000; */
 992         pci_write_config_dword(pdev, 0xf8, val);
 993 
 994         pci_read_config_dword(pdev, 0x54c, &val);
 995         val |= 1 << 0xc;
 996         pci_write_config_dword(pdev, 0x54c, val);
 997 
 998         pci_read_config_dword(pdev, 0x4a4, &val);
 999         val &= 0xff;
1000         val |= 0x01060100;
1001         pci_write_config_dword(pdev, 0x4a4, val);
1002 
1003         pci_read_config_dword(pdev, 0x54c, &val);
1004         val &= ~(1 << 0xc);
1005         pci_write_config_dword(pdev, 0x54c, val);
1006 
1007         pci_read_config_dword(pdev, 0xf8, &val);
1008         val &= ~(1 << 0x1b);
1009         pci_write_config_dword(pdev, 0xf8, val);
1010 }
1011 
1012 static bool is_mcp89_apple(struct pci_dev *pdev)
1013 {
1014         return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1015                 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1016                 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1017                 pdev->subsystem_device == 0xcb89;
1018 }
1019 
1020 /* only some SB600 ahci controllers can do 64bit DMA */
1021 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1022 {
1023         static const struct dmi_system_id sysids[] = {
1024                 /*
1025                  * The oldest version known to be broken is 0901 and
1026                  * working is 1501 which was released on 2007-10-26.
1027                  * Enable 64bit DMA on 1501 and anything newer.
1028                  *
1029                  * Please read bko#9412 for more info.
1030                  */
1031                 {
1032                         .ident = "ASUS M2A-VM",
1033                         .matches = {
1034                                 DMI_MATCH(DMI_BOARD_VENDOR,
1035                                           "ASUSTeK Computer INC."),
1036                                 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1037                         },
1038                         .driver_data = "20071026",      /* yyyymmdd */
1039                 },
1040                 /*
1041                  * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1042                  * support 64bit DMA.
1043                  *
1044                  * BIOS versions earlier than 1.5 had the Manufacturer DMI
1045                  * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1046                  * This spelling mistake was fixed in BIOS version 1.5, so
1047                  * 1.5 and later have the Manufacturer as
1048                  * "MICRO-STAR INTERNATIONAL CO.,LTD".
1049                  * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1050                  *
1051                  * BIOS versions earlier than 1.9 had a Board Product Name
1052                  * DMI field of "MS-7376". This was changed to be
1053                  * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1054                  * match on DMI_BOARD_NAME of "MS-7376".
1055                  */
1056                 {
1057                         .ident = "MSI K9A2 Platinum",
1058                         .matches = {
1059                                 DMI_MATCH(DMI_BOARD_VENDOR,
1060                                           "MICRO-STAR INTER"),
1061                                 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1062                         },
1063                 },
1064                 /*
1065                  * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1066                  * 64bit DMA.
1067                  *
1068                  * This board also had the typo mentioned above in the
1069                  * Manufacturer DMI field (fixed in BIOS version 1.5), so
1070                  * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1071                  */
1072                 {
1073                         .ident = "MSI K9AGM2",
1074                         .matches = {
1075                                 DMI_MATCH(DMI_BOARD_VENDOR,
1076                                           "MICRO-STAR INTER"),
1077                                 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1078                         },
1079                 },
1080                 /*
1081                  * All BIOS versions for the Asus M3A support 64bit DMA.
1082                  * (all release versions from 0301 to 1206 were tested)
1083                  */
1084                 {
1085                         .ident = "ASUS M3A",
1086                         .matches = {
1087                                 DMI_MATCH(DMI_BOARD_VENDOR,
1088                                           "ASUSTeK Computer INC."),
1089                                 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1090                         },
1091                 },
1092                 { }
1093         };
1094         const struct dmi_system_id *match;
1095         int year, month, date;
1096         char buf[9];
1097 
1098         match = dmi_first_match(sysids);
1099         if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1100             !match)
1101                 return false;
1102 
1103         if (!match->driver_data)
1104                 goto enable_64bit;
1105 
1106         dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1107         snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1108 
1109         if (strcmp(buf, match->driver_data) >= 0)
1110                 goto enable_64bit;
1111         else {
1112                 dev_warn(&pdev->dev,
1113                          "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1114                          match->ident);
1115                 return false;
1116         }
1117 
1118 enable_64bit:
1119         dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1120         return true;
1121 }
1122 
1123 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1124 {
1125         static const struct dmi_system_id broken_systems[] = {
1126                 {
1127                         .ident = "HP Compaq nx6310",
1128                         .matches = {
1129                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1130                                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1131                         },
1132                         /* PCI slot number of the controller */
1133                         .driver_data = (void *)0x1FUL,
1134                 },
1135                 {
1136                         .ident = "HP Compaq 6720s",
1137                         .matches = {
1138                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1139                                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1140                         },
1141                         /* PCI slot number of the controller */
1142                         .driver_data = (void *)0x1FUL,
1143                 },
1144 
1145                 { }     /* terminate list */
1146         };
1147         const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1148 
1149         if (dmi) {
1150                 unsigned long slot = (unsigned long)dmi->driver_data;
1151                 /* apply the quirk only to on-board controllers */
1152                 return slot == PCI_SLOT(pdev->devfn);
1153         }
1154 
1155         return false;
1156 }
1157 
1158 static bool ahci_broken_suspend(struct pci_dev *pdev)
1159 {
1160         static const struct dmi_system_id sysids[] = {
1161                 /*
1162                  * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1163                  * to the harddisk doesn't become online after
1164                  * resuming from STR.  Warn and fail suspend.
1165                  *
1166                  * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1167                  *
1168                  * Use dates instead of versions to match as HP is
1169                  * apparently recycling both product and version
1170                  * strings.
1171                  *
1172                  * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1173                  */
1174                 {
1175                         .ident = "dv4",
1176                         .matches = {
1177                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1178                                 DMI_MATCH(DMI_PRODUCT_NAME,
1179                                           "HP Pavilion dv4 Notebook PC"),
1180                         },
1181                         .driver_data = "20090105",      /* F.30 */
1182                 },
1183                 {
1184                         .ident = "dv5",
1185                         .matches = {
1186                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1187                                 DMI_MATCH(DMI_PRODUCT_NAME,
1188                                           "HP Pavilion dv5 Notebook PC"),
1189                         },
1190                         .driver_data = "20090506",      /* F.16 */
1191                 },
1192                 {
1193                         .ident = "dv6",
1194                         .matches = {
1195                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1196                                 DMI_MATCH(DMI_PRODUCT_NAME,
1197                                           "HP Pavilion dv6 Notebook PC"),
1198                         },
1199                         .driver_data = "20090423",      /* F.21 */
1200                 },
1201                 {
1202                         .ident = "HDX18",
1203                         .matches = {
1204                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1205                                 DMI_MATCH(DMI_PRODUCT_NAME,
1206                                           "HP HDX18 Notebook PC"),
1207                         },
1208                         .driver_data = "20090430",      /* F.23 */
1209                 },
1210                 /*
1211                  * Acer eMachines G725 has the same problem.  BIOS
1212                  * V1.03 is known to be broken.  V3.04 is known to
1213                  * work.  Between, there are V1.06, V2.06 and V3.03
1214                  * that we don't have much idea about.  For now,
1215                  * blacklist anything older than V3.04.
1216                  *
1217                  * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1218                  */
1219                 {
1220                         .ident = "G725",
1221                         .matches = {
1222                                 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1223                                 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1224                         },
1225                         .driver_data = "20091216",      /* V3.04 */
1226                 },
1227                 { }     /* terminate list */
1228         };
1229         const struct dmi_system_id *dmi = dmi_first_match(sysids);
1230         int year, month, date;
1231         char buf[9];
1232 
1233         if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1234                 return false;
1235 
1236         dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1237         snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1238 
1239         return strcmp(buf, dmi->driver_data) < 0;
1240 }
1241 
1242 static bool ahci_broken_lpm(struct pci_dev *pdev)
1243 {
1244         static const struct dmi_system_id sysids[] = {
1245                 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1246                 {
1247                         .matches = {
1248                                 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1249                                 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1250                         },
1251                         .driver_data = "20180406", /* 1.31 */
1252                 },
1253                 {
1254                         .matches = {
1255                                 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1256                                 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1257                         },
1258                         .driver_data = "20180420", /* 1.28 */
1259                 },
1260                 {
1261                         .matches = {
1262                                 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1263                                 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1264                         },
1265                         .driver_data = "20180315", /* 1.33 */
1266                 },
1267                 {
1268                         .matches = {
1269                                 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1270                                 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1271                         },
1272                         /*
1273                          * Note date based on release notes, 2.35 has been
1274                          * reported to be good, but I've been unable to get
1275                          * a hold of the reporter to get the DMI BIOS date.
1276                          * TODO: fix this.
1277                          */
1278                         .driver_data = "20180310", /* 2.35 */
1279                 },
1280                 { }     /* terminate list */
1281         };
1282         const struct dmi_system_id *dmi = dmi_first_match(sysids);
1283         int year, month, date;
1284         char buf[9];
1285 
1286         if (!dmi)
1287                 return false;
1288 
1289         dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1290         snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1291 
1292         return strcmp(buf, dmi->driver_data) < 0;
1293 }
1294 
1295 static bool ahci_broken_online(struct pci_dev *pdev)
1296 {
1297 #define ENCODE_BUSDEVFN(bus, slot, func)                        \
1298         (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1299         static const struct dmi_system_id sysids[] = {
1300                 /*
1301                  * There are several gigabyte boards which use
1302                  * SIMG5723s configured as hardware RAID.  Certain
1303                  * 5723 firmware revisions shipped there keep the link
1304                  * online but fail to answer properly to SRST or
1305                  * IDENTIFY when no device is attached downstream
1306                  * causing libata to retry quite a few times leading
1307                  * to excessive detection delay.
1308                  *
1309                  * As these firmwares respond to the second reset try
1310                  * with invalid device signature, considering unknown
1311                  * sig as offline works around the problem acceptably.
1312                  */
1313                 {
1314                         .ident = "EP45-DQ6",
1315                         .matches = {
1316                                 DMI_MATCH(DMI_BOARD_VENDOR,
1317                                           "Gigabyte Technology Co., Ltd."),
1318                                 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1319                         },
1320                         .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1321                 },
1322                 {
1323                         .ident = "EP45-DS5",
1324                         .matches = {
1325                                 DMI_MATCH(DMI_BOARD_VENDOR,
1326                                           "Gigabyte Technology Co., Ltd."),
1327                                 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1328                         },
1329                         .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1330                 },
1331                 { }     /* terminate list */
1332         };
1333 #undef ENCODE_BUSDEVFN
1334         const struct dmi_system_id *dmi = dmi_first_match(sysids);
1335         unsigned int val;
1336 
1337         if (!dmi)
1338                 return false;
1339 
1340         val = (unsigned long)dmi->driver_data;
1341 
1342         return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1343 }
1344 
1345 static bool ahci_broken_devslp(struct pci_dev *pdev)
1346 {
1347         /* device with broken DEVSLP but still showing SDS capability */
1348         static const struct pci_device_id ids[] = {
1349                 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1350                 {}
1351         };
1352 
1353         return pci_match_id(ids, pdev);
1354 }
1355 
1356 #ifdef CONFIG_ATA_ACPI
1357 static void ahci_gtf_filter_workaround(struct ata_host *host)
1358 {
1359         static const struct dmi_system_id sysids[] = {
1360                 /*
1361                  * Aspire 3810T issues a bunch of SATA enable commands
1362                  * via _GTF including an invalid one and one which is
1363                  * rejected by the device.  Among the successful ones
1364                  * is FPDMA non-zero offset enable which when enabled
1365                  * only on the drive side leads to NCQ command
1366                  * failures.  Filter it out.
1367                  */
1368                 {
1369                         .ident = "Aspire 3810T",
1370                         .matches = {
1371                                 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1372                                 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1373                         },
1374                         .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1375                 },
1376                 { }
1377         };
1378         const struct dmi_system_id *dmi = dmi_first_match(sysids);
1379         unsigned int filter;
1380         int i;
1381 
1382         if (!dmi)
1383                 return;
1384 
1385         filter = (unsigned long)dmi->driver_data;
1386         dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1387                  filter, dmi->ident);
1388 
1389         for (i = 0; i < host->n_ports; i++) {
1390                 struct ata_port *ap = host->ports[i];
1391                 struct ata_link *link;
1392                 struct ata_device *dev;
1393 
1394                 ata_for_each_link(link, ap, EDGE)
1395                         ata_for_each_dev(dev, link, ALL)
1396                                 dev->gtf_filter |= filter;
1397         }
1398 }
1399 #else
1400 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1401 {}
1402 #endif
1403 
1404 /*
1405  * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1406  * as DUMMY, or detected but eventually get a "link down" and never get up
1407  * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1408  * port_map may hold a value of 0x00.
1409  *
1410  * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1411  * and can significantly reduce the occurrence of the problem.
1412  *
1413  * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1414  */
1415 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1416                                     struct pci_dev *pdev)
1417 {
1418         static const struct dmi_system_id sysids[] = {
1419                 {
1420                         .ident = "Acer Switch Alpha 12",
1421                         .matches = {
1422                                 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1423                                 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1424                         },
1425                 },
1426                 { }
1427         };
1428 
1429         if (dmi_check_system(sysids)) {
1430                 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1431                 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1432                         hpriv->port_map = 0x7;
1433                         hpriv->cap = 0xC734FF02;
1434                 }
1435         }
1436 }
1437 
1438 #ifdef CONFIG_ARM64
1439 /*
1440  * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1441  * Workaround is to make sure all pending IRQs are served before leaving
1442  * handler.
1443  */
1444 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1445 {
1446         struct ata_host *host = dev_instance;
1447         struct ahci_host_priv *hpriv;
1448         unsigned int rc = 0;
1449         void __iomem *mmio;
1450         u32 irq_stat, irq_masked;
1451         unsigned int handled = 1;
1452 
1453         VPRINTK("ENTER\n");
1454         hpriv = host->private_data;
1455         mmio = hpriv->mmio;
1456         irq_stat = readl(mmio + HOST_IRQ_STAT);
1457         if (!irq_stat)
1458                 return IRQ_NONE;
1459 
1460         do {
1461                 irq_masked = irq_stat & hpriv->port_map;
1462                 spin_lock(&host->lock);
1463                 rc = ahci_handle_port_intr(host, irq_masked);
1464                 if (!rc)
1465                         handled = 0;
1466                 writel(irq_stat, mmio + HOST_IRQ_STAT);
1467                 irq_stat = readl(mmio + HOST_IRQ_STAT);
1468                 spin_unlock(&host->lock);
1469         } while (irq_stat);
1470         VPRINTK("EXIT\n");
1471 
1472         return IRQ_RETVAL(handled);
1473 }
1474 #endif
1475 
1476 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1477                 struct ahci_host_priv *hpriv)
1478 {
1479         int i, count = 0;
1480         u32 cap;
1481 
1482         /*
1483          * Check if this device might have remapped nvme devices.
1484          */
1485         if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1486             pci_resource_len(pdev, bar) < SZ_512K ||
1487             bar != AHCI_PCI_BAR_STANDARD ||
1488             !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1489                 return;
1490 
1491         cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1492         for (i = 0; i < AHCI_MAX_REMAP; i++) {
1493                 if ((cap & (1 << i)) == 0)
1494                         continue;
1495                 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1496                                 != PCI_CLASS_STORAGE_EXPRESS)
1497                         continue;
1498 
1499                 /* We've found a remapped device */
1500                 count++;
1501         }
1502 
1503         if (!count)
1504                 return;
1505 
1506         dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1507         dev_warn(&pdev->dev,
1508                  "Switch your BIOS from RAID to AHCI mode to use them.\n");
1509 
1510         /*
1511          * Don't rely on the msi-x capability in the remap case,
1512          * share the legacy interrupt across ahci and remapped devices.
1513          */
1514         hpriv->flags |= AHCI_HFLAG_NO_MSI;
1515 }
1516 
1517 static int ahci_get_irq_vector(struct ata_host *host, int port)
1518 {
1519         return pci_irq_vector(to_pci_dev(host->dev), port);
1520 }
1521 
1522 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1523                         struct ahci_host_priv *hpriv)
1524 {
1525         int nvec;
1526 
1527         if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1528                 return -ENODEV;
1529 
1530         /*
1531          * If number of MSIs is less than number of ports then Sharing Last
1532          * Message mode could be enforced. In this case assume that advantage
1533          * of multipe MSIs is negated and use single MSI mode instead.
1534          */
1535         if (n_ports > 1) {
1536                 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1537                                 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1538                 if (nvec > 0) {
1539                         if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1540                                 hpriv->get_irq_vector = ahci_get_irq_vector;
1541                                 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1542                                 return nvec;
1543                         }
1544 
1545                         /*
1546                          * Fallback to single MSI mode if the controller
1547                          * enforced MRSM mode.
1548                          */
1549                         printk(KERN_INFO
1550                                 "ahci: MRSM is on, fallback to single MSI\n");
1551                         pci_free_irq_vectors(pdev);
1552                 }
1553         }
1554 
1555         /*
1556          * If the host is not capable of supporting per-port vectors, fall
1557          * back to single MSI before finally attempting single MSI-X.
1558          */
1559         nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1560         if (nvec == 1)
1561                 return nvec;
1562         return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1563 }
1564 
1565 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1566                                            struct ahci_host_priv *hpriv)
1567 {
1568         int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1569 
1570 
1571         /* Ignore processing for non mobile platforms */
1572         if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1573                 return;
1574 
1575         /* user modified policy via module param */
1576         if (mobile_lpm_policy != -1) {
1577                 policy = mobile_lpm_policy;
1578                 goto update_policy;
1579         }
1580 
1581 #ifdef CONFIG_ACPI
1582         if (policy > ATA_LPM_MED_POWER &&
1583             (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1584                 if (hpriv->cap & HOST_CAP_PART)
1585                         policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1586                 else if (hpriv->cap & HOST_CAP_SSC)
1587                         policy = ATA_LPM_MIN_POWER;
1588         }
1589 #endif
1590 
1591 update_policy:
1592         if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1593                 ap->target_lpm_policy = policy;
1594 }
1595 
1596 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1597 {
1598         const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1599         u16 tmp16;
1600 
1601         /*
1602          * Only apply the 6-port PCS quirk for known legacy platforms.
1603          */
1604         if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1605                 return;
1606 
1607         /* Skip applying the quirk on Denverton and beyond */
1608         if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1609                 return;
1610 
1611         /*
1612          * port_map is determined from PORTS_IMPL PCI register which is
1613          * implemented as write or write-once register.  If the register
1614          * isn't programmed, ahci automatically generates it from number
1615          * of ports, which is good enough for PCS programming. It is
1616          * otherwise expected that platform firmware enables the ports
1617          * before the OS boots.
1618          */
1619         pci_read_config_word(pdev, PCS_6, &tmp16);
1620         if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1621                 tmp16 |= hpriv->port_map;
1622                 pci_write_config_word(pdev, PCS_6, tmp16);
1623         }
1624 }
1625 
1626 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1627 {
1628         unsigned int board_id = ent->driver_data;
1629         struct ata_port_info pi = ahci_port_info[board_id];
1630         const struct ata_port_info *ppi[] = { &pi, NULL };
1631         struct device *dev = &pdev->dev;
1632         struct ahci_host_priv *hpriv;
1633         struct ata_host *host;
1634         int n_ports, i, rc;
1635         int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1636 
1637         VPRINTK("ENTER\n");
1638 
1639         WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1640 
1641         ata_print_version_once(&pdev->dev, DRV_VERSION);
1642 
1643         /* The AHCI driver can only drive the SATA ports, the PATA driver
1644            can drive them all so if both drivers are selected make sure
1645            AHCI stays out of the way */
1646         if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1647                 return -ENODEV;
1648 
1649         /* Apple BIOS on MCP89 prevents us using AHCI */
1650         if (is_mcp89_apple(pdev))
1651                 ahci_mcp89_apple_enable(pdev);
1652 
1653         /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1654          * At the moment, we can only use the AHCI mode. Let the users know
1655          * that for SAS drives they're out of luck.
1656          */
1657         if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1658                 dev_info(&pdev->dev,
1659                          "PDC42819 can only drive SATA devices with this driver\n");
1660 
1661         /* Some devices use non-standard BARs */
1662         if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1663                 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1664         else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1665                 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1666         else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1667                 if (pdev->device == 0xa01c)
1668                         ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1669                 if (pdev->device == 0xa084)
1670                         ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1671         }
1672 
1673         /* acquire resources */
1674         rc = pcim_enable_device(pdev);
1675         if (rc)
1676                 return rc;
1677 
1678         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1679             (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1680                 u8 map;
1681 
1682                 /* ICH6s share the same PCI ID for both piix and ahci
1683                  * modes.  Enabling ahci mode while MAP indicates
1684                  * combined mode is a bad idea.  Yield to ata_piix.
1685                  */
1686                 pci_read_config_byte(pdev, ICH_MAP, &map);
1687                 if (map & 0x3) {
1688                         dev_info(&pdev->dev,
1689                                  "controller is in combined mode, can't enable AHCI mode\n");
1690                         return -ENODEV;
1691                 }
1692         }
1693 
1694         /* AHCI controllers often implement SFF compatible interface.
1695          * Grab all PCI BARs just in case.
1696          */
1697         rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1698         if (rc == -EBUSY)
1699                 pcim_pin_device(pdev);
1700         if (rc)
1701                 return rc;
1702 
1703         hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1704         if (!hpriv)
1705                 return -ENOMEM;
1706         hpriv->flags |= (unsigned long)pi.private_data;
1707 
1708         /* MCP65 revision A1 and A2 can't do MSI */
1709         if (board_id == board_ahci_mcp65 &&
1710             (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1711                 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1712 
1713         /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1714         if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1715                 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1716 
1717         /* only some SB600s can do 64bit DMA */
1718         if (ahci_sb600_enable_64bit(pdev))
1719                 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1720 
1721         hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1722 
1723         /* detect remapped nvme devices */
1724         ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1725 
1726         /* must set flag prior to save config in order to take effect */
1727         if (ahci_broken_devslp(pdev))
1728                 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1729 
1730 #ifdef CONFIG_ARM64
1731         if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1732                 hpriv->irq_handler = ahci_thunderx_irq_handler;
1733 #endif
1734 
1735         /* save initial config */
1736         ahci_pci_save_initial_config(pdev, hpriv);
1737 
1738         /*
1739          * If platform firmware failed to enable ports, try to enable
1740          * them here.
1741          */
1742         ahci_intel_pcs_quirk(pdev, hpriv);
1743 
1744         /* prepare host */
1745         if (hpriv->cap & HOST_CAP_NCQ) {
1746                 pi.flags |= ATA_FLAG_NCQ;
1747                 /*
1748                  * Auto-activate optimization is supposed to be
1749                  * supported on all AHCI controllers indicating NCQ
1750                  * capability, but it seems to be broken on some
1751                  * chipsets including NVIDIAs.
1752                  */
1753                 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1754                         pi.flags |= ATA_FLAG_FPDMA_AA;
1755 
1756                 /*
1757                  * All AHCI controllers should be forward-compatible
1758                  * with the new auxiliary field. This code should be
1759                  * conditionalized if any buggy AHCI controllers are
1760                  * encountered.
1761                  */
1762                 pi.flags |= ATA_FLAG_FPDMA_AUX;
1763         }
1764 
1765         if (hpriv->cap & HOST_CAP_PMP)
1766                 pi.flags |= ATA_FLAG_PMP;
1767 
1768         ahci_set_em_messages(hpriv, &pi);
1769 
1770         if (ahci_broken_system_poweroff(pdev)) {
1771                 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1772                 dev_info(&pdev->dev,
1773                         "quirky BIOS, skipping spindown on poweroff\n");
1774         }
1775 
1776         if (ahci_broken_lpm(pdev)) {
1777                 pi.flags |= ATA_FLAG_NO_LPM;
1778                 dev_warn(&pdev->dev,
1779                          "BIOS update required for Link Power Management support\n");
1780         }
1781 
1782         if (ahci_broken_suspend(pdev)) {
1783                 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1784                 dev_warn(&pdev->dev,
1785                          "BIOS update required for suspend/resume\n");
1786         }
1787 
1788         if (ahci_broken_online(pdev)) {
1789                 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1790                 dev_info(&pdev->dev,
1791                          "online status unreliable, applying workaround\n");
1792         }
1793 
1794 
1795         /* Acer SA5-271 workaround modifies private_data */
1796         acer_sa5_271_workaround(hpriv, pdev);
1797 
1798         /* CAP.NP sometimes indicate the index of the last enabled
1799          * port, at other times, that of the last possible port, so
1800          * determining the maximum port number requires looking at
1801          * both CAP.NP and port_map.
1802          */
1803         n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1804 
1805         host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1806         if (!host)
1807                 return -ENOMEM;
1808         host->private_data = hpriv;
1809 
1810         if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1811                 /* legacy intx interrupts */
1812                 pci_intx(pdev, 1);
1813         }
1814         hpriv->irq = pci_irq_vector(pdev, 0);
1815 
1816         if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1817                 host->flags |= ATA_HOST_PARALLEL_SCAN;
1818         else
1819                 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1820 
1821         if (pi.flags & ATA_FLAG_EM)
1822                 ahci_reset_em(host);
1823 
1824         for (i = 0; i < host->n_ports; i++) {
1825                 struct ata_port *ap = host->ports[i];
1826 
1827                 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1828                 ata_port_pbar_desc(ap, ahci_pci_bar,
1829                                    0x100 + ap->port_no * 0x80, "port");
1830 
1831                 /* set enclosure management message type */
1832                 if (ap->flags & ATA_FLAG_EM)
1833                         ap->em_message_type = hpriv->em_msg_type;
1834 
1835                 ahci_update_initial_lpm_policy(ap, hpriv);
1836 
1837                 /* disabled/not-implemented port */
1838                 if (!(hpriv->port_map & (1 << i)))
1839                         ap->ops = &ata_dummy_port_ops;
1840         }
1841 
1842         /* apply workaround for ASUS P5W DH Deluxe mainboard */
1843         ahci_p5wdh_workaround(host);
1844 
1845         /* apply gtf filter quirk */
1846         ahci_gtf_filter_workaround(host);
1847 
1848         /* initialize adapter */
1849         rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1850         if (rc)
1851                 return rc;
1852 
1853         rc = ahci_reset_controller(host);
1854         if (rc)
1855                 return rc;
1856 
1857         ahci_pci_init_controller(host);
1858         ahci_pci_print_info(host);
1859 
1860         pci_set_master(pdev);
1861 
1862         rc = ahci_host_activate(host, &ahci_sht);
1863         if (rc)
1864                 return rc;
1865 
1866         pm_runtime_put_noidle(&pdev->dev);
1867         return 0;
1868 }
1869 
1870 static void ahci_shutdown_one(struct pci_dev *pdev)
1871 {
1872         ata_pci_shutdown_one(pdev);
1873 }
1874 
1875 static void ahci_remove_one(struct pci_dev *pdev)
1876 {
1877         pm_runtime_get_noresume(&pdev->dev);
1878         ata_pci_remove_one(pdev);
1879 }
1880 
1881 module_pci_driver(ahci_pci_driver);
1882 
1883 MODULE_AUTHOR("Jeff Garzik");
1884 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1885 MODULE_LICENSE("GPL");
1886 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1887 MODULE_VERSION(DRV_VERSION);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/ata/ahci.c

DEFINITIONS
