drivers/ata/pata_octeon

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This source file includes following definitions.
ns_to_tim_reg
octeon_cf_set_boot_reg_cfg
octeon_cf_set_piomode
octeon_cf_set_dmamode
octeon_cf_data_xfer8
octeon_cf_data_xfer16
octeon_cf_tf_read16
octeon_cf_check_status16
octeon_cf_softreset16
octeon_cf_tf_load16
octeon_cf_dev_select
octeon_cf_exec_command16
octeon_cf_ata_port_noaction
octeon_cf_dma_setup
octeon_cf_dma_start
octeon_cf_dma_finished
octeon_cf_interrupt
octeon_cf_delayed_finish
octeon_cf_dev_config
octeon_cf_check_atapi_dma
octeon_cf_qc_issue
octeon_cf_probe
octeon_cf_shutdown
octeon_cf_init
   1 /*
   2  * Driver for the Octeon bootbus compact flash.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2005 - 2012 Cavium Inc.
   9  * Copyright (C) 2008 Wind River Systems
  10  */
  11 
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/libata.h>
  15 #include <linux/hrtimer.h>
  16 #include <linux/slab.h>
  17 #include <linux/irq.h>
  18 #include <linux/of.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/platform_device.h>
  21 #include <scsi/scsi_host.h>
  22 
  23 #include <asm/byteorder.h>
  24 #include <asm/octeon/octeon.h>
  25 
  26 /*
  27  * The Octeon bootbus compact flash interface is connected in at least
  28  * 3 different configurations on various evaluation boards:
  29  *
  30  * -- 8  bits no irq, no DMA
  31  * -- 16 bits no irq, no DMA
  32  * -- 16 bits True IDE mode with DMA, but no irq.
  33  *
  34  * In the last case the DMA engine can generate an interrupt when the
  35  * transfer is complete.  For the first two cases only PIO is supported.
  36  *
  37  */
  38 
  39 #define DRV_NAME        "pata_octeon_cf"
  40 #define DRV_VERSION     "2.2"
  41 
  42 /* Poll interval in nS. */
  43 #define OCTEON_CF_BUSY_POLL_INTERVAL 500000
  44 
  45 #define DMA_CFG 0
  46 #define DMA_TIM 0x20
  47 #define DMA_INT 0x38
  48 #define DMA_INT_EN 0x50
  49 
  50 struct octeon_cf_port {
  51         struct hrtimer delayed_finish;
  52         struct ata_port *ap;
  53         int dma_finished;
  54         void            *c0;
  55         unsigned int cs0;
  56         unsigned int cs1;
  57         bool is_true_ide;
  58         u64 dma_base;
  59 };
  60 
  61 static struct scsi_host_template octeon_cf_sht = {
  62         ATA_PIO_SHT(DRV_NAME),
  63 };
  64 
  65 static int enable_dma;
  66 module_param(enable_dma, int, 0444);
  67 MODULE_PARM_DESC(enable_dma,
  68                  "Enable use of DMA on interfaces that support it (0=no dma [default], 1=use dma)");
  69 
  70 /**
  71  * Convert nanosecond based time to setting used in the
  72  * boot bus timing register, based on timing multiple
  73  */
  74 static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs)
  75 {
  76         unsigned int val;
  77 
  78         /*
  79          * Compute # of eclock periods to get desired duration in
  80          * nanoseconds.
  81          */
  82         val = DIV_ROUND_UP(nsecs * (octeon_get_io_clock_rate() / 1000000),
  83                           1000 * tim_mult);
  84 
  85         return val;
  86 }
  87 
  88 static void octeon_cf_set_boot_reg_cfg(int cs, unsigned int multiplier)
  89 {
  90         union cvmx_mio_boot_reg_cfgx reg_cfg;
  91         unsigned int tim_mult;
  92 
  93         switch (multiplier) {
  94         case 8:
  95                 tim_mult = 3;
  96                 break;
  97         case 4:
  98                 tim_mult = 0;
  99                 break;
 100         case 2:
 101                 tim_mult = 2;
 102                 break;
 103         default:
 104                 tim_mult = 1;
 105                 break;
 106         }
 107 
 108         reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
 109         reg_cfg.s.dmack = 0;    /* Don't assert DMACK on access */
 110         reg_cfg.s.tim_mult = tim_mult;  /* Timing mutiplier */
 111         reg_cfg.s.rd_dly = 0;   /* Sample on falling edge of BOOT_OE */
 112         reg_cfg.s.sam = 0;      /* Don't combine write and output enable */
 113         reg_cfg.s.we_ext = 0;   /* No write enable extension */
 114         reg_cfg.s.oe_ext = 0;   /* No read enable extension */
 115         reg_cfg.s.en = 1;       /* Enable this region */
 116         reg_cfg.s.orbit = 0;    /* Don't combine with previous region */
 117         reg_cfg.s.ale = 0;      /* Don't do address multiplexing */
 118         cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64);
 119 }
 120 
 121 /**
 122  * Called after libata determines the needed PIO mode. This
 123  * function programs the Octeon bootbus regions to support the
 124  * timing requirements of the PIO mode.
 125  *
 126  * @ap:     ATA port information
 127  * @dev:    ATA device
 128  */
 129 static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev)
 130 {
 131         struct octeon_cf_port *cf_port = ap->private_data;
 132         union cvmx_mio_boot_reg_timx reg_tim;
 133         int T;
 134         struct ata_timing timing;
 135 
 136         unsigned int div;
 137         int use_iordy;
 138         int trh;
 139         int pause;
 140         /* These names are timing parameters from the ATA spec */
 141         int t2;
 142 
 143         /*
 144          * A divisor value of four will overflow the timing fields at
 145          * clock rates greater than 800MHz
 146          */
 147         if (octeon_get_io_clock_rate() <= 800000000)
 148                 div = 4;
 149         else
 150                 div = 8;
 151         T = (int)((1000000000000LL * div) / octeon_get_io_clock_rate());
 152 
 153         BUG_ON(ata_timing_compute(dev, dev->pio_mode, &timing, T, T));
 154 
 155         t2 = timing.active;
 156         if (t2)
 157                 t2--;
 158 
 159         trh = ns_to_tim_reg(div, 20);
 160         if (trh)
 161                 trh--;
 162 
 163         pause = (int)timing.cycle - (int)timing.active -
 164                 (int)timing.setup - trh;
 165         if (pause < 0)
 166                 pause = 0;
 167         if (pause)
 168                 pause--;
 169 
 170         octeon_cf_set_boot_reg_cfg(cf_port->cs0, div);
 171         if (cf_port->is_true_ide)
 172                 /* True IDE mode, program both chip selects.  */
 173                 octeon_cf_set_boot_reg_cfg(cf_port->cs1, div);
 174 
 175 
 176         use_iordy = ata_pio_need_iordy(dev);
 177 
 178         reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0));
 179         /* Disable page mode */
 180         reg_tim.s.pagem = 0;
 181         /* Enable dynamic timing */
 182         reg_tim.s.waitm = use_iordy;
 183         /* Pages are disabled */
 184         reg_tim.s.pages = 0;
 185         /* We don't use multiplexed address mode */
 186         reg_tim.s.ale = 0;
 187         /* Not used */
 188         reg_tim.s.page = 0;
 189         /* Time after IORDY to coninue to assert the data */
 190         reg_tim.s.wait = 0;
 191         /* Time to wait to complete the cycle. */
 192         reg_tim.s.pause = pause;
 193         /* How long to hold after a write to de-assert CE. */
 194         reg_tim.s.wr_hld = trh;
 195         /* How long to wait after a read to de-assert CE. */
 196         reg_tim.s.rd_hld = trh;
 197         /* How long write enable is asserted */
 198         reg_tim.s.we = t2;
 199         /* How long read enable is asserted */
 200         reg_tim.s.oe = t2;
 201         /* Time after CE that read/write starts */
 202         reg_tim.s.ce = ns_to_tim_reg(div, 5);
 203         /* Time before CE that address is valid */
 204         reg_tim.s.adr = 0;
 205 
 206         /* Program the bootbus region timing for the data port chip select. */
 207         cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64);
 208         if (cf_port->is_true_ide)
 209                 /* True IDE mode, program both chip selects.  */
 210                 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1),
 211                                reg_tim.u64);
 212 }
 213 
 214 static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev)
 215 {
 216         struct octeon_cf_port *cf_port = ap->private_data;
 217         union cvmx_mio_boot_pin_defs pin_defs;
 218         union cvmx_mio_boot_dma_timx dma_tim;
 219         unsigned int oe_a;
 220         unsigned int oe_n;
 221         unsigned int dma_ackh;
 222         unsigned int dma_arq;
 223         unsigned int pause;
 224         unsigned int T0, Tkr, Td;
 225         unsigned int tim_mult;
 226         int c;
 227 
 228         const struct ata_timing *timing;
 229 
 230         timing = ata_timing_find_mode(dev->dma_mode);
 231         T0      = timing->cycle;
 232         Td      = timing->active;
 233         Tkr     = timing->recover;
 234         dma_ackh = timing->dmack_hold;
 235 
 236         dma_tim.u64 = 0;
 237         /* dma_tim.s.tim_mult = 0 --> 4x */
 238         tim_mult = 4;
 239 
 240         /* not spec'ed, value in eclocks, not affected by tim_mult */
 241         dma_arq = 8;
 242         pause = 25 - dma_arq * 1000 /
 243                 (octeon_get_io_clock_rate() / 1000000); /* Tz */
 244 
 245         oe_a = Td;
 246         /* Tkr from cf spec, lengthened to meet T0 */
 247         oe_n = max(T0 - oe_a, Tkr);
 248 
 249         pin_defs.u64 = cvmx_read_csr(CVMX_MIO_BOOT_PIN_DEFS);
 250 
 251         /* DMA channel number. */
 252         c = (cf_port->dma_base & 8) >> 3;
 253 
 254         /* Invert the polarity if the default is 0*/
 255         dma_tim.s.dmack_pi = (pin_defs.u64 & (1ull << (11 + c))) ? 0 : 1;
 256 
 257         dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n);
 258         dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a);
 259 
 260         /*
 261          * This is tI, C.F. spec. says 0, but Sony CF card requires
 262          * more, we use 20 nS.
 263          */
 264         dma_tim.s.dmack_s = ns_to_tim_reg(tim_mult, 20);
 265         dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh);
 266 
 267         dma_tim.s.dmarq = dma_arq;
 268         dma_tim.s.pause = ns_to_tim_reg(tim_mult, pause);
 269 
 270         dma_tim.s.rd_dly = 0;   /* Sample right on edge */
 271 
 272         /*  writes only */
 273         dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n);
 274         dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a);
 275 
 276         pr_debug("ns to ticks (mult %d) of %d is: %d\n", tim_mult, 60,
 277                  ns_to_tim_reg(tim_mult, 60));
 278         pr_debug("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n",
 279                  dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s,
 280                  dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause);
 281 
 282         cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64);
 283 }
 284 
 285 /**
 286  * Handle an 8 bit I/O request.
 287  *
 288  * @qc:         Queued command
 289  * @buffer:     Data buffer
 290  * @buflen:     Length of the buffer.
 291  * @rw:         True to write.
 292  */
 293 static unsigned int octeon_cf_data_xfer8(struct ata_queued_cmd *qc,
 294                                          unsigned char *buffer,
 295                                          unsigned int buflen,
 296                                          int rw)
 297 {
 298         struct ata_port *ap             = qc->dev->link->ap;
 299         void __iomem *data_addr         = ap->ioaddr.data_addr;
 300         unsigned long words;
 301         int count;
 302 
 303         words = buflen;
 304         if (rw) {
 305                 count = 16;
 306                 while (words--) {
 307                         iowrite8(*buffer, data_addr);
 308                         buffer++;
 309                         /*
 310                          * Every 16 writes do a read so the bootbus
 311                          * FIFO doesn't fill up.
 312                          */
 313                         if (--count == 0) {
 314                                 ioread8(ap->ioaddr.altstatus_addr);
 315                                 count = 16;
 316                         }
 317                 }
 318         } else {
 319                 ioread8_rep(data_addr, buffer, words);
 320         }
 321         return buflen;
 322 }
 323 
 324 /**
 325  * Handle a 16 bit I/O request.
 326  *
 327  * @qc:         Queued command
 328  * @buffer:     Data buffer
 329  * @buflen:     Length of the buffer.
 330  * @rw:         True to write.
 331  */
 332 static unsigned int octeon_cf_data_xfer16(struct ata_queued_cmd *qc,
 333                                           unsigned char *buffer,
 334                                           unsigned int buflen,
 335                                           int rw)
 336 {
 337         struct ata_port *ap             = qc->dev->link->ap;
 338         void __iomem *data_addr         = ap->ioaddr.data_addr;
 339         unsigned long words;
 340         int count;
 341 
 342         words = buflen / 2;
 343         if (rw) {
 344                 count = 16;
 345                 while (words--) {
 346                         iowrite16(*(uint16_t *)buffer, data_addr);
 347                         buffer += sizeof(uint16_t);
 348                         /*
 349                          * Every 16 writes do a read so the bootbus
 350                          * FIFO doesn't fill up.
 351                          */
 352                         if (--count == 0) {
 353                                 ioread8(ap->ioaddr.altstatus_addr);
 354                                 count = 16;
 355                         }
 356                 }
 357         } else {
 358                 while (words--) {
 359                         *(uint16_t *)buffer = ioread16(data_addr);
 360                         buffer += sizeof(uint16_t);
 361                 }
 362         }
 363         /* Transfer trailing 1 byte, if any. */
 364         if (unlikely(buflen & 0x01)) {
 365                 __le16 align_buf[1] = { 0 };
 366 
 367                 if (rw == READ) {
 368                         align_buf[0] = cpu_to_le16(ioread16(data_addr));
 369                         memcpy(buffer, align_buf, 1);
 370                 } else {
 371                         memcpy(align_buf, buffer, 1);
 372                         iowrite16(le16_to_cpu(align_buf[0]), data_addr);
 373                 }
 374                 words++;
 375         }
 376         return buflen;
 377 }
 378 
 379 /**
 380  * Read the taskfile for 16bit non-True IDE only.
 381  */
 382 static void octeon_cf_tf_read16(struct ata_port *ap, struct ata_taskfile *tf)
 383 {
 384         u16 blob;
 385         /* The base of the registers is at ioaddr.data_addr. */
 386         void __iomem *base = ap->ioaddr.data_addr;
 387 
 388         blob = __raw_readw(base + 0xc);
 389         tf->feature = blob >> 8;
 390 
 391         blob = __raw_readw(base + 2);
 392         tf->nsect = blob & 0xff;
 393         tf->lbal = blob >> 8;
 394 
 395         blob = __raw_readw(base + 4);
 396         tf->lbam = blob & 0xff;
 397         tf->lbah = blob >> 8;
 398 
 399         blob = __raw_readw(base + 6);
 400         tf->device = blob & 0xff;
 401         tf->command = blob >> 8;
 402 
 403         if (tf->flags & ATA_TFLAG_LBA48) {
 404                 if (likely(ap->ioaddr.ctl_addr)) {
 405                         iowrite8(tf->ctl | ATA_HOB, ap->ioaddr.ctl_addr);
 406 
 407                         blob = __raw_readw(base + 0xc);
 408                         tf->hob_feature = blob >> 8;
 409 
 410                         blob = __raw_readw(base + 2);
 411                         tf->hob_nsect = blob & 0xff;
 412                         tf->hob_lbal = blob >> 8;
 413 
 414                         blob = __raw_readw(base + 4);
 415                         tf->hob_lbam = blob & 0xff;
 416                         tf->hob_lbah = blob >> 8;
 417 
 418                         iowrite8(tf->ctl, ap->ioaddr.ctl_addr);
 419                         ap->last_ctl = tf->ctl;
 420                 } else {
 421                         WARN_ON(1);
 422                 }
 423         }
 424 }
 425 
 426 static u8 octeon_cf_check_status16(struct ata_port *ap)
 427 {
 428         u16 blob;
 429         void __iomem *base = ap->ioaddr.data_addr;
 430 
 431         blob = __raw_readw(base + 6);
 432         return blob >> 8;
 433 }
 434 
 435 static int octeon_cf_softreset16(struct ata_link *link, unsigned int *classes,
 436                                  unsigned long deadline)
 437 {
 438         struct ata_port *ap = link->ap;
 439         void __iomem *base = ap->ioaddr.data_addr;
 440         int rc;
 441         u8 err;
 442 
 443         DPRINTK("about to softreset\n");
 444         __raw_writew(ap->ctl, base + 0xe);
 445         udelay(20);
 446         __raw_writew(ap->ctl | ATA_SRST, base + 0xe);
 447         udelay(20);
 448         __raw_writew(ap->ctl, base + 0xe);
 449 
 450         rc = ata_sff_wait_after_reset(link, 1, deadline);
 451         if (rc) {
 452                 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
 453                 return rc;
 454         }
 455 
 456         /* determine by signature whether we have ATA or ATAPI devices */
 457         classes[0] = ata_sff_dev_classify(&link->device[0], 1, &err);
 458         DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
 459         return 0;
 460 }
 461 
 462 /**
 463  * Load the taskfile for 16bit non-True IDE only.  The device_addr is
 464  * not loaded, we do this as part of octeon_cf_exec_command16.
 465  */
 466 static void octeon_cf_tf_load16(struct ata_port *ap,
 467                                 const struct ata_taskfile *tf)
 468 {
 469         unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
 470         /* The base of the registers is at ioaddr.data_addr. */
 471         void __iomem *base = ap->ioaddr.data_addr;
 472 
 473         if (tf->ctl != ap->last_ctl) {
 474                 iowrite8(tf->ctl, ap->ioaddr.ctl_addr);
 475                 ap->last_ctl = tf->ctl;
 476                 ata_wait_idle(ap);
 477         }
 478         if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
 479                 __raw_writew(tf->hob_feature << 8, base + 0xc);
 480                 __raw_writew(tf->hob_nsect | tf->hob_lbal << 8, base + 2);
 481                 __raw_writew(tf->hob_lbam | tf->hob_lbah << 8, base + 4);
 482                 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
 483                         tf->hob_feature,
 484                         tf->hob_nsect,
 485                         tf->hob_lbal,
 486                         tf->hob_lbam,
 487                         tf->hob_lbah);
 488         }
 489         if (is_addr) {
 490                 __raw_writew(tf->feature << 8, base + 0xc);
 491                 __raw_writew(tf->nsect | tf->lbal << 8, base + 2);
 492                 __raw_writew(tf->lbam | tf->lbah << 8, base + 4);
 493                 VPRINTK("feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
 494                         tf->feature,
 495                         tf->nsect,
 496                         tf->lbal,
 497                         tf->lbam,
 498                         tf->lbah);
 499         }
 500         ata_wait_idle(ap);
 501 }
 502 
 503 
 504 static void octeon_cf_dev_select(struct ata_port *ap, unsigned int device)
 505 {
 506 /*  There is only one device, do nothing. */
 507         return;
 508 }
 509 
 510 /*
 511  * Issue ATA command to host controller.  The device_addr is also sent
 512  * as it must be written in a combined write with the command.
 513  */
 514 static void octeon_cf_exec_command16(struct ata_port *ap,
 515                                 const struct ata_taskfile *tf)
 516 {
 517         /* The base of the registers is at ioaddr.data_addr. */
 518         void __iomem *base = ap->ioaddr.data_addr;
 519         u16 blob;
 520 
 521         if (tf->flags & ATA_TFLAG_DEVICE) {
 522                 VPRINTK("device 0x%X\n", tf->device);
 523                 blob = tf->device;
 524         } else {
 525                 blob = 0;
 526         }
 527 
 528         DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
 529         blob |= (tf->command << 8);
 530         __raw_writew(blob, base + 6);
 531 
 532 
 533         ata_wait_idle(ap);
 534 }
 535 
 536 static void octeon_cf_ata_port_noaction(struct ata_port *ap)
 537 {
 538 }
 539 
 540 static void octeon_cf_dma_setup(struct ata_queued_cmd *qc)
 541 {
 542         struct ata_port *ap = qc->ap;
 543         struct octeon_cf_port *cf_port;
 544 
 545         cf_port = ap->private_data;
 546         DPRINTK("ENTER\n");
 547         /* issue r/w command */
 548         qc->cursg = qc->sg;
 549         cf_port->dma_finished = 0;
 550         ap->ops->sff_exec_command(ap, &qc->tf);
 551         DPRINTK("EXIT\n");
 552 }
 553 
 554 /**
 555  * Start a DMA transfer that was already setup
 556  *
 557  * @qc:     Information about the DMA
 558  */
 559 static void octeon_cf_dma_start(struct ata_queued_cmd *qc)
 560 {
 561         struct octeon_cf_port *cf_port = qc->ap->private_data;
 562         union cvmx_mio_boot_dma_cfgx mio_boot_dma_cfg;
 563         union cvmx_mio_boot_dma_intx mio_boot_dma_int;
 564         struct scatterlist *sg;
 565 
 566         VPRINTK("%d scatterlists\n", qc->n_elem);
 567 
 568         /* Get the scatter list entry we need to DMA into */
 569         sg = qc->cursg;
 570         BUG_ON(!sg);
 571 
 572         /*
 573          * Clear the DMA complete status.
 574          */
 575         mio_boot_dma_int.u64 = 0;
 576         mio_boot_dma_int.s.done = 1;
 577         cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64);
 578 
 579         /* Enable the interrupt.  */
 580         cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64);
 581 
 582         /* Set the direction of the DMA */
 583         mio_boot_dma_cfg.u64 = 0;
 584 #ifdef __LITTLE_ENDIAN
 585         mio_boot_dma_cfg.s.endian = 1;
 586 #endif
 587         mio_boot_dma_cfg.s.en = 1;
 588         mio_boot_dma_cfg.s.rw = ((qc->tf.flags & ATA_TFLAG_WRITE) != 0);
 589 
 590         /*
 591          * Don't stop the DMA if the device deasserts DMARQ. Many
 592          * compact flashes deassert DMARQ for a short time between
 593          * sectors. Instead of stopping and restarting the DMA, we'll
 594          * let the hardware do it. If the DMA is really stopped early
 595          * due to an error condition, a later timeout will force us to
 596          * stop.
 597          */
 598         mio_boot_dma_cfg.s.clr = 0;
 599 
 600         /* Size is specified in 16bit words and minus one notation */
 601         mio_boot_dma_cfg.s.size = sg_dma_len(sg) / 2 - 1;
 602 
 603         /* We need to swap the high and low bytes of every 16 bits */
 604         mio_boot_dma_cfg.s.swap8 = 1;
 605 
 606         mio_boot_dma_cfg.s.adr = sg_dma_address(sg);
 607 
 608         VPRINTK("%s %d bytes address=%p\n",
 609                 (mio_boot_dma_cfg.s.rw) ? "write" : "read", sg->length,
 610                 (void *)(unsigned long)mio_boot_dma_cfg.s.adr);
 611 
 612         cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64);
 613 }
 614 
 615 /**
 616  *
 617  *      LOCKING:
 618  *      spin_lock_irqsave(host lock)
 619  *
 620  */
 621 static unsigned int octeon_cf_dma_finished(struct ata_port *ap,
 622                                         struct ata_queued_cmd *qc)
 623 {
 624         struct ata_eh_info *ehi = &ap->link.eh_info;
 625         struct octeon_cf_port *cf_port = ap->private_data;
 626         union cvmx_mio_boot_dma_cfgx dma_cfg;
 627         union cvmx_mio_boot_dma_intx dma_int;
 628         u8 status;
 629 
 630         VPRINTK("ata%u: protocol %d task_state %d\n",
 631                 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
 632 
 633 
 634         if (ap->hsm_task_state != HSM_ST_LAST)
 635                 return 0;
 636 
 637         dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
 638         if (dma_cfg.s.size != 0xfffff) {
 639                 /* Error, the transfer was not complete.  */
 640                 qc->err_mask |= AC_ERR_HOST_BUS;
 641                 ap->hsm_task_state = HSM_ST_ERR;
 642         }
 643 
 644         /* Stop and clear the dma engine.  */
 645         dma_cfg.u64 = 0;
 646         dma_cfg.s.size = -1;
 647         cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
 648 
 649         /* Disable the interrupt.  */
 650         dma_int.u64 = 0;
 651         cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
 652 
 653         /* Clear the DMA complete status */
 654         dma_int.s.done = 1;
 655         cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
 656 
 657         status = ap->ops->sff_check_status(ap);
 658 
 659         ata_sff_hsm_move(ap, qc, status, 0);
 660 
 661         if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA))
 662                 ata_ehi_push_desc(ehi, "DMA stat 0x%x", status);
 663 
 664         return 1;
 665 }
 666 
 667 /*
 668  * Check if any queued commands have more DMAs, if so start the next
 669  * transfer, else do end of transfer handling.
 670  */
 671 static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance)
 672 {
 673         struct ata_host *host = dev_instance;
 674         struct octeon_cf_port *cf_port;
 675         int i;
 676         unsigned int handled = 0;
 677         unsigned long flags;
 678 
 679         spin_lock_irqsave(&host->lock, flags);
 680 
 681         DPRINTK("ENTER\n");
 682         for (i = 0; i < host->n_ports; i++) {
 683                 u8 status;
 684                 struct ata_port *ap;
 685                 struct ata_queued_cmd *qc;
 686                 union cvmx_mio_boot_dma_intx dma_int;
 687                 union cvmx_mio_boot_dma_cfgx dma_cfg;
 688 
 689                 ap = host->ports[i];
 690                 cf_port = ap->private_data;
 691 
 692                 dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT);
 693                 dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
 694 
 695                 qc = ata_qc_from_tag(ap, ap->link.active_tag);
 696 
 697                 if (!qc || (qc->tf.flags & ATA_TFLAG_POLLING))
 698                         continue;
 699 
 700                 if (dma_int.s.done && !dma_cfg.s.en) {
 701                         if (!sg_is_last(qc->cursg)) {
 702                                 qc->cursg = sg_next(qc->cursg);
 703                                 handled = 1;
 704                                 octeon_cf_dma_start(qc);
 705                                 continue;
 706                         } else {
 707                                 cf_port->dma_finished = 1;
 708                         }
 709                 }
 710                 if (!cf_port->dma_finished)
 711                         continue;
 712                 status = ioread8(ap->ioaddr.altstatus_addr);
 713                 if (status & (ATA_BUSY | ATA_DRQ)) {
 714                         /*
 715                          * We are busy, try to handle it later.  This
 716                          * is the DMA finished interrupt, and it could
 717                          * take a little while for the card to be
 718                          * ready for more commands.
 719                          */
 720                         /* Clear DMA irq. */
 721                         dma_int.u64 = 0;
 722                         dma_int.s.done = 1;
 723                         cvmx_write_csr(cf_port->dma_base + DMA_INT,
 724                                        dma_int.u64);
 725                         hrtimer_start_range_ns(&cf_port->delayed_finish,
 726                                                ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL),
 727                                                OCTEON_CF_BUSY_POLL_INTERVAL / 5,
 728                                                HRTIMER_MODE_REL);
 729                         handled = 1;
 730                 } else {
 731                         handled |= octeon_cf_dma_finished(ap, qc);
 732                 }
 733         }
 734         spin_unlock_irqrestore(&host->lock, flags);
 735         DPRINTK("EXIT\n");
 736         return IRQ_RETVAL(handled);
 737 }
 738 
 739 static enum hrtimer_restart octeon_cf_delayed_finish(struct hrtimer *hrt)
 740 {
 741         struct octeon_cf_port *cf_port = container_of(hrt,
 742                                                       struct octeon_cf_port,
 743                                                       delayed_finish);
 744         struct ata_port *ap = cf_port->ap;
 745         struct ata_host *host = ap->host;
 746         struct ata_queued_cmd *qc;
 747         unsigned long flags;
 748         u8 status;
 749         enum hrtimer_restart rv = HRTIMER_NORESTART;
 750 
 751         spin_lock_irqsave(&host->lock, flags);
 752 
 753         /*
 754          * If the port is not waiting for completion, it must have
 755          * handled it previously.  The hsm_task_state is
 756          * protected by host->lock.
 757          */
 758         if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished)
 759                 goto out;
 760 
 761         status = ioread8(ap->ioaddr.altstatus_addr);
 762         if (status & (ATA_BUSY | ATA_DRQ)) {
 763                 /* Still busy, try again. */
 764                 hrtimer_forward_now(hrt,
 765                                     ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL));
 766                 rv = HRTIMER_RESTART;
 767                 goto out;
 768         }
 769         qc = ata_qc_from_tag(ap, ap->link.active_tag);
 770         if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
 771                 octeon_cf_dma_finished(ap, qc);
 772 out:
 773         spin_unlock_irqrestore(&host->lock, flags);
 774         return rv;
 775 }
 776 
 777 static void octeon_cf_dev_config(struct ata_device *dev)
 778 {
 779         /*
 780          * A maximum of 2^20 - 1 16 bit transfers are possible with
 781          * the bootbus DMA.  So we need to throttle max_sectors to
 782          * (2^12 - 1 == 4095) to assure that this can never happen.
 783          */
 784         dev->max_sectors = min(dev->max_sectors, 4095U);
 785 }
 786 
 787 /*
 788  * We don't do ATAPI DMA so return 0.
 789  */
 790 static int octeon_cf_check_atapi_dma(struct ata_queued_cmd *qc)
 791 {
 792         return 0;
 793 }
 794 
 795 static unsigned int octeon_cf_qc_issue(struct ata_queued_cmd *qc)
 796 {
 797         struct ata_port *ap = qc->ap;
 798 
 799         switch (qc->tf.protocol) {
 800         case ATA_PROT_DMA:
 801                 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
 802 
 803                 ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
 804                 octeon_cf_dma_setup(qc);            /* set up dma */
 805                 octeon_cf_dma_start(qc);            /* initiate dma */
 806                 ap->hsm_task_state = HSM_ST_LAST;
 807                 break;
 808 
 809         case ATAPI_PROT_DMA:
 810                 dev_err(ap->dev, "Error, ATAPI not supported\n");
 811                 BUG();
 812 
 813         default:
 814                 return ata_sff_qc_issue(qc);
 815         }
 816 
 817         return 0;
 818 }
 819 
 820 static struct ata_port_operations octeon_cf_ops = {
 821         .inherits               = &ata_sff_port_ops,
 822         .check_atapi_dma        = octeon_cf_check_atapi_dma,
 823         .qc_prep                = ata_noop_qc_prep,
 824         .qc_issue               = octeon_cf_qc_issue,
 825         .sff_dev_select         = octeon_cf_dev_select,
 826         .sff_irq_on             = octeon_cf_ata_port_noaction,
 827         .sff_irq_clear          = octeon_cf_ata_port_noaction,
 828         .cable_detect           = ata_cable_40wire,
 829         .set_piomode            = octeon_cf_set_piomode,
 830         .set_dmamode            = octeon_cf_set_dmamode,
 831         .dev_config             = octeon_cf_dev_config,
 832 };
 833 
 834 static int octeon_cf_probe(struct platform_device *pdev)
 835 {
 836         struct resource *res_cs0, *res_cs1;
 837 
 838         bool is_16bit;
 839         const __be32 *cs_num;
 840         struct property *reg_prop;
 841         int n_addr, n_size, reg_len;
 842         struct device_node *node;
 843         void __iomem *cs0;
 844         void __iomem *cs1 = NULL;
 845         struct ata_host *host;
 846         struct ata_port *ap;
 847         int irq = 0;
 848         irq_handler_t irq_handler = NULL;
 849         void __iomem *base;
 850         struct octeon_cf_port *cf_port;
 851         int rv = -ENOMEM;
 852         u32 bus_width;
 853 
 854         node = pdev->dev.of_node;
 855         if (node == NULL)
 856                 return -EINVAL;
 857 
 858         cf_port = devm_kzalloc(&pdev->dev, sizeof(*cf_port), GFP_KERNEL);
 859         if (!cf_port)
 860                 return -ENOMEM;
 861 
 862         cf_port->is_true_ide = of_property_read_bool(node, "cavium,true-ide");
 863 
 864         if (of_property_read_u32(node, "cavium,bus-width", &bus_width) == 0)
 865                 is_16bit = (bus_width == 16);
 866         else
 867                 is_16bit = false;
 868 
 869         n_addr = of_n_addr_cells(node);
 870         n_size = of_n_size_cells(node);
 871 
 872         reg_prop = of_find_property(node, "reg", &reg_len);
 873         if (!reg_prop || reg_len < sizeof(__be32))
 874                 return -EINVAL;
 875 
 876         cs_num = reg_prop->value;
 877         cf_port->cs0 = be32_to_cpup(cs_num);
 878 
 879         if (cf_port->is_true_ide) {
 880                 struct device_node *dma_node;
 881                 dma_node = of_parse_phandle(node,
 882                                             "cavium,dma-engine-handle", 0);
 883                 if (dma_node) {
 884                         struct platform_device *dma_dev;
 885                         dma_dev = of_find_device_by_node(dma_node);
 886                         if (dma_dev) {
 887                                 struct resource *res_dma;
 888                                 int i;
 889                                 res_dma = platform_get_resource(dma_dev, IORESOURCE_MEM, 0);
 890                                 if (!res_dma) {
 891                                         of_node_put(dma_node);
 892                                         return -EINVAL;
 893                                 }
 894                                 cf_port->dma_base = (u64)devm_ioremap_nocache(&pdev->dev, res_dma->start,
 895                                                                          resource_size(res_dma));
 896                                 if (!cf_port->dma_base) {
 897                                         of_node_put(dma_node);
 898                                         return -EINVAL;
 899                                 }
 900 
 901                                 irq_handler = octeon_cf_interrupt;
 902                                 i = platform_get_irq(dma_dev, 0);
 903                                 if (i > 0)
 904                                         irq = i;
 905                         }
 906                         of_node_put(dma_node);
 907                 }
 908                 res_cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 909                 if (!res_cs1)
 910                         return -EINVAL;
 911 
 912                 cs1 = devm_ioremap_nocache(&pdev->dev, res_cs1->start,
 913                                            resource_size(res_cs1));
 914                 if (!cs1)
 915                         return rv;
 916 
 917                 if (reg_len < (n_addr + n_size + 1) * sizeof(__be32))
 918                         return -EINVAL;
 919 
 920                 cs_num += n_addr + n_size;
 921                 cf_port->cs1 = be32_to_cpup(cs_num);
 922         }
 923 
 924         res_cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 925         if (!res_cs0)
 926                 return -EINVAL;
 927 
 928         cs0 = devm_ioremap_nocache(&pdev->dev, res_cs0->start,
 929                                    resource_size(res_cs0));
 930         if (!cs0)
 931                 return rv;
 932 
 933         /* allocate host */
 934         host = ata_host_alloc(&pdev->dev, 1);
 935         if (!host)
 936                 return rv;
 937 
 938         ap = host->ports[0];
 939         ap->private_data = cf_port;
 940         pdev->dev.platform_data = cf_port;
 941         cf_port->ap = ap;
 942         ap->ops = &octeon_cf_ops;
 943         ap->pio_mask = ATA_PIO6;
 944         ap->flags |= ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING;
 945 
 946         if (!is_16bit) {
 947                 base = cs0 + 0x800;
 948                 ap->ioaddr.cmd_addr     = base;
 949                 ata_sff_std_ports(&ap->ioaddr);
 950 
 951                 ap->ioaddr.altstatus_addr = base + 0xe;
 952                 ap->ioaddr.ctl_addr     = base + 0xe;
 953                 octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer8;
 954         } else if (cf_port->is_true_ide) {
 955                 base = cs0;
 956                 ap->ioaddr.cmd_addr     = base + (ATA_REG_CMD << 1) + 1;
 957                 ap->ioaddr.data_addr    = base + (ATA_REG_DATA << 1);
 958                 ap->ioaddr.error_addr   = base + (ATA_REG_ERR << 1) + 1;
 959                 ap->ioaddr.feature_addr = base + (ATA_REG_FEATURE << 1) + 1;
 960                 ap->ioaddr.nsect_addr   = base + (ATA_REG_NSECT << 1) + 1;
 961                 ap->ioaddr.lbal_addr    = base + (ATA_REG_LBAL << 1) + 1;
 962                 ap->ioaddr.lbam_addr    = base + (ATA_REG_LBAM << 1) + 1;
 963                 ap->ioaddr.lbah_addr    = base + (ATA_REG_LBAH << 1) + 1;
 964                 ap->ioaddr.device_addr  = base + (ATA_REG_DEVICE << 1) + 1;
 965                 ap->ioaddr.status_addr  = base + (ATA_REG_STATUS << 1) + 1;
 966                 ap->ioaddr.command_addr = base + (ATA_REG_CMD << 1) + 1;
 967                 ap->ioaddr.altstatus_addr = cs1 + (6 << 1) + 1;
 968                 ap->ioaddr.ctl_addr     = cs1 + (6 << 1) + 1;
 969                 octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16;
 970 
 971                 ap->mwdma_mask  = enable_dma ? ATA_MWDMA4 : 0;
 972 
 973                 /* True IDE mode needs a timer to poll for not-busy.  */
 974                 hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC,
 975                              HRTIMER_MODE_REL);
 976                 cf_port->delayed_finish.function = octeon_cf_delayed_finish;
 977         } else {
 978                 /* 16 bit but not True IDE */
 979                 base = cs0 + 0x800;
 980                 octeon_cf_ops.sff_data_xfer     = octeon_cf_data_xfer16;
 981                 octeon_cf_ops.softreset         = octeon_cf_softreset16;
 982                 octeon_cf_ops.sff_check_status  = octeon_cf_check_status16;
 983                 octeon_cf_ops.sff_tf_read       = octeon_cf_tf_read16;
 984                 octeon_cf_ops.sff_tf_load       = octeon_cf_tf_load16;
 985                 octeon_cf_ops.sff_exec_command  = octeon_cf_exec_command16;
 986 
 987                 ap->ioaddr.data_addr    = base + ATA_REG_DATA;
 988                 ap->ioaddr.nsect_addr   = base + ATA_REG_NSECT;
 989                 ap->ioaddr.lbal_addr    = base + ATA_REG_LBAL;
 990                 ap->ioaddr.ctl_addr     = base + 0xe;
 991                 ap->ioaddr.altstatus_addr = base + 0xe;
 992         }
 993         cf_port->c0 = ap->ioaddr.ctl_addr;
 994 
 995         rv = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 996         if (rv)
 997                 return rv;
 998 
 999         ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr);
1000 
1001         dev_info(&pdev->dev, "version " DRV_VERSION" %d bit%s.\n",
1002                  is_16bit ? 16 : 8,
1003                  cf_port->is_true_ide ? ", True IDE" : "");
1004 
1005         return ata_host_activate(host, irq, irq_handler,
1006                                  IRQF_SHARED, &octeon_cf_sht);
1007 }
1008 
1009 static void octeon_cf_shutdown(struct device *dev)
1010 {
1011         union cvmx_mio_boot_dma_cfgx dma_cfg;
1012         union cvmx_mio_boot_dma_intx dma_int;
1013 
1014         struct octeon_cf_port *cf_port = dev_get_platdata(dev);
1015 
1016         if (cf_port->dma_base) {
1017                 /* Stop and clear the dma engine.  */
1018                 dma_cfg.u64 = 0;
1019                 dma_cfg.s.size = -1;
1020                 cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
1021 
1022                 /* Disable the interrupt.  */
1023                 dma_int.u64 = 0;
1024                 cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
1025 
1026                 /* Clear the DMA complete status */
1027                 dma_int.s.done = 1;
1028                 cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
1029 
1030                 __raw_writeb(0, cf_port->c0);
1031                 udelay(20);
1032                 __raw_writeb(ATA_SRST, cf_port->c0);
1033                 udelay(20);
1034                 __raw_writeb(0, cf_port->c0);
1035                 mdelay(100);
1036         }
1037 }
1038 
1039 static const struct of_device_id octeon_cf_match[] = {
1040         {
1041                 .compatible = "cavium,ebt3000-compact-flash",
1042         },
1043         {},
1044 };
1045 MODULE_DEVICE_TABLE(of, octeon_cf_match);
1046 
1047 static struct platform_driver octeon_cf_driver = {
1048         .probe          = octeon_cf_probe,
1049         .driver         = {
1050                 .name   = DRV_NAME,
1051                 .of_match_table = octeon_cf_match,
1052                 .shutdown = octeon_cf_shutdown
1053         },
1054 };
1055 
1056 static int __init octeon_cf_init(void)
1057 {
1058         return platform_driver_register(&octeon_cf_driver);
1059 }
1060 
1061 
1062 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
1063 MODULE_DESCRIPTION("low-level driver for Cavium OCTEON Compact Flash PATA");
1064 MODULE_LICENSE("GPL");
1065 MODULE_VERSION(DRV_VERSION);
1066 MODULE_ALIAS("platform:" DRV_NAME);
1067 
1068 module_init(octeon_cf_init);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/ata/pata_octeon_cf.c

DEFINITIONS
