drivers/ide/sc1200.c

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This source file includes following definitions.
sc1200_get_pci_clock
sc1200_tunepio
sc1200_udma_filter
sc1200_set_dma_mode
sc1200_dma_end
sc1200_set_pio_mode
sc1200_suspend
sc1200_resume
sc1200_init_one
sc1200_ide_init
sc1200_ide_exit
   1 /*
   2  * Copyright (C) 2000-2002              Mark Lord <mlord@pobox.com>
   3  * Copyright (C)      2007              Bartlomiej Zolnierkiewicz
   4  *
   5  * May be copied or modified under the terms of the GNU General Public License
   6  *
   7  * Development of this chipset driver was funded
   8  * by the nice folks at National Semiconductor.
   9  *
  10  * Documentation:
  11  *      Available from National Semiconductor
  12  */
  13 
  14 #include <linux/module.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/pci.h>
  19 #include <linux/init.h>
  20 #include <linux/ide.h>
  21 #include <linux/pm.h>
  22 
  23 #include <asm/io.h>
  24 
  25 #define DRV_NAME "sc1200"
  26 
  27 #define SC1200_REV_A    0x00
  28 #define SC1200_REV_B1   0x01
  29 #define SC1200_REV_B3   0x02
  30 #define SC1200_REV_C1   0x03
  31 #define SC1200_REV_D1   0x04
  32 
  33 #define PCI_CLK_33      0x00
  34 #define PCI_CLK_48      0x01
  35 #define PCI_CLK_66      0x02
  36 #define PCI_CLK_33A     0x03
  37 
  38 static unsigned short sc1200_get_pci_clock (void)
  39 {
  40         unsigned char chip_id, silicon_revision;
  41         unsigned int pci_clock;
  42         /*
  43          * Check the silicon revision, as not all versions of the chip
  44          * have the register with the fast PCI bus timings.
  45          */
  46         chip_id = inb (0x903c);
  47         silicon_revision = inb (0x903d);
  48 
  49         // Read the fast pci clock frequency
  50         if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
  51                 pci_clock = PCI_CLK_33;
  52         } else {
  53                 // check clock generator configuration (cfcc)
  54                 // the clock is in bits 8 and 9 of this word
  55 
  56                 pci_clock = inw (0x901e);
  57                 pci_clock >>= 8;
  58                 pci_clock &= 0x03;
  59                 if (pci_clock == PCI_CLK_33A)
  60                         pci_clock = PCI_CLK_33;
  61         }
  62         return pci_clock;
  63 }
  64 
  65 /*
  66  * Here are the standard PIO mode 0-4 timings for each "format".
  67  * Format-0 uses fast data reg timings, with slower command reg timings.
  68  * Format-1 uses fast timings for all registers, but won't work with all drives.
  69  */
  70 static const unsigned int sc1200_pio_timings[4][5] =
  71         {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},  // format0  33Mhz
  72          {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010},  // format1, 33Mhz
  73          {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021},  // format1, 48Mhz
  74          {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
  75 
  76 /*
  77  * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
  78  */
  79 //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
  80 
  81 static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
  82 {
  83         ide_hwif_t *hwif = drive->hwif;
  84         struct pci_dev *pdev = to_pci_dev(hwif->dev);
  85         unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
  86 
  87         pci_read_config_dword(pdev, basereg + 4, &format);
  88         format = (format >> 31) & 1;
  89         if (format)
  90                 format += sc1200_get_pci_clock();
  91         pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
  92                                sc1200_pio_timings[format][pio]);
  93 }
  94 
  95 /*
  96  *      The SC1200 specifies that two drives sharing a cable cannot mix
  97  *      UDMA/MDMA.  It has to be one or the other, for the pair, though
  98  *      different timings can still be chosen for each drive.  We could
  99  *      set the appropriate timing bits on the fly, but that might be
 100  *      a bit confusing.  So, for now we statically handle this requirement
 101  *      by looking at our mate drive to see what it is capable of, before
 102  *      choosing a mode for our own drive.
 103  */
 104 static u8 sc1200_udma_filter(ide_drive_t *drive)
 105 {
 106         ide_hwif_t *hwif = drive->hwif;
 107         ide_drive_t *mate = ide_get_pair_dev(drive);
 108         u16 *mateid;
 109         u8 mask = hwif->ultra_mask;
 110 
 111         if (mate == NULL)
 112                 goto out;
 113         mateid = mate->id;
 114 
 115         if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
 116                 if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
 117                     (mateid[ATA_ID_UDMA_MODES] & 7))
 118                         goto out;
 119                 if (mateid[ATA_ID_MWDMA_MODES] & 7)
 120                         mask = 0;
 121         }
 122 out:
 123         return mask;
 124 }
 125 
 126 static void sc1200_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 127 {
 128         struct pci_dev          *dev = to_pci_dev(hwif->dev);
 129         unsigned int            reg, timings;
 130         unsigned short          pci_clock;
 131         unsigned int            basereg = hwif->channel ? 0x50 : 0x40;
 132         const u8                mode = drive->dma_mode;
 133 
 134         static const u32 udma_timing[3][3] = {
 135                 { 0x00921250, 0x00911140, 0x00911030 },
 136                 { 0x00932470, 0x00922260, 0x00922140 },
 137                 { 0x009436a1, 0x00933481, 0x00923261 },
 138         };
 139 
 140         static const u32 mwdma_timing[3][3] = {
 141                 { 0x00077771, 0x00012121, 0x00002020 },
 142                 { 0x000bbbb2, 0x00024241, 0x00013131 },
 143                 { 0x000ffff3, 0x00035352, 0x00015151 },
 144         };
 145 
 146         pci_clock = sc1200_get_pci_clock();
 147 
 148         /*
 149          * Note that each DMA mode has several timings associated with it.
 150          * The correct timing depends on the fast PCI clock freq.
 151          */
 152 
 153         if (mode >= XFER_UDMA_0)
 154                 timings =  udma_timing[pci_clock][mode - XFER_UDMA_0];
 155         else
 156                 timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];
 157 
 158         if ((drive->dn & 1) == 0) {
 159                 pci_read_config_dword(dev, basereg + 4, &reg);
 160                 timings |= reg & 0x80000000;    /* preserve PIO format bit */
 161                 pci_write_config_dword(dev, basereg + 4, timings);
 162         } else
 163                 pci_write_config_dword(dev, basereg + 12, timings);
 164 }
 165 
 166 /*  Replacement for the standard ide_dma_end action in
 167  *  dma_proc.
 168  *
 169  *  returns 1 on error, 0 otherwise
 170  */
 171 static int sc1200_dma_end(ide_drive_t *drive)
 172 {
 173         ide_hwif_t *hwif = drive->hwif;
 174         unsigned long dma_base = hwif->dma_base;
 175         u8 dma_stat;
 176 
 177         dma_stat = inb(dma_base+2);             /* get DMA status */
 178 
 179         if (!(dma_stat & 4))
 180                 printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
 181                   dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
 182 
 183         outb(dma_stat|0x1b, dma_base+2);        /* clear the INTR & ERROR bits */
 184         outb(inb(dma_base)&~1, dma_base);       /* !! DO THIS HERE !! stop DMA */
 185 
 186         return (dma_stat & 7) != 4;             /* verify good DMA status */
 187 }
 188 
 189 /*
 190  * sc1200_set_pio_mode() handles setting of PIO modes
 191  * for both the chipset and drive.
 192  *
 193  * All existing BIOSs for this chipset guarantee that all drives
 194  * will have valid default PIO timings set up before we get here.
 195  */
 196 
 197 static void sc1200_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 198 {
 199         int             mode = -1;
 200         const u8        pio = drive->pio_mode - XFER_PIO_0;
 201 
 202         /*
 203          * bad abuse of ->set_pio_mode interface
 204          */
 205         switch (pio) {
 206                 case 200: mode = XFER_UDMA_0;   break;
 207                 case 201: mode = XFER_UDMA_1;   break;
 208                 case 202: mode = XFER_UDMA_2;   break;
 209                 case 100: mode = XFER_MW_DMA_0; break;
 210                 case 101: mode = XFER_MW_DMA_1; break;
 211                 case 102: mode = XFER_MW_DMA_2; break;
 212         }
 213         if (mode != -1) {
 214                 printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
 215                 ide_dma_off_quietly(drive);
 216                 if (ide_set_dma_mode(drive, mode) == 0 &&
 217                     (drive->dev_flags & IDE_DFLAG_USING_DMA))
 218                         hwif->dma_ops->dma_host_set(drive, 1);
 219                 return;
 220         }
 221 
 222         sc1200_tunepio(drive, pio);
 223 }
 224 
 225 #ifdef CONFIG_PM
 226 struct sc1200_saved_state {
 227         u32 regs[8];
 228 };
 229 
 230 static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
 231 {
 232         printk("SC1200: suspend(%u)\n", state.event);
 233 
 234         /*
 235          * we only save state when going from full power to less
 236          */
 237         if (state.event == PM_EVENT_ON) {
 238                 struct ide_host *host = pci_get_drvdata(dev);
 239                 struct sc1200_saved_state *ss = host->host_priv;
 240                 unsigned int r;
 241 
 242                 /*
 243                  * save timing registers
 244                  * (this may be unnecessary if BIOS also does it)
 245                  */
 246                 for (r = 0; r < 8; r++)
 247                         pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
 248         }
 249 
 250         pci_disable_device(dev);
 251         pci_set_power_state(dev, pci_choose_state(dev, state));
 252         return 0;
 253 }
 254 
 255 static int sc1200_resume (struct pci_dev *dev)
 256 {
 257         struct ide_host *host = pci_get_drvdata(dev);
 258         struct sc1200_saved_state *ss = host->host_priv;
 259         unsigned int r;
 260         int i;
 261 
 262         i = pci_enable_device(dev);
 263         if (i)
 264                 return i;
 265 
 266         /*
 267          * restore timing registers
 268          * (this may be unnecessary if BIOS also does it)
 269          */
 270         for (r = 0; r < 8; r++)
 271                 pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);
 272 
 273         return 0;
 274 }
 275 #endif
 276 
 277 static const struct ide_port_ops sc1200_port_ops = {
 278         .set_pio_mode           = sc1200_set_pio_mode,
 279         .set_dma_mode           = sc1200_set_dma_mode,
 280         .udma_filter            = sc1200_udma_filter,
 281 };
 282 
 283 static const struct ide_dma_ops sc1200_dma_ops = {
 284         .dma_host_set           = ide_dma_host_set,
 285         .dma_setup              = ide_dma_setup,
 286         .dma_start              = ide_dma_start,
 287         .dma_end                = sc1200_dma_end,
 288         .dma_test_irq           = ide_dma_test_irq,
 289         .dma_lost_irq           = ide_dma_lost_irq,
 290         .dma_timer_expiry       = ide_dma_sff_timer_expiry,
 291         .dma_sff_read_status    = ide_dma_sff_read_status,
 292 };
 293 
 294 static const struct ide_port_info sc1200_chipset = {
 295         .name           = DRV_NAME,
 296         .port_ops       = &sc1200_port_ops,
 297         .dma_ops        = &sc1200_dma_ops,
 298         .host_flags     = IDE_HFLAG_SERIALIZE |
 299                           IDE_HFLAG_POST_SET_MODE |
 300                           IDE_HFLAG_ABUSE_DMA_MODES,
 301         .pio_mask       = ATA_PIO4,
 302         .mwdma_mask     = ATA_MWDMA2,
 303         .udma_mask      = ATA_UDMA2,
 304 };
 305 
 306 static int sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 307 {
 308         struct sc1200_saved_state *ss = NULL;
 309         int rc;
 310 
 311 #ifdef CONFIG_PM
 312         ss = kmalloc(sizeof(*ss), GFP_KERNEL);
 313         if (ss == NULL)
 314                 return -ENOMEM;
 315 #endif
 316         rc = ide_pci_init_one(dev, &sc1200_chipset, ss);
 317         if (rc)
 318                 kfree(ss);
 319 
 320         return rc;
 321 }
 322 
 323 static const struct pci_device_id sc1200_pci_tbl[] = {
 324         { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
 325         { 0, },
 326 };
 327 MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
 328 
 329 static struct pci_driver sc1200_pci_driver = {
 330         .name           = "SC1200_IDE",
 331         .id_table       = sc1200_pci_tbl,
 332         .probe          = sc1200_init_one,
 333         .remove         = ide_pci_remove,
 334 #ifdef CONFIG_PM
 335         .suspend        = sc1200_suspend,
 336         .resume         = sc1200_resume,
 337 #endif
 338 };
 339 
 340 static int __init sc1200_ide_init(void)
 341 {
 342         return ide_pci_register_driver(&sc1200_pci_driver);
 343 }
 344 
 345 static void __exit sc1200_ide_exit(void)
 346 {
 347         pci_unregister_driver(&sc1200_pci_driver);
 348 }
 349 
 350 module_init(sc1200_ide_init);
 351 module_exit(sc1200_ide_exit);
 352 
 353 MODULE_AUTHOR("Mark Lord");
 354 MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
 355 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/ide/sc1200.c

DEFINITIONS
