This source file includes following definitions.
- pdc202xx_set_mode
- pdc202xx_set_pio_mode
- pdc202xx_test_irq
- pdc2026x_cable_detect
- pdc_old_enable_66MHz_clock
- pdc_old_disable_66MHz_clock
- pdc2026x_init_hwif
- pdc202xx_dma_start
- pdc202xx_dma_end
- init_chipset_pdc202xx
- pdc202ata4_fixup_irq
- pdc202xx_init_one
- pdc202xx_ide_init
- pdc202xx_ide_exit
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12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/delay.h>
16 #include <linux/blkdev.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ide.h>
20
21 #include <asm/io.h>
22
23 #define DRV_NAME "pdc202xx_old"
24
25 static void pdc202xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
26 {
27 struct pci_dev *dev = to_pci_dev(hwif->dev);
28 u8 drive_pci = 0x60 + (drive->dn << 2);
29 const u8 speed = drive->dma_mode;
30
31 u8 AP = 0, BP = 0, CP = 0;
32 u8 TA = 0, TB = 0, TC = 0;
33
34 pci_read_config_byte(dev, drive_pci, &AP);
35 pci_read_config_byte(dev, drive_pci + 1, &BP);
36 pci_read_config_byte(dev, drive_pci + 2, &CP);
37
38 switch(speed) {
39 case XFER_UDMA_5:
40 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
41 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
42 case XFER_UDMA_3:
43 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
44 case XFER_UDMA_0:
45 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
46 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
47 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
48 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
49 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
50 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
51 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
52 case XFER_PIO_0:
53 default: TA = 0x09; TB = 0x13; break;
54 }
55
56 if (speed < XFER_SW_DMA_0) {
57
58
59
60
61 AP &= ~0x3f;
62 if (ide_pio_need_iordy(drive, speed - XFER_PIO_0))
63 AP |= 0x20;
64 if (drive->media == ide_disk)
65 AP |= 0x10;
66
67 BP &= ~0x1f;
68 pci_write_config_byte(dev, drive_pci, AP | TA);
69 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
70 } else {
71
72 BP &= ~0xe0;
73
74 CP &= ~0x0f;
75 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
76 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
77 }
78 }
79
80 static void pdc202xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
81 {
82 drive->dma_mode = drive->pio_mode;
83 pdc202xx_set_mode(hwif, drive);
84 }
85
86 static int pdc202xx_test_irq(ide_hwif_t *hwif)
87 {
88 struct pci_dev *dev = to_pci_dev(hwif->dev);
89 unsigned long high_16 = pci_resource_start(dev, 4);
90 u8 sc1d = inb(high_16 + 0x1d);
91
92 if (hwif->channel) {
93
94
95
96
97 return (sc1d & 0x40) ? 1 : 0;
98 } else {
99
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101
102
103 return (sc1d & 0x04) ? 1 : 0;
104 }
105 }
106
107 static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
108 {
109 struct pci_dev *dev = to_pci_dev(hwif->dev);
110 u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
111
112 pci_read_config_word(dev, 0x50, &CIS);
113
114 return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
115 }
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125
126 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
127 {
128 unsigned long clock_reg = hwif->extra_base + 0x01;
129 u8 clock = inb(clock_reg);
130
131 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
132 }
133
134 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
135 {
136 unsigned long clock_reg = hwif->extra_base + 0x01;
137 u8 clock = inb(clock_reg);
138
139 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
140 }
141
142 static void pdc2026x_init_hwif(ide_hwif_t *hwif)
143 {
144 pdc_old_disable_66MHz_clock(hwif);
145 }
146
147 static void pdc202xx_dma_start(ide_drive_t *drive)
148 {
149 if (drive->current_speed > XFER_UDMA_2)
150 pdc_old_enable_66MHz_clock(drive->hwif);
151 if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
152 ide_hwif_t *hwif = drive->hwif;
153 struct request *rq = hwif->rq;
154 unsigned long high_16 = hwif->extra_base - 16;
155 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
156 u32 word_count = 0;
157 u8 clock = inb(high_16 + 0x11);
158
159 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
160 word_count = (blk_rq_sectors(rq) << 8);
161 word_count = (rq_data_dir(rq) == READ) ?
162 word_count | 0x05000000 :
163 word_count | 0x06000000;
164 outl(word_count, atapi_reg);
165 }
166 ide_dma_start(drive);
167 }
168
169 static int pdc202xx_dma_end(ide_drive_t *drive)
170 {
171 if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
172 ide_hwif_t *hwif = drive->hwif;
173 unsigned long high_16 = hwif->extra_base - 16;
174 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
175 u8 clock = 0;
176
177 outl(0, atapi_reg);
178 clock = inb(high_16 + 0x11);
179 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
180 }
181 if (drive->current_speed > XFER_UDMA_2)
182 pdc_old_disable_66MHz_clock(drive->hwif);
183 return ide_dma_end(drive);
184 }
185
186 static int init_chipset_pdc202xx(struct pci_dev *dev)
187 {
188 unsigned long dmabase = pci_resource_start(dev, 4);
189 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
190
191 if (dmabase == 0)
192 goto out;
193
194 udma_speed_flag = inb(dmabase | 0x1f);
195 primary_mode = inb(dmabase | 0x1a);
196 secondary_mode = inb(dmabase | 0x1b);
197 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
198 "Primary %s Mode " \
199 "Secondary %s Mode.\n", pci_name(dev),
200 (udma_speed_flag & 1) ? "EN" : "DIS",
201 (primary_mode & 1) ? "MASTER" : "PCI",
202 (secondary_mode & 1) ? "MASTER" : "PCI" );
203
204 if (!(udma_speed_flag & 1)) {
205 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
206 pci_name(dev), udma_speed_flag,
207 (udma_speed_flag|1));
208 outb(udma_speed_flag | 1, dmabase | 0x1f);
209 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
210 }
211 out:
212 return 0;
213 }
214
215 static void pdc202ata4_fixup_irq(struct pci_dev *dev, const char *name)
216 {
217 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
218 u8 irq = 0, irq2 = 0;
219 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
220
221 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
222 if (irq != irq2) {
223 pci_write_config_byte(dev,
224 (PCI_INTERRUPT_LINE)|0x80, irq);
225 printk(KERN_INFO "%s %s: PCI config space interrupt "
226 "mirror fixed\n", name, pci_name(dev));
227 }
228 }
229 }
230
231 #define IDE_HFLAGS_PDC202XX \
232 (IDE_HFLAG_ERROR_STOPS_FIFO | \
233 IDE_HFLAG_OFF_BOARD)
234
235 static const struct ide_port_ops pdc20246_port_ops = {
236 .set_pio_mode = pdc202xx_set_pio_mode,
237 .set_dma_mode = pdc202xx_set_mode,
238 .test_irq = pdc202xx_test_irq,
239 };
240
241 static const struct ide_port_ops pdc2026x_port_ops = {
242 .set_pio_mode = pdc202xx_set_pio_mode,
243 .set_dma_mode = pdc202xx_set_mode,
244 .test_irq = pdc202xx_test_irq,
245 .cable_detect = pdc2026x_cable_detect,
246 };
247
248 static const struct ide_dma_ops pdc2026x_dma_ops = {
249 .dma_host_set = ide_dma_host_set,
250 .dma_setup = ide_dma_setup,
251 .dma_start = pdc202xx_dma_start,
252 .dma_end = pdc202xx_dma_end,
253 .dma_test_irq = ide_dma_test_irq,
254 .dma_lost_irq = ide_dma_lost_irq,
255 .dma_timer_expiry = ide_dma_sff_timer_expiry,
256 .dma_sff_read_status = ide_dma_sff_read_status,
257 };
258
259 #define DECLARE_PDC2026X_DEV(udma, sectors) \
260 { \
261 .name = DRV_NAME, \
262 .init_chipset = init_chipset_pdc202xx, \
263 .init_hwif = pdc2026x_init_hwif, \
264 .port_ops = &pdc2026x_port_ops, \
265 .dma_ops = &pdc2026x_dma_ops, \
266 .host_flags = IDE_HFLAGS_PDC202XX, \
267 .pio_mask = ATA_PIO4, \
268 .mwdma_mask = ATA_MWDMA2, \
269 .udma_mask = udma, \
270 .max_sectors = sectors, \
271 }
272
273 static const struct ide_port_info pdc202xx_chipsets[] = {
274 {
275 .name = DRV_NAME,
276 .init_chipset = init_chipset_pdc202xx,
277 .port_ops = &pdc20246_port_ops,
278 .dma_ops = &sff_dma_ops,
279 .host_flags = IDE_HFLAGS_PDC202XX,
280 .pio_mask = ATA_PIO4,
281 .mwdma_mask = ATA_MWDMA2,
282 .udma_mask = ATA_UDMA2,
283 },
284
285
286 DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
287
288 DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
289 };
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299
300 static int pdc202xx_init_one(struct pci_dev *dev,
301 const struct pci_device_id *id)
302 {
303 const struct ide_port_info *d;
304 u8 idx = id->driver_data;
305
306 d = &pdc202xx_chipsets[idx];
307
308 if (idx < 2)
309 pdc202ata4_fixup_irq(dev, d->name);
310
311 if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
312 struct pci_dev *bridge = dev->bus->self;
313
314 if (bridge &&
315 bridge->vendor == PCI_VENDOR_ID_INTEL &&
316 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
317 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
318 printk(KERN_INFO DRV_NAME " %s: skipping Promise "
319 "PDC20265 attached to I2O RAID controller\n",
320 pci_name(dev));
321 return -ENODEV;
322 }
323 }
324
325 return ide_pci_init_one(dev, d, NULL);
326 }
327
328 static const struct pci_device_id pdc202xx_pci_tbl[] = {
329 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
330 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
331 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
332 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
333 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
334 { 0, },
335 };
336 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
337
338 static struct pci_driver pdc202xx_pci_driver = {
339 .name = "Promise_Old_IDE",
340 .id_table = pdc202xx_pci_tbl,
341 .probe = pdc202xx_init_one,
342 .remove = ide_pci_remove,
343 .suspend = ide_pci_suspend,
344 .resume = ide_pci_resume,
345 };
346
347 static int __init pdc202xx_ide_init(void)
348 {
349 return ide_pci_register_driver(&pdc202xx_pci_driver);
350 }
351
352 static void __exit pdc202xx_ide_exit(void)
353 {
354 pci_unregister_driver(&pdc202xx_pci_driver);
355 }
356
357 module_init(pdc202xx_ide_init);
358 module_exit(pdc202xx_ide_exit);
359
360 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Bartlomiej Zolnierkiewicz");
361 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
362 MODULE_LICENSE("GPL");