drivers/ide/ns87415.c

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This source file includes following definitions.
superio_ide_inb
superio_read_status
superio_dma_sff_read_status
superio_tf_read
superio_init_iops
ns87415_prepare_drive
ns87415_dev_select
ns87415_dma_start
ns87415_dma_end
init_hwif_ns87415
ns87415_init_one
ns87415_ide_init
ns87415_ide_exit
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 1997-1998      Mark Lord <mlord@pobox.com>
   4  * Copyright (C) 1998           Eddie C. Dost <ecd@skynet.be>
   5  * Copyright (C) 1999-2000      Andre Hedrick <andre@linux-ide.org>
   6  * Copyright (C) 2004           Grant Grundler <grundler at parisc-linux.org>
   7  *
   8  * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
   9  */
  10 
  11 #include <linux/module.h>
  12 #include <linux/types.h>
  13 #include <linux/kernel.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/pci.h>
  16 #include <linux/delay.h>
  17 #include <linux/ide.h>
  18 #include <linux/init.h>
  19 
  20 #include <asm/io.h>
  21 
  22 #define DRV_NAME "ns87415"
  23 
  24 #ifdef CONFIG_SUPERIO
  25 /* SUPERIO 87560 is a PoS chip that NatSem denies exists.
  26  * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
  27  * which use the integrated NS87514 cell for CD-ROM support.
  28  * i.e we have to support for CD-ROM installs.
  29  * See drivers/parisc/superio.c for more gory details.
  30  */
  31 #include <asm/superio.h>
  32 
  33 #define SUPERIO_IDE_MAX_RETRIES 25
  34 
  35 /* Because of a defect in Super I/O, all reads of the PCI DMA status 
  36  * registers, IDE status register and the IDE select register need to be 
  37  * retried
  38  */
  39 static u8 superio_ide_inb (unsigned long port)
  40 {
  41         u8 tmp;
  42         int retries = SUPERIO_IDE_MAX_RETRIES;
  43 
  44         /* printk(" [ reading port 0x%x with retry ] ", port); */
  45 
  46         do {
  47                 tmp = inb(port);
  48                 if (tmp == 0)
  49                         udelay(50);
  50         } while (tmp == 0 && retries-- > 0);
  51 
  52         return tmp;
  53 }
  54 
  55 static u8 superio_read_status(ide_hwif_t *hwif)
  56 {
  57         return superio_ide_inb(hwif->io_ports.status_addr);
  58 }
  59 
  60 static u8 superio_dma_sff_read_status(ide_hwif_t *hwif)
  61 {
  62         return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
  63 }
  64 
  65 static void superio_tf_read(ide_drive_t *drive, struct ide_taskfile *tf,
  66                             u8 valid)
  67 {
  68         struct ide_io_ports *io_ports = &drive->hwif->io_ports;
  69 
  70         if (valid & IDE_VALID_ERROR)
  71                 tf->error  = inb(io_ports->feature_addr);
  72         if (valid & IDE_VALID_NSECT)
  73                 tf->nsect  = inb(io_ports->nsect_addr);
  74         if (valid & IDE_VALID_LBAL)
  75                 tf->lbal   = inb(io_ports->lbal_addr);
  76         if (valid & IDE_VALID_LBAM)
  77                 tf->lbam   = inb(io_ports->lbam_addr);
  78         if (valid & IDE_VALID_LBAH)
  79                 tf->lbah   = inb(io_ports->lbah_addr);
  80         if (valid & IDE_VALID_DEVICE)
  81                 tf->device = superio_ide_inb(io_ports->device_addr);
  82 }
  83 
  84 static void ns87415_dev_select(ide_drive_t *drive);
  85 
  86 static const struct ide_tp_ops superio_tp_ops = {
  87         .exec_command           = ide_exec_command,
  88         .read_status            = superio_read_status,
  89         .read_altstatus         = ide_read_altstatus,
  90         .write_devctl           = ide_write_devctl,
  91 
  92         .dev_select             = ns87415_dev_select,
  93         .tf_load                = ide_tf_load,
  94         .tf_read                = superio_tf_read,
  95 
  96         .input_data             = ide_input_data,
  97         .output_data            = ide_output_data,
  98 };
  99 
 100 static void superio_init_iops(struct hwif_s *hwif)
 101 {
 102         struct pci_dev *pdev = to_pci_dev(hwif->dev);
 103         u32 dma_stat;
 104         u8 port = hwif->channel, tmp;
 105 
 106         dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);
 107 
 108         /* Clear error/interrupt, enable dma */
 109         tmp = superio_ide_inb(dma_stat);
 110         outb(tmp | 0x66, dma_stat);
 111 }
 112 #else
 113 #define superio_dma_sff_read_status ide_dma_sff_read_status
 114 #endif
 115 
 116 static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
 117 
 118 /*
 119  * This routine either enables/disables (according to IDE_DFLAG_PRESENT)
 120  * the IRQ associated with the port,
 121  * and selects either PIO or DMA handshaking for the next I/O operation.
 122  */
 123 static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
 124 {
 125         ide_hwif_t *hwif = drive->hwif;
 126         struct pci_dev *dev = to_pci_dev(hwif->dev);
 127         unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
 128         unsigned long flags;
 129 
 130         local_irq_save(flags);
 131         new = *old;
 132 
 133         /* Adjust IRQ enable bit */
 134         bit = 1 << (8 + hwif->channel);
 135 
 136         if (drive->dev_flags & IDE_DFLAG_PRESENT)
 137                 new &= ~bit;
 138         else
 139                 new |= bit;
 140 
 141         /* Select PIO or DMA, DMA may only be selected for one drive/channel. */
 142         bit   = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
 143         other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
 144         new = use_dma ? ((new & ~other) | bit) : (new & ~bit);
 145 
 146         if (new != *old) {
 147                 unsigned char stat;
 148 
 149                 /*
 150                  * Don't change DMA engine settings while Write Buffers
 151                  * are busy.
 152                  */
 153                 (void) pci_read_config_byte(dev, 0x43, &stat);
 154                 while (stat & 0x03) {
 155                         udelay(1);
 156                         (void) pci_read_config_byte(dev, 0x43, &stat);
 157                 }
 158 
 159                 *old = new;
 160                 (void) pci_write_config_dword(dev, 0x40, new);
 161 
 162                 /*
 163                  * And let things settle...
 164                  */
 165                 udelay(10);
 166         }
 167 
 168         local_irq_restore(flags);
 169 }
 170 
 171 static void ns87415_dev_select(ide_drive_t *drive)
 172 {
 173         ns87415_prepare_drive(drive,
 174                               !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
 175 
 176         outb(drive->select | ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr);
 177 }
 178 
 179 static void ns87415_dma_start(ide_drive_t *drive)
 180 {
 181         ns87415_prepare_drive(drive, 1);
 182         ide_dma_start(drive);
 183 }
 184 
 185 static int ns87415_dma_end(ide_drive_t *drive)
 186 {
 187         ide_hwif_t *hwif = drive->hwif;
 188         u8 dma_stat = 0, dma_cmd = 0;
 189 
 190         dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
 191         /* get DMA command mode */
 192         dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
 193         /* stop DMA */
 194         outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
 195         /* from ERRATA: clear the INTR & ERROR bits */
 196         dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
 197         outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
 198 
 199         ns87415_prepare_drive(drive, 0);
 200 
 201         /* verify good DMA status */
 202         return (dma_stat & 7) != 4;
 203 }
 204 
 205 static void init_hwif_ns87415 (ide_hwif_t *hwif)
 206 {
 207         struct pci_dev *dev = to_pci_dev(hwif->dev);
 208         unsigned int ctrl, using_inta;
 209         u8 progif;
 210 #ifdef __sparc_v9__
 211         int timeout;
 212         u8 stat;
 213 #endif
 214 
 215         /*
 216          * We cannot probe for IRQ: both ports share common IRQ on INTA.
 217          * Also, leave IRQ masked during drive probing, to prevent infinite
 218          * interrupts from a potentially floating INTA..
 219          *
 220          * IRQs get unmasked in dev_select() when drive is first used.
 221          */
 222         (void) pci_read_config_dword(dev, 0x40, &ctrl);
 223         (void) pci_read_config_byte(dev, 0x09, &progif);
 224         /* is irq in "native" mode? */
 225         using_inta = progif & (1 << (hwif->channel << 1));
 226         if (!using_inta)
 227                 using_inta = ctrl & (1 << (4 + hwif->channel));
 228         if (hwif->mate) {
 229                 hwif->select_data = hwif->mate->select_data;
 230         } else {
 231                 hwif->select_data = (unsigned long)
 232                                         &ns87415_control[ns87415_count++];
 233                 ctrl |= (1 << 8) | (1 << 9);    /* mask both IRQs */
 234                 if (using_inta)
 235                         ctrl &= ~(1 << 6);      /* unmask INTA */
 236                 *((unsigned int *)hwif->select_data) = ctrl;
 237                 (void) pci_write_config_dword(dev, 0x40, ctrl);
 238 
 239                 /*
 240                  * Set prefetch size to 512 bytes for both ports,
 241                  * but don't turn on/off prefetching here.
 242                  */
 243                 pci_write_config_byte(dev, 0x55, 0xee);
 244 
 245 #ifdef __sparc_v9__
 246                 /*
 247                  * XXX: Reset the device, if we don't it will not respond to
 248                  *      dev_select() properly during first ide_probe_port().
 249                  */
 250                 timeout = 10000;
 251                 outb(12, hwif->io_ports.ctl_addr);
 252                 udelay(10);
 253                 outb(8, hwif->io_ports.ctl_addr);
 254                 do {
 255                         udelay(50);
 256                         stat = hwif->tp_ops->read_status(hwif);
 257                         if (stat == 0xff)
 258                                 break;
 259                 } while ((stat & ATA_BUSY) && --timeout);
 260 #endif
 261         }
 262 
 263         if (!using_inta)
 264                 hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
 265 
 266         if (!hwif->dma_base)
 267                 return;
 268 
 269         outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
 270 }
 271 
 272 static const struct ide_tp_ops ns87415_tp_ops = {
 273         .exec_command           = ide_exec_command,
 274         .read_status            = ide_read_status,
 275         .read_altstatus         = ide_read_altstatus,
 276         .write_devctl           = ide_write_devctl,
 277 
 278         .dev_select             = ns87415_dev_select,
 279         .tf_load                = ide_tf_load,
 280         .tf_read                = ide_tf_read,
 281 
 282         .input_data             = ide_input_data,
 283         .output_data            = ide_output_data,
 284 };
 285 
 286 static const struct ide_dma_ops ns87415_dma_ops = {
 287         .dma_host_set           = ide_dma_host_set,
 288         .dma_setup              = ide_dma_setup,
 289         .dma_start              = ns87415_dma_start,
 290         .dma_end                = ns87415_dma_end,
 291         .dma_test_irq           = ide_dma_test_irq,
 292         .dma_lost_irq           = ide_dma_lost_irq,
 293         .dma_timer_expiry       = ide_dma_sff_timer_expiry,
 294         .dma_sff_read_status    = superio_dma_sff_read_status,
 295 };
 296 
 297 static const struct ide_port_info ns87415_chipset = {
 298         .name           = DRV_NAME,
 299         .init_hwif      = init_hwif_ns87415,
 300         .tp_ops         = &ns87415_tp_ops,
 301         .dma_ops        = &ns87415_dma_ops,
 302         .host_flags     = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
 303                           IDE_HFLAG_NO_ATAPI_DMA,
 304 };
 305 
 306 static int ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 307 {
 308         struct ide_port_info d = ns87415_chipset;
 309 
 310 #ifdef CONFIG_SUPERIO
 311         if (PCI_SLOT(dev->devfn) == 0xE) {
 312                 /* Built-in - assume it's under superio. */
 313                 d.init_iops = superio_init_iops;
 314                 d.tp_ops = &superio_tp_ops;
 315         }
 316 #endif
 317         return ide_pci_init_one(dev, &d, NULL);
 318 }
 319 
 320 static const struct pci_device_id ns87415_pci_tbl[] = {
 321         { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
 322         { 0, },
 323 };
 324 MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
 325 
 326 static struct pci_driver ns87415_pci_driver = {
 327         .name           = "NS87415_IDE",
 328         .id_table       = ns87415_pci_tbl,
 329         .probe          = ns87415_init_one,
 330         .remove         = ide_pci_remove,
 331         .suspend        = ide_pci_suspend,
 332         .resume         = ide_pci_resume,
 333 };
 334 
 335 static int __init ns87415_ide_init(void)
 336 {
 337         return ide_pci_register_driver(&ns87415_pci_driver);
 338 }
 339 
 340 static void __exit ns87415_ide_exit(void)
 341 {
 342         pci_unregister_driver(&ns87415_pci_driver);
 343 }
 344 
 345 module_init(ns87415_ide_init);
 346 module_exit(ns87415_ide_exit);
 347 
 348 MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
 349 MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
 350 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/ide/ns87415.c

DEFINITIONS
