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7 #ifndef __RTW_RF_H_
8 #define __RTW_RF_H_
9
10
11 #define OFDM_PHY 1
12 #define MIXED_PHY 2
13 #define CCK_PHY 3
14
15 #define NumRates 13
16
17
18 #define SHORT_SLOT_TIME 9
19 #define NON_SHORT_SLOT_TIME 20
20
21 #define RTL8711_RF_MAX_SENS 6
22 #define RTL8711_RF_DEF_SENS 4
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30
31 #define MAX_CHANNEL_NUM_2G 14
32 #define MAX_CHANNEL_NUM_5G 24
33 #define MAX_CHANNEL_NUM 38
34
35 #define NUM_REGULATORYS 1
36
37
38 #define USA 0x555320
39 #define EUROPE 0x1
40 #define JAPAN 0x2
41
42 struct regulatory_class {
43 u32 starting_freq;
44 u8 channel_set[MAX_CHANNEL_NUM];
45 u8 channel_cck_power[MAX_CHANNEL_NUM];
46 u8 channel_ofdm_power[MAX_CHANNEL_NUM];
47 u8 txpower_limit;
48 u8 channel_spacing;
49 u8 modem;
50 };
51
52 enum CAPABILITY {
53 cESS = 0x0001,
54 cIBSS = 0x0002,
55 cPollable = 0x0004,
56 cPollReq = 0x0008,
57 cPrivacy = 0x0010,
58 cShortPreamble = 0x0020,
59 cPBCC = 0x0040,
60 cChannelAgility = 0x0080,
61 cSpectrumMgnt = 0x0100,
62 cQos = 0x0200,
63 cShortSlotTime = 0x0400,
64 cAPSD = 0x0800,
65 cRM = 0x1000,
66 cDSSS_OFDM = 0x2000,
67 cDelayedBA = 0x4000,
68 cImmediateBA = 0x8000,
69 };
70
71 enum _REG_PREAMBLE_MODE {
72 PREAMBLE_LONG = 1,
73 PREAMBLE_AUTO = 2,
74 PREAMBLE_SHORT = 3,
75 };
76
77 enum _RTL8712_RF_MIMO_CONFIG_ {
78 RTL8712_RFCONFIG_1T = 0x10,
79 RTL8712_RFCONFIG_2T = 0x20,
80 RTL8712_RFCONFIG_1R = 0x01,
81 RTL8712_RFCONFIG_2R = 0x02,
82 RTL8712_RFCONFIG_1T1R = 0x11,
83 RTL8712_RFCONFIG_1T2R = 0x12,
84 RTL8712_RFCONFIG_TURBO = 0x92,
85 RTL8712_RFCONFIG_2T2R = 0x22
86 };
87
88 enum RF90_RADIO_PATH {
89 RF90_PATH_A = 0,
90 RF90_PATH_B = 1,
91 RF90_PATH_C = 2,
92 RF90_PATH_D = 3
93 };
94
95
96 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
97 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
98 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
99
100
101 enum CHANNEL_WIDTH {
102 CHANNEL_WIDTH_20 = 0,
103 CHANNEL_WIDTH_40 = 1,
104 CHANNEL_WIDTH_80 = 2,
105 CHANNEL_WIDTH_160 = 3,
106 CHANNEL_WIDTH_80_80 = 4,
107 CHANNEL_WIDTH_MAX = 5,
108 };
109
110
111
112 enum EXTCHNL_OFFSET {
113 EXTCHNL_OFFSET_NO_EXT = 0,
114 EXTCHNL_OFFSET_UPPER = 1,
115 EXTCHNL_OFFSET_NO_DEF = 2,
116 EXTCHNL_OFFSET_LOWER = 3,
117 };
118
119 enum VHT_DATA_SC {
120 VHT_DATA_SC_DONOT_CARE = 0,
121 VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
122 VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
123 VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
124 VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
125 VHT_DATA_SC_20_RECV1 = 5,
126 VHT_DATA_SC_20_RECV2 = 6,
127 VHT_DATA_SC_20_RECV3 = 7,
128 VHT_DATA_SC_20_RECV4 = 8,
129 VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
130 VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
131 };
132
133 enum PROTECTION_MODE {
134 PROTECTION_MODE_AUTO = 0,
135 PROTECTION_MODE_FORCE_ENABLE = 1,
136 PROTECTION_MODE_FORCE_DISABLE = 2,
137 };
138
139
140 enum RT_RF_TYPE_DEFINITION {
141 RF_1T2R = 0,
142 RF_2T4R = 1,
143 RF_2T2R = 2,
144 RF_1T1R = 3,
145 RF_2T2R_GREEN = 4,
146 RF_MAX_TYPE = 5,
147 };
148
149 u32 rtw_ch2freq(u32 ch);
150
151 #endif