root/drivers/staging/rtl8723bs/include/hal_com_reg.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7 #ifndef __HAL_COMMON_REG_H__
   8 #define __HAL_COMMON_REG_H__
   9 
  10 
  11 #define MAC_ADDR_LEN                            6
  12 
  13 #define HAL_NAV_UPPER_UNIT              128             /*  micro-second */
  14 
  15 /*  8188E PKT_BUFF_ACCESS_CTRL value */
  16 #define TXPKT_BUF_SELECT                                0x69
  17 #define RXPKT_BUF_SELECT                                0xA5
  18 #define DISABLE_TRXPKT_BUF_ACCESS               0x0
  19 
  20 /*  */
  21 /*  */
  22 /*  */
  23 
  24 /*  */
  25 /*  */
  26 /*      0x0000h ~ 0x00FFh       System Configuration */
  27 /*  */
  28 /*  */
  29 #define REG_SYS_ISO_CTRL                                0x0000
  30 #define REG_SYS_FUNC_EN                         0x0002
  31 #define REG_APS_FSMCO                                   0x0004
  32 #define REG_SYS_CLKR                                    0x0008
  33 #define REG_9346CR                                              0x000A
  34 #define REG_SYS_EEPROM_CTRL                     0x000A
  35 #define REG_EE_VPD                                              0x000C
  36 #define REG_AFE_MISC                                    0x0010
  37 #define REG_SPS0_CTRL                                   0x0011
  38 #define REG_SPS0_CTRL_6                                 0x0016
  39 #define REG_POWER_OFF_IN_PROCESS                0x0017
  40 #define REG_SPS_OCP_CFG                         0x0018
  41 #define REG_RSV_CTRL                                    0x001C
  42 #define REG_RF_CTRL                                             0x001F
  43 #define REG_LDOA15_CTRL                         0x0020
  44 #define REG_LDOV12D_CTRL                                0x0021
  45 #define REG_LDOHCI12_CTRL                               0x0022
  46 #define REG_LPLDO_CTRL                                  0x0023
  47 #define REG_AFE_XTAL_CTRL                               0x0024
  48 #define REG_AFE_LDO_CTRL                                0x0027 /*  1.5v for 8188EE test chip, 1.4v for MP chip */
  49 #define REG_AFE_PLL_CTRL                                0x0028
  50 #define REG_MAC_PHY_CTRL                                0x002c /* for 92d, DMDP, SMSP, DMSP contrl */
  51 #define REG_APE_PLL_CTRL_EXT                    0x002c
  52 #define REG_EFUSE_CTRL                                  0x0030
  53 #define REG_EFUSE_TEST                                  0x0034
  54 #define REG_PWR_DATA                                    0x0038
  55 #define REG_CAL_TIMER                                   0x003C
  56 #define REG_ACLK_MON                                    0x003E
  57 #define REG_GPIO_MUXCFG                         0x0040
  58 #define REG_GPIO_IO_SEL                                 0x0042
  59 #define REG_MAC_PINMUX_CFG                      0x0043
  60 #define REG_GPIO_PIN_CTRL                               0x0044
  61 #define REG_GPIO_INTM                                   0x0048
  62 #define REG_LEDCFG0                                             0x004C
  63 #define REG_LEDCFG1                                             0x004D
  64 #define REG_LEDCFG2                                             0x004E
  65 #define REG_LEDCFG3                                             0x004F
  66 #define REG_FSIMR                                               0x0050
  67 #define REG_FSISR                                               0x0054
  68 #define REG_HSIMR                                               0x0058
  69 #define REG_HSISR                                               0x005c
  70 #define REG_GPIO_PIN_CTRL_2                     0x0060 /*  RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
  71 #define REG_GPIO_IO_SEL_2                               0x0062 /*  RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
  72 #define REG_MULTI_FUNC_CTRL                     0x0068 /*  RTL8723 WIFI/BT/GPS Multi-Function control source. */
  73 #define REG_GSSR                                                0x006c
  74 #define REG_AFE_XTAL_CTRL_EXT                   0x0078 /* RTL8188E */
  75 #define REG_XCK_OUT_CTRL                                0x007c /* RTL8188E */
  76 #define REG_MCUFWDL                                     0x0080
  77 #define REG_WOL_EVENT                                   0x0081 /* RTL8188E */
  78 #define REG_MCUTSTCFG                                   0x0084
  79 #define REG_FDHM0                                               0x0088
  80 #define REG_HOST_SUSP_CNT                               0x00BC  /*  RTL8192C Host suspend counter on FPGA platform */
  81 #define REG_SYSTEM_ON_CTRL                      0x00CC  /*  For 8723AE Reset after S3 */
  82 #define REG_EFUSE_ACCESS                                0x00CF  /*  Efuse access protection for RTL8723 */
  83 #define REG_BIST_SCAN                                   0x00D0
  84 #define REG_BIST_RPT                                    0x00D4
  85 #define REG_BIST_ROM_RPT                                0x00D8
  86 #define REG_USB_SIE_INTF                                0x00E0
  87 #define REG_PCIE_MIO_INTF                               0x00E4
  88 #define REG_PCIE_MIO_INTD                               0x00E8
  89 #define REG_HPON_FSM                                    0x00EC
  90 #define REG_SYS_CFG                                             0x00F0
  91 #define REG_GPIO_OUTSTS                         0x00F4  /*  For RTL8723 only. */
  92 #define REG_TYPE_ID                                             0x00FC
  93 
  94 /*  */
  95 /*  2010/12/29 MH Add for 92D */
  96 /*  */
  97 #define REG_MAC_PHY_CTRL_NORMAL         0x00f8
  98 
  99 
 100 /*  */
 101 /*  */
 102 /*      0x0100h ~ 0x01FFh       MACTOP General Configuration */
 103 /*  */
 104 /*  */
 105 #define REG_CR                                                  0x0100
 106 #define REG_PBP                                                 0x0104
 107 #define REG_PKT_BUFF_ACCESS_CTRL                0x0106
 108 #define REG_TRXDMA_CTRL                         0x010C
 109 #define REG_TRXFF_BNDY                                  0x0114
 110 #define REG_TRXFF_STATUS                                0x0118
 111 #define REG_RXFF_PTR                                    0x011C
 112 #define REG_HIMR                                                0x0120
 113 #define REG_HISR                                                0x0124
 114 #define REG_HIMRE                                               0x0128
 115 #define REG_HISRE                                               0x012C
 116 #define REG_CPWM                                                0x012F
 117 #define REG_FWIMR                                               0x0130
 118 #define REG_FWISR                                               0x0134
 119 #define REG_FTIMR                                               0x0138
 120 #define REG_FTISR                                               0x013C /* RTL8192C */
 121 #define REG_PKTBUF_DBG_CTRL                     0x0140
 122 #define REG_RXPKTBUF_CTRL                               (REG_PKTBUF_DBG_CTRL+2)
 123 #define REG_PKTBUF_DBG_DATA_L                   0x0144
 124 #define REG_PKTBUF_DBG_DATA_H           0x0148
 125 
 126 #define REG_TC0_CTRL                                    0x0150
 127 #define REG_TC1_CTRL                                    0x0154
 128 #define REG_TC2_CTRL                                    0x0158
 129 #define REG_TC3_CTRL                                    0x015C
 130 #define REG_TC4_CTRL                                    0x0160
 131 #define REG_TCUNIT_BASE                         0x0164
 132 #define REG_MBIST_START                         0x0174
 133 #define REG_MBIST_DONE                                  0x0178
 134 #define REG_MBIST_FAIL                                  0x017C
 135 #define REG_32K_CTRL                                    0x0194 /* RTL8188E */
 136 #define REG_C2HEVT_MSG_NORMAL           0x01A0
 137 #define REG_C2HEVT_CLEAR                                0x01AF
 138 #define REG_MCUTST_1                                    0x01c0
 139 #define REG_MCUTST_WOWLAN                       0x01C7  /*  Defined after 8188E series. */
 140 #define REG_FMETHR                                              0x01C8
 141 #define REG_HMETFR                                              0x01CC
 142 #define REG_HMEBOX_0                                    0x01D0
 143 #define REG_HMEBOX_1                                    0x01D4
 144 #define REG_HMEBOX_2                                    0x01D8
 145 #define REG_HMEBOX_3                                    0x01DC
 146 #define REG_LLT_INIT                                    0x01E0
 147 
 148 
 149 /*  */
 150 /*  */
 151 /*      0x0200h ~ 0x027Fh       TXDMA Configuration */
 152 /*  */
 153 /*  */
 154 #define REG_RQPN                                                0x0200
 155 #define REG_FIFOPAGE                                    0x0204
 156 #define REG_TDECTRL                                             0x0208
 157 #define REG_TXDMA_OFFSET_CHK                    0x020C
 158 #define REG_TXDMA_STATUS                                0x0210
 159 #define REG_RQPN_NPQ                                    0x0214
 160 #define REG_AUTO_LLT                                    0x0224
 161 
 162 
 163 /*  */
 164 /*  */
 165 /*      0x0280h ~ 0x02FFh       RXDMA Configuration */
 166 /*  */
 167 /*  */
 168 #define REG_RXDMA_AGG_PG_TH                     0x0280
 169 #define REG_RXPKT_NUM                                   0x0284
 170 #define REG_RXDMA_STATUS                                0x0288
 171 
 172 /*  */
 173 /*  */
 174 /*      0x0300h ~ 0x03FFh       PCIe */
 175 /*  */
 176 /*  */
 177 #define REG_PCIE_CTRL_REG                               0x0300
 178 #define REG_INT_MIG                                             0x0304  /*  Interrupt Migration */
 179 #define REG_BCNQ_DESA                                   0x0308  /*  TX Beacon Descriptor Address */
 180 #define REG_HQ_DESA                                     0x0310  /*  TX High Queue Descriptor Address */
 181 #define REG_MGQ_DESA                                    0x0318  /*  TX Manage Queue Descriptor Address */
 182 #define REG_VOQ_DESA                                    0x0320  /*  TX VO Queue Descriptor Address */
 183 #define REG_VIQ_DESA                                    0x0328  /*  TX VI Queue Descriptor Address */
 184 #define REG_BEQ_DESA                                    0x0330  /*  TX BE Queue Descriptor Address */
 185 #define REG_BKQ_DESA                                    0x0338  /*  TX BK Queue Descriptor Address */
 186 #define REG_RX_DESA                                             0x0340  /*  RX Queue    Descriptor Address */
 187 /* sherry added for DBI Read/Write  20091126 */
 188 #define REG_DBI_WDATA                                   0x0348  /*  Backdoor REG for Access Configuration */
 189 #define REG_DBI_RDATA                           0x034C  /* Backdoor REG for Access Configuration */
 190 #define REG_DBI_CTRL                                    0x0350  /* Backdoor REG for Access Configuration */
 191 #define REG_DBI_FLAG                                    0x0352  /* Backdoor REG for Access Configuration */
 192 #define REG_MDIO                                                0x0354  /*  MDIO for Access PCIE PHY */
 193 #define REG_DBG_SEL                                             0x0360  /*  Debug Selection Register */
 194 #define REG_PCIE_HRPWM                                  0x0361  /* PCIe RPWM */
 195 #define REG_PCIE_HCPWM                                  0x0363  /* PCIe CPWM */
 196 #define REG_WATCH_DOG                                   0x0368
 197 
 198 /*  RTL8723 series ------------------------------- */
 199 #define REG_PCIE_HISR_EN                                0x0394  /* PCIE Local Interrupt Enable Register */
 200 #define REG_PCIE_HISR                                   0x03A0
 201 #define REG_PCIE_HISRE                                  0x03A4
 202 #define REG_PCIE_HIMR                                   0x03A8
 203 #define REG_PCIE_HIMRE                                  0x03AC
 204 
 205 #define REG_USB_HIMR                                    0xFE38
 206 #define REG_USB_HIMRE                                   0xFE3C
 207 #define REG_USB_HISR                                    0xFE78
 208 #define REG_USB_HISRE                                   0xFE7C
 209 
 210 
 211 /*  */
 212 /*  */
 213 /*      0x0400h ~ 0x047Fh       Protocol Configuration */
 214 /*  */
 215 /*  */
 216 #define REG_VOQ_INFORMATION                     0x0400
 217 #define REG_VIQ_INFORMATION                     0x0404
 218 #define REG_BEQ_INFORMATION                     0x0408
 219 #define REG_BKQ_INFORMATION                     0x040C
 220 #define REG_MGQ_INFORMATION                     0x0410
 221 #define REG_HGQ_INFORMATION                     0x0414
 222 #define REG_BCNQ_INFORMATION                    0x0418
 223 #define REG_TXPKT_EMPTY                         0x041A
 224 #define REG_CPU_MGQ_INFORMATION         0x041C
 225 #define REG_FWHW_TXQ_CTRL                               0x0420
 226 #define REG_HWSEQ_CTRL                                  0x0423
 227 #define REG_BCNQ_BDNY                                   0x0424
 228 #define REG_MGQ_BDNY                                    0x0425
 229 #define REG_LIFETIME_CTRL                               0x0426
 230 #define REG_MULTI_BCNQ_OFFSET                   0x0427
 231 #define REG_SPEC_SIFS                                   0x0428
 232 #define REG_RL                                                  0x042A
 233 #define REG_DARFRC                                              0x0430
 234 #define REG_RARFRC                                              0x0438
 235 #define REG_RRSR                                                0x0440
 236 #define REG_ARFR0                                               0x0444
 237 #define REG_ARFR1                                               0x0448
 238 #define REG_ARFR2                                               0x044C
 239 #define REG_ARFR3                                               0x0450
 240 #define REG_BCNQ1_BDNY                                  0x0457
 241 
 242 #define REG_AGGLEN_LMT                                  0x0458
 243 #define REG_AMPDU_MIN_SPACE                     0x045C
 244 #define REG_WMAC_LBK_BF_HD                      0x045D
 245 #define REG_FAST_EDCA_CTRL                              0x0460
 246 #define REG_RD_RESP_PKT_TH                              0x0463
 247 
 248 #define REG_INIRTS_RATE_SEL                             0x0480
 249 #define REG_INIDATA_RATE_SEL                    0x0484
 250 
 251 #define REG_POWER_STAGE1                                0x04B4
 252 #define REG_POWER_STAGE2                                0x04B8
 253 #define REG_PKT_VO_VI_LIFE_TIME         0x04C0
 254 #define REG_PKT_BE_BK_LIFE_TIME         0x04C2
 255 #define REG_STBC_SETTING                                0x04C4
 256 #define REG_QUEUE_CTRL                                  0x04C6
 257 #define REG_SINGLE_AMPDU_CTRL                   0x04c7
 258 #define REG_PROT_MODE_CTRL                      0x04C8
 259 #define REG_MAX_AGGR_NUM                                0x04CA
 260 #define REG_RTS_MAX_AGGR_NUM                    0x04CB
 261 #define REG_BAR_MODE_CTRL                               0x04CC
 262 #define REG_RA_TRY_RATE_AGG_LMT         0x04CF
 263 #define REG_EARLY_MODE_CONTROL          0x04D0
 264 #define REG_MACID_SLEEP                         0x04D4
 265 #define REG_NQOS_SEQ                                    0x04DC
 266 #define REG_QOS_SEQ                                     0x04DE
 267 #define REG_NEED_CPU_HANDLE                     0x04E0
 268 #define REG_PKT_LOSE_RPT                                0x04E1
 269 #define REG_PTCL_ERR_STATUS                     0x04E2
 270 #define REG_TX_RPT_CTRL                                 0x04EC
 271 #define REG_TX_RPT_TIME                                 0x04F0  /*  2 byte */
 272 #define REG_DUMMY                                               0x04FC
 273 
 274 /*  */
 275 /*  */
 276 /*      0x0500h ~ 0x05FFh       EDCA Configuration */
 277 /*  */
 278 /*  */
 279 #define REG_EDCA_VO_PARAM                               0x0500
 280 #define REG_EDCA_VI_PARAM                               0x0504
 281 #define REG_EDCA_BE_PARAM                               0x0508
 282 #define REG_EDCA_BK_PARAM                               0x050C
 283 #define REG_BCNTCFG                                             0x0510
 284 #define REG_PIFS                                                        0x0512
 285 #define REG_RDG_PIFS                                    0x0513
 286 #define REG_SIFS_CTX                                    0x0514
 287 #define REG_SIFS_TRX                                    0x0516
 288 #define REG_TSFTR_SYN_OFFSET                    0x0518
 289 #define REG_AGGR_BREAK_TIME                     0x051A
 290 #define REG_SLOT                                                0x051B
 291 #define REG_TX_PTCL_CTRL                                0x0520
 292 #define REG_TXPAUSE                                             0x0522
 293 #define REG_DIS_TXREQ_CLR                               0x0523
 294 #define REG_RD_CTRL                                             0x0524
 295 /*  */
 296 /*  Format for offset 540h-542h: */
 297 /*      [3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. */
 298 /*      [7:4]:   Reserved. */
 299 /*      [19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. */
 300 /*      [23:20]: Reserved */
 301 /*  Description: */
 302 /*                    | */
 303 /*      |<--Setup--|--Hold------------>| */
 304 /*      --------------|---------------------- */
 305 /*                 | */
 306 /*                TBTT */
 307 /*  Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. */
 308 /*  Described by Designer Tim and Bruce, 2011-01-14. */
 309 /*  */
 310 #define REG_TBTT_PROHIBIT                               0x0540
 311 #define REG_RD_NAV_NXT                                  0x0544
 312 #define REG_NAV_PROT_LEN                                0x0546
 313 #define REG_BCN_CTRL                                    0x0550
 314 #define REG_BCN_CTRL_1                                  0x0551
 315 #define REG_MBID_NUM                                    0x0552
 316 #define REG_DUAL_TSF_RST                                0x0553
 317 #define REG_BCN_INTERVAL                                0x0554  /*  The same as REG_MBSSID_BCN_SPACE */
 318 #define REG_DRVERLYINT                                  0x0558
 319 #define REG_BCNDMATIM                                   0x0559
 320 #define REG_ATIMWND                                     0x055A
 321 #define REG_USTIME_TSF                                  0x055C
 322 #define REG_BCN_MAX_ERR                         0x055D
 323 #define REG_RXTSF_OFFSET_CCK                    0x055E
 324 #define REG_RXTSF_OFFSET_OFDM                   0x055F
 325 #define REG_TSFTR                                               0x0560
 326 #define REG_TSFTR1                                              0x0568  /*  HW Port 1 TSF Register */
 327 #define REG_ATIMWND_1                                   0x0570
 328 #define REG_P2P_CTWIN                                   0x0572 /*  1 Byte long (in unit of TU) */
 329 #define REG_PSTIMER                                             0x0580
 330 #define REG_TIMER0                                              0x0584
 331 #define REG_TIMER1                                              0x0588
 332 #define REG_ACMHWCTRL                                   0x05C0
 333 #define REG_NOA_DESC_SEL                                0x05CF
 334 #define REG_NOA_DESC_DURATION           0x05E0
 335 #define REG_NOA_DESC_INTERVAL                   0x05E4
 336 #define REG_NOA_DESC_START                      0x05E8
 337 #define REG_NOA_DESC_COUNT                      0x05EC
 338 
 339 #define REG_DMC                                                 0x05F0  /* Dual MAC Co-Existence Register */
 340 #define REG_SCH_TX_CMD                                  0x05F8
 341 
 342 #define REG_FW_RESET_TSF_CNT_1          0x05FC
 343 #define REG_FW_RESET_TSF_CNT_0          0x05FD
 344 #define REG_FW_BCN_DIS_CNT                      0x05FE
 345 
 346 /*  */
 347 /*  */
 348 /*      0x0600h ~ 0x07FFh       WMAC Configuration */
 349 /*  */
 350 /*  */
 351 #define REG_APSD_CTRL                                   0x0600
 352 #define REG_BWOPMODE                                    0x0603
 353 #define REG_TCR                                                 0x0604
 354 #define REG_RCR                                                 0x0608
 355 #define REG_RX_PKT_LIMIT                                0x060C
 356 #define REG_RX_DLK_TIME                         0x060D
 357 #define REG_RX_DRVINFO_SZ                               0x060F
 358 
 359 #define REG_MACID                                               0x0610
 360 #define REG_BSSID                                               0x0618
 361 #define REG_MAR                                                 0x0620
 362 #define REG_MBIDCAMCFG                                  0x0628
 363 
 364 #define REG_PNO_STATUS                                  0x0631
 365 #define REG_USTIME_EDCA                         0x0638
 366 #define REG_MAC_SPEC_SIFS                               0x063A
 367 /*  20100719 Joseph: Hardware register definition change. (HW datasheet v54) */
 368 #define REG_RESP_SIFS_CCK                               0x063C  /*  [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
 369 #define REG_RESP_SIFS_OFDM                    0x063E    /*  [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
 370 
 371 #define REG_ACKTO                                               0x0640
 372 #define REG_CTS2TO                                              0x0641
 373 #define REG_EIFS                                                        0x0642
 374 
 375 
 376 /* RXERR_RPT */
 377 #define RXERR_TYPE_OFDM_PPDU                    0
 378 #define RXERR_TYPE_OFDMfalse_ALARM      1
 379 #define RXERR_TYPE_OFDM_MPDU_OK                 2
 380 #define RXERR_TYPE_OFDM_MPDU_FAIL       3
 381 #define RXERR_TYPE_CCK_PPDU                     4
 382 #define RXERR_TYPE_CCKfalse_ALARM       5
 383 #define RXERR_TYPE_CCK_MPDU_OK          6
 384 #define RXERR_TYPE_CCK_MPDU_FAIL                7
 385 #define RXERR_TYPE_HT_PPDU                              8
 386 #define RXERR_TYPE_HTfalse_ALARM        9
 387 #define RXERR_TYPE_HT_MPDU_TOTAL                10
 388 #define RXERR_TYPE_HT_MPDU_OK                   11
 389 #define RXERR_TYPE_HT_MPDU_FAIL                 12
 390 #define RXERR_TYPE_RX_FULL_DROP                 15
 391 
 392 #define RXERR_COUNTER_MASK                      0xFFFFF
 393 #define RXERR_RPT_RST                                   BIT(27)
 394 #define _RXERR_RPT_SEL(type)                    ((type) << 28)
 395 
 396 /*  */
 397 /*  Note: */
 398 /*      The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is */
 399 /*      always too small, but the WiFi TestPlan test by 25, 000 microseconds of NAV through sending */
 400 /*      CTS in the air. We must update this value greater than 25, 000 microseconds to pass the item. */
 401 /*      The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented */
 402 /*      by SD1 Scott. */
 403 /*  By Bruce, 2011-07-18. */
 404 /*  */
 405 #define REG_NAV_UPPER                                   0x0652  /*  unit of 128 */
 406 
 407 /* WMA, BA, CCX */
 408 #define REG_NAV_CTRL                                    0x0650
 409 #define REG_BACAMCMD                                    0x0654
 410 #define REG_BACAMCONTENT                                0x0658
 411 #define REG_LBDLY                                               0x0660
 412 #define REG_FWDLY                                               0x0661
 413 #define REG_RXERR_RPT                                   0x0664
 414 #define REG_WMAC_TRXPTCL_CTL                    0x0668
 415 
 416 /*  Security */
 417 #define REG_CAMCMD                                              0x0670
 418 #define REG_CAMWRITE                                    0x0674
 419 #define REG_CAMREAD                                     0x0678
 420 #define REG_CAMDBG                                              0x067C
 421 #define REG_SECCFG                                              0x0680
 422 
 423 /*  Power */
 424 #define REG_WOW_CTRL                                    0x0690
 425 #define REG_PS_RX_INFO                                  0x0692
 426 #define REG_UAPSD_TID                                   0x0693
 427 #define REG_WKFMCAM_CMD                         0x0698
 428 #define REG_WKFMCAM_NUM                         REG_WKFMCAM_CMD
 429 #define REG_WKFMCAM_RWD                         0x069C
 430 #define REG_RXFLTMAP0                                   0x06A0
 431 #define REG_RXFLTMAP1                                   0x06A2
 432 #define REG_RXFLTMAP2                                   0x06A4
 433 #define REG_BCN_PSR_RPT                         0x06A8
 434 #define REG_BT_COEX_TABLE                               0x06C0
 435 
 436 /*  Hardware Port 2 */
 437 #define REG_MACID1                                              0x0700
 438 #define REG_BSSID1                                              0x0708
 439 
 440 
 441 /*  */
 442 /*  */
 443 /*      0xFE00h ~ 0xFE55h       USB Configuration */
 444 /*  */
 445 /*  */
 446 #define REG_USB_INFO                                    0xFE17
 447 #define REG_USB_SPECIAL_OPTION          0xFE55
 448 #define REG_USB_DMA_AGG_TO                      0xFE5B
 449 #define REG_USB_AGG_TO                                  0xFE5C
 450 #define REG_USB_AGG_TH                                  0xFE5D
 451 
 452 #define REG_USB_HRPWM                                   0xFE58
 453 #define REG_USB_HCPWM                                   0xFE57
 454 
 455 /*  for 92DU high_Queue low_Queue Normal_Queue select */
 456 #define REG_USB_High_NORMAL_Queue_Select_MAC0   0xFE44
 457 /* define REG_USB_LOW_Queue_Select_MAC0         0xFE45 */
 458 #define REG_USB_High_NORMAL_Queue_Select_MAC1   0xFE47
 459 /* define REG_USB_LOW_Queue_Select_MAC1         0xFE48 */
 460 
 461 /*  For test chip */
 462 #define REG_TEST_USB_TXQS                               0xFE48
 463 #define REG_TEST_SIE_VID                                0xFE60          /*  0xFE60~0xFE61 */
 464 #define REG_TEST_SIE_PID                                0xFE62          /*  0xFE62~0xFE63 */
 465 #define REG_TEST_SIE_OPTIONAL                   0xFE64
 466 #define REG_TEST_SIE_CHIRP_K                    0xFE65
 467 #define REG_TEST_SIE_PHY                                0xFE66          /*  0xFE66~0xFE6B */
 468 #define REG_TEST_SIE_MAC_ADDR                   0xFE70          /*  0xFE70~0xFE75 */
 469 #define REG_TEST_SIE_STRING                     0xFE80          /*  0xFE80~0xFEB9 */
 470 
 471 
 472 /*  For normal chip */
 473 #define REG_NORMAL_SIE_VID                              0xFE60          /*  0xFE60~0xFE61 */
 474 #define REG_NORMAL_SIE_PID                              0xFE62          /*  0xFE62~0xFE63 */
 475 #define REG_NORMAL_SIE_OPTIONAL         0xFE64
 476 #define REG_NORMAL_SIE_EP                               0xFE65          /*  0xFE65~0xFE67 */
 477 #define REG_NORMAL_SIE_PHY                      0xFE68          /*  0xFE68~0xFE6B */
 478 #define REG_NORMAL_SIE_OPTIONAL2                0xFE6C
 479 #define REG_NORMAL_SIE_GPS_EP                   0xFE6D          /*  0xFE6D, for RTL8723 only. */
 480 #define REG_NORMAL_SIE_MAC_ADDR         0xFE70          /*  0xFE70~0xFE75 */
 481 #define REG_NORMAL_SIE_STRING                   0xFE80          /*  0xFE80~0xFEDF */
 482 
 483 
 484 /*  */
 485 /*  */
 486 /*      Redifine 8192C register definition for compatibility */
 487 /*  */
 488 /*  */
 489 
 490 /*  TODO: use these definition when using REG_xxx naming rule. */
 491 /*  NOTE: DO NOT Remove these definition. Use later. */
 492 
 493 #define EFUSE_CTRL                              REG_EFUSE_CTRL          /*  E-Fuse Control. */
 494 #define EFUSE_TEST                              REG_EFUSE_TEST          /*  E-Fuse Test. */
 495 #define MSR                                             (REG_CR + 2)            /*  Media Status register */
 496 /* define ISR                                           REG_HISR */
 497 
 498 #define TSFR                                            REG_TSFTR                       /*  Timing Sync Function Timer Register. */
 499 #define TSFR1                                   REG_TSFTR1                      /*  HW Port 1 TSF Register */
 500 
 501 #define PBP                                             REG_PBP
 502 
 503 /*  Redifine MACID register, to compatible prior ICs. */
 504 #define IDR0                                            REG_MACID                       /*  MAC ID Register, Offset 0x0050-0x0053 */
 505 #define IDR4                                            (REG_MACID + 4)         /*  MAC ID Register, Offset 0x0054-0x0055 */
 506 
 507 
 508 /*  */
 509 /*  9. Security Control Registers       (Offset:) */
 510 /*  */
 511 #define RWCAM                                   REG_CAMCMD              /* IN 8190 Data Sheet is called CAMcmd */
 512 #define WCAMI                                   REG_CAMWRITE    /*  Software write CAM input content */
 513 #define RCAMO                                   REG_CAMREAD             /*  Software read/write CAM config */
 514 #define CAMDBG                                  REG_CAMDBG
 515 #define SECR                                            REG_SECCFG              /* Security Configuration Register */
 516 
 517 /*  Unused register */
 518 #define UnusedRegister                  0x1BF
 519 #define DCAM                                    UnusedRegister
 520 #define PSR                                             UnusedRegister
 521 #define BBAddr                                  UnusedRegister
 522 #define PhyDataR                                        UnusedRegister
 523 
 524 /*  Min Spacing related settings. */
 525 #define MAX_MSS_DENSITY_2T                      0x13
 526 #define MAX_MSS_DENSITY_1T                      0x0A
 527 
 528 /*  */
 529 /*        8192C Cmd9346CR bits                                  (Offset 0xA, 16bit) */
 530 /*  */
 531 #define CmdEEPROM_En                            BIT5     /*  EEPROM enable when set 1 */
 532 #define CmdEERPOMSEL                            BIT4    /*  System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */
 533 #define Cmd9346CR_9356SEL                       BIT4
 534 
 535 /*  */
 536 /*        8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */
 537 /*  */
 538 #define GPIOSEL_GPIO                            0
 539 #define GPIOSEL_ENBT                            BIT5
 540 
 541 /*  */
 542 /*        8192C GPIO PIN Control Register (offset 0x44, 4 byte) */
 543 /*  */
 544 #define GPIO_IN                                 REG_GPIO_PIN_CTRL               /*  GPIO pins input value */
 545 #define GPIO_OUT                                (REG_GPIO_PIN_CTRL+1)   /*  GPIO pins output value */
 546 #define GPIO_IO_SEL                             (REG_GPIO_PIN_CTRL+2)   /*  GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */
 547 #define GPIO_MOD                                (REG_GPIO_PIN_CTRL+3)
 548 
 549 /*  */
 550 /*        8811A GPIO PIN Control Register (offset 0x60, 4 byte) */
 551 /*  */
 552 #define GPIO_IN_8811A                   REG_GPIO_PIN_CTRL_2             /*  GPIO pins input value */
 553 #define GPIO_OUT_8811A                  (REG_GPIO_PIN_CTRL_2+1) /*  GPIO pins output value */
 554 #define GPIO_IO_SEL_8811A               (REG_GPIO_PIN_CTRL_2+2) /*  GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */
 555 #define GPIO_MOD_8811A                  (REG_GPIO_PIN_CTRL_2+3)
 556 
 557 /*  */
 558 /*        8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
 559 /*  */
 560 #define HSIMR_GPIO12_0_INT_EN                   BIT0
 561 #define HSIMR_SPS_OCP_INT_EN                    BIT5
 562 #define HSIMR_RON_INT_EN                                BIT6
 563 #define HSIMR_PDN_INT_EN                                BIT7
 564 #define HSIMR_GPIO9_INT_EN                              BIT25
 565 
 566 /*  */
 567 /*        8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
 568 /*  */
 569 #define HSISR_GPIO12_0_INT                              BIT0
 570 #define HSISR_SPS_OCP_INT                               BIT5
 571 #define HSISR_RON_INT                                   BIT6
 572 #define HSISR_PDNINT                                    BIT7
 573 #define HSISR_GPIO9_INT                                 BIT25
 574 
 575 /*  */
 576 /*        8192C (MSR) Media Status Register     (Offset 0x4C, 8 bits) */
 577 /*  */
 578 /*
 579 Network Type
 580 00: No link
 581 01: Link in ad hoc network
 582 10: Link in infrastructure network
 583 11: AP mode
 584 Default: 00b.
 585 */
 586 #define MSR_NOLINK                              0x00
 587 #define MSR_ADHOC                               0x01
 588 #define MSR_INFRA                               0x02
 589 #define MSR_AP                                  0x03
 590 
 591 /*  */
 592 /*        USB INTR CONTENT */
 593 /*  */
 594 #define USB_C2H_CMDID_OFFSET                                    0
 595 #define USB_C2H_SEQ_OFFSET                                      1
 596 #define USB_C2H_EVENT_OFFSET                                    2
 597 #define USB_INTR_CPWM_OFFSET                                    16
 598 #define USB_INTR_CONTENT_C2H_OFFSET                     0
 599 #define USB_INTR_CONTENT_CPWM1_OFFSET           16
 600 #define USB_INTR_CONTENT_CPWM2_OFFSET           20
 601 #define USB_INTR_CONTENT_HISR_OFFSET                    48
 602 #define USB_INTR_CONTENT_HISRE_OFFSET           52
 603 #define USB_INTR_CONTENT_LENGTH                         56
 604 
 605 /*  */
 606 /*        Response Rate Set Register    (offset 0x440, 24bits) */
 607 /*  */
 608 #define RRSR_1M                                 BIT0
 609 #define RRSR_2M                                 BIT1
 610 #define RRSR_5_5M                               BIT2
 611 #define RRSR_11M                                BIT3
 612 #define RRSR_6M                                 BIT4
 613 #define RRSR_9M                                 BIT5
 614 #define RRSR_12M                                BIT6
 615 #define RRSR_18M                                BIT7
 616 #define RRSR_24M                                BIT8
 617 #define RRSR_36M                                BIT9
 618 #define RRSR_48M                                BIT10
 619 #define RRSR_54M                                BIT11
 620 #define RRSR_MCS0                               BIT12
 621 #define RRSR_MCS1                               BIT13
 622 #define RRSR_MCS2                               BIT14
 623 #define RRSR_MCS3                               BIT15
 624 #define RRSR_MCS4                               BIT16
 625 #define RRSR_MCS5                               BIT17
 626 #define RRSR_MCS6                               BIT18
 627 #define RRSR_MCS7                               BIT19
 628 
 629 #define RRSR_CCK_RATES (RRSR_11M|RRSR_5_5M|RRSR_2M|RRSR_1M)
 630 #define RRSR_OFDM_RATES (RRSR_54M|RRSR_48M|RRSR_36M|RRSR_24M|RRSR_18M|RRSR_12M|RRSR_9M|RRSR_6M)
 631 
 632 /*  WOL bit information */
 633 #define HAL92C_WOL_PTK_UPDATE_EVENT             BIT0
 634 #define HAL92C_WOL_GTK_UPDATE_EVENT             BIT1
 635 #define HAL92C_WOL_DISASSOC_EVENT               BIT2
 636 #define HAL92C_WOL_DEAUTH_EVENT                 BIT3
 637 #define HAL92C_WOL_FW_DISCONNECT_EVENT  BIT4
 638 
 639 /*  */
 640 /*        Rate Definition */
 641 /*  */
 642 /* CCK */
 643 #define RATR_1M                                 0x00000001
 644 #define RATR_2M                                 0x00000002
 645 #define RATR_55M                                        0x00000004
 646 #define RATR_11M                                        0x00000008
 647 /* OFDM */
 648 #define RATR_6M                                 0x00000010
 649 #define RATR_9M                                 0x00000020
 650 #define RATR_12M                                        0x00000040
 651 #define RATR_18M                                        0x00000080
 652 #define RATR_24M                                        0x00000100
 653 #define RATR_36M                                        0x00000200
 654 #define RATR_48M                                        0x00000400
 655 #define RATR_54M                                        0x00000800
 656 /* MCS 1 Spatial Stream */
 657 #define RATR_MCS0                                       0x00001000
 658 #define RATR_MCS1                                       0x00002000
 659 #define RATR_MCS2                                       0x00004000
 660 #define RATR_MCS3                                       0x00008000
 661 #define RATR_MCS4                                       0x00010000
 662 #define RATR_MCS5                                       0x00020000
 663 #define RATR_MCS6                                       0x00040000
 664 #define RATR_MCS7                                       0x00080000
 665 /* MCS 2 Spatial Stream */
 666 #define RATR_MCS8                                       0x00100000
 667 #define RATR_MCS9                                       0x00200000
 668 #define RATR_MCS10                                      0x00400000
 669 #define RATR_MCS11                                      0x00800000
 670 #define RATR_MCS12                                      0x01000000
 671 #define RATR_MCS13                                      0x02000000
 672 #define RATR_MCS14                                      0x04000000
 673 #define RATR_MCS15                                      0x08000000
 674 
 675 /* CCK */
 676 #define RATE_1M                                 BIT(0)
 677 #define RATE_2M                                 BIT(1)
 678 #define RATE_5_5M                               BIT(2)
 679 #define RATE_11M                                BIT(3)
 680 /* OFDM */
 681 #define RATE_6M                                 BIT(4)
 682 #define RATE_9M                                 BIT(5)
 683 #define RATE_12M                                BIT(6)
 684 #define RATE_18M                                BIT(7)
 685 #define RATE_24M                                BIT(8)
 686 #define RATE_36M                                BIT(9)
 687 #define RATE_48M                                BIT(10)
 688 #define RATE_54M                                BIT(11)
 689 /* MCS 1 Spatial Stream */
 690 #define RATE_MCS0                               BIT(12)
 691 #define RATE_MCS1                               BIT(13)
 692 #define RATE_MCS2                               BIT(14)
 693 #define RATE_MCS3                               BIT(15)
 694 #define RATE_MCS4                               BIT(16)
 695 #define RATE_MCS5                               BIT(17)
 696 #define RATE_MCS6                               BIT(18)
 697 #define RATE_MCS7                               BIT(19)
 698 /* MCS 2 Spatial Stream */
 699 #define RATE_MCS8                               BIT(20)
 700 #define RATE_MCS9                               BIT(21)
 701 #define RATE_MCS10                              BIT(22)
 702 #define RATE_MCS11                              BIT(23)
 703 #define RATE_MCS12                              BIT(24)
 704 #define RATE_MCS13                              BIT(25)
 705 #define RATE_MCS14                              BIT(26)
 706 #define RATE_MCS15                              BIT(27)
 707 
 708 
 709 /*  ALL CCK Rate */
 710 #define RATE_ALL_CCK                            RATR_1M|RATR_2M|RATR_55M|RATR_11M
 711 #define RATE_ALL_OFDM_AG                        RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\
 712                                                 RATR_36M|RATR_48M|RATR_54M
 713 #define RATE_ALL_OFDM_1SS                       RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\
 714                                                 RATR_MCS4|RATR_MCS5|RATR_MCS6   |RATR_MCS7
 715 #define RATE_ALL_OFDM_2SS                       RATR_MCS8|RATR_MCS9     |RATR_MCS10|RATR_MCS11|\
 716                                                 RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
 717 
 718 #define RATE_BITMAP_ALL                 0xFFFFF
 719 
 720 /*  Only use CCK 1M rate for ACK */
 721 #define RATE_RRSR_CCK_ONLY_1M           0xFFFF1
 722 #define RATE_RRSR_WITHOUT_CCK           0xFFFF0
 723 
 724 /*  */
 725 /*        BW_OPMODE bits                                (Offset 0x603, 8bit) */
 726 /*  */
 727 #define BW_OPMODE_20MHZ                 BIT2
 728 #define BW_OPMODE_5G                            BIT1
 729 
 730 /*  */
 731 /*        CAM Config Setting (offset 0x680, 1 byte) */
 732 /*  */
 733 #define CAM_VALID                               BIT15
 734 #define CAM_NOTVALID                    0x0000
 735 #define CAM_USEDK                               BIT5
 736 
 737 #define CAM_CONTENT_COUNT       8
 738 
 739 #define CAM_NONE                                0x0
 740 #define CAM_WEP40                               0x01
 741 #define CAM_TKIP                                0x02
 742 #define CAM_AES                                 0x04
 743 #define CAM_WEP104                              0x05
 744 #define CAM_SMS4                                0x6
 745 
 746 #define TOTAL_CAM_ENTRY         32
 747 #define HALF_CAM_ENTRY                  16
 748 
 749 #define CAM_CONFIG_USEDK                true
 750 #define CAM_CONFIG_NO_USEDK     false
 751 
 752 #define CAM_WRITE                               BIT16
 753 #define CAM_READ                                0x00000000
 754 #define CAM_POLLINIG                    BIT31
 755 
 756 /*  */
 757 /*  10. Power Save Control Registers */
 758 /*  */
 759 #define WOW_PMEN                                BIT0 /*  Power management Enable. */
 760 #define WOW_WOMEN                               BIT1 /*  WoW function on or off. */
 761 #define WOW_MAGIC                               BIT2 /*  Magic packet */
 762 #define WOW_UWF                         BIT3 /*  Unicast Wakeup frame. */
 763 
 764 /*  */
 765 /*  12. Host Interrupt Status Registers */
 766 /*  */
 767 /*  */
 768 /*       8190 IMR/ISR bits */
 769 /*  */
 770 #define IMR8190_DISABLED                0x0
 771 #define IMR_DISABLED                    0x0
 772 /*  IMR DW0 Bit 0-31 */
 773 #define IMR_BCNDMAINT6                  BIT31           /*  Beacon DMA Interrupt 6 */
 774 #define IMR_BCNDMAINT5                  BIT30           /*  Beacon DMA Interrupt 5 */
 775 #define IMR_BCNDMAINT4                  BIT29           /*  Beacon DMA Interrupt 4 */
 776 #define IMR_BCNDMAINT3                  BIT28           /*  Beacon DMA Interrupt 3 */
 777 #define IMR_BCNDMAINT2                  BIT27           /*  Beacon DMA Interrupt 2 */
 778 #define IMR_BCNDMAINT1                  BIT26           /*  Beacon DMA Interrupt 1 */
 779 #define IMR_BCNDOK8                             BIT25           /*  Beacon Queue DMA OK Interrup 8 */
 780 #define IMR_BCNDOK7                             BIT24           /*  Beacon Queue DMA OK Interrup 7 */
 781 #define IMR_BCNDOK6                             BIT23           /*  Beacon Queue DMA OK Interrup 6 */
 782 #define IMR_BCNDOK5                             BIT22           /*  Beacon Queue DMA OK Interrup 5 */
 783 #define IMR_BCNDOK4                             BIT21           /*  Beacon Queue DMA OK Interrup 4 */
 784 #define IMR_BCNDOK3                             BIT20           /*  Beacon Queue DMA OK Interrup 3 */
 785 #define IMR_BCNDOK2                             BIT19           /*  Beacon Queue DMA OK Interrup 2 */
 786 #define IMR_BCNDOK1                             BIT18           /*  Beacon Queue DMA OK Interrup 1 */
 787 #define IMR_TIMEOUT2                    BIT17           /*  Timeout interrupt 2 */
 788 #define IMR_TIMEOUT1                    BIT16           /*  Timeout interrupt 1 */
 789 #define IMR_TXFOVW                              BIT15           /*  Transmit FIFO Overflow */
 790 #define IMR_PSTIMEOUT                   BIT14           /*  Power save time out interrupt */
 791 #define IMR_BcnInt                              BIT13           /*  Beacon DMA Interrupt 0 */
 792 #define IMR_RXFOVW                              BIT12           /*  Receive FIFO Overflow */
 793 #define IMR_RDU                                 BIT11           /*  Receive Descriptor Unavailable */
 794 #define IMR_ATIMEND                             BIT10           /*  For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. */
 795 #define IMR_BDOK                                BIT9            /*  Beacon Queue DMA OK Interrup */
 796 #define IMR_HIGHDOK                             BIT8            /*  High Queue DMA OK Interrupt */
 797 #define IMR_TBDOK                               BIT7            /*  Transmit Beacon OK interrup */
 798 #define IMR_MGNTDOK                     BIT6            /*  Management Queue DMA OK Interrupt */
 799 #define IMR_TBDER                               BIT5            /*  For 92C, Transmit Beacon Error Interrupt */
 800 #define IMR_BKDOK                               BIT4            /*  AC_BK DMA OK Interrupt */
 801 #define IMR_BEDOK                               BIT3            /*  AC_BE DMA OK Interrupt */
 802 #define IMR_VIDOK                               BIT2            /*  AC_VI DMA OK Interrupt */
 803 #define IMR_VODOK                               BIT1            /*  AC_VO DMA Interrupt */
 804 #define IMR_ROK                                 BIT0            /*  Receive DMA OK Interrupt */
 805 
 806 /*  13. Host Interrupt Status Extension Register         (Offset: 0x012C-012Eh) */
 807 #define IMR_TSF_BIT32_TOGGLE    BIT15
 808 #define IMR_BcnInt_E                            BIT12
 809 #define IMR_TXERR                               BIT11
 810 #define IMR_RXERR                               BIT10
 811 #define IMR_C2HCMD                              BIT9
 812 #define IMR_CPWM                                BIT8
 813 /* RSVD [2-7] */
 814 #define IMR_OCPINT                              BIT1
 815 #define IMR_WLANOFF                     BIT0
 816 
 817 /*  */
 818 /*  8723E series PCIE Host IMR/ISR bit */
 819 /*  */
 820 /*  IMR DW0 Bit 0-31 */
 821 #define PHIMR_TIMEOUT2                          BIT31
 822 #define PHIMR_TIMEOUT1                          BIT30
 823 #define PHIMR_PSTIMEOUT                 BIT29
 824 #define PHIMR_GTINT4                            BIT28
 825 #define PHIMR_GTINT3                            BIT27
 826 #define PHIMR_TXBCNERR                          BIT26
 827 #define PHIMR_TXBCNOK                           BIT25
 828 #define PHIMR_TSF_BIT32_TOGGLE  BIT24
 829 #define PHIMR_BCNDMAINT3                        BIT23
 830 #define PHIMR_BCNDMAINT2                        BIT22
 831 #define PHIMR_BCNDMAINT1                        BIT21
 832 #define PHIMR_BCNDMAINT0                        BIT20
 833 #define PHIMR_BCNDOK3                           BIT19
 834 #define PHIMR_BCNDOK2                           BIT18
 835 #define PHIMR_BCNDOK1                           BIT17
 836 #define PHIMR_BCNDOK0                           BIT16
 837 #define PHIMR_HSISR_IND_ON                      BIT15
 838 #define PHIMR_BCNDMAINT_E                       BIT14
 839 #define PHIMR_ATIMEND_E                 BIT13
 840 #define PHIMR_ATIM_CTW_END              BIT12
 841 #define PHIMR_HISRE_IND                 BIT11   /*  RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) */
 842 #define PHIMR_C2HCMD                            BIT10
 843 #define PHIMR_CPWM2                             BIT9
 844 #define PHIMR_CPWM                                      BIT8
 845 #define PHIMR_HIGHDOK                           BIT7            /*  High Queue DMA OK Interrupt */
 846 #define PHIMR_MGNTDOK                           BIT6            /*  Management Queue DMA OK Interrupt */
 847 #define PHIMR_BKDOK                                     BIT5            /*  AC_BK DMA OK Interrupt */
 848 #define PHIMR_BEDOK                                     BIT4            /*  AC_BE DMA OK Interrupt */
 849 #define PHIMR_VIDOK                                     BIT3            /*  AC_VI DMA OK Interrupt */
 850 #define PHIMR_VODOK                             BIT2            /*  AC_VO DMA Interrupt */
 851 #define PHIMR_RDU                                       BIT1            /*  Receive Descriptor Unavailable */
 852 #define PHIMR_ROK                                       BIT0            /*  Receive DMA OK Interrupt */
 853 
 854 /*  PCIE Host Interrupt Status Extension bit */
 855 #define PHIMR_BCNDMAINT7                        BIT23
 856 #define PHIMR_BCNDMAINT6                        BIT22
 857 #define PHIMR_BCNDMAINT5                        BIT21
 858 #define PHIMR_BCNDMAINT4                        BIT20
 859 #define PHIMR_BCNDOK7                           BIT19
 860 #define PHIMR_BCNDOK6                           BIT18
 861 #define PHIMR_BCNDOK5                           BIT17
 862 #define PHIMR_BCNDOK4                           BIT16
 863 /*  bit12 15: RSVD */
 864 #define PHIMR_TXERR                                     BIT11
 865 #define PHIMR_RXERR                                     BIT10
 866 #define PHIMR_TXFOVW                            BIT9
 867 #define PHIMR_RXFOVW                            BIT8
 868 /*  bit2-7: RSVD */
 869 #define PHIMR_OCPINT                            BIT1
 870 /*  bit0: RSVD */
 871 
 872 #define UHIMR_TIMEOUT2                          BIT31
 873 #define UHIMR_TIMEOUT1                          BIT30
 874 #define UHIMR_PSTIMEOUT                 BIT29
 875 #define UHIMR_GTINT4                            BIT28
 876 #define UHIMR_GTINT3                            BIT27
 877 #define UHIMR_TXBCNERR                          BIT26
 878 #define UHIMR_TXBCNOK                           BIT25
 879 #define UHIMR_TSF_BIT32_TOGGLE  BIT24
 880 #define UHIMR_BCNDMAINT3                        BIT23
 881 #define UHIMR_BCNDMAINT2                        BIT22
 882 #define UHIMR_BCNDMAINT1                        BIT21
 883 #define UHIMR_BCNDMAINT0                        BIT20
 884 #define UHIMR_BCNDOK3                           BIT19
 885 #define UHIMR_BCNDOK2                           BIT18
 886 #define UHIMR_BCNDOK1                           BIT17
 887 #define UHIMR_BCNDOK0                           BIT16
 888 #define UHIMR_HSISR_IND                 BIT15
 889 #define UHIMR_BCNDMAINT_E                       BIT14
 890 /* RSVD BIT13 */
 891 #define UHIMR_CTW_END                           BIT12
 892 /* RSVD BIT11 */
 893 #define UHIMR_C2HCMD                            BIT10
 894 #define UHIMR_CPWM2                             BIT9
 895 #define UHIMR_CPWM                                      BIT8
 896 #define UHIMR_HIGHDOK                           BIT7            /*  High Queue DMA OK Interrupt */
 897 #define UHIMR_MGNTDOK                           BIT6            /*  Management Queue DMA OK Interrupt */
 898 #define UHIMR_BKDOK                             BIT5            /*  AC_BK DMA OK Interrupt */
 899 #define UHIMR_BEDOK                             BIT4            /*  AC_BE DMA OK Interrupt */
 900 #define UHIMR_VIDOK                                     BIT3            /*  AC_VI DMA OK Interrupt */
 901 #define UHIMR_VODOK                             BIT2            /*  AC_VO DMA Interrupt */
 902 #define UHIMR_RDU                                       BIT1            /*  Receive Descriptor Unavailable */
 903 #define UHIMR_ROK                                       BIT0            /*  Receive DMA OK Interrupt */
 904 
 905 /*  USB Host Interrupt Status Extension bit */
 906 #define UHIMR_BCNDMAINT7                        BIT23
 907 #define UHIMR_BCNDMAINT6                        BIT22
 908 #define UHIMR_BCNDMAINT5                        BIT21
 909 #define UHIMR_BCNDMAINT4                        BIT20
 910 #define UHIMR_BCNDOK7                           BIT19
 911 #define UHIMR_BCNDOK6                           BIT18
 912 #define UHIMR_BCNDOK5                           BIT17
 913 #define UHIMR_BCNDOK4                           BIT16
 914 /*  bit14-15: RSVD */
 915 #define UHIMR_ATIMEND_E                 BIT13
 916 #define UHIMR_ATIMEND                           BIT12
 917 #define UHIMR_TXERR                                     BIT11
 918 #define UHIMR_RXERR                                     BIT10
 919 #define UHIMR_TXFOVW                            BIT9
 920 #define UHIMR_RXFOVW                            BIT8
 921 /*  bit2-7: RSVD */
 922 #define UHIMR_OCPINT                            BIT1
 923 /*  bit0: RSVD */
 924 
 925 
 926 #define HAL_NIC_UNPLUG_ISR                      0xFFFFFFFF      /*  The value when the NIC is unplugged for PCI. */
 927 #define HAL_NIC_UNPLUG_PCI_ISR          0xEAEAEAEA      /*  The value when the NIC is unplugged for PCI in PCI interrupt (page 3). */
 928 
 929 /*  */
 930 /*        8188 IMR/ISR bits */
 931 /*  */
 932 #define IMR_DISABLED_88E                        0x0
 933 /*  IMR DW0(0x0060-0063) Bit 0-31 */
 934 #define IMR_TXCCK_88E                           BIT30           /*  TXRPT interrupt when CCX bit of the packet is set */
 935 #define IMR_PSTIMEOUT_88E                       BIT29           /*  Power Save Time Out Interrupt */
 936 #define IMR_GTINT4_88E                          BIT28           /*  When GTIMER4 expires, this bit is set to 1 */
 937 #define IMR_GTINT3_88E                          BIT27           /*  When GTIMER3 expires, this bit is set to 1 */
 938 #define IMR_TBDER_88E                           BIT26           /*  Transmit Beacon0 Error */
 939 #define IMR_TBDOK_88E                           BIT25           /*  Transmit Beacon0 OK */
 940 #define IMR_TSF_BIT32_TOGGLE_88E        BIT24           /*  TSF Timer BIT32 toggle indication interrupt */
 941 #define IMR_BCNDMAINT0_88E              BIT20           /*  Beacon DMA Interrupt 0 */
 942 #define IMR_BCNDERR0_88E                        BIT16           /*  Beacon Queue DMA Error 0 */
 943 #define IMR_HSISR_IND_ON_INT_88E        BIT15           /*  HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
 944 #define IMR_BCNDMAINT_E_88E             BIT14           /*  Beacon DMA Interrupt Extension for Win7 */
 945 #define IMR_ATIMEND_88E                 BIT12           /*  CTWidnow End or ATIM Window End */
 946 #define IMR_HISR1_IND_INT_88E           BIT11           /*  HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */
 947 #define IMR_C2HCMD_88E                          BIT10           /*  CPU to Host Command INT Status, Write 1 clear */
 948 #define IMR_CPWM2_88E                           BIT9                    /*  CPU power Mode exchange INT Status, Write 1 clear */
 949 #define IMR_CPWM_88E                            BIT8                    /*  CPU power Mode exchange INT Status, Write 1 clear */
 950 #define IMR_HIGHDOK_88E                 BIT7                    /*  High Queue DMA OK */
 951 #define IMR_MGNTDOK_88E                 BIT6                    /*  Management Queue DMA OK */
 952 #define IMR_BKDOK_88E                           BIT5                    /*  AC_BK DMA OK */
 953 #define IMR_BEDOK_88E                           BIT4                    /*  AC_BE DMA OK */
 954 #define IMR_VIDOK_88E                           BIT3                    /*  AC_VI DMA OK */
 955 #define IMR_VODOK_88E                           BIT2                    /*  AC_VO DMA OK */
 956 #define IMR_RDU_88E                                     BIT1                    /*  Rx Descriptor Unavailable */
 957 #define IMR_ROK_88E                                     BIT0                    /*  Receive DMA OK */
 958 
 959 /*  IMR DW1(0x00B4-00B7) Bit 0-31 */
 960 #define IMR_BCNDMAINT7_88E              BIT27           /*  Beacon DMA Interrupt 7 */
 961 #define IMR_BCNDMAINT6_88E              BIT26           /*  Beacon DMA Interrupt 6 */
 962 #define IMR_BCNDMAINT5_88E              BIT25           /*  Beacon DMA Interrupt 5 */
 963 #define IMR_BCNDMAINT4_88E              BIT24           /*  Beacon DMA Interrupt 4 */
 964 #define IMR_BCNDMAINT3_88E              BIT23           /*  Beacon DMA Interrupt 3 */
 965 #define IMR_BCNDMAINT2_88E              BIT22           /*  Beacon DMA Interrupt 2 */
 966 #define IMR_BCNDMAINT1_88E              BIT21           /*  Beacon DMA Interrupt 1 */
 967 #define IMR_BCNDOK7_88E                 BIT20           /*  Beacon Queue DMA OK Interrup 7 */
 968 #define IMR_BCNDOK6_88E                 BIT19           /*  Beacon Queue DMA OK Interrup 6 */
 969 #define IMR_BCNDOK5_88E                 BIT18           /*  Beacon Queue DMA OK Interrup 5 */
 970 #define IMR_BCNDOK4_88E                 BIT17           /*  Beacon Queue DMA OK Interrup 4 */
 971 #define IMR_BCNDOK3_88E                 BIT16           /*  Beacon Queue DMA OK Interrup 3 */
 972 #define IMR_BCNDOK2_88E                 BIT15           /*  Beacon Queue DMA OK Interrup 2 */
 973 #define IMR_BCNDOK1_88E                 BIT14           /*  Beacon Queue DMA OK Interrup 1 */
 974 #define IMR_ATIMEND_E_88E                       BIT13           /*  ATIM Window End Extension for Win7 */
 975 #define IMR_TXERR_88E                           BIT11           /*  Tx Error Flag Interrupt Status, write 1 clear. */
 976 #define IMR_RXERR_88E                           BIT10           /*  Rx Error Flag INT Status, Write 1 clear */
 977 #define IMR_TXFOVW_88E                          BIT9                    /*  Transmit FIFO Overflow */
 978 #define IMR_RXFOVW_88E                          BIT8                    /*  Receive FIFO Overflow */
 979 
 980 /*===================================================================
 981 =====================================================================
 982 Here the register defines are for 92C. When the define is as same with 92C,
 983 we will use the 92C's define for the consistency
 984 So the following defines for 92C is not entire!!!!!!
 985 =====================================================================
 986 =====================================================================*/
 987 /*
 988 Based on Datasheet V33---090401
 989 Register Summary
 990 Current IOREG MAP
 991 0x0000h ~ 0x00FFh   System Configuration (256 Bytes)
 992 0x0100h ~ 0x01FFh   MACTOP General Configuration (256 Bytes)
 993 0x0200h ~ 0x027Fh   TXDMA Configuration (128 Bytes)
 994 0x0280h ~ 0x02FFh   RXDMA Configuration (128 Bytes)
 995 0x0300h ~ 0x03FFh   PCIE EMAC Reserved Region (256 Bytes)
 996 0x0400h ~ 0x04FFh   Protocol Configuration (256 Bytes)
 997 0x0500h ~ 0x05FFh   EDCA Configuration (256 Bytes)
 998 0x0600h ~ 0x07FFh   WMAC Configuration (512 Bytes)
 999 0x2000h ~ 0x3FFFh   8051 FW Download Region (8196 Bytes)
1000 */
1001         /*  */
1002         /*               8192C (TXPAUSE) transmission pause     (Offset 0x522, 8 bits) */
1003         /*  */
1004 /*  Note: */
1005 /*      The the bits of stoping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong, */
1006 /*      the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3. */
1007 /*      8723 and 88E may be not correct either in the eralier version. Confirmed with DD Tim. */
1008 /*  By Bruce, 2011-09-22. */
1009 #define StopBecon               BIT6
1010 #define StopHigh                        BIT5
1011 #define StopMgt                 BIT4
1012 #define StopBK                  BIT3
1013 #define StopBE                  BIT2
1014 #define StopVI                  BIT1
1015 #define StopVO                  BIT0
1016 
1017 /*  */
1018 /*        8192C (RCR) Receive Configuration Register    (Offset 0x608, 32 bits) */
1019 /*  */
1020 #define RCR_APPFCS                              BIT31   /*  WMAC append FCS after pauload */
1021 #define RCR_APP_MIC                             BIT30   /*  MACRX will retain the MIC at the bottom of the packet. */
1022 #define RCR_APP_ICV                             BIT29   /*  MACRX will retain the ICV at the bottom of the packet. */
1023 #define RCR_APP_PHYST_RXFF              BIT28   /*  PHY Status is appended before RX packet in RXFF */
1024 #define RCR_APP_BA_SSN                  BIT27   /*  SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */
1025 #define RCR_NONQOS_VHT                  BIT26   /*  Reserved */
1026 #define RCR_RSVD_BIT25                  BIT25   /*  Reserved */
1027 #define RCR_ENMBID                              BIT24   /*  Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. */
1028 #define RCR_LSIGEN                              BIT23   /*  Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. */
1029 #define RCR_MFBEN                               BIT22   /*  Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. */
1030 #define RCR_RSVD_BIT21                  BIT21   /*  Reserved */
1031 #define RCR_RSVD_BIT20                  BIT20   /*  Reserved */
1032 #define RCR_RSVD_BIT19                  BIT19   /*  Reserved */
1033 #define RCR_TIM_PARSER_EN               BIT18   /*  RX Beacon TIM Parser. */
1034 #define RCR_BM_DATA_EN                  BIT17   /*  Broadcast data packet interrupt enable. */
1035 #define RCR_UC_DATA_EN                  BIT16   /*  Unicast data packet interrupt enable. */
1036 #define RCR_RSVD_BIT15                  BIT15   /*  Reserved */
1037 #define RCR_HTC_LOC_CTRL                BIT14   /*  MFC<--HTC = 1 MFC-->HTC = 0 */
1038 #define RCR_AMF                                 BIT13   /*  Accept management type frame */
1039 #define RCR_ACF                                 BIT12   /*  Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */
1040 #define RCR_ADF                                 BIT11   /*  Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */
1041 #define RCR_RSVD_BIT10                  BIT10   /*  Reserved */
1042 #define RCR_AICV                                        BIT9            /*  Accept ICV error packet */
1043 #define RCR_ACRC32                              BIT8            /*  Accept CRC32 error packet */
1044 #define RCR_CBSSID_BCN                  BIT7            /*  Accept BSSID match packet (Rx beacon, probe rsp) */
1045 #define RCR_CBSSID_DATA         BIT6            /*  Accept BSSID match packet (Data) */
1046 #define RCR_CBSSID                              RCR_CBSSID_DATA /*  Accept BSSID match packet */
1047 #define RCR_APWRMGT                     BIT5            /*  Accept power management packet */
1048 #define RCR_ADD3                                BIT4            /*  Accept address 3 match packet */
1049 #define RCR_AB                                  BIT3            /*  Accept broadcast packet */
1050 #define RCR_AM                                  BIT2            /*  Accept multicast packet */
1051 #define RCR_APM                                 BIT1            /*  Accept physical match packet */
1052 #define RCR_AAP                                 BIT0            /*  Accept all unicast packet */
1053 
1054 
1055 /*  */
1056 /*  */
1057 /*      0x0000h ~ 0x00FFh       System Configuration */
1058 /*  */
1059 /*  */
1060 
1061 /* 2 SYS_ISO_CTRL */
1062 #define ISO_MD2PP                               BIT(0)
1063 #define ISO_UA2USB                              BIT(1)
1064 #define ISO_UD2CORE                             BIT(2)
1065 #define ISO_PA2PCIE                             BIT(3)
1066 #define ISO_PD2CORE                             BIT(4)
1067 #define ISO_IP2MAC                              BIT(5)
1068 #define ISO_DIOP                                        BIT(6)
1069 #define ISO_DIOE                                        BIT(7)
1070 #define ISO_EB2CORE                             BIT(8)
1071 #define ISO_DIOR                                        BIT(9)
1072 #define PWC_EV12V                               BIT(15)
1073 
1074 
1075 /* 2 SYS_FUNC_EN */
1076 #define FEN_BBRSTB                              BIT(0)
1077 #define FEN_BB_GLB_RSTn         BIT(1)
1078 #define FEN_USBA                                BIT(2)
1079 #define FEN_UPLL                                BIT(3)
1080 #define FEN_USBD                                BIT(4)
1081 #define FEN_DIO_PCIE                    BIT(5)
1082 #define FEN_PCIEA                               BIT(6)
1083 #define FEN_PPLL                                        BIT(7)
1084 #define FEN_PCIED                               BIT(8)
1085 #define FEN_DIOE                                BIT(9)
1086 #define FEN_CPUEN                               BIT(10)
1087 #define FEN_DCORE                               BIT(11)
1088 #define FEN_ELDR                                BIT(12)
1089 #define FEN_EN_25_1                             BIT(13)
1090 #define FEN_HWPDN                               BIT(14)
1091 #define FEN_MREGEN                              BIT(15)
1092 
1093 /* 2 APS_FSMCO */
1094 #define PFM_LDALL                               BIT(0)
1095 #define PFM_ALDN                                BIT(1)
1096 #define PFM_LDKP                                BIT(2)
1097 #define PFM_WOWL                                BIT(3)
1098 #define EnPDN                                   BIT(4)
1099 #define PDN_PL                                  BIT(5)
1100 #define APFM_ONMAC                              BIT(8)
1101 #define APFM_OFF                                BIT(9)
1102 #define APFM_RSM                                BIT(10)
1103 #define AFSM_HSUS                               BIT(11)
1104 #define AFSM_PCIE                               BIT(12)
1105 #define APDM_MAC                                BIT(13)
1106 #define APDM_HOST                               BIT(14)
1107 #define APDM_HPDN                               BIT(15)
1108 #define RDY_MACON                               BIT(16)
1109 #define SUS_HOST                                BIT(17)
1110 #define ROP_ALD                                 BIT(20)
1111 #define ROP_PWR                                 BIT(21)
1112 #define ROP_SPS                                 BIT(22)
1113 #define SOP_MRST                                BIT(25)
1114 #define SOP_FUSE                                BIT(26)
1115 #define SOP_ABG                                 BIT(27)
1116 #define SOP_AMB                                 BIT(28)
1117 #define SOP_RCK                                 BIT(29)
1118 #define SOP_A8M                                 BIT(30)
1119 #define XOP_BTCK                                BIT(31)
1120 
1121 /* 2 SYS_CLKR */
1122 #define ANAD16V_EN                              BIT(0)
1123 #define ANA8M                                   BIT(1)
1124 #define MACSLP                                  BIT(4)
1125 #define LOADER_CLK_EN                   BIT(5)
1126 
1127 
1128 /* 2 9346CR /REG_SYS_EEPROM_CTRL */
1129 #define BOOT_FROM_EEPROM                BIT(4)
1130 #define EEPROMSEL                               BIT(4)
1131 #define EEPROM_EN                               BIT(5)
1132 
1133 
1134 /* 2 RF_CTRL */
1135 #define RF_EN                                   BIT(0)
1136 #define RF_RSTB                                 BIT(1)
1137 #define RF_SDMRSTB                              BIT(2)
1138 
1139 
1140 /* 2 LDOV12D_CTRL */
1141 #define LDV12_EN                                BIT(0)
1142 #define LDV12_SDBY                              BIT(1)
1143 #define LPLDO_HSM                               BIT(2)
1144 #define LPLDO_LSM_DIS                   BIT(3)
1145 #define _LDV12_VADJ(x)                  (((x) & 0xF) << 4)
1146 
1147 
1148 
1149 /* 2 EFUSE_TEST (For RTL8723 partially) */
1150 #define EF_TRPT                                 BIT(7)
1151 #define EF_CELL_SEL                             (BIT(8)|BIT(9)) /*  00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
1152 #define LDOE25_EN                               BIT(31)
1153 #define EFUSE_SEL(x)                            (((x) & 0x3) << 8)
1154 #define EFUSE_SEL_MASK                  0x300
1155 #define EFUSE_WIFI_SEL_0                0x0
1156 #define EFUSE_BT_SEL_0                  0x1
1157 #define EFUSE_BT_SEL_1                  0x2
1158 #define EFUSE_BT_SEL_2                  0x3
1159 
1160 
1161 /* 2 8051FWDL */
1162 /* 2 MCUFWDL */
1163 #define MCUFWDL_EN                              BIT(0)
1164 #define MCUFWDL_RDY                     BIT(1)
1165 #define FWDL_ChkSum_rpt         BIT(2)
1166 #define MACINI_RDY                              BIT(3)
1167 #define BBINI_RDY                               BIT(4)
1168 #define RFINI_RDY                               BIT(5)
1169 #define WINTINI_RDY                             BIT(6)
1170 #define RAM_DL_SEL                              BIT(7)
1171 #define ROM_DLEN                                BIT(19)
1172 #define CPRST                                   BIT(23)
1173 
1174 
1175 /* 2 REG_SYS_CFG */
1176 #define XCLK_VLD                                BIT(0)
1177 #define ACLK_VLD                                BIT(1)
1178 #define UCLK_VLD                                BIT(2)
1179 #define PCLK_VLD                                BIT(3)
1180 #define PCIRSTB                                 BIT(4)
1181 #define V15_VLD                                 BIT(5)
1182 #define SW_OFFLOAD_EN                   BIT(7)
1183 #define SIC_IDLE                                        BIT(8)
1184 #define BD_MAC2                                 BIT(9)
1185 #define BD_MAC1                                 BIT(10)
1186 #define IC_MACPHY_MODE          BIT(11)
1187 #define CHIP_VER                                (BIT(12)|BIT(13)|BIT(14)|BIT(15))
1188 #define BT_FUNC                                 BIT(16)
1189 #define VENDOR_ID                               BIT(19)
1190 #define EXT_VENDOR_ID                   (BIT(18)|BIT(19)) /* Currently only for RTL8723B */
1191 #define PAD_HWPD_IDN                    BIT(22)
1192 #define TRP_VAUX_EN                             BIT(23) /*  RTL ID */
1193 #define TRP_BT_EN                               BIT(24)
1194 #define BD_PKG_SEL                              BIT(25)
1195 #define BD_HCI_SEL                              BIT(26)
1196 #define TYPE_ID                                 BIT(27)
1197 #define RF_TYPE_ID                              BIT(27)
1198 
1199 #define RTL_ID                                  BIT(23) /*  TestChip ID, 1:Test(RLE); 0:MP(RL) */
1200 #define SPS_SEL                                 BIT(24) /*  1:LDO regulator mode; 0:Switching regulator mode */
1201 
1202 
1203 #define CHIP_VER_RTL_MASK               0xF000  /* Bit 12 ~ 15 */
1204 #define CHIP_VER_RTL_SHIFT              12
1205 #define EXT_VENDOR_ID_SHIFT     18
1206 
1207 /* 2 REG_GPIO_OUTSTS (For RTL8723 only) */
1208 #define EFS_HCI_SEL                             (BIT(0)|BIT(1))
1209 #define PAD_HCI_SEL                             (BIT(2)|BIT(3))
1210 #define HCI_SEL                                 (BIT(4)|BIT(5))
1211 #define PKG_SEL_HCI                             BIT(6)
1212 #define FEN_GPS                                 BIT(7)
1213 #define FEN_BT                                  BIT(8)
1214 #define FEN_WL                                  BIT(9)
1215 #define FEN_PCI                                 BIT(10)
1216 #define FEN_USB                                 BIT(11)
1217 #define BTRF_HWPDN_N                    BIT(12)
1218 #define WLRF_HWPDN_N                    BIT(13)
1219 #define PDN_BT_N                                BIT(14)
1220 #define PDN_GPS_N                               BIT(15)
1221 #define BT_CTL_HWPDN                    BIT(16)
1222 #define GPS_CTL_HWPDN                   BIT(17)
1223 #define PPHY_SUSB                               BIT(20)
1224 #define UPHY_SUSB                               BIT(21)
1225 #define PCI_SUSEN                               BIT(22)
1226 #define USB_SUSEN                               BIT(23)
1227 #define RF_RL_ID                                        (BIT(31)|BIT(30)|BIT(29)|BIT(28))
1228 
1229 
1230 /*  */
1231 /*  */
1232 /*      0x0100h ~ 0x01FFh       MACTOP General Configuration */
1233 /*  */
1234 /*  */
1235 
1236 /* 2 Function Enable Registers */
1237 /* 2 CR */
1238 #define HCI_TXDMA_EN                    BIT(0)
1239 #define HCI_RXDMA_EN                    BIT(1)
1240 #define TXDMA_EN                                BIT(2)
1241 #define RXDMA_EN                                BIT(3)
1242 #define PROTOCOL_EN                             BIT(4)
1243 #define SCHEDULE_EN                             BIT(5)
1244 #define MACTXEN                                 BIT(6)
1245 #define MACRXEN                                 BIT(7)
1246 #define ENSWBCN                                 BIT(8)
1247 #define ENSEC                                   BIT(9)
1248 #define CALTMR_EN                               BIT(10) /*  32k CAL TMR enable */
1249 
1250 /*  Network type */
1251 #define _NETTYPE(x)                             (((x) & 0x3) << 16)
1252 #define MASK_NETTYPE                    0x30000
1253 #define NT_NO_LINK                              0x0
1254 #define NT_LINK_AD_HOC                  0x1
1255 #define NT_LINK_AP                              0x2
1256 #define NT_AS_AP                                0x3
1257 
1258 /* 2 PBP - Page Size Register */
1259 #define GET_RX_PAGE_SIZE(value)                 ((value) & 0xF)
1260 #define GET_TX_PAGE_SIZE(value)                 (((value) & 0xF0) >> 4)
1261 #define _PSRX_MASK                              0xF
1262 #define _PSTX_MASK                              0xF0
1263 #define _PSRX(x)                                (x)
1264 #define _PSTX(x)                                ((x) << 4)
1265 
1266 #define PBP_64                                  0x0
1267 #define PBP_128                                 0x1
1268 #define PBP_256                                 0x2
1269 #define PBP_512                                 0x3
1270 #define PBP_1024                                0x4
1271 
1272 
1273 /* 2 TX/RXDMA */
1274 #define RXDMA_ARBBW_EN          BIT(0)
1275 #define RXSHFT_EN                               BIT(1)
1276 #define RXDMA_AGG_EN                    BIT(2)
1277 #define QS_VO_QUEUE                     BIT(8)
1278 #define QS_VI_QUEUE                             BIT(9)
1279 #define QS_BE_QUEUE                     BIT(10)
1280 #define QS_BK_QUEUE                     BIT(11)
1281 #define QS_MANAGER_QUEUE                BIT(12)
1282 #define QS_HIGH_QUEUE                   BIT(13)
1283 
1284 #define HQSEL_VOQ                               BIT(0)
1285 #define HQSEL_VIQ                               BIT(1)
1286 #define HQSEL_BEQ                               BIT(2)
1287 #define HQSEL_BKQ                               BIT(3)
1288 #define HQSEL_MGTQ                              BIT(4)
1289 #define HQSEL_HIQ                               BIT(5)
1290 
1291 /*  For normal driver, 0x10C */
1292 #define _TXDMA_CMQ_MAP(x)                       (((x)&0x3) << 16)
1293 #define _TXDMA_HIQ_MAP(x)                       (((x)&0x3) << 14)
1294 #define _TXDMA_MGQ_MAP(x)                       (((x)&0x3) << 12)
1295 #define _TXDMA_BKQ_MAP(x)                       (((x)&0x3) << 10)
1296 #define _TXDMA_BEQ_MAP(x)                       (((x)&0x3) << 8)
1297 #define _TXDMA_VIQ_MAP(x)                       (((x)&0x3) << 6)
1298 #define _TXDMA_VOQ_MAP(x)                       (((x)&0x3) << 4)
1299 
1300 #define QUEUE_EXTRA                             0
1301 #define QUEUE_LOW                               1
1302 #define QUEUE_NORMAL                    2
1303 #define QUEUE_HIGH                              3
1304 
1305 
1306 /* 2 TRXFF_BNDY */
1307 
1308 
1309 /* 2 LLT_INIT */
1310 #define _LLT_NO_ACTIVE                          0x0
1311 #define _LLT_WRITE_ACCESS                       0x1
1312 #define _LLT_READ_ACCESS                        0x2
1313 
1314 #define _LLT_INIT_DATA(x)                       ((x) & 0xFF)
1315 #define _LLT_INIT_ADDR(x)                       (((x) & 0xFF) << 8)
1316 #define _LLT_OP(x)                                      (((x) & 0x3) << 30)
1317 #define _LLT_OP_VALUE(x)                        (((x) >> 30) & 0x3)
1318 
1319 
1320 /*  */
1321 /*  */
1322 /*      0x0200h ~ 0x027Fh       TXDMA Configuration */
1323 /*  */
1324 /*  */
1325 /* 2 RQPN */
1326 #define _HPQ(x)                                 ((x) & 0xFF)
1327 #define _LPQ(x)                                 (((x) & 0xFF) << 8)
1328 #define _PUBQ(x)                                        (((x) & 0xFF) << 16)
1329 #define _NPQ(x)                                 ((x) & 0xFF)                    /*  NOTE: in RQPN_NPQ register */
1330 #define _EPQ(x)                                 (((x) & 0xFF) << 16)    /*  NOTE: in RQPN_EPQ register */
1331 
1332 
1333 #define HPQ_PUBLIC_DIS                  BIT(24)
1334 #define LPQ_PUBLIC_DIS                  BIT(25)
1335 #define LD_RQPN                                 BIT(31)
1336 
1337 
1338 /* 2 TDECTL */
1339 #define BLK_DESC_NUM_SHIFT                      4
1340 #define BLK_DESC_NUM_MASK                       0xF
1341 
1342 
1343 /* 2 TXDMA_OFFSET_CHK */
1344 #define DROP_DATA_EN                            BIT(9)
1345 
1346 /* 2 AUTO_LLT */
1347 #define BIT_SHIFT_TXPKTNUM 24
1348 #define BIT_MASK_TXPKTNUM 0xff
1349 #define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM)
1350 
1351 #define BIT_TDE_DBG_SEL BIT(23)
1352 #define BIT_AUTO_INIT_LLT BIT(16)
1353 
1354 #define BIT_SHIFT_Tx_OQT_free_space 8
1355 #define BIT_MASK_Tx_OQT_free_space 0xff
1356 #define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space)
1357 
1358 
1359 /*  */
1360 /*  */
1361 /*      0x0280h ~ 0x028Bh       RX DMA Configuration */
1362 /*  */
1363 /*  */
1364 
1365 /* 2 REG_RXDMA_CONTROL, 0x0286h */
1366 /*  Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before */
1367 /*  this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. */
1368 /* define RXPKT_RELEASE_POLL                    BIT(0) */
1369 /*  Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in */
1370 /*  this bit. FW can start releasing packets after RXDMA entering idle mode. */
1371 /* define RXDMA_IDLE                                    BIT(1) */
1372 /*  When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host */
1373 /*  completed, and stop DMA packet to host. RXDMA will then report Default: 0; */
1374 /* define RW_RELEASE_EN                         BIT(2) */
1375 
1376 /* 2 REG_RXPKT_NUM, 0x0284 */
1377 #define         RXPKT_RELEASE_POLL      BIT(16)
1378 #define RXDMA_IDLE                              BIT(17)
1379 #define RW_RELEASE_EN                   BIT(18)
1380 
1381 /*  */
1382 /*  */
1383 /*      0x0400h ~ 0x047Fh       Protocol Configuration */
1384 /*  */
1385 /*  */
1386 /* 2 FWHW_TXQ_CTRL */
1387 #define EN_AMPDU_RTY_NEW                        BIT(7)
1388 
1389 
1390 /* 2 SPEC SIFS */
1391 #define _SPEC_SIFS_CCK(x)                       ((x) & 0xFF)
1392 #define _SPEC_SIFS_OFDM(x)                      (((x) & 0xFF) << 8)
1393 
1394 /* 2 RL */
1395 #define RETRY_LIMIT_SHORT_SHIFT                 8
1396 #define RETRY_LIMIT_LONG_SHIFT                  0
1397 
1398 /*  */
1399 /*  */
1400 /*      0x0500h ~ 0x05FFh       EDCA Configuration */
1401 /*  */
1402 /*  */
1403 
1404 /* 2 EDCA setting */
1405 #define AC_PARAM_TXOP_LIMIT_OFFSET              16
1406 #define AC_PARAM_ECW_MAX_OFFSET                 12
1407 #define AC_PARAM_ECW_MIN_OFFSET                 8
1408 #define AC_PARAM_AIFS_OFFSET                            0
1409 
1410 
1411 #define _LRL(x)                                 ((x) & 0x3F)
1412 #define _SRL(x)                                 (((x) & 0x3F) << 8)
1413 
1414 
1415 /* 2 BCN_CTRL */
1416 #define EN_TXBCN_RPT                    BIT(2)
1417 #define EN_BCN_FUNCTION         BIT(3)
1418 #define STOP_BCNQ                               BIT(6)
1419 #define DIS_RX_BSSID_FIT                BIT(6)
1420 
1421 #define DIS_ATIM                                        BIT(0)
1422 #define DIS_BCNQ_SUB                    BIT(1)
1423 #define DIS_TSF_UDT                             BIT(4)
1424 
1425 /*  The same function but different bit field. */
1426 #define DIS_TSF_UDT0_NORMAL_CHIP        BIT(4)
1427 #define DIS_TSF_UDT0_TEST_CHIP  BIT(5)
1428 
1429 
1430 /* 2 ACMHWCTRL */
1431 #define AcmHw_HwEn                              BIT(0)
1432 #define AcmHw_BeqEn                     BIT(1)
1433 #define AcmHw_ViqEn                             BIT(2)
1434 #define AcmHw_VoqEn                     BIT(3)
1435 #define AcmHw_BeqStatus         BIT(4)
1436 #define AcmHw_ViqStatus                 BIT(5)
1437 #define AcmHw_VoqStatus         BIT(6)
1438 
1439 /* 2 REG_DUAL_TSF_RST (0x553) */
1440 #define DUAL_TSF_RST_P2P                BIT(4)
1441 
1442 /* 2  REG_NOA_DESC_SEL (0x5CF) */
1443 #define NOA_DESC_SEL_0                  0
1444 #define NOA_DESC_SEL_1                  BIT(4)
1445 
1446 /*  */
1447 /*  */
1448 /*      0x0600h ~ 0x07FFh       WMAC Configuration */
1449 /*  */
1450 /*  */
1451 
1452 /* 2 APSD_CTRL */
1453 #define APSDOFF                                 BIT(6)
1454 
1455 /* 2 TCR */
1456 #define TSFRST                                  BIT(0)
1457 #define DIS_GCLK                                        BIT(1)
1458 #define PAD_SEL                                 BIT(2)
1459 #define PWR_ST                                  BIT(6)
1460 #define PWRBIT_OW_EN                    BIT(7)
1461 #define ACRC                                            BIT(8)
1462 #define CFENDFORM                               BIT(9)
1463 #define ICV                                             BIT(10)
1464 
1465 
1466 /* 2 RCR */
1467 #define AAP                                             BIT(0)
1468 #define APM                                             BIT(1)
1469 #define AM                                              BIT(2)
1470 #define AB                                              BIT(3)
1471 #define ADD3                                            BIT(4)
1472 #define APWRMGT                         BIT(5)
1473 #define CBSSID                                  BIT(6)
1474 #define CBSSID_DATA                             BIT(6)
1475 #define CBSSID_BCN                              BIT(7)
1476 #define ACRC32                                  BIT(8)
1477 #define AICV                                            BIT(9)
1478 #define ADF                                             BIT(11)
1479 #define ACF                                             BIT(12)
1480 #define AMF                                             BIT(13)
1481 #define HTC_LOC_CTRL                    BIT(14)
1482 #define UC_DATA_EN                              BIT(16)
1483 #define BM_DATA_EN                              BIT(17)
1484 #define MFBEN                                   BIT(22)
1485 #define LSIGEN                                  BIT(23)
1486 #define EnMBID                                  BIT(24)
1487 #define FORCEACK                                BIT(26)
1488 #define APP_BASSN                               BIT(27)
1489 #define APP_PHYSTS                              BIT(28)
1490 #define APP_ICV                                 BIT(29)
1491 #define APP_MIC                                 BIT(30)
1492 #define APP_FCS                                 BIT(31)
1493 
1494 
1495 /* 2 SECCFG */
1496 #define SCR_TxUseDK                             BIT(0)                  /* Force Tx Use Default Key */
1497 #define SCR_RxUseDK                             BIT(1)                  /* Force Rx Use Default Key */
1498 #define SCR_TxEncEnable                 BIT(2)                  /* Enable Tx Encryption */
1499 #define SCR_RxDecEnable                 BIT(3)                  /* Enable Rx Decryption */
1500 #define SCR_SKByA2                              BIT(4)                  /* Search kEY BY A2 */
1501 #define SCR_NoSKMC                              BIT(5)                  /* No Key Search Multicast */
1502 #define SCR_TXBCUSEDK                   BIT(6)                  /*  Force Tx Broadcast packets Use Default Key */
1503 #define SCR_RXBCUSEDK                   BIT(7)                  /*  Force Rx Broadcast packets Use Default Key */
1504 #define SCR_CHK_KEYID                   BIT(8)
1505 
1506 /*  */
1507 /*  */
1508 /*      SDIO Bus Specification */
1509 /*  */
1510 /*  */
1511 
1512 /*  I/O bus domain address mapping */
1513 #define SDIO_LOCAL_BASE         0x10250000
1514 #define WLAN_IOREG_BASE         0x10260000
1515 #define FIRMWARE_FIFO_BASE      0x10270000
1516 #define TX_HIQ_BASE                             0x10310000
1517 #define TX_MIQ_BASE                             0x10320000
1518 #define TX_LOQ_BASE                             0x10330000
1519 #define TX_EPQ_BASE                             0x10350000
1520 #define RX_RX0FF_BASE                   0x10340000
1521 
1522 /* SDIO host local register space mapping. */
1523 #define SDIO_LOCAL_MSK                          0x0FFF
1524 #define WLAN_IOREG_MSK                  0x7FFF
1525 #define WLAN_FIFO_MSK                           0x1FFF  /*  Aggregation Length[12:0] */
1526 #define WLAN_RX0FF_MSK                          0x0003
1527 
1528 #define SDIO_WITHOUT_REF_DEVICE_ID      0       /*  Without reference to the SDIO Device ID */
1529 #define SDIO_LOCAL_DEVICE_ID                    0       /*  0b[16], 000b[15:13] */
1530 #define WLAN_TX_HIQ_DEVICE_ID                   4       /*  0b[16], 100b[15:13] */
1531 #define WLAN_TX_MIQ_DEVICE_ID           5       /*  0b[16], 101b[15:13] */
1532 #define WLAN_TX_LOQ_DEVICE_ID           6       /*  0b[16], 110b[15:13] */
1533 #define WLAN_TX_EXQ_DEVICE_ID           3       /*  0b[16], 011b[15:13] */
1534 #define WLAN_RX0FF_DEVICE_ID                    7       /*  0b[16], 111b[15:13] */
1535 #define WLAN_IOREG_DEVICE_ID                    8       /*  1b[16] */
1536 
1537 /* SDIO Tx Free Page Index */
1538 #define HI_QUEUE_IDX                            0
1539 #define MID_QUEUE_IDX                           1
1540 #define LOW_QUEUE_IDX                           2
1541 #define PUBLIC_QUEUE_IDX                        3
1542 
1543 #define SDIO_MAX_TX_QUEUE                       3               /*  HIQ, MIQ and LOQ */
1544 #define SDIO_MAX_RX_QUEUE                       1
1545 
1546 #define SDIO_REG_TX_CTRL                        0x0000 /*  SDIO Tx Control */
1547 #define SDIO_REG_HIMR                           0x0014 /*  SDIO Host Interrupt Mask */
1548 #define SDIO_REG_HISR                           0x0018 /*  SDIO Host Interrupt Service Routine */
1549 #define SDIO_REG_HCPWM                  0x0019 /*  HCI Current Power Mode */
1550 #define SDIO_REG_RX0_REQ_LEN            0x001C /*  RXDMA Request Length */
1551 #define SDIO_REG_OQT_FREE_PG            0x001E /*  OQT Free Page */
1552 #define SDIO_REG_FREE_TXPG                      0x0020 /*  Free Tx Buffer Page */
1553 #define SDIO_REG_HCPWM1                 0x0024 /*  HCI Current Power Mode 1 */
1554 #define SDIO_REG_HCPWM2                 0x0026 /*  HCI Current Power Mode 2 */
1555 #define SDIO_REG_FREE_TXPG_SEQ  0x0028 /*  Free Tx Page Sequence */
1556 #define SDIO_REG_HTSFR_INFO             0x0030 /*  HTSF Informaion */
1557 #define SDIO_REG_HRPWM1                 0x0080 /*  HCI Request Power Mode 1 */
1558 #define SDIO_REG_HRPWM2                 0x0082 /*  HCI Request Power Mode 2 */
1559 #define SDIO_REG_HPS_CLKR                       0x0084 /*  HCI Power Save Clock */
1560 #define SDIO_REG_HSUS_CTRL                      0x0086 /*  SDIO HCI Suspend Control */
1561 #define SDIO_REG_HIMR_ON                        0x0090 /* SDIO Host Extension Interrupt Mask Always */
1562 #define SDIO_REG_HISR_ON                        0x0091 /* SDIO Host Extension Interrupt Status Always */
1563 
1564 #define SDIO_HIMR_DISABLED                      0
1565 
1566 /*  RTL8723/RTL8188E SDIO Host Interrupt Mask Register */
1567 #define SDIO_HIMR_RX_REQUEST_MSK                BIT0
1568 #define SDIO_HIMR_AVAL_MSK                      BIT1
1569 #define SDIO_HIMR_TXERR_MSK                     BIT2
1570 #define SDIO_HIMR_RXERR_MSK                     BIT3
1571 #define SDIO_HIMR_TXFOVW_MSK                    BIT4
1572 #define SDIO_HIMR_RXFOVW_MSK                    BIT5
1573 #define SDIO_HIMR_TXBCNOK_MSK                   BIT6
1574 #define SDIO_HIMR_TXBCNERR_MSK          BIT7
1575 #define SDIO_HIMR_BCNERLY_INT_MSK               BIT16
1576 #define SDIO_HIMR_C2HCMD_MSK                    BIT17
1577 #define SDIO_HIMR_CPWM1_MSK                     BIT18
1578 #define SDIO_HIMR_CPWM2_MSK                     BIT19
1579 #define SDIO_HIMR_HSISR_IND_MSK         BIT20
1580 #define SDIO_HIMR_GTINT3_IND_MSK                BIT21
1581 #define SDIO_HIMR_GTINT4_IND_MSK                BIT22
1582 #define SDIO_HIMR_PSTIMEOUT_MSK         BIT23
1583 #define SDIO_HIMR_OCPINT_MSK                    BIT24
1584 #define SDIO_HIMR_ATIMEND_MSK                   BIT25
1585 #define SDIO_HIMR_ATIMEND_E_MSK         BIT26
1586 #define SDIO_HIMR_CTWEND_MSK                    BIT27
1587 
1588 /* RTL8188E SDIO Specific */
1589 #define SDIO_HIMR_MCU_ERR_MSK                   BIT28
1590 #define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK          BIT29
1591 
1592 /*  SDIO Host Interrupt Service Routine */
1593 #define SDIO_HISR_RX_REQUEST                    BIT0
1594 #define SDIO_HISR_AVAL                                  BIT1
1595 #define SDIO_HISR_TXERR                                 BIT2
1596 #define SDIO_HISR_RXERR                                 BIT3
1597 #define SDIO_HISR_TXFOVW                                BIT4
1598 #define SDIO_HISR_RXFOVW                                BIT5
1599 #define SDIO_HISR_TXBCNOK                               BIT6
1600 #define SDIO_HISR_TXBCNERR                              BIT7
1601 #define SDIO_HISR_BCNERLY_INT                   BIT16
1602 #define SDIO_HISR_C2HCMD                                BIT17
1603 #define SDIO_HISR_CPWM1                         BIT18
1604 #define SDIO_HISR_CPWM2                         BIT19
1605 #define SDIO_HISR_HSISR_IND                     BIT20
1606 #define SDIO_HISR_GTINT3_IND                    BIT21
1607 #define SDIO_HISR_GTINT4_IND                    BIT22
1608 #define SDIO_HISR_PSTIMEOUT                     BIT23
1609 #define SDIO_HISR_OCPINT                                BIT24
1610 #define SDIO_HISR_ATIMEND                               BIT25
1611 #define SDIO_HISR_ATIMEND_E                     BIT26
1612 #define SDIO_HISR_CTWEND                                BIT27
1613 
1614 /* RTL8188E SDIO Specific */
1615 #define SDIO_HISR_MCU_ERR                               BIT28
1616 #define SDIO_HISR_TSF_BIT32_TOGGLE      BIT29
1617 
1618 #define MASK_SDIO_HISR_CLEAR            (SDIO_HISR_TXERR |\
1619                                                                         SDIO_HISR_RXERR |\
1620                                                                         SDIO_HISR_TXFOVW |\
1621                                                                         SDIO_HISR_RXFOVW |\
1622                                                                         SDIO_HISR_TXBCNOK |\
1623                                                                         SDIO_HISR_TXBCNERR |\
1624                                                                         SDIO_HISR_C2HCMD |\
1625                                                                         SDIO_HISR_CPWM1 |\
1626                                                                         SDIO_HISR_CPWM2 |\
1627                                                                         SDIO_HISR_HSISR_IND |\
1628                                                                         SDIO_HISR_GTINT3_IND |\
1629                                                                         SDIO_HISR_GTINT4_IND |\
1630                                                                         SDIO_HISR_PSTIMEOUT |\
1631                                                                         SDIO_HISR_OCPINT)
1632 
1633 /*  SDIO HCI Suspend Control Register */
1634 #define HCI_RESUME_PWR_RDY                      BIT1
1635 #define HCI_SUS_CTRL                                    BIT0
1636 
1637 /*  SDIO Tx FIFO related */
1638 #define SDIO_TX_FREE_PG_QUEUE                   4       /*  The number of Tx FIFO free page */
1639 #define SDIO_TX_FIFO_PAGE_SZ                    128
1640 
1641 #define MAX_TX_AGG_PACKET_NUMBER        0x8
1642 
1643 /*  */
1644 /*  */
1645 /*      0xFE00h ~ 0xFE55h       USB Configuration */
1646 /*  */
1647 /*  */
1648 
1649 /* 2 USB Information (0xFE17) */
1650 #define USB_IS_HIGH_SPEED                       0
1651 #define USB_IS_FULL_SPEED                       1
1652 #define USB_SPEED_MASK                          BIT(5)
1653 
1654 #define USB_NORMAL_SIE_EP_MASK  0xF
1655 #define USB_NORMAL_SIE_EP_SHIFT 4
1656 
1657 /* 2 Special Option */
1658 #define USB_AGG_EN                              BIT(3)
1659 
1660 /*  0; Use interrupt endpoint to upload interrupt pkt */
1661 /*  1; Use bulk endpoint to upload interrupt pkt, */
1662 #define INT_BULK_SEL                    BIT(4)
1663 
1664 /* 2REG_C2HEVT_CLEAR */
1665 #define C2H_EVT_HOST_CLOSE              0x00    /*  Set by driver and notify FW that the driver has read the C2H command message */
1666 #define C2H_EVT_FW_CLOSE                0xFF    /*  Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */
1667 
1668 
1669 /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */
1670 #define WL_HWPDN_EN                     BIT0    /*  Enable GPIO[9] as WiFi HW PDn source */
1671 #define WL_HWPDN_SL                     BIT1    /*  WiFi HW PDn polarity control */
1672 #define WL_FUNC_EN                              BIT2    /*  WiFi function enable */
1673 #define WL_HWROF_EN                     BIT3    /*  Enable GPIO[9] as WiFi RF HW PDn source */
1674 #define BT_HWPDN_EN                     BIT16   /*  Enable GPIO[11] as BT HW PDn source */
1675 #define BT_HWPDN_SL                     BIT17   /*  BT HW PDn polarity control */
1676 #define BT_FUNC_EN                              BIT18   /*  BT function enable */
1677 #define BT_HWROF_EN                     BIT19   /*  Enable GPIO[11] as BT/GPS RF HW PDn source */
1678 #define GPS_HWPDN_EN                    BIT20   /*  Enable GPIO[10] as GPS HW PDn source */
1679 #define GPS_HWPDN_SL                    BIT21   /*  GPS HW PDn polarity control */
1680 #define GPS_FUNC_EN                     BIT22   /*  GPS function enable */
1681 
1682 /* 3 REG_LIFECTRL_CTRL */
1683 #define HAL92C_EN_PKT_LIFE_TIME_BK              BIT3
1684 #define HAL92C_EN_PKT_LIFE_TIME_BE              BIT2
1685 #define HAL92C_EN_PKT_LIFE_TIME_VI              BIT1
1686 #define HAL92C_EN_PKT_LIFE_TIME_VO              BIT0
1687 
1688 #define HAL92C_MSDU_LIFE_TIME_UNIT              128     /*  in us, said by Tim. */
1689 
1690 /* 2 8192D PartNo. */
1691 #define PARTNO_92D_NIC                                                  (BIT7|BIT6)
1692 #define PARTNO_92D_NIC_REMARK                           (BIT5|BIT4)
1693 #define PARTNO_SINGLE_BAND_VS                           BIT3
1694 #define PARTNO_SINGLE_BAND_VS_REMARK            BIT1
1695 #define PARTNO_CONCURRENT_BAND_VC                       (BIT3|BIT2)
1696 #define PARTNO_CONCURRENT_BAND_VC_REMARK        (BIT1|BIT0)
1697 
1698 /*  */
1699 /*  General definitions */
1700 /*  */
1701 
1702 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E               176
1703 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8812                        255
1704 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B               255
1705 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C               255
1706 #define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC    127
1707 
1708 #define POLLING_LLT_THRESHOLD                           20
1709 #define POLLING_READY_TIMEOUT_COUNT             1000
1710 
1711 
1712 /*  GPIO BIT */
1713 #define HAL_8192C_HW_GPIO_WPS_BIT       BIT2
1714 #define HAL_8192EU_HW_GPIO_WPS_BIT      BIT7
1715 #define HAL_8188E_HW_GPIO_WPS_BIT       BIT7
1716 
1717 #endif /* __HAL_COMMON_H__ */