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7 #ifndef __HAL_PHY_H__
8 #define __HAL_PHY_H__
9
10
11 #if DISABLE_BB_RF
12 #define HAL_FW_ENABLE 0
13 #define HAL_MAC_ENABLE 0
14 #define HAL_BB_ENABLE 0
15 #define HAL_RF_ENABLE 0
16 #else
17 #define HAL_FW_ENABLE 1
18 #define HAL_MAC_ENABLE 1
19 #define HAL_BB_ENABLE 1
20 #define HAL_RF_ENABLE 1
21 #endif
22
23 #define RF6052_MAX_TX_PWR 0x3F
24 #define RF6052_MAX_REG_88E 0xFF
25 #define RF6052_MAX_REG_92C 0x7F
26
27 #define RF6052_MAX_REG \
28 (RF6052_MAX_REG_88E > RF6052_MAX_REG_92C) ? RF6052_MAX_REG_88E: RF6052_MAX_REG_92C
29
30 #define GET_RF6052_REAL_MAX_REG(_Adapter) RF6052_MAX_REG_92C
31
32 #define RF6052_MAX_PATH 2
33
34
35
36
37
38 #define ANT_DETECT_BY_SINGLE_TONE BIT0
39 #define ANT_DETECT_BY_RSSI BIT1
40 #define IS_ANT_DETECT_SUPPORT_SINGLE_TONE(__Adapter) ((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_SINGLE_TONE)
41 #define IS_ANT_DETECT_SUPPORT_RSSI(__Adapter) ((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_RSSI)
42
43
44
45 enum BAND_TYPE {
46 BAND_ON_2_4G = 0,
47 BAND_ON_5G,
48 BAND_ON_BOTH,
49 BANDMAX
50 };
51
52 enum RF_TYPE {
53 RF_TYPE_MIN = 0,
54 RF_8225 = 1,
55 RF_8256 = 2,
56 RF_8258 = 3,
57 RF_6052 = 4,
58 RF_PSEUDO_11N = 5,
59 RF_TYPE_MAX
60 };
61
62 enum RF_PATH {
63 RF_PATH_A = 0,
64 RF_PATH_B,
65 RF_PATH_C,
66 RF_PATH_D
67 };
68
69 #define TX_1S 0
70 #define TX_2S 1
71 #define TX_3S 2
72 #define TX_4S 3
73
74 #define RF_PATH_MAX_92C_88E 2
75 #define RF_PATH_MAX_90_8812 4
76
77 enum ANTENNA_PATH {
78 ANTENNA_NONE = 0,
79 ANTENNA_D = 1,
80 ANTENNA_C = 2,
81 ANTENNA_CD = 3,
82 ANTENNA_B = 4,
83 ANTENNA_BD = 5,
84 ANTENNA_BC = 6,
85 ANTENNA_BCD = 7,
86 ANTENNA_A = 8,
87 ANTENNA_AD = 9,
88 ANTENNA_AC = 10,
89 ANTENNA_ACD = 11,
90 ANTENNA_AB = 12,
91 ANTENNA_ABD = 13,
92 ANTENNA_ABC = 14,
93 ANTENNA_ABCD = 15
94 };
95
96 enum RF_CONTENT {
97 radioa_txt = 0x1000,
98 radiob_txt = 0x1001,
99 radioc_txt = 0x1002,
100 radiod_txt = 0x1003
101 };
102
103 enum BaseBand_Config_Type {
104 BaseBand_Config_PHY_REG = 0,
105 BaseBand_Config_AGC_TAB = 1,
106 BaseBand_Config_AGC_TAB_2G = 2,
107 BaseBand_Config_AGC_TAB_5G = 3,
108 BaseBand_Config_PHY_REG_PG
109 };
110
111 enum HW_BLOCK {
112 HW_BLOCK_MAC = 0,
113 HW_BLOCK_PHY0 = 1,
114 HW_BLOCK_PHY1 = 2,
115 HW_BLOCK_RF = 3,
116 HW_BLOCK_MAXIMUM = 4,
117 };
118
119 enum WIRELESS_MODE {
120 WIRELESS_MODE_UNKNOWN = 0x00,
121 WIRELESS_MODE_A = 0x01,
122 WIRELESS_MODE_B = 0x02,
123 WIRELESS_MODE_G = 0x04,
124 WIRELESS_MODE_AUTO = 0x08,
125 WIRELESS_MODE_N_24G = 0x10,
126 WIRELESS_MODE_N_5G = 0x20,
127 WIRELESS_MODE_AC_5G = 0x40,
128 WIRELESS_MODE_AC_24G = 0x80,
129 WIRELESS_MODE_AC_ONLY = 0x100,
130 };
131
132 enum SwChnlCmdID {
133 CmdID_End,
134 CmdID_SetTxPowerLevel,
135 CmdID_BBRegWrite10,
136 CmdID_WritePortUlong,
137 CmdID_WritePortUshort,
138 CmdID_WritePortUchar,
139 CmdID_RF_WriteReg,
140 };
141
142 struct SwChnlCmd {
143 enum SwChnlCmdID CmdID;
144 u32 Para1;
145 u32 Para2;
146 u32 msDelay;
147 };
148
149 struct R_ANTENNA_SELECT_OFDM {
150 #ifdef __LITTLE_ENDIAN
151 u32 r_tx_antenna:4;
152 u32 r_ant_l:4;
153 u32 r_ant_non_ht:4;
154 u32 r_ant_ht1:4;
155 u32 r_ant_ht2:4;
156 u32 r_ant_ht_s1:4;
157 u32 r_ant_non_ht_s1:4;
158 u32 OFDM_TXSC:2;
159 u32 Reserved:2;
160 #else
161 u32 Reserved:2;
162 u32 OFDM_TXSC:2;
163 u32 r_ant_non_ht_s1:4;
164 u32 r_ant_ht_s1:4;
165 u32 r_ant_ht2:4;
166 u32 r_ant_ht1:4;
167 u32 r_ant_non_ht:4;
168 u32 r_ant_l:4;
169 u32 r_tx_antenna:4;
170 #endif
171 };
172
173
174
175 #endif