root/drivers/staging/rtl8723bs/hal/odm_HWConfig.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7 
   8 
   9 #ifndef __HALHWOUTSRC_H__
  10 #define __HALHWOUTSRC_H__
  11 
  12 
  13 /*--------------------------Define -------------------------------------------*/
  14 /* define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0) */
  15 #define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \
  16         sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u32)))
  17 #define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \
  18         sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u32)))
  19 
  20 #define AGC_DIFF_CONFIG(ic, band)\
  21         do {\
  22                 if (pDM_Odm->bIsMPChip)\
  23                         AGC_DIFF_CONFIG_MP(ic, band);\
  24                 else\
  25                         AGC_DIFF_CONFIG_TC(ic, band);\
  26         } while (0)
  27 
  28 
  29 /*  */
  30 /*  structure and define */
  31 /*  */
  32 
  33 typedef struct _Phy_Rx_AGC_Info {
  34         #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
  35                 u8 gain:7, trsw:1;
  36         #else
  37                 u8 trsw:1, gain:7;
  38         #endif
  39 } PHY_RX_AGC_INFO_T, *pPHY_RX_AGC_INFO_T;
  40 
  41 typedef struct _Phy_Status_Rpt_8192cd {
  42         PHY_RX_AGC_INFO_T path_agc[2];
  43         u8 ch_corr[2];
  44         u8 cck_sig_qual_ofdm_pwdb_all;
  45         u8 cck_agc_rpt_ofdm_cfosho_a;
  46         u8 cck_rpt_b_ofdm_cfosho_b;
  47         u8 rsvd_1;/* ch_corr_msb; */
  48         u8 noise_power_db_msb;
  49         s8 path_cfotail[2];
  50         u8 pcts_mask[2];
  51         s8 stream_rxevm[2];
  52         u8 path_rxsnr[2];
  53         u8 noise_power_db_lsb;
  54         u8 rsvd_2[3];
  55         u8 stream_csi[2];
  56         u8 stream_target_csi[2];
  57         s8      sig_evm;
  58         u8 rsvd_3;
  59 
  60 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
  61         u8 antsel_rx_keep_2:1;  /* ex_intf_flg:1; */
  62         u8 sgi_en:1;
  63         u8 rxsc:2;
  64         u8 idle_long:1;
  65         u8 r_ant_train_en:1;
  66         u8 ant_sel_b:1;
  67         u8 ant_sel:1;
  68 #else   /*  _BIG_ENDIAN_ */
  69         u8 ant_sel:1;
  70         u8 ant_sel_b:1;
  71         u8 r_ant_train_en:1;
  72         u8 idle_long:1;
  73         u8 rxsc:2;
  74         u8 sgi_en:1;
  75         u8 antsel_rx_keep_2:1;  /* ex_intf_flg:1; */
  76 #endif
  77 } PHY_STATUS_RPT_8192CD_T, *PPHY_STATUS_RPT_8192CD_T;
  78 
  79 
  80 typedef struct _Phy_Status_Rpt_8812 {
  81         /* 2012.05.24 LukeLee: This structure should take big/little endian in consideration later..... */
  82 
  83         /* DWORD 0 */
  84         u8 gain_trsw[2];
  85 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
  86         u16 chl_num:10;
  87         u16 sub_chnl:4;
  88         u16 r_RFMOD:2;
  89 #else   /*  _BIG_ENDIAN_ */
  90         u16 r_RFMOD:2;
  91         u16 sub_chnl:4;
  92         u16 chl_num:10;
  93 #endif
  94 
  95         /* DWORD 1 */
  96         u8 pwdb_all;
  97         u8 cfosho[4];   /*  DW 1 byte 1 DW 2 byte 0 */
  98 
  99         /* DWORD 2 */
 100         s8 cfotail[4]; /*  DW 2 byte 1 DW 3 byte 0 */
 101 
 102         /* DWORD 3 */
 103         s8 rxevm[2]; /*  DW 3 byte 1 DW 3 byte 2 */
 104         s8 rxsnr[2]; /*  DW 3 byte 3 DW 4 byte 0 */
 105 
 106         /* DWORD 4 */
 107         u8 PCTS_MSK_RPT[2];
 108         u8 pdsnr[2]; /*  DW 4 byte 3 DW 5 Byte 0 */
 109 
 110         /* DWORD 5 */
 111         u8 csi_current[2];
 112         u8 rx_gain_c;
 113 
 114         /* DWORD 6 */
 115         u8 rx_gain_d;
 116         s8 sigevm;
 117         u8 resvd_0;
 118         u8 antidx_anta:3;
 119         u8 antidx_antb:3;
 120         u8 resvd_1:2;
 121 } PHY_STATUS_RPT_8812_T, *PPHY_STATUS_RPT_8812_T;
 122 
 123 
 124 void ODM_PhyStatusQuery(
 125         PDM_ODM_T pDM_Odm,
 126         struct odm_phy_info *pPhyInfo,
 127         u8 *pPhyStatus,
 128         struct odm_packet_info *pPktinfo
 129 );
 130 
 131 HAL_STATUS ODM_ConfigRFWithTxPwrTrackHeaderFile(PDM_ODM_T pDM_Odm);
 132 
 133 HAL_STATUS ODM_ConfigRFWithHeaderFile(
 134         PDM_ODM_T pDM_Odm,
 135         ODM_RF_Config_Type ConfigType,
 136         ODM_RF_RADIO_PATH_E eRFPath
 137 );
 138 
 139 HAL_STATUS ODM_ConfigBBWithHeaderFile(
 140         PDM_ODM_T pDM_Odm, ODM_BB_Config_Type ConfigType
 141 );
 142 
 143 HAL_STATUS ODM_ConfigFWWithHeaderFile(
 144         PDM_ODM_T pDM_Odm,
 145         ODM_FW_Config_Type ConfigType,
 146         u8 *pFirmware,
 147         u32 *pSize
 148 );
 149 
 150 s32 odm_SignalScaleMapping(PDM_ODM_T pDM_Odm, s32 CurrSig);
 151 
 152 #endif