drivers/staging/rtl8723bs/hal/odm.h

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   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7 
   8 
   9 #ifndef __HALDMOUTSRC_H__
  10 #define __HALDMOUTSRC_H__
  11 
  12 #include "odm_EdcaTurboCheck.h"
  13 #include "odm_DIG.h"
  14 #include "odm_PathDiv.h"
  15 #include "odm_DynamicBBPowerSaving.h"
  16 #include "odm_DynamicTxPower.h"
  17 #include "odm_CfoTracking.h"
  18 #include "odm_NoiseMonitor.h"
  19 
  20 #define TP_MODE         0
  21 #define RSSI_MODE               1
  22 #define TRAFFIC_LOW     0
  23 #define TRAFFIC_HIGH    1
  24 #define NONE                    0
  25 
  26 /* 3 Tx Power Tracking */
  27 /* 3 ============================================================ */
  28 #define         DPK_DELTA_MAPPING_NUM   13
  29 #define         index_mapping_HP_NUM    15
  30 #define OFDM_TABLE_SIZE         43
  31 #define CCK_TABLE_SIZE                  33
  32 #define TXSCALE_TABLE_SIZE              37
  33 #define TXPWR_TRACK_TABLE_SIZE  30
  34 #define DELTA_SWINGIDX_SIZE     30
  35 #define BAND_NUM                                4
  36 
  37 /* 3 PSD Handler */
  38 /* 3 ============================================================ */
  39 
  40 #define AFH_PSD         1       /* 0:normal PSD scan, 1: only do 20 pts PSD */
  41 #define MODE_40M                0       /* 0:20M, 1:40M */
  42 #define PSD_TH2         3
  43 #define PSD_CHMIN               20   /*  Minimum channel number for BT AFH */
  44 #define SIR_STEP_SIZE   3
  45 #define   Smooth_Size_1         5
  46 #define Smooth_TH_1     3
  47 #define   Smooth_Size_2         10
  48 #define Smooth_TH_2     4
  49 #define   Smooth_Size_3         20
  50 #define Smooth_TH_3     4
  51 #define   Smooth_Step_Size 5
  52 #define Adaptive_SIR    1
  53 #define PSD_RESCAN              4
  54 #define PSD_SCAN_INTERVAL       700 /* ms */
  55 
  56 /* 8723A High Power IGI Setting */
  57 #define         DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
  58 #define                 DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
  59 #define         DM_DIG_HIGH_PWR_THRESHOLD       0x3a
  60 #define         DM_DIG_LOW_PWR_THRESHOLD        0x14
  61 
  62 /* ANT Test */
  63 #define                 ANTTESTALL              0x00            /* Ant A or B will be Testing */
  64 #define         ANTTESTA                0x01            /* Ant A will be Testing */
  65 #define         ANTTESTB                0x02            /* Ant B will be testing */
  66 
  67 #define PS_MODE_ACTIVE 0x01
  68 
  69 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */
  70 #define         MAIN_ANT                1               /* Ant A or Ant Main */
  71 #define         AUX_ANT         2               /* AntB or Ant Aux */
  72 #define         MAX_ANT         3               /*  3 for AP using */
  73 
  74 /* Antenna Diversity Type */
  75 #define SW_ANTDIV       0
  76 #define HW_ANTDIV       1
  77 /*  structure and define */
  78 
  79 /* Remove DIG by Yuchen */
  80 
  81 /* Remoce BB power saving by Yuchn */
  82 
  83 /* Remove DIG by yuchen */
  84 
  85 struct dynamic_primary_CCA {
  86         u8 PriCCA_flag;
  87         u8 intf_flag;
  88         u8 intf_type;
  89         u8 DupRTS_flag;
  90         u8 Monitor_flag;
  91         u8 CH_offset;
  92         u8 MF_state;
  93 };
  94 
  95 typedef struct _Rate_Adaptive_Table_ {
  96         u8 firstconnect;
  97 } RA_T, *pRA_T;
  98 
  99 typedef struct _RX_High_Power_ {
 100         u8 RXHP_flag;
 101         u8 PSD_func_trigger;
 102         u8 PSD_bitmap_RXHP[80];
 103         u8 Pre_IGI;
 104         u8 Cur_IGI;
 105         u8 Pre_pw_th;
 106         u8 Cur_pw_th;
 107         bool First_time_enter;
 108         bool RXHP_enable;
 109         u8 TP_Mode;
 110         RT_TIMER PSDTimer;
 111 } RXHP_T, *pRXHP_T;
 112 
 113 #define ASSOCIATE_ENTRY_NUM                                     32 /*  Max size of AsocEntry[]. */
 114 #define ODM_ASSOCIATE_ENTRY_NUM                         ASSOCIATE_ENTRY_NUM
 115 
 116 /*  This indicates two different the steps. */
 117 /*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
 118 /*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
 119 /*  with original RSSI to determine if it is necessary to switch antenna. */
 120 #define SWAW_STEP_PEAK          0
 121 #define SWAW_STEP_DETERMINE     1
 122 
 123 #define TP_MODE         0
 124 #define RSSI_MODE               1
 125 #define TRAFFIC_LOW     0
 126 #define TRAFFIC_HIGH    1
 127 #define TRAFFIC_UltraLOW        2
 128 
 129 typedef struct _SW_Antenna_Switch_ {
 130         u8 Double_chk_flag;
 131         u8 try_flag;
 132         s32 PreRSSI;
 133         u8 CurAntenna;
 134         u8 PreAntenna;
 135         u8 RSSI_Trying;
 136         u8 TestMode;
 137         u8 bTriggerAntennaSwitch;
 138         u8 SelectAntennaMap;
 139         u8 RSSI_target;
 140         u8 reset_idx;
 141         u16 Single_Ant_Counter;
 142         u16 Dual_Ant_Counter;
 143         u16 Aux_FailDetec_Counter;
 144         u16 Retry_Counter;
 145 
 146         /*  Before link Antenna Switch check */
 147         u8 SWAS_NoLink_State;
 148         u32 SWAS_NoLink_BK_Reg860;
 149         u32 SWAS_NoLink_BK_Reg92c;
 150         u32 SWAS_NoLink_BK_Reg948;
 151         bool ANTA_ON;   /* To indicate Ant A is or not */
 152         bool ANTB_ON;   /* To indicate Ant B is on or not */
 153         bool Pre_Aux_FailDetec;
 154         bool RSSI_AntDect_bResult;
 155         u8 Ant5G;
 156         u8 Ant2G;
 157 
 158         s32 RSSI_sum_A;
 159         s32 RSSI_sum_B;
 160         s32 RSSI_cnt_A;
 161         s32 RSSI_cnt_B;
 162 
 163         u64 lastTxOkCnt;
 164         u64 lastRxOkCnt;
 165         u64 TXByteCnt_A;
 166         u64 TXByteCnt_B;
 167         u64 RXByteCnt_A;
 168         u64 RXByteCnt_B;
 169         u8 TrafficLoad;
 170         u8 Train_time;
 171         u8 Train_time_flag;
 172         RT_TIMER SwAntennaSwitchTimer;
 173         RT_TIMER SwAntennaSwitchTimer_8723B;
 174         u32 PktCnt_SWAntDivByCtrlFrame;
 175         bool bSWAntDivByCtrlFrame;
 176 } SWAT_T, *pSWAT_T;
 177 
 178 /* Remove Edca by YuChen */
 179 
 180 
 181 typedef struct _ODM_RATE_ADAPTIVE {
 182         u8 Type;                                /*  DM_Type_ByFW/DM_Type_ByDriver */
 183         u8 LdpcThres;                   /*  if RSSI > LdpcThres => switch from LPDC to BCC */
 184         bool bUseLdpc;
 185         bool bLowerRtsRate;
 186         u8 HighRSSIThresh;              /*  if RSSI > HighRSSIThresh    => RATRState is DM_RATR_STA_HIGH */
 187         u8 LowRSSIThresh;               /*  if RSSI <= LowRSSIThresh    => RATRState is DM_RATR_STA_LOW */
 188         u8 RATRState;                   /*  Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
 189 
 190 } ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
 191 
 192 #define IQK_MAC_REG_NUM         4
 193 #define IQK_ADDA_REG_NUM                16
 194 #define IQK_BB_REG_NUM_MAX      10
 195 #define IQK_BB_REG_NUM          9
 196 #define HP_THERMAL_NUM          8
 197 
 198 #define AVG_THERMAL_NUM         8
 199 #define IQK_Matrix_REG_NUM      8
 200 #define IQK_Matrix_Settings_NUM (14 + 24 + 21) /*   Channels_2_4G_NUM
 201                                                 * + Channels_5G_20M_NUM
 202                                                 * + Channels_5G
 203                                                 */
 204 
 205 #define         DM_Type_ByFW                    0
 206 #define         DM_Type_ByDriver                1
 207 
 208 /*  */
 209 /*  Declare for common info */
 210 /*  */
 211 #define MAX_PATH_NUM_92CS               2
 212 #define MAX_PATH_NUM_8188E              1
 213 #define MAX_PATH_NUM_8192E              2
 214 #define MAX_PATH_NUM_8723B              1
 215 #define MAX_PATH_NUM_8812A              2
 216 #define MAX_PATH_NUM_8821A              1
 217 #define MAX_PATH_NUM_8814A              4
 218 #define MAX_PATH_NUM_8822B              2
 219 
 220 #define IQK_THRESHOLD                   8
 221 #define DPK_THRESHOLD                   4
 222 
 223 struct odm_phy_info {
 224         /*
 225          *  Be care, if you want to add any element, please insert it between
 226          *  rx_pwd_ball and signal_strength.
 227          */
 228         u8 rx_pwd_ba11;
 229 
 230         u8 signal_quality;             /* in 0-100 index. */
 231         s8 rx_mimo_signal_quality[4];  /* per-path's EVM */
 232         u8 rx_mimo_evm_dbm[4];         /* per-path's EVM dbm */
 233 
 234         u8 rx_mimo_signal_strength[4]; /* in 0~100 index */
 235 
 236         u16 cfo_short[4];              /* per-path's Cfo_short */
 237         u16 cfo_tail[4];               /* per-path's Cfo_tail */
 238 
 239         s8 rx_power;                   /* in dBm Translate from PWdB */
 240 
 241         /*
 242          * Real power in dBm for this packet, no beautification and
 243          * aggregation. Keep this raw info to be used for the other procedures.
 244          */
 245         s8 recv_signal_power;
 246         u8 bt_rx_rssi_percentage;
 247         u8 signal_strength;            /* in 0-100 index. */
 248 
 249         s8 rx_pwr[4];                  /* per-path's pwdb */
 250 
 251         u8 rx_snr[4];                  /* per-path's SNR */
 252         u8 band_width;
 253         u8 bt_coex_pwr_adjust;
 254 };
 255 
 256 struct odm_packet_info {
 257         u8 data_rate;
 258         u8 station_id;
 259         bool bssid_match;
 260         bool to_self;
 261         bool is_beacon;
 262 };
 263 
 264 struct odm_phy_dbg_info {
 265         /* ODM Write, debug info */
 266         s8 RxSNRdB[4];
 267         u32 NumQryPhyStatus;
 268         u32 NumQryPhyStatusCCK;
 269         u32 NumQryPhyStatusOFDM;
 270         u8 NumQryBeaconPkt;
 271         /* Others */
 272         s32 RxEVM[4];
 273 
 274 };
 275 
 276 struct odm_mac_status_info {
 277         u8 test;
 278 };
 279 
 280 typedef enum tag_Dynamic_ODM_Support_Ability_Type {
 281         /*  BB Team */
 282         ODM_DIG                         = 0x00000001,
 283         ODM_HIGH_POWER          = 0x00000002,
 284         ODM_CCK_CCA_TH          = 0x00000004,
 285         ODM_FA_STATISTICS       = 0x00000008,
 286         ODM_RAMASK                      = 0x00000010,
 287         ODM_RSSI_MONITOR        = 0x00000020,
 288         ODM_SW_ANTDIV           = 0x00000040,
 289         ODM_HW_ANTDIV           = 0x00000080,
 290         ODM_BB_PWRSV            = 0x00000100,
 291         ODM_2TPATHDIV           = 0x00000200,
 292         ODM_1TPATHDIV           = 0x00000400,
 293         ODM_PSD2AFH                     = 0x00000800
 294 } ODM_Ability_E;
 295 
 296 /*  */
 297 /*  2011/20/20 MH For MP driver RT_WLAN_STA =  STA_INFO_T */
 298 /*  Please declare below ODM relative info in your STA info structure. */
 299 /*  */
 300 typedef struct _ODM_STA_INFO {
 301         /*  Driver Write */
 302         bool bUsed;                             /*  record the sta status link or not? */
 303         /* u8 WirelessMode;              */
 304         u8 IOTPeer;                     /*  Enum value. HT_IOT_PEER_E */
 305 
 306         /*  ODM Write */
 307         /* 1 PHY_STATUS_INFO */
 308         u8 RSSI_Path[4];                /*  */
 309         u8 RSSI_Ave;
 310         u8 RXEVM[4];
 311         u8 RXSNR[4];
 312 
 313         /*  ODM Write */
 314         /* 1 TX_INFO (may changed by IC) */
 315         /* TX_INFO_T            pTxInfo;                Define in IC folder. Move lower layer. */
 316 
 317         /*  */
 318         /*      Please use compile flag to disabe the strcutrue for other IC except 88E. */
 319         /*      Move To lower layer. */
 320         /*  */
 321         /*  ODM Write Wilson will handle this part(said by Luke.Lee) */
 322         /* TX_RPT_T             pTxRpt;                 Define in IC folder. Move lower layer. */
 323 } ODM_STA_INFO_T, *PODM_STA_INFO_T;
 324 
 325 /*  */
 326 /*  2011/10/20 MH Define Common info enum for all team. */
 327 /*  */
 328 typedef enum _ODM_Common_Info_Definition {
 329         /*  Fixed value: */
 330 
 331         /* HOOK BEFORE REG INIT----------- */
 332         ODM_CMNINFO_PLATFORM = 0,
 333         ODM_CMNINFO_ABILITY,                                    /*  ODM_ABILITY_E */
 334         ODM_CMNINFO_INTERFACE,                          /*  ODM_INTERFACE_E */
 335         ODM_CMNINFO_MP_TEST_CHIP,
 336         ODM_CMNINFO_IC_TYPE,                                    /*  ODM_IC_TYPE_E */
 337         ODM_CMNINFO_CUT_VER,                                    /*  ODM_CUT_VERSION_E */
 338         ODM_CMNINFO_FAB_VER,                                    /*  ODM_FAB_E */
 339         ODM_CMNINFO_RF_TYPE,                                    /*  ODM_RF_PATH_E or ODM_RF_TYPE_E? */
 340         ODM_CMNINFO_RFE_TYPE,
 341         ODM_CMNINFO_BOARD_TYPE,                         /*  ODM_BOARD_TYPE_E */
 342         ODM_CMNINFO_PACKAGE_TYPE,
 343         ODM_CMNINFO_EXT_LNA,                                    /*  true */
 344         ODM_CMNINFO_5G_EXT_LNA,
 345         ODM_CMNINFO_EXT_PA,
 346         ODM_CMNINFO_5G_EXT_PA,
 347         ODM_CMNINFO_GPA,
 348         ODM_CMNINFO_APA,
 349         ODM_CMNINFO_GLNA,
 350         ODM_CMNINFO_ALNA,
 351         ODM_CMNINFO_EXT_TRSW,
 352         ODM_CMNINFO_PATCH_ID,                           /* CUSTOMER ID */
 353         ODM_CMNINFO_BINHCT_TEST,
 354         ODM_CMNINFO_BWIFI_TEST,
 355         ODM_CMNINFO_SMART_CONCURRENT,
 356         /* HOOK BEFORE REG INIT----------- */
 357 
 358         /*  Dynamic value: */
 359 /*  POINTER REFERENCE----------- */
 360         ODM_CMNINFO_MAC_PHY_MODE,       /*  ODM_MAC_PHY_MODE_E */
 361         ODM_CMNINFO_TX_UNI,
 362         ODM_CMNINFO_RX_UNI,
 363         ODM_CMNINFO_WM_MODE,            /*  ODM_WIRELESS_MODE_E */
 364         ODM_CMNINFO_BAND,               /*  ODM_BAND_TYPE_E */
 365         ODM_CMNINFO_SEC_CHNL_OFFSET,    /*  ODM_SEC_CHNL_OFFSET_E */
 366         ODM_CMNINFO_SEC_MODE,           /*  ODM_SECURITY_E */
 367         ODM_CMNINFO_BW,                 /*  ODM_BW_E */
 368         ODM_CMNINFO_CHNL,
 369         ODM_CMNINFO_FORCED_RATE,
 370 
 371         ODM_CMNINFO_DMSP_GET_VALUE,
 372         ODM_CMNINFO_BUDDY_ADAPTOR,
 373         ODM_CMNINFO_DMSP_IS_MASTER,
 374         ODM_CMNINFO_SCAN,
 375         ODM_CMNINFO_POWER_SAVING,
 376         ODM_CMNINFO_ONE_PATH_CCA,       /*  ODM_CCA_PATH_E */
 377         ODM_CMNINFO_DRV_STOP,
 378         ODM_CMNINFO_PNP_IN,
 379         ODM_CMNINFO_INIT_ON,
 380         ODM_CMNINFO_ANT_TEST,
 381         ODM_CMNINFO_NET_CLOSED,
 382         ODM_CMNINFO_MP_MODE,
 383         /* ODM_CMNINFO_RTSTA_AID,        For win driver only? */
 384         ODM_CMNINFO_FORCED_IGI_LB,
 385         ODM_CMNINFO_IS1ANTENNA,
 386         ODM_CMNINFO_RFDEFAULTPATH,
 387 /*  POINTER REFERENCE----------- */
 388 
 389 /* CALL BY VALUE------------- */
 390         ODM_CMNINFO_WIFI_DIRECT,
 391         ODM_CMNINFO_WIFI_DISPLAY,
 392         ODM_CMNINFO_LINK_IN_PROGRESS,
 393         ODM_CMNINFO_LINK,
 394         ODM_CMNINFO_STATION_STATE,
 395         ODM_CMNINFO_RSSI_MIN,
 396         ODM_CMNINFO_DBG_COMP,                   /*  u64 */
 397         ODM_CMNINFO_DBG_LEVEL,                  /*  u32 */
 398         ODM_CMNINFO_RA_THRESHOLD_HIGH,          /*  u8 */
 399         ODM_CMNINFO_RA_THRESHOLD_LOW,           /*  u8 */
 400         ODM_CMNINFO_RF_ANTENNA_TYPE,            /*  u8 */
 401         ODM_CMNINFO_BT_ENABLED,
 402         ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
 403         ODM_CMNINFO_BT_HS_RSSI,
 404         ODM_CMNINFO_BT_OPERATION,
 405         ODM_CMNINFO_BT_LIMITED_DIG,             /* Need to Limited Dig or not */
 406         ODM_CMNINFO_BT_DISABLE_EDCA,
 407 /* CALL BY VALUE------------- */
 408 
 409         /*  Dynamic ptr array hook itms. */
 410         ODM_CMNINFO_STA_STATUS,
 411         ODM_CMNINFO_PHY_STATUS,
 412         ODM_CMNINFO_MAC_STATUS,
 413 
 414         ODM_CMNINFO_MAX,
 415 } ODM_CMNINFO_E;
 416 
 417 /*  2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY */
 418 typedef enum _ODM_Support_Ability_Definition {
 419         /*  */
 420         /*  BB ODM section BIT 0-15 */
 421         /*  */
 422         ODM_BB_DIG                      = BIT0,
 423         ODM_BB_RA_MASK                  = BIT1,
 424         ODM_BB_DYNAMIC_TXPWR            = BIT2,
 425         ODM_BB_FA_CNT                   = BIT3,
 426         ODM_BB_RSSI_MONITOR             = BIT4,
 427         ODM_BB_CCK_PD                   = BIT5,
 428         ODM_BB_ANT_DIV                  = BIT6,
 429         ODM_BB_PWR_SAVE                 = BIT7,
 430         ODM_BB_PWR_TRAIN                = BIT8,
 431         ODM_BB_RATE_ADAPTIVE            = BIT9,
 432         ODM_BB_PATH_DIV                 = BIT10,
 433         ODM_BB_PSD                      = BIT11,
 434         ODM_BB_RXHP                     = BIT12,
 435         ODM_BB_ADAPTIVITY               = BIT13,
 436         ODM_BB_CFO_TRACKING             = BIT14,
 437 
 438         /*  MAC DM section BIT 16-23 */
 439         ODM_MAC_EDCA_TURBO              = BIT16,
 440         ODM_MAC_EARLY_MODE              = BIT17,
 441 
 442         /*  RF ODM section BIT 24-31 */
 443         ODM_RF_TX_PWR_TRACK             = BIT24,
 444         ODM_RF_RX_GAIN_TRACK    = BIT25,
 445         ODM_RF_CALIBRATION              = BIT26,
 446 } ODM_ABILITY_E;
 447 
 448 /*      ODM_CMNINFO_INTERFACE */
 449 typedef enum tag_ODM_Support_Interface_Definition {
 450         ODM_ITRF_SDIO   =       0x4,
 451         ODM_ITRF_ALL    =       0x7,
 452 } ODM_INTERFACE_E;
 453 
 454 /*  ODM_CMNINFO_IC_TYPE */
 455 typedef enum tag_ODM_Support_IC_Type_Definition {
 456         ODM_RTL8723B    =       BIT8,
 457 } ODM_IC_TYPE_E;
 458 
 459 /* ODM_CMNINFO_CUT_VER */
 460 typedef enum tag_ODM_Cut_Version_Definition {
 461         ODM_CUT_A               =       0,
 462         ODM_CUT_B               =       1,
 463         ODM_CUT_C               =       2,
 464         ODM_CUT_D               =       3,
 465         ODM_CUT_E               =       4,
 466         ODM_CUT_F               =       5,
 467 
 468         ODM_CUT_I               =       8,
 469         ODM_CUT_J               =       9,
 470         ODM_CUT_K               =       10,
 471         ODM_CUT_TEST    =       15,
 472 } ODM_CUT_VERSION_E;
 473 
 474 /*  ODM_CMNINFO_FAB_VER */
 475 typedef enum tag_ODM_Fab_Version_Definition {
 476         ODM_TSMC        =       0,
 477         ODM_UMC         =       1,
 478 } ODM_FAB_E;
 479 
 480 /*  ODM_CMNINFO_RF_TYPE */
 481 /*  */
 482 /*  For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
 483 /*  */
 484 typedef enum tag_ODM_RF_Path_Bit_Definition {
 485         ODM_RF_TX_A     =       BIT0,
 486         ODM_RF_TX_B     =       BIT1,
 487         ODM_RF_TX_C     =       BIT2,
 488         ODM_RF_TX_D     =       BIT3,
 489         ODM_RF_RX_A     =       BIT4,
 490         ODM_RF_RX_B     =       BIT5,
 491         ODM_RF_RX_C     =       BIT6,
 492         ODM_RF_RX_D     =       BIT7,
 493 } ODM_RF_PATH_E;
 494 
 495 typedef enum tag_ODM_RF_Type_Definition {
 496         ODM_1T1R        =       0,
 497         ODM_1T2R        =       1,
 498         ODM_2T2R        =       2,
 499         ODM_2T3R        =       3,
 500         ODM_2T4R        =       4,
 501         ODM_3T3R        =       5,
 502         ODM_3T4R        =       6,
 503         ODM_4T4R        =       7,
 504 } ODM_RF_TYPE_E;
 505 
 506 /*  */
 507 /*  ODM Dynamic common info value definition */
 508 /*  */
 509 
 510 /* typedef enum _MACPHY_MODE_8192D{ */
 511 /*      SINGLEMAC_SINGLEPHY, */
 512 /*      DUALMAC_DUALPHY, */
 513 /*      DUALMAC_SINGLEPHY, */
 514 /* MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; */
 515 /*  Above is the original define in MP driver. Please use the same define. THX. */
 516 typedef enum tag_ODM_MAC_PHY_Mode_Definition {
 517         ODM_SMSP        = 0,
 518         ODM_DMSP        = 1,
 519         ODM_DMDP        = 2,
 520 } ODM_MAC_PHY_MODE_E;
 521 
 522 typedef enum tag_BT_Coexist_Definition {
 523         ODM_BT_BUSY             = 1,
 524         ODM_BT_ON               = 2,
 525         ODM_BT_OFF              = 3,
 526         ODM_BT_NONE             = 4,
 527 } ODM_BT_COEXIST_E;
 528 
 529 /*  ODM_CMNINFO_OP_MODE */
 530 typedef enum tag_Operation_Mode_Definition {
 531         ODM_NO_LINK      = BIT0,
 532         ODM_LINK         = BIT1,
 533         ODM_SCAN         = BIT2,
 534         ODM_POWERSAVE    = BIT3,
 535         ODM_AP_MODE      = BIT4,
 536         ODM_CLIENT_MODE  = BIT5,
 537         ODM_AD_HOC       = BIT6,
 538         ODM_WIFI_DIRECT  = BIT7,
 539         ODM_WIFI_DISPLAY = BIT8,
 540 } ODM_OPERATION_MODE_E;
 541 
 542 /*  ODM_CMNINFO_WM_MODE */
 543 typedef enum tag_Wireless_Mode_Definition {
 544         ODM_WM_UNKNOW     = 0x0,
 545         ODM_WM_B          = BIT0,
 546         ODM_WM_G          = BIT1,
 547         ODM_WM_A          = BIT2,
 548         ODM_WM_N24G       = BIT3,
 549         ODM_WM_N5G        = BIT4,
 550         ODM_WM_AUTO       = BIT5,
 551         ODM_WM_AC         = BIT6,
 552 } ODM_WIRELESS_MODE_E;
 553 
 554 /*  ODM_CMNINFO_BAND */
 555 typedef enum tag_Band_Type_Definition {
 556         ODM_BAND_2_4G = 0,
 557         ODM_BAND_5G,
 558         ODM_BAND_ON_BOTH,
 559         ODM_BANDMAX
 560 } ODM_BAND_TYPE_E;
 561 
 562 /*  ODM_CMNINFO_SEC_CHNL_OFFSET */
 563 typedef enum tag_Secondary_Channel_Offset_Definition {
 564         ODM_DONT_CARE   = 0,
 565         ODM_BELOW               = 1,
 566         ODM_ABOVE               = 2
 567 } ODM_SEC_CHNL_OFFSET_E;
 568 
 569 /*  ODM_CMNINFO_SEC_MODE */
 570 typedef enum tag_Security_Definition {
 571         ODM_SEC_OPEN            = 0,
 572         ODM_SEC_WEP40           = 1,
 573         ODM_SEC_TKIP            = 2,
 574         ODM_SEC_RESERVE         = 3,
 575         ODM_SEC_AESCCMP         = 4,
 576         ODM_SEC_WEP104          = 5,
 577         ODM_WEP_WPA_MIXED       = 6, /*  WEP + WPA */
 578         ODM_SEC_SMS4            = 7,
 579 } ODM_SECURITY_E;
 580 
 581 /*  ODM_CMNINFO_BW */
 582 typedef enum tag_Bandwidth_Definition {
 583         ODM_BW20M               = 0,
 584         ODM_BW40M               = 1,
 585         ODM_BW80M               = 2,
 586         ODM_BW160M              = 3,
 587         ODM_BW10M               = 4,
 588 } ODM_BW_E;
 589 
 590 /*  ODM_CMNINFO_BOARD_TYPE */
 591 /*  For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored */
 592 /*  For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G */
 593 typedef enum tag_Board_Definition {
 594         ODM_BOARD_DEFAULT    = 0,      /*  The DEFAULT case. */
 595         ODM_BOARD_MINICARD   = BIT(0), /*  0 = non-mini card, 1 = mini card. */
 596         ODM_BOARD_SLIM       = BIT(1), /*  0 = non-slim card, 1 = slim card */
 597         ODM_BOARD_BT         = BIT(2), /*  0 = without BT card, 1 = with BT */
 598         ODM_BOARD_EXT_PA     = BIT(3), /*  0 = no 2G ext-PA, 1 = existing 2G ext-PA */
 599         ODM_BOARD_EXT_LNA    = BIT(4), /*  0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
 600         ODM_BOARD_EXT_TRSW   = BIT(5), /*  0 = no ext-TRSW, 1 = existing ext-TRSW */
 601         ODM_BOARD_EXT_PA_5G  = BIT(6), /*  0 = no 5G ext-PA, 1 = existing 5G ext-PA */
 602         ODM_BOARD_EXT_LNA_5G = BIT(7), /*  0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
 603 } ODM_BOARD_TYPE_E;
 604 
 605 typedef enum tag_ODM_Package_Definition {
 606         ODM_PACKAGE_DEFAULT      = 0,
 607         ODM_PACKAGE_QFN68        = BIT(0),
 608         ODM_PACKAGE_TFBGA90      = BIT(1),
 609         ODM_PACKAGE_TFBGA79      = BIT(2),
 610 } ODM_Package_TYPE_E;
 611 
 612 typedef enum tag_ODM_TYPE_GPA_Definition {
 613         TYPE_GPA0 = 0,
 614         TYPE_GPA1 = BIT(1)|BIT(0)
 615 } ODM_TYPE_GPA_E;
 616 
 617 typedef enum tag_ODM_TYPE_APA_Definition {
 618         TYPE_APA0 = 0,
 619         TYPE_APA1 = BIT(1)|BIT(0)
 620 } ODM_TYPE_APA_E;
 621 
 622 typedef enum tag_ODM_TYPE_GLNA_Definition {
 623         TYPE_GLNA0 = 0,
 624         TYPE_GLNA1 = BIT(2)|BIT(0),
 625         TYPE_GLNA2 = BIT(3)|BIT(1),
 626         TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
 627 } ODM_TYPE_GLNA_E;
 628 
 629 typedef enum tag_ODM_TYPE_ALNA_Definition {
 630         TYPE_ALNA0 = 0,
 631         TYPE_ALNA1 = BIT(2)|BIT(0),
 632         TYPE_ALNA2 = BIT(3)|BIT(1),
 633         TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
 634 } ODM_TYPE_ALNA_E;
 635 
 636 /*  ODM_CMNINFO_ONE_PATH_CCA */
 637 typedef enum tag_CCA_Path {
 638         ODM_CCA_2R                      = 0,
 639         ODM_CCA_1R_A            = 1,
 640         ODM_CCA_1R_B            = 2,
 641 } ODM_CCA_PATH_E;
 642 
 643 typedef struct _ODM_RA_Info_ {
 644         u8 RateID;
 645         u32 RateMask;
 646         u32 RAUseRate;
 647         u8 RateSGI;
 648         u8 RssiStaRA;
 649         u8 PreRssiStaRA;
 650         u8 SGIEnable;
 651         u8 DecisionRate;
 652         u8 PreRate;
 653         u8 HighestRate;
 654         u8 LowestRate;
 655         u32 NscUp;
 656         u32 NscDown;
 657         u16 RTY[5];
 658         u32 TOTAL;
 659         u16 DROP;
 660         u8 Active;
 661         u16 RptTime;
 662         u8 RAWaitingCounter;
 663         u8 RAPendingCounter;
 664         u8 PTActive;  /*  on or off */
 665         u8 PTTryState;  /*  0 trying state, 1 for decision state */
 666         u8 PTStage;  /*  0~6 */
 667         u8 PTStopCount; /* Stop PT counter */
 668         u8 PTPreRate;  /*  if rate change do PT */
 669         u8 PTPreRssi; /*  if RSSI change 5% do PT */
 670         u8 PTModeSS;  /*  decide whitch rate should do PT */
 671         u8 RAstage;  /*  StageRA, decide how many times RA will be done between PT */
 672         u8 PTSmoothFactor;
 673 } ODM_RA_INFO_T, *PODM_RA_INFO_T;
 674 
 675 typedef struct _IQK_MATRIX_REGS_SETTING {
 676         bool bIQKDone;
 677         s32 Value[3][IQK_Matrix_REG_NUM];
 678         bool bBWIqkResultSaved[3];
 679 } IQK_MATRIX_REGS_SETTING, *PIQK_MATRIX_REGS_SETTING;
 680 
 681 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */
 682 
 683 typedef struct ODM_RF_Calibration_Structure {
 684         /* for tx power tracking */
 685 
 686         u32 RegA24; /*  for TempCCK */
 687         s32 RegE94;
 688         s32 RegE9C;
 689         s32 RegEB4;
 690         s32 RegEBC;
 691 
 692         u8 TXPowercount;
 693         bool bTXPowerTrackingInit;
 694         bool bTXPowerTracking;
 695         u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
 696         u8 TM_Trigger;
 697         u8 InternalPA5G[2];     /* pathA / pathB */
 698 
 699         u8 ThermalMeter[2];    /*  ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
 700         u8 ThermalValue;
 701         u8 ThermalValue_LCK;
 702         u8 ThermalValue_IQK;
 703         u8 ThermalValue_DPK;
 704         u8 ThermalValue_AVG[AVG_THERMAL_NUM];
 705         u8 ThermalValue_AVG_index;
 706         u8 ThermalValue_RxGain;
 707         u8 ThermalValue_Crystal;
 708         u8 ThermalValue_DPKstore;
 709         u8 ThermalValue_DPKtrack;
 710         bool TxPowerTrackingInProgress;
 711 
 712         bool bReloadtxpowerindex;
 713         u8 bRfPiEnable;
 714         u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
 715 
 716         /*  Tx power Tracking ------------------------- */
 717         u8 bCCKinCH14;
 718         u8 CCK_index;
 719         u8 OFDM_index[MAX_RF_PATH];
 720         s8 PowerIndexOffset[MAX_RF_PATH];
 721         s8 DeltaPowerIndex[MAX_RF_PATH];
 722         s8 DeltaPowerIndexLast[MAX_RF_PATH];
 723         bool bTxPowerChanged;
 724 
 725         u8 ThermalValue_HP[HP_THERMAL_NUM];
 726         u8 ThermalValue_HP_index;
 727         IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
 728         bool bNeedIQK;
 729         bool bIQKInProgress;
 730         u8 Delta_IQK;
 731         u8 Delta_LCK;
 732         s8 BBSwingDiff2G, BBSwingDiff5G; /*  Unit: dB */
 733         u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
 734         u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
 735         u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
 736         u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
 737         u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
 738         u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
 739         u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
 740         u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
 741         u8 DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
 742         u8 DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
 743         u8 DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
 744         u8 DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
 745         u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
 746         u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
 747 
 748         /*  */
 749 
 750         /* for IQK */
 751         u32 RegC04;
 752         u32 Reg874;
 753         u32 RegC08;
 754         u32 RegB68;
 755         u32 RegB6C;
 756         u32 Reg870;
 757         u32 Reg860;
 758         u32 Reg864;
 759 
 760         bool bIQKInitialized;
 761         bool bLCKInProgress;
 762         bool bAntennaDetected;
 763         u32 ADDA_backup[IQK_ADDA_REG_NUM];
 764         u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
 765         u32 IQK_BB_backup_recover[9];
 766         u32 IQK_BB_backup[IQK_BB_REG_NUM];
 767         u32 TxIQC_8723B[2][3][2]; /*  { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
 768         u32 RxIQC_8723B[2][2][2]; /*  { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
 769 
 770         /* for APK */
 771         u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
 772         u8 bAPKdone;
 773         u8 bAPKThermalMeterIgnore;
 774 
 775         /*  DPK */
 776         bool bDPKFail;
 777         u8 bDPdone;
 778         u8 bDPPathAOK;
 779         u8 bDPPathBOK;
 780 
 781         u32 TxLOK[2];
 782 
 783 } ODM_RF_CAL_T, *PODM_RF_CAL_T;
 784 /*  */
 785 /*  ODM Dynamic common info value definition */
 786 /*  */
 787 
 788 typedef struct _FAST_ANTENNA_TRAINNING_ {
 789         u8 Bssid[6];
 790         u8 antsel_rx_keep_0;
 791         u8 antsel_rx_keep_1;
 792         u8 antsel_rx_keep_2;
 793         u8 antsel_rx_keep_3;
 794         u32 antSumRSSI[7];
 795         u32 antRSSIcnt[7];
 796         u32 antAveRSSI[7];
 797         u8 FAT_State;
 798         u32 TrainIdx;
 799         u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
 800         u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
 801         u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
 802         u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 803         u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 804         u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 805         u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 806         u8 RxIdleAnt;
 807         bool    bBecomeLinked;
 808         u32 MinMaxRSSI;
 809         u8 idx_AntDiv_counter_2G;
 810         u8 idx_AntDiv_counter_5G;
 811         u32 AntDiv_2G_5G;
 812         u32 CCK_counter_main;
 813         u32 CCK_counter_aux;
 814         u32 OFDM_counter_main;
 815         u32 OFDM_counter_aux;
 816 
 817         u32 CCK_CtrlFrame_Cnt_main;
 818         u32 CCK_CtrlFrame_Cnt_aux;
 819         u32 OFDM_CtrlFrame_Cnt_main;
 820         u32 OFDM_CtrlFrame_Cnt_aux;
 821         u32 MainAnt_CtrlFrame_Sum;
 822         u32 AuxAnt_CtrlFrame_Sum;
 823         u32 MainAnt_CtrlFrame_Cnt;
 824         u32 AuxAnt_CtrlFrame_Cnt;
 825 
 826 } FAT_T, *pFAT_T;
 827 
 828 typedef enum _FAT_STATE {
 829         FAT_NORMAL_STATE                        = 0,
 830         FAT_TRAINING_STATE              = 1,
 831 } FAT_STATE_E, *PFAT_STATE_E;
 832 
 833 typedef enum _ANT_DIV_TYPE {
 834         NO_ANTDIV                       = 0xFF,
 835         CG_TRX_HW_ANTDIV                = 0x01,
 836         CGCS_RX_HW_ANTDIV       = 0x02,
 837         FIXED_HW_ANTDIV         = 0x03,
 838         CG_TRX_SMART_ANTDIV     = 0x04,
 839         CGCS_RX_SW_ANTDIV       = 0x05,
 840         S0S1_SW_ANTDIV          = 0x06 /* 8723B intrnal switch S0 S1 */
 841 } ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
 842 
 843 typedef struct _ODM_PATH_DIVERSITY_ {
 844         u8 RespTxPath;
 845         u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM];
 846         u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 847         u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 848         u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 849         u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 850 } PATHDIV_T, *pPATHDIV_T;
 851 
 852 typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{
 853         PHY_REG_PG_RELATIVE_VALUE = 0,
 854         PHY_REG_PG_EXACT_VALUE = 1
 855 } PHY_REG_PG_TYPE;
 856 
 857 /*  */
 858 /*  Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */
 859 /*  */
 860 typedef struct _ANT_DETECTED_INFO {
 861         bool bAntDetected;
 862         u32 dBForAntA;
 863         u32 dBForAntB;
 864         u32 dBForAntO;
 865 } ANT_DETECTED_INFO, *PANT_DETECTED_INFO;
 866 
 867 /*  */
 868 /*  2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */
 869 /*  */
 870 typedef  struct DM_Out_Source_Dynamic_Mechanism_Structure {
 871         /* RT_TIMER     FastAntTrainingTimer; */
 872         /*  */
 873         /*      Add for different team use temporarily */
 874         /*  */
 875         struct adapter *Adapter;                /*  For CE/NIC team */
 876         /*  WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */
 877         bool odm_ready;
 878 
 879         PHY_REG_PG_TYPE PhyRegPgValueType;
 880         u8 PhyRegPgVersion;
 881 
 882         u64     DebugComponents;
 883         u32 DebugLevel;
 884 
 885         u32 NumQryPhyStatusAll; /* CCK + OFDM */
 886         u32 LastNumQryPhyStatusAll;
 887         u32 RxPWDBAve;
 888         bool MPDIG_2G;          /* off MPDIG */
 889         u8 Times_2G;
 890 
 891 /*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
 892         bool bCckHighPower;
 893         u8 RFPathRxEnable;              /*  ODM_CMNINFO_RFPATH_ENABLE */
 894         u8 ControlChannel;
 895 /*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
 896 
 897 /* REMOVED COMMON INFO---------- */
 898         /* u8           PseudoMacPhyMode; */
 899         /* bool                 *BTCoexist; */
 900         /* bool                 PseudoBtCoexist; */
 901         /* u8           OPMode; */
 902         /* bool                 bAPMode; */
 903         /* bool                 bClientMode; */
 904         /* bool                 bAdHocMode; */
 905         /* bool                 bSlaveOfDMSP; */
 906 /* REMOVED COMMON INFO---------- */
 907 
 908 /* 1  COMMON INFORMATION */
 909 
 910         /*  */
 911         /*  Init Value */
 912         /*  */
 913 /* HOOK BEFORE REG INIT----------- */
 914         /*  ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
 915         u8 SupportPlatform;
 916         /*  ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */
 917         u32 SupportAbility;
 918         /*  ODM PCIE/USB/SDIO = 1/2/3 */
 919         u8 SupportInterface;
 920         /*  ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */
 921         u32 SupportICType;
 922         /*  Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
 923         u8 CutVersion;
 924         /*  Fab Version TSMC/UMC = 0/1 */
 925         u8 FabVersion;
 926         /*  RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
 927         u8 RFType;
 928         u8 RFEType;
 929         /*  Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */
 930         u8 BoardType;
 931         u8 PackageType;
 932         u8 TypeGLNA;
 933         u8 TypeGPA;
 934         u8 TypeALNA;
 935         u8 TypeAPA;
 936         /*  with external LNA  NO/Yes = 0/1 */
 937         u8 ExtLNA;
 938         u8 ExtLNA5G;
 939         /*  with external PA  NO/Yes = 0/1 */
 940         u8 ExtPA;
 941         u8 ExtPA5G;
 942         /*  with external TRSW  NO/Yes = 0/1 */
 943         u8 ExtTRSW;
 944         u8 PatchID; /* Customer ID */
 945         bool bInHctTest;
 946         bool bWIFITest;
 947 
 948         bool bDualMacSmartConcurrent;
 949         u32 BK_SupportAbility;
 950         u8 AntDivType;
 951 /* HOOK BEFORE REG INIT----------- */
 952 
 953         /*  */
 954         /*  Dynamic Value */
 955         /*  */
 956 /*  POINTER REFERENCE----------- */
 957 
 958         u8 u8_temp;
 959         bool bool_temp;
 960         struct adapter *adapter_temp;
 961 
 962         /*  MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
 963         u8 *pMacPhyMode;
 964         /* TX Unicast byte count */
 965         u64 *pNumTxBytesUnicast;
 966         /* RX Unicast byte count */
 967         u64 *pNumRxBytesUnicast;
 968         /*  Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
 969         u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */
 970         /*  Frequence band 2.4G/5G = 0/1 */
 971         u8 *pBandType;
 972         /*  Secondary channel offset don't_care/below/above = 0/1/2 */
 973         u8 *pSecChOffset;
 974         /*  Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
 975         u8 *pSecurity;
 976         /*  BW info 20M/40M/80M = 0/1/2 */
 977         u8 *pBandWidth;
 978         /*  Central channel location Ch1/Ch2/.... */
 979         u8 *pChannel; /* central channel number */
 980         bool DPK_Done;
 981         /*  Common info for 92D DMSP */
 982 
 983         bool *pbGetValueFromOtherMac;
 984         struct adapter **pBuddyAdapter;
 985         bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
 986         /*  Common info for Status */
 987         bool *pbScanInProcess;
 988         bool *pbPowerSaving;
 989         /*  CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
 990         u8 *pOnePathCCA;
 991         /* pMgntInfo->AntennaTest */
 992         u8 *pAntennaTest;
 993         bool *pbNet_closed;
 994         u8 *mp_mode;
 995         /* u8   *pAidMap; */
 996         u8 *pu1ForcedIgiLb;
 997 /*  For 8723B IQK----------- */
 998         bool *pIs1Antenna;
 999         u8 *pRFDefaultPath;
1000         /*  0:S1, 1:S0 */
1001 
1002 /*  POINTER REFERENCE----------- */
1003         u16 *pForcedDataRate;
1004 /* CALL BY VALUE------------- */
1005         bool bLinkInProcess;
1006         bool bWIFI_Direct;
1007         bool bWIFI_Display;
1008         bool bLinked;
1009 
1010         bool bsta_state;
1011         u8 RSSI_Min;
1012         u8 InterfaceIndex; /*  Add for 92D  dual MAC: 0--Mac0 1--Mac1 */
1013         bool bIsMPChip;
1014         bool bOneEntryOnly;
1015         /*  Common info for BTDM */
1016         bool bBtEnabled;                        /*  BT is disabled */
1017         bool bBtConnectProcess; /*  BT HS is under connection progress. */
1018         u8 btHsRssi;                            /*  BT HS mode wifi rssi value. */
1019         bool bBtHsOperation;            /*  BT HS mode is under progress */
1020         bool bBtDisableEdcaTurbo;       /*  Under some condition, don't enable the EDCA Turbo */
1021         bool bBtLimitedDig;                     /*  BT is busy. */
1022 /* CALL BY VALUE------------- */
1023         u8 RSSI_A;
1024         u8 RSSI_B;
1025         u64 RSSI_TRSW;
1026         u64 RSSI_TRSW_H;
1027         u64 RSSI_TRSW_L;
1028         u64 RSSI_TRSW_iso;
1029 
1030         u8 RxRate;
1031         bool bNoisyState;
1032         u8 TxRate;
1033         u8 LinkedInterval;
1034         u8 preChannel;
1035         u32 TxagcOffsetValueA;
1036         bool IsTxagcOffsetPositiveA;
1037         u32 TxagcOffsetValueB;
1038         bool IsTxagcOffsetPositiveB;
1039         u64     lastTxOkCnt;
1040         u64     lastRxOkCnt;
1041         u32 BbSwingOffsetA;
1042         bool IsBbSwingOffsetPositiveA;
1043         u32 BbSwingOffsetB;
1044         bool IsBbSwingOffsetPositiveB;
1045         s8 TH_L2H_ini;
1046         s8 TH_EDCCA_HL_diff;
1047         s8 IGI_Base;
1048         u8 IGI_target;
1049         bool ForceEDCCA;
1050         u8 AdapEn_RSSI;
1051         s8 Force_TH_H;
1052         s8 Force_TH_L;
1053         u8 IGI_LowerBound;
1054         u8 antdiv_rssi;
1055         u8 AntType;
1056         u8 pre_AntType;
1057         u8 antdiv_period;
1058         u8 antdiv_select;
1059         u8 NdpaPeriod;
1060         bool H2C_RARpt_connect;
1061 
1062         /*  add by Yu Cehn for adaptivtiy */
1063         bool adaptivity_flag;
1064         bool NHM_disable;
1065         bool TxHangFlg;
1066         bool Carrier_Sense_enable;
1067         u8 tolerance_cnt;
1068         u64 NHMCurTxOkcnt;
1069         u64 NHMCurRxOkcnt;
1070         u64 NHMLastTxOkcnt;
1071         u64 NHMLastRxOkcnt;
1072         u8 txEdcca1;
1073         u8 txEdcca0;
1074         s8 H2L_lb;
1075         s8 L2H_lb;
1076         u8 Adaptivity_IGI_upper;
1077         u8 NHM_cnt_0;
1078 
1079         ODM_NOISE_MONITOR noise_level;/* ODM_MAX_CHANNEL_NUM]; */
1080         /*  */
1081         /* 2 Define STA info. */
1082         /*  _ODM_STA_INFO */
1083         /*  2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */
1084         PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
1085 
1086         /*  */
1087         /*  2012/02/14 MH Add to share 88E ra with other SW team. */
1088         /*  We need to colelct all support abilit to a proper area. */
1089         /*  */
1090         bool RaSupport88E;
1091 
1092         /*  Define ........... */
1093 
1094         /*  Latest packet phy info (ODM write) */
1095         struct odm_phy_dbg_info PhyDbgInfo;
1096         /* PHY_INFO_88E         PhyInfo; */
1097 
1098         /*  Latest packet phy info (ODM write) */
1099         struct odm_mac_status_info *pMacInfo;
1100         /* MAC_INFO_88E         MacInfo; */
1101 
1102         /*  Different Team independt structure?? */
1103 
1104         /*  */
1105         /* TX_RTP_CMN           TX_retrpo; */
1106         /* TX_RTP_88E           TX_retrpo; */
1107         /* TX_RTP_8195          TX_retrpo; */
1108 
1109         /*  */
1110         /* ODM Structure */
1111         /*  */
1112         FAT_T DM_FatTable;
1113         DIG_T DM_DigTable;
1114         PS_T DM_PSTable;
1115         struct dynamic_primary_CCA DM_PriCCA;
1116         RXHP_T DM_RXHP_Table;
1117         RA_T DM_RA_Table;
1118         false_ALARM_STATISTICS FalseAlmCnt;
1119         false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter;
1120         SWAT_T DM_SWAT_Table;
1121         bool RSSI_test;
1122         CFO_TRACKING DM_CfoTrack;
1123 
1124         EDCA_T DM_EDCA_Table;
1125         u32 WMMEDCA_BE;
1126         PATHDIV_T DM_PathDiv;
1127         /*  Copy from SD4 structure */
1128         /*  */
1129         /*  ================================================== */
1130         /*  */
1131 
1132         /* common */
1133         /* u8 DM_Type; */
1134         /* u8    PSD_Report_RXHP[80];    Add By Gary */
1135         /* u8    PSD_func_flag;                Add By Gary */
1136         /* for DIG */
1137         /* u8 bDMInitialGainEnable; */
1138         /* u8 binitialized;  for dm_initial_gain_Multi_STA use. */
1139         /* for Antenna diversity */
1140         /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */
1141         /* PSTA_INFO_T RSSI_target; */
1142 
1143         bool *pbDriverStopped;
1144         bool *pbDriverIsGoingToPnpSetPowerSleep;
1145         bool *pinit_adpt_in_progress;
1146 
1147         /* PSD */
1148         bool bUserAssignLevel;
1149         RT_TIMER PSDTimer;
1150         u8 RSSI_BT;                     /* come from BT */
1151         bool bPSDinProcess;
1152         bool bPSDactive;
1153         bool bDMInitialGainEnable;
1154 
1155         /* MPT DIG */
1156         RT_TIMER MPT_DIGTimer;
1157 
1158         /* for rate adaptive, in fact,  88c/92c fw will handle this */
1159         u8 bUseRAMask;
1160 
1161         ODM_RATE_ADAPTIVE RateAdaptive;
1162 
1163         ANT_DETECTED_INFO AntDetectedInfo; /*  Antenna detected information for RSSI tool */
1164 
1165         ODM_RF_CAL_T RFCalibrateInfo;
1166 
1167         /*  */
1168         /*  TX power tracking */
1169         /*  */
1170         u8 BbSwingIdxOfdm[MAX_RF_PATH];
1171         u8 BbSwingIdxOfdmCurrent;
1172         u8 BbSwingIdxOfdmBase[MAX_RF_PATH];
1173         bool BbSwingFlagOfdm;
1174         u8 BbSwingIdxCck;
1175         u8 BbSwingIdxCckCurrent;
1176         u8 BbSwingIdxCckBase;
1177         u8 DefaultOfdmIndex;
1178         u8 DefaultCckIndex;
1179         bool BbSwingFlagCck;
1180 
1181         s8 Absolute_OFDMSwingIdx[MAX_RF_PATH];
1182         s8 Remnant_OFDMSwingIdx[MAX_RF_PATH];
1183         s8 Remnant_CCKSwingIdx;
1184         s8 Modify_TxAGC_Value;       /* Remnat compensate value at TxAGC */
1185         bool Modify_TxAGC_Flag_PathA;
1186         bool Modify_TxAGC_Flag_PathB;
1187         bool Modify_TxAGC_Flag_PathC;
1188         bool Modify_TxAGC_Flag_PathD;
1189         bool Modify_TxAGC_Flag_PathA_CCK;
1190 
1191         s8 KfreeOffset[MAX_RF_PATH];
1192         /*  */
1193         /*  ODM system resource. */
1194         /*  */
1195 
1196         /*  ODM relative time. */
1197         RT_TIMER PathDivSwitchTimer;
1198         /* 2011.09.27 add for Path Diversity */
1199         RT_TIMER CCKPathDiversityTimer;
1200         RT_TIMER FastAntTrainingTimer;
1201 
1202         /*  ODM relative workitem. */
1203 
1204         #if (BEAMFORMING_SUPPORT == 1)
1205         RT_BEAMFORMING_INFO BeamformingInfo;
1206         #endif
1207 } DM_ODM_T, *PDM_ODM_T; /*  DM_Dynamic_Mechanism_Structure */
1208 
1209 #define ODM_RF_PATH_MAX 2
1210 
1211 typedef enum _ODM_RF_RADIO_PATH {
1212         ODM_RF_PATH_A = 0,   /* Radio Path A */
1213         ODM_RF_PATH_B = 1,   /* Radio Path B */
1214         ODM_RF_PATH_C = 2,   /* Radio Path C */
1215         ODM_RF_PATH_D = 3,   /* Radio Path D */
1216         ODM_RF_PATH_AB,
1217         ODM_RF_PATH_AC,
1218         ODM_RF_PATH_AD,
1219         ODM_RF_PATH_BC,
1220         ODM_RF_PATH_BD,
1221         ODM_RF_PATH_CD,
1222         ODM_RF_PATH_ABC,
1223         ODM_RF_PATH_ACD,
1224         ODM_RF_PATH_BCD,
1225         ODM_RF_PATH_ABCD,
1226         /*   ODM_RF_PATH_MAX,    Max RF number 90 support */
1227 } ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;
1228 
1229  typedef enum _ODM_RF_CONTENT {
1230         odm_radioa_txt = 0x1000,
1231         odm_radiob_txt = 0x1001,
1232         odm_radioc_txt = 0x1002,
1233         odm_radiod_txt = 0x1003
1234 } ODM_RF_CONTENT;
1235 
1236 typedef enum _ODM_BB_Config_Type {
1237         CONFIG_BB_PHY_REG,
1238         CONFIG_BB_AGC_TAB,
1239         CONFIG_BB_AGC_TAB_2G,
1240         CONFIG_BB_AGC_TAB_5G,
1241         CONFIG_BB_PHY_REG_PG,
1242         CONFIG_BB_PHY_REG_MP,
1243         CONFIG_BB_AGC_TAB_DIFF,
1244 } ODM_BB_Config_Type, *PODM_BB_Config_Type;
1245 
1246 typedef enum _ODM_RF_Config_Type {
1247         CONFIG_RF_RADIO,
1248         CONFIG_RF_TXPWR_LMT,
1249 } ODM_RF_Config_Type, *PODM_RF_Config_Type;
1250 
1251 typedef enum _ODM_FW_Config_Type {
1252         CONFIG_FW_NIC,
1253         CONFIG_FW_NIC_2,
1254         CONFIG_FW_AP,
1255         CONFIG_FW_WoWLAN,
1256         CONFIG_FW_WoWLAN_2,
1257         CONFIG_FW_AP_WoWLAN,
1258         CONFIG_FW_BT,
1259 } ODM_FW_Config_Type;
1260 
1261 /*  Status code */
1262 typedef enum _RT_STATUS {
1263         RT_STATUS_SUCCESS,
1264         RT_STATUS_FAILURE,
1265         RT_STATUS_PENDING,
1266         RT_STATUS_RESOURCE,
1267         RT_STATUS_INVALID_CONTEXT,
1268         RT_STATUS_INVALID_PARAMETER,
1269         RT_STATUS_NOT_SUPPORT,
1270         RT_STATUS_OS_API_FAILED,
1271 } RT_STATUS, *PRT_STATUS;
1272 
1273 #ifdef REMOVE_PACK
1274 #pragma pack()
1275 #endif
1276 
1277 /* include "odm_function.h" */
1278 
1279 /* 3 =========================================================== */
1280 /* 3 DIG */
1281 /* 3 =========================================================== */
1282 
1283 /* Remove DIG by Yuchen */
1284 
1285 /* 3 =========================================================== */
1286 /* 3 AGC RX High Power Mode */
1287 /* 3 =========================================================== */
1288 #define          LNA_Low_Gain_1                      0x64
1289 #define          LNA_Low_Gain_2                      0x5A
1290 #define          LNA_Low_Gain_3                      0x58
1291 
1292 #define          FA_RXHP_TH1                           5000
1293 #define          FA_RXHP_TH2                           1500
1294 #define          FA_RXHP_TH3                             800
1295 #define          FA_RXHP_TH4                             600
1296 #define          FA_RXHP_TH5                             500
1297 
1298 /* 3 =========================================================== */
1299 /* 3 EDCA */
1300 /* 3 =========================================================== */
1301 
1302 /* 3 =========================================================== */
1303 /* 3 Dynamic Tx Power */
1304 /* 3 =========================================================== */
1305 /* Dynamic Tx Power Control Threshold */
1306 
1307 /* 3 =========================================================== */
1308 /* 3 Rate Adaptive */
1309 /* 3 =========================================================== */
1310 #define         DM_RATR_STA_INIT                        0
1311 #define         DM_RATR_STA_HIGH                        1
1312 #define         DM_RATR_STA_MIDDLE                      2
1313 #define         DM_RATR_STA_LOW                         3
1314 
1315 /* 3 =========================================================== */
1316 /* 3 BB Power Save */
1317 /* 3 =========================================================== */
1318 
1319 typedef enum tag_1R_CCA_Type_Definition {
1320         CCA_1R = 0,
1321         CCA_2R = 1,
1322         CCA_MAX = 2,
1323 } DM_1R_CCA_E;
1324 
1325 typedef enum tag_RF_Type_Definition {
1326         RF_Save = 0,
1327         RF_Normal = 1,
1328         RF_MAX = 2,
1329 } DM_RF_E;
1330 
1331 /* 3 =========================================================== */
1332 /* 3 Antenna Diversity */
1333 /* 3 =========================================================== */
1334 typedef enum tag_SW_Antenna_Switch_Definition {
1335         Antenna_A = 1,
1336         Antenna_B = 2,
1337         Antenna_MAX = 3,
1338 } DM_SWAS_E;
1339 
1340 /*  Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */
1341 #define MAX_ANTENNA_DETECTION_CNT       10
1342 
1343 /*  */
1344 /*  Extern Global Variables. */
1345 /*  */
1346 extern  u32 OFDMSwingTable[OFDM_TABLE_SIZE];
1347 extern  u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1348 extern  u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8];
1349 
1350 extern  u32 OFDMSwingTable_New[OFDM_TABLE_SIZE];
1351 extern  u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
1352 extern  u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8];
1353 
1354 extern  u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
1355 
1356 /*  */
1357 /*  check Sta pointer valid or not */
1358 /*  */
1359 #define IS_STA_VALID(pSta)              (pSta)
1360 /*  20100514 Joseph: Add definition for antenna switching test after link. */
1361 /*  This indicates two different the steps. */
1362 /*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
1363 /*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
1364 /*  with original RSSI to determine if it is necessary to switch antenna. */
1365 #define SWAW_STEP_PEAK          0
1366 #define SWAW_STEP_DETERMINE     1
1367 
1368 /* Remove BB power saving by Yuchen */
1369 
1370 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1371 void ODM_TXPowerTrackingCheck(PDM_ODM_T pDM_Odm);
1372 
1373 bool ODM_RAStateCheck(
1374         PDM_ODM_T pDM_Odm,
1375         s32     RSSI,
1376         bool bForceUpdate,
1377         u8 *pRATRState
1378 );
1379 
1380 #define dm_SWAW_RSSI_Check      ODM_SwAntDivChkPerPktRssi
1381 void ODM_SwAntDivChkPerPktRssi(
1382         PDM_ODM_T pDM_Odm,
1383         u8 StationID,
1384         struct odm_phy_info *pPhyInfo
1385 );
1386 
1387 u32 ODM_Get_Rate_Bitmap(
1388         PDM_ODM_T pDM_Odm,
1389         u32 macid,
1390         u32 ra_mask,
1391         u8 rssi_level
1392 );
1393 
1394 #if (BEAMFORMING_SUPPORT == 1)
1395 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId);
1396 #endif
1397 
1398 void odm_TXPowerTrackingInit(PDM_ODM_T pDM_Odm);
1399 
1400 void ODM_DMInit(PDM_ODM_T pDM_Odm);
1401 
1402 void ODM_DMWatchdog(PDM_ODM_T pDM_Odm); /*  For common use in the future */
1403 
1404 void ODM_CmnInfoInit(PDM_ODM_T pDM_Odm, ODM_CMNINFO_E CmnInfo, u32 Value);
1405 
1406 void ODM_CmnInfoHook(PDM_ODM_T pDM_Odm, ODM_CMNINFO_E CmnInfo, void *pValue);
1407 
1408 void ODM_CmnInfoPtrArrayHook(
1409         PDM_ODM_T pDM_Odm,
1410         ODM_CMNINFO_E CmnInfo,
1411         u16 Index,
1412         void *pValue
1413 );
1414 
1415 void ODM_CmnInfoUpdate(PDM_ODM_T pDM_Odm, u32 CmnInfo, u64 Value);
1416 
1417 void ODM_InitAllTimers(PDM_ODM_T pDM_Odm);
1418 
1419 void ODM_CancelAllTimers(PDM_ODM_T pDM_Odm);
1420 
1421 void ODM_ReleaseAllTimers(PDM_ODM_T pDM_Odm);
1422 
1423 void ODM_AntselStatistics_88C(
1424         PDM_ODM_T pDM_Odm,
1425         u8 MacId,
1426         u32 PWDBAll,
1427         bool isCCKrate
1428 );
1429 
1430 void ODM_DynamicARFBSelect(PDM_ODM_T pDM_Odm, u8 rate, bool Collision_State);
1431 
1432 #endif
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root/drivers/staging/rtl8723bs/hal/odm.h

INCLUDED FROM
